02-03-2024

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: Dr. Shameem Ahmad
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Micro-Processor
SE-CS
UNIT 1

1. Features of 80386DX
1. 80386 is a 32 bit µP i.e. it can operate on 32bit data in
one machine cycle.
2. it has 32bit ALU which can perform arithmetic
operations on 32 bit no.s at a time
3. 80386 has a “32 bit” Address Bus. This means it can
access a total of 232 = 4GB of physical memory
4. 80386 has a “32-bit” DATA BUS. This means 80386
can transfer 32-bit data at a time.
5. 80386 performs ADDRESS PIPELINING. It puts
address of the next machine cycle on the address bus
during T2 state of the current machine cycle.
6. It can access a total Virtual Memory of 64 TB (246).

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1. Features of 80386DX
7. 80386 uses a Protection Mechanism for accessing
both memory and I/O. It uses 4 Privilege Levels
8. 80386 allows multitasking using timesharing. Here
several tasks can execute simultaneously by taking a
small time slice of the µP. this gives higher system
performance.
9. 80386 uses a 16-bit I/O address and hence can
access up to 216 i.e. 65536 I/O devices.
10. It works on 16, 20, 25 and 33Mhz clock freq.
11. It used 3 stage instruction pipeline:
i.) Fetch ii.) Decode iii.) Execute

2. 80386DX ARCHITECTURE

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2. 80386DX ARCHITECTURE
1. Bus Unit (Bus Interface Unit)
• The Bus unit is responsible for transferring data in and out of the
µP. It is connected to the external memory and I/O devices, using the
system bus.
2. Code Prefetch Unit
• The prefetcher fetches further instructions in advance to
implement pipelining.
• It fetches the next 16 bytes of the program and stores it
into the Prefetch Queue
• It refills the queue when at least 4 bytes are empty as 80386
has a 32 bit data bus.
• During a branch, the instructions in the queue are invalid and
hence are discarded

2. 80386DX ARCHITECTURE
3. Decode Unit:
• It decodes the next three instructions and keeps them
ready in the Decode Queue.
• During a branch, the instructions in the queue are invalid
and hence are discarded.
4. Segmentation Unit
• It converts Virtual Address (Logical address) to
Linear Address.
• There are six segment registers in segmentation unit.
• Segmentation is compulsory, while Paging is optional.

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2. 80386DX ARCHITECTURE
5. Paging Unit:
• It converts Linear Address to Physical Address.
• If paging is not enabled Physical address is identical to
linear address.
6. Execution Unit
• It performs the main task of executing instructions.
• Arithmetic or Logic operations are performed by a 32-bit
ALU.
• It also has dedicated circuits for 32-bit multiplication and
division.
• A 64-bit barrel shifter is also provided for faster shifts during
multiplication and division.
• Additionally there is a 32-bit Flag register (EFLAGS) giving
the Status of the current result.

3. Operating Modes

• Real Mode:
• It is the default mode selected when
80386 is reset.
• 80386 works as a fast 8086µP.
• the memory used is only 1 MB
• Registers:
6, 16-bit segment registers: CS, SS, DS, ES,
FS and GS.
5, 16-bit offset registers IP,SP,BP,SI,DI.
4, 16-bit data registers :AX, BX CX and
DX
lower 12-bits of the Flag Register are used
Only the LSB of CR0 (PE)is available in
Real Mode

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3. Operating Modes

• Protected Mode:
• In Protected Mode, 80386 µP provides
dedicated hardware to prevent user
programs from affecting other user
programs and Operating System.
• There are Four Privilege Levels, assigned
to programs and data to define their Registers:
privileges. six, 16-bit segment registers.
five, 32-bit extended offset
Level0 is assigned to the Operating System Kernel
registers(EIP,ESP,EBP,EDI,ESI)
(Main part of the Operating System)
Four, 32-bit general purpose
Level1 is assigned to the System Services. registers EAX,EBX,ECX,EDX
Level2 is assigned to the Custom Extensions of the OS32 bit flag register called
EFLAGS (or PSW)
level3 is assigned to all the User Application and Four 32bit control registers:
Programs CR0,CR1,CR2,CR3

3. Operating Modes
• Virtual 86 Mode:
• In this mode the 80386 works as 8086.
• Once in protected mode we cannot go back to real mode.
• So we use Virtual86 mode to run 8086 programs.
• The VM bit in flag register is set to enter in virtual86
mode.
• After the 8086 programs are over and VM bit in flag
register is made 0 to come back in protected mode.
• Features available in protected mode are also available.

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4. Addressing Modes
• The 80386 provides a total of 11 addressing modes

4. Addressing Modes
1. Register Addressing Mode:
• Operand is in register.
• Example: MOV EAX, EDX; EAX ← EDX
2. Immediate addressing mode:
• Operand is in instruction.
• Example: MOV ECX, 20563545H; ECX←20563545H
3. Direct addressing mode:
• The operand's offset address is given in the instruction.
• Example: MOV AX, [3545H]; AX←[DS+3545H]
4. Register indirect addressing mode:
• A BASE register contains the address of the operand.
• Example: MOV EAX, [EDX]; EAX ← [EDX]
5. Based addressing mode:
• A BASE register's contents is added to a DISPLACEMENT to form the operands
offset.
• Example: MOV EAX, [EDX+24H];
6. Index:
• An INDEX register's contents is added to a DISPLACEMENT to form the
operands offset
• Example: MOV EAX, TABLE[ESI], ; EAX ← Segment:[ESI+ offset of TABLE]

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4. Addressing Modes
7. Based Index:
• The contents of a BASE register is added to the contents of an INDEX register to form the
effective address of an operand.
• Example: MOV EAX, [ESI] [EBX]; EAX←Segment: [ESI+EBX]
8. Based Index Mode with Displacement:
• The contents of an INDEX Register and a BASE register's contents and a
DISPLACEMENT are all summed together to form the operand offset.
• Example: MOV EAX, [ESI] [EBP+000FFF0H]; EAX←Segment:[ESI][EBP+000FFF0H]
9. Scale Index:
• An INDEX register's contents is multiplied by a scaling factor which is added to a
DISPLACEMENT to form the operands offset.
• Example: MOV ECX, TABLE[ESI*4]; ECX←Segment:[ESI*4+ offset of TABLE]
10. Based Scaled Index:
• The contents of an INDEX register is multiplied by a SCALING factor and the result is
added to the contents of a BASE register to obtain the operands offset.
• Example: MOV ECX, [EDI*8] [EAX]; ECX ← Segment:[EDI*8+EAX]
11. Based Scale Index Mode with Displacement:
• The contents of an INDEX register are multiplied by a SCALING factor, the result is added
to the contents of a BASE register and a DISPLACEMENT to form the operand's offset.
• Example: MOV EAX, [ESI*5] [EBP+000FFF0H];
EAX←Segment:[(ESI*5)+EBP+000FFF0H]

4. Addressing Modes

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5. Data types
• Byte 8bit
• Word 16bit
• Double word 32bit
• Signed integer 16bit
• Unsigned integer 16bit
• Bit field upto 32bits
• Bit string upto 4Gbits
• String upto 4Gbytes
• Unpacked BCD 8bits
• Packed BCD 8bits

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