Scribd
Upload
26 views

Computer Architecture - 09 - Review For Midterm

Here is the code with NOP instructions added to address data hazards: addi $t0, $t1, 10 addi $t0, $t1, 10 NOP add $t2, $t0, $t1 NOP addi $t3, $t0, 5 NOP add $t2, $t0, $t1 add $t4, $t2, $t1 NOP addi $t3, $t0, 5 NOP NOP add $t4, $t2, $t1

Uploaded by

dlwodbs031
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
26 views

Computer Architecture - 09 - Review For Midterm

Here is the code with NOP instructions added to address data hazards: addi $t0, $t1, 10 addi $t0, $t1, 10 NOP add $t2, $t0, $t1 NOP addi $t3, $t0, 5 NOP add $t2, $t0, $t1 add $t4, $t2, $t1 NOP addi $t3, $t0, 5 NOP NOP add $t4, $t2, $t1

Uploaded by

dlwodbs031
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

CSE203 Computer Architecture

09. Review for Midterm Exam

Prof. Seong Tae Kim ([email protected])


Augmented Intelligence Lab. (ailab.khu.ac.kr)
School of Computing, Kyung Hee University
1
HW1-Assignment 1
Processor X has a clock speed of 2 GHz and takes 1 cycle for integer operations, 5
cycles for memory operations, and 5 cycles for floating-point operations. Empirical
data shows that programs run on Processor X typically are composed of 50%
floating-point operations, 10% memory operations, and 40% integer operations. You
are designing Processor X-v2, an improvement on Processor X which will run the
same programs and you have 2 options to improve the performance:
a) Increase the clock speed to 3GHz, but memory operations take 4 cycles but
floating-point operation takes 8 cycles
b) Reduce floating-point operations only take 3 cycles but clock speed becomes 1.6
GHz
Please compute the speed up for both options and decide the option Processor X-v2
should take
2
HW1-Assignment 1
Sol)
Performance of processor X = 1/execution time of processor X
Execution time of processor X = 1/ clock speed × the number of cycle
The number of cycle = A(0.5 × 5 + 0.4 × 1 + 0.1 × 5) = 3.4 A
Execution time X = (1/2GHz) × 3.4A = 1.7A ns
a) Execution time of A = (1/3GHz) × (0.5 × 8+ 0.4 × 1 + 0.1 ×4)A = 1.6A ns
b) Execution time of B = (1/1.6GHz) × (0.5 × 3 + 0.4 × 1 + 0.1 × 5)A =
1.5Ans.

• Therefore, you should select B as Processor X-v2.


3
HW1-Assignment 2
Consider two different implementations, M1 and M2, of the same instruction
set. There are four classes of instructions (A, B, C, and D) in the instruction
set. M1 has a clock rate of 1GHz. M2 has a clock rate of 1.5GHz.
M1: CPI for class A,B,C,D are 4,4,1,3, respectively
M2: CPI for class A,B,C,D are 5,2,3,5, respectively

If the number of instructions executed in a certain program is divided equally


among the classes of instructions above, please provide answers to the
following questions:
a) Which one is faster between M1 and M2?
b) And how much faster? 4
HW1-Assignment 2
Sol)
• Let the number of instructions be A for both cases. Then, execution
time = number of instructions × avg CPI × 1/clock rate
• Execution time of M1 = A ×(4+4+1+3)/4 × 1/1G = 3A ns
• Execution time of M2 = A ×(5+2+3+5)/4 × 1/1.5G = 2.5A ns
M2 is faster than M1 (1.2 times)

5
HW1-Assignment 3
• In the following code segment, f, g, h, i, and j are variables. If the five
variables f through j correspond to the five registers $s0 through $s4,
what is the compiled MIPS code for this C if statement?

if (i == j)
f = g + h;
else
f = g – h;

6
HW1-Assignment 3
Sol)
In general, the code will be more efficient if we test for the opposite
condition to branch over the code that performs the subsequent then part
of the if (the label Else is defined below) and so we use the branch if
registers are not equal instruction (bne):
bne $s3,$s4,Else # go to Else if i ≠ j
add $s0,$s1,$s2 # f = g + h (skipped if i ≠ j)
j Exit # go to Exit
Else: sub $s0,$s1,$s2 # f = g – h (skipped if i = j)
Exit:
7
HW1-Assignment 3 참고자료
if (i==j && i==k)
f = g + h;
else
f = g - h;

---beq 의 경우--- ---bne 의 경우---


beq $s3, $s4, And bne $s3, $s4, Else
j Else bne $s3, $s5, Else
And: add $s0, $s1, $s2
beq $s3, $s5, Then: j Exit
j Else Else:
Then: sub $s0, $s1, $s2
add $s0, $s1, $s2 Exit:
j Exit
Else:
sub $s0, $s1, $s2
Exit: 8
HW1-Assignment 4
What is the assembly language statement corresponding to this machine
instruction? (Please find the information from the following tables)
0000 0000 1110 1110 1000 0000 0010 0101

or $s0,$a3,$t6
9
HW1-Assignment 5
• Following figure shows the datapath of the MIPS processor. Please write the
following five control signals (RegWrite, ALUSrc, PCSrc, MemToReg) for R-
format, lw, sw, beq instructions, respectively.

RegDst RegWrite ALUSrc MemWrite MemRead MemToReg

Add 1 1 0 0 0 0

lw 0 1 1 0 1 1

sw X 0 1 1 0 X

beq X 0 0 0 0 X

10
Q&A
• case1에서 j C1_BODY로 가서
case1에 해당하는 instruction(addi
$s1, $s1, 1)을 실행하게 됩니다.
• 그 후 C2_BODY의 명령어가
실행되지 않기 위해서 jump를
넣어줘야하는게 아닌지
궁금합니다.

11
• For the following C statement, write the corresponding MIPS
assembly code. Assume that the variables i and j are assigned to
registers $s0 and $s1, respectively. Assume that the base address of the
arrays A and B are in registers $s2 and $s3, respectively.

B[5] = A[i − j];

sub $t0, $s0, $s1 *sll: Shift left logical


sll $t0, $t0, 2
add $t0, $s2, $t0
lw $t1, 0($t0)
sw $t1, 20($s3)
12
• Add NOP instructions to the code below so that it will run correctly on
a pipeline that does not handle data hazards.

addi $t0, $t1, 10


addi $t0, $t1, 10
NOP
add $t2, $t0, $t1
NOP
addi $t3, $t0, 5
add $t2, $t0, $t1
add $t4, $t2, $t1
addi $t3, $t0, 5
NOP
add $t4, $t2, $t1
13

You might also like