Question Bank (MCQ & Descriptive)

Sem. :- II Class :- F. Y. B. Sc. (Comp. Sci.)

Subject :- Basics of Computer Organization (Electronics - II)

Q. 1 Multiple Choice Questions

1. Latches constructed with NOR and NAND gates tend to remain in the
latched condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
2. When both inputs of a J-K flip-flop 1 and without clock cycle, the output will
___________
a) Be invalid
b) Change
c) Not change
d) Toggle
3. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or
LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
4. A basic S-R flip-flop can be constructed by cross-coupling of which basic
logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
5. The logic circuits whose outputs at any instant of time depends only on the
present input but also on the past outputs are called ________________
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
6. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
7. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
8. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
9. The output of latches will remain in set/reset until ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
10. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
11. The circuits of NOR based S-R latch classified as asynchronous sequential
circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
12. Combinational circuit have Memory Element to store data.
a) True
b) False
13. Latches are classified as Synchronous & Asynchronous latch.
a) True
b) False
14. D flip flop eliminates the --------- combinations of SR inputs, therefore it
holds information available on its input.
a) Different
b) Same
c) None of above
15. In the level Triggered “T” Flip Flop output Toggles after every --------- time.
a) Propagation delay
b) Input delay
c) T=1
d) None of above
16. A shift register that will accept a parallel input or a bidirectional serial load
and internal shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
17. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
18. The group of bits 1111 is serially shifted (right-most bit first) into a 4-bit
parallel output shift register with an initial state 0000. After three clock pulses,
the register contains ______
a) 1100
b) 1001
c) 1110
d) 1111
19. Assume that a 4-bit serial in/serial out shift register is initially clear. We
wish to store the nibble 1100. What will be the 4-bit pattern after the second
clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
20. ------ no. of clock pulses needs to shift in 4 bit data serially & shift out
parallel.
a) 7
b) 4
c) 5
d) 3
21. In digital logic, a counter is a device which ____________
a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
22. A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
23. What is the maximum possible range of bit-count specifically in n-bit
binary counter consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
24. Ripple counters are also called ____________
a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
25. BCD counter is also known as ____________
a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
26. The type of register, in which we have access only to leftmost or rightmost
flip-flop is.
a) shift left & shift right register
b) serial in & serial out shift register
c) serial in &parallel out shift register
d) parallel in & serial out shift register
27. Which of the following statement are true regarding a synchronous
up/down counter?
a) It can count in any direction but direction can't be changed once counting
has started
b) The direction can be changed midway, but the counter has to be reset before
that can be done
c) The counter can be reversed at any moment, no strings attached
d) The direction cannot be changed midway, and when changed the counter
has to be reset first
28. The delay problems encountered with asynchronous counters are removed
with synchronous counters because the:
a) Input clock pulses are applied simultaneously to each stage
b) Input clock pulses are not used to activate any of the counter stages
c) Input clock pulses are not used to activate any of the counter stages
d) Input clock pulses are applied only to the first and last stages
29. Which is not an example of a truncated modulus counter?
a) 8
b) 5
c) 6
d) 15
30. _______ is the basic memory unit in digital electronics and hold 1-bit of
data.
a) Encoder
b) NAND gate
c) EX-OR gate
d) Flip-Flop
31. A 32-bit address bus allows access to a memory of capacity

a) 64 Mb

b) 16 Mb

c) 1 Gb
d) 4 Gb

32. The system bus is made up of

a) data bus

b) data bus and address bus

c) data bus and control bus

d) data bus, control bus and address bus

33. Which of the following data transfer mode takes relatively more time?

a) DMA

b) interrupt initiated I/O

c) programmed I/O

d) Isolated I/O

34. Which of the following holds data and processing instructions temporarily
unit the CPU needs it?

a) ROM

b) control unit

c) main memory

d) coprocessor chips

35. Which of the following affects processing power?

a) data bus capacity

b) addressing scheme

c) clock speed

d) all of the above

36. Both the arithmetic logic unit (ALU) and control selection of CPU employ
special purpose storage locations called

a) decoders

b) buffers

c) multiplexer

d) registers
37. If the width of data bus is 16, ----- is the largest no. data bus can carry.

a) 256

b) 1KB

c) 65535

d) 65536

38. Input unit receives data from input device & decodes into -------- language,
and then load it to CPU.

a) 1 & 0

b) Machine

c) High

d) Assembly

39. The combined value of a binary selection inputs specifies the ------- word.

a) data

b) address

c) control

d) none of above

40. ---- register holds the topmost address on stack.

a) program counter

b) stack pointer

c) address register

d) none of the above

41. Stack pointer is incremented after PUSH operation in Memory Stack.

a) True

b) False

42. I/O interface unit is required, due to the difference in the mode of
operation of both peripheral devices and CPU.

a) True

b) False
43. Transferring data under programmed I/O requires --------- monitoring of
the peripherals by the CPU.

a) frequent

b) Interrupt based

c) constant

d) none of above

44. The stack is useful for

a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned

45. The method which offers higher speeds of I/O transfers is ___________
a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
46. What is true about memory unit?
a) A memory unit is the collection of storage units or devices together.
b) The memory unit stores the binary information in the form of bits.
c) Both A and B
d) None of the above
47. Auxiliary memory access time is generally ________ times that of the main
memory
a) 10
b) 100
c) 1000
d) 10000
48. What is the formula for Hit Ratio?
a) Hit/(Hit + Miss)
b) Miss/(Hit + Miss)
c) (Hit + Miss)/Miss
d) (Hit + Miss)/Hit
49. The fastest data access is provided using _______
a) Cache
b) DRAM's
c) SRAM's
d) Registers
50. Which of the following is true?
a) To overcome the slow operating speeds of the secondary memory we make
use of faster flash drives.
b) If we use the flash drives instead of the hard disks, then the secondary
storage can go above primary memory in the hierarchy.
c) In the memory hierarchy, as the speed of operation increases the memory
size also increases.
d) Both A and C
51. Cache Memory is implemented using the DRAM chips.
a) True
b) False
52. In ____________ mapping, the data can be mapped anywhere in the Cache
Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect
53. The transfer between CPU and Cache is ______________
a) Block transfer
b) Word transfer
c) Set transfer
d) Associative transfer
54. --------- is the time interval between the read/write request and the
availability of the data.
a) Execution Time
b) Access Time
c) Instruction Cycle
d) Processing Time
55. When data and code lie in same memory blocks, then the architecture is
referred as Harvard architecture.
a) True
b) False
56. Because of virtual memory, the memory can be shared among ____________
a) processes
b) threads
c) instructions
d) none of the mentioned
57. Which algorithm chooses the page that has not been used for the longest
period of time whenever the page required to be replaced?
a) first in first out algorithm
b) additional reference bit algorithm
c) least recently used algorithm
d) counting based page replacement algorithm
58. Which memory is called separation of user logical memory and physical
memory
a) Memory sharing
b)Virtual memory
c)Memory management
d) Memory control
59. Logical address space is smaller than physical address space.
a) True
b) False
60. Vertical memory expansion is modifies the no. of address lines (N) that is
memory locations (2N). It expands the --------- of memory.
a) Word length
b) Word capacity
c) Memory capacity
d) None of above

Q. 2. Explain in brief the following questions.

1. Draw & explain working of SR latch using NOR gate with truth table.
2. Note down the difference between combinational & sequential circuit
3. Draw & explain JK flip flop using NAND gate with truth table.
4. Draw logic diagram & truth table for D & T flip flop.
5. Explain the terms Propagation delay, Race-around condition & Toggling.
6. Draw & Explain 4 bit SISO shift register.
7. Draw & Explain 4 bit bidirectional shift register.
8. Explain with suitable diagram 4 bit PISO shift register.
9. With suitable diagram & timing diagram explain asynchronous 3 bit
binary down counter.
10. Draw 3 bit binary synchronous up/down counter and its timing diagram.
11. Note down the difference between Synchronous & asynchronous counter.
12. Draw & Explain decade counter using JK flip-flop.
13. With suitable diagram explain 4 bit binary Ring Counter.
14. Draw Universal Shift register.
15. Explain the working of decade counter using IC 7490.
16. Explain with suitable diagram System Bus
17. Explain the operation R3=R1+R2 in register based CPU, with suitable
diagram.
18. Explain Register based stack organization.
19. Define Memory Stack & explain with suitable diagram.
20. What is the need of I/O interface? Explain in short concept of I/O
interface.
21. Draw & explain DMA controller.
22. What is the difference between Programmed I/O, Interrupt Initiated I/O
& DMA?
23. Draw & explain general I/O interface unit.
24. Explain Programmed & Interrupt initiated I/O.

25. Define the following terms Capacity, Hit Rati, Performance, and Cost per
bit
26. Explain memory write cycle using suitable timing diagram.
27. Design 64X8 memory using 16X8 memory chips.
28. Explain Direct Cache mapping using suitable example.
29. Explain virtual memory mapping using segmentation.
30. Draw and explain Computer Block Diagram with functions of each block.

@@@@@@@@@@@@