PCS-978S - X - Technical Manual - EN - Overseas General - X - R1.25
PCS-978S - X - Technical Manual - EN - Overseas General - X - R1.25
NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR
trademarks may be used without written permission. NR products appearing in this document may
be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and
benefits afforded under P.R. China and international copyright and patent laws in its products,
including but not limited to software, firmware and documentation. NR Engineering Co., Ltd. is
licensed to use this document as well as all intellectual property rights owned or held by NR
Electric Co., Ltd, including but not limited to copyright, rights in inventions, patents, know-how,
trade secrets, trademarks and trade names, service marks, design rights, database rights and
rights in data, utility models, domain names and all similar rights.
The information in this document is provided for informational use only and does not constitute a
legal contract between NR and any person or entity unless otherwise specified. Information in this
document is subject to change without prior notice.
To the extent required the products described herein meet applicable IEC and IEEE standards,
but no such assurance is given with respect to local codes and ordinances because they vary
greatly.
Although every reasonable effort is made to present current and accurate information, this
document does not purport to cover all details or variations in equipment nor provide for every
possible contingency to be met in connection with installation, operation, or maintenance. Should
further information be desired or should particular problems arise which are not covered
sufficiently for your purposes, please do not hesitate to contact us.
Preface
Preface
The manual describes the protection, control, measurement and supervision functions with the
information of relevant hardware for PCS-978S Transformer Relay.
The intended use of manuals throughout the product lifecycle is shown in the figure below.
Planning
Ordering
Engineering
Installing
Commissioning
Operation
Maintenance
Disposal
The datasheet (DS) contains describes the control, protection, measurement and supervision
functions with the information of relevant hardware for the device.
The selection guide (SLG) contains the explanation about the application option, the firmware
option, the software option, the hardware option and etc., and is instructive about how to order the
device based on expected configurations.
The technical manual (TM) contains operation principle descriptions, and lists function blocks,
logic diagrams, input and output signals, setting parameters and technical data, sorted per
function. The manual can be used as a technical reference during the engineering phase,
installation and commissioning phase, and during normal service.
The application manual (AM) contains application descriptions and instructions on how to
engineer the device using the configuration tool PCS-Studio. The manual can be used to find out
when and for what purpose a typical protection function can be used. The manual also
recommends a sequence for the engineering of protection, control, measurement and supervision
functions, HMI functions as well as communication engineering.
The communication protocol manual (CPM) describes the communication protocols supported
by the device. The manual concentrates on the vendor-specific implementations.
The operation and commissioning manual (OCM) contains instructions on how to operate and
commission the device. The manual describes how to identify disturbances and how to view
calculated and measured power grid data to determine the cause of a fault. The manual also
describes the process of testing the device in a substation which is not in service.
The installation and maintenance manual (IMM) contains instructions on how to install,
maintain and disposal the device. The manual provides procedures for mechanical and electrical
installation, lifecycle maintenance and repairing, and scrap disposal when decommissioning.
The cybersecurity manual (CM) describes the process for handling cyber security when
communicating with the device. Certification, Authorization with role-based access control, and
product engineering for cyber security related events are described and sorted by function. The
guideline can be used as a technical reference during the engineering phase, commissioning
phase, and during normal service.
The settings guide (STG) contains instructions on how to calculate the device's settings of
various functions (including the protection, automation, control, and supervision functions)
according to the different system parameters and fault conditions.
Safety Information
This manual is not a complete index of all safety measures required for operation of the
equipment (module or device). However, it comprises important information that must be followed
for personal safety, as well as to avoid material damage. Information is highlighted and illustrated
as follows according to the degree of danger:
Date: 2022-01-17
Preface
Indicates that property damage can result if the measures specified are
not taken.
Contact with instrument terminals can cause electrical shock that can
result in injury or death.
Use of this equipment in a manner other than specified in this manual can
impair operator safety safeguards provided by this equipment.
Have only qualified personnel service this equipment. If you are not
qualified to service this equipment, you can injure yourself or others, or
cause equipment damage.
Date: 2022-01-17
Preface
DO NOT connect power to the relay until you have completed these
procedures and receive instruction to apply power. Equipment damage
can result otherwise.
Document Conventions
The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The
Glossary also contains definitions of important terms.
For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1
Binary input signals, binary output signals, analogs, LED lights, buttons, and other fixed
meanings, should be written in double quotes and bold.
Symbols
AND Gate
OR Gate
Comparator
BI xxx
Signal input
SIG xxx
Setting input
SET xxx
Enable input
EN xxx
Timer
Timer
t
t
Timer
10ms 2ms
Timer
Date: 2022-01-17
Preface
[Tset1] 0ms
Timer
0ms [Tset2]
Timer
[Tset1] [Tset2]
Generator
Transformer
Reactor
Motor
Capacitor
Busbar
Circuit breaker
52
Current transformer
3CT
*
Voltage transformer
3VT
Disconnector
Earth
Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
Warranty
Date: 2022-01-17
Preface
NR can provide up to 10-year warranty for this product. For warranty details, please consult the
manufacturer or agent for warranty information.
Document Structure
This manual is a comprehensive work covering the theories of protection, control, supervision,
measurement, etc. and the structure & technical data of relevant hardware. Read the sections that
pertain to your application to gain valuable information about using the PCS-978S. To concentrate
on the target sections of this manual as your job needs and responsibilities dictate. An overview of
each manual section and section topics follows.
1 Introduction
Introduces PCS-978S features, summarizes functions and applications of the device.
2 Technical Data
Lists device specifications, type tests, and ratings.
3 Protection Functions
Describes the function of various protection elements, gives detailed specifics on protection
scheme logic, and provides the relevant logic diagrams.
4 Control Functions
Describes the logic for the control of disconnectors and circuit breakers.
5 Measurement
Provides information on viewing fundamental and rms metering quantities for voltages and
currents, as well as power and energy metering data.
6 Supervision
Describes self-supervision technique to help diagnose potential difficulties should these occur and
includes the list of status notification messages. Provides a troubleshooting chart for common
device operation problems.
7 System Functions
Describes how to perform fundamental operations such as clock synchronization, communicating
with the device, switching active setting group, checking relay status, reading event reports and
SER (Sequential Events Recorder) records.
8 Hardware
Describes the hardware of the PCS series device family and provides general information on the
product structure and the modules technical data.
9 Settings
Provides a list of all settings and their ranges, unit, steps, defaults. The organization of the
settings is similar to the settings organization in the device and in the PCS-Studio software.
Appendix A Glossary
Describes the abbreviations adopted in this manual.
Corresponding Version
Date Description of change
Document Software
1588
Add SV links
Date: 2022-01-17
Preface
protection
R1.21 R1.31 2020-07-07 Added runaway trip description for tap changer control
NR6106BP
preface part
protection
underfrequency protection
[81Ui.Opt_Trp/Alm]
R1.24 R1.35 2021-08-16
Added the alarm signal “81Oi.Alm” and “81Ui.Alm”
Deleted PPM
Synchronization Settings
Date: 2022-01-17
1 Introduction
1 Introduction
1
Table of Contents
List of Figures
Date: 2022-01-17
1 Introduction
1.1 Application
1
PCS-978S transformer relay provides fast and selective protection, control and monitoring for
two-winding transformers, three-winding transformers, auto-transformers, as well as reactors. The
full transformer protections are configurable by user. Ancillary functions of fault diagnostic,
disturbance records, event records and communication function are integrated in the device.
The PCS-978S is applicable not only to conventional substations, but also to digital substations. It
supports IEC 61850 Editions 1 and 2 and provides GOOSE and SV network interfaces with high
real-time performance. The process level network supports peer-to-peer (P2P) mode and
networking mode, including single network mode and dual network mode. The station level
network could also receive and send MMS messages (such as interlocking signals) or process
level GOOSE messages (such as trip signals).
The function diagrams for protecting an auto-transformer and a reactor are respectively shown
below.
HVS
52 3 VT
*
3 CT
64 50B
87T 49 87W 67G 67P 21T
REF F
MVS 50/
*
51P
1 CT
* *
52 50/
* 67Q
3 CT 51G
1 CT
1 CT
*
50/
MR
51Q
1 CT
3 VT
3 CT
*
52
3 VT
LVS
Bus1
1 52
Line
3VT
52 50/
21IT 49 87R
51P
*
3 CT
50/
Shunt reactor 51G
3 CT
52
*
Bus2
1 CT
*
Date: 2022-01-17
1 Introduction
Date: 2022-01-17
1 Introduction
Switchgear control
Direct control
U, I, P, Q, S, Cos, f
Max.15th harmonics
Energy metering (active and reactive energies for import and export)
Self diagnostic
Powerful faults recording (max. buffer for 10,000 sampled points at 1.2 or 9.6 kHz)
Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.
Disturbance recorder including 64 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)
Date: 2022-01-17
1 Introduction
Two RS-485 serial ports for communication, the second one could be used as a RS-232 port
for printer
Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and set-point
adjustment
Push buttons for open/close, switch for selection between local and remote control, and user's
login and logout authority management
Configuration tool—PCS-Studio
Clock synchronization
IRIG-B: IRIG-B via serial port (RS-485 or TTL level), female BNC (TTL level) or
ST-connector port
1 PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), female BNC (TTL
level), ST-connector port or binary input
IEEE 1588: Clock message based on IEEE 1588 via Ethernet network
Cyber security
NERC CIP
IEC 62351
IEC 62443
IEEE 1686
1.9 Features
Unified software and hardware platform, comprehensive power grid solutions of protection,
measurement and monitoring, easy to use and maintain.
High reliability and redundancy design for drive systems of the sampling circuit and the output
circuit ensure that overall reliability of the device is high. Real-time sampling based on dual AD
can mutually check and detect the potential abnormality in the sampling circuit in time. The
control power supply of the output relay is independent with the control circuit of trigger signals,
which can prevent from undesired operation caused by the abnormality of drive circuit of
output relays.
Various function modules can satisfy various situations according to the different requirements
of users. Flexible and universal logic programming, user-defined configuration of BI/BOs,
buttons and LEDs and powerful analog programming are supported.
Modularized hardware design makes the device be easily upgraded or repaired by a qualified
service person. It can be mixed with different I/O modules, with online self-check and
monitoring function, and the device can be restored from abnormal operation only need to
replace a single abnormal module.
Support memory check and error correction function, ensure high reliability and safety.
Fully compatible with IEC 61850 edition 1 & edition 2, support MMS service, IEC 62351
communication service, GOOSE communication in station level & process level, SV
Date: 2022-01-17
1 Introduction
Full comply with cyber security standards, including IEC62443, IEC62351, IEEE1686,
NERC-CIP, support role based access control (RBAC), security audit, security encryption 1
communication and security tool, improve the cyber security capability of devices.
Powerful COMTRADE fault and disturbance recording function is supported. The whole
recording time is automatically configurable by the fault duration, which is convenient to fault
analysis and replay. The recording sample rate is up to 9.6kHz.
Settable secondary rated current (1A/5A) and settable voltage threshold of binary input
Support flush mounting, semi-flush mounting, surface mounting, wall mounting and other
mounting methods.
Cross screw IO, CT/VT terminals can support AWG12 specification connector and 4mm 2 lead
PCS-Studio is the application software on the user's PC for the interface with PCS S series
devices providing all the related functionality. It ranges from device configuration to full
substation design of bay integration.
Support actual system phase sequence, either ABC or ACB, incorrect connection of actual
phase sequence can automatically be verified and relevant protection functions can be
blocked.
Equipped with high-speed large capacity output relay, its operation speed is less than 1ms and
its break capacity is up to 10A. The real-time supervision for output drive circuit can detect the
abnormality in advance.
Support setup up to 40 users and allow each user to own different password and access
authority.
High degree of functional integration and flexible configuration modes, transformer main
protection and back-up protection can be integrated in one device, or be separated in two
devices.
The tripping output contacts can be configured by tripping matrix, which is flexible, convenient
and suitable to any mode of tripping.
The relay supports at most 6 branches differential protection. The transformer angle can be
adjusted flexibly, and any transformer angle compensation mode is supported and any side
can be chosen as the reference side of differential protection.
Reliable differential CT circuit failure supervision. The relay can detect multi-phase CT
wire-break, multi-side CT wire-break, short-circuit, and other complex situation. The
1 corresponding logic setting can be used to select blocking differential protection or not, in case
of CT circuit failure.
Multiple inrush current blocking options are provided. Self-adaptive inrush current blocking
criterion can ensure the relay fast operation for transformer energized on to a slight fault,
meanwhile it will avoid the unwanted operation in the case of the energization inrush current
caused by energizing transformer with no load, the recovery inrush current caused by cutting
off the transformer external fault, and the sympathetic inrush current.
Biased DPFC differential protection is regardless of load current and is sensitive to small
internal fault current within the transformer. Its anti CT saturation performance is also strong.
Date: 2022-01-17
2 Technical Data
2 Technical Data
Table of Contents
Date: 2022-01-17
2 Technical Data
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 1s 100In
Linear to 1V~300V
100Vac/110Vac/
24Vdc/30Vdc 110Vdc/125Vdc/ 115Vac/120Vac/
Rated voltage
2 48Vdc/60Vdc 220Vdc/250Vdc
127Vac/220Vac/
230Vac/240Vac/250Vac
IEC 61000-4-11:2017
IEC 60255-26-2013
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage
binary output (BO) module Additional for each energized Max. 0.44W
Date: 2022-01-17
2 Technical Data
relay
module
Up to 84 (6U, 1/2 × 19", ring ferrule), 105 (6U, 1/2 × 19", pin ferrule), 234
Number (6U, 1/1 × 19", ring ferrule), or 297 (6U, 1/1 × 19", pin ferrule) binary
inputs
Up to 84 (6U, 1/2 × 19", ring ferrule), 105 (6U, 1/2 × 19", pin ferrule), 234
Number (6U, 1/1 × 19", ring ferrule), or 297 (6U, 1/1 × 19", pin ferrule) binary
inputs
Up to 84 (6U, 1/2 × 19", ring ferrule), 105 (6U, 1/2 × 19", pin ferrule), 234
Number (6U, 1/1 × 19", ring ferrule), or 297 (6U, 1/1 × 19", pin ferrule) binary
inputs
Settable pickup voltage and dropout voltage for high power binary input
Up to 39 (6U, 1/2 × 19", ring ferrule), 42 (6U, 1/2 × 19", pin ferrule), 117
Number (6U, 1/1 × 19", ring ferrule) or 126 (6U, 1/1 × 19", pin ferrule), binary
inputs
Settable pickup voltage and dropout voltage for high power binary input
Date: 2022-01-17
2 Technical Data
Up to 39 (6U, 1/2 × 19", ring ferrule), 42 (6U, 1/2 × 19", pin ferrule), 117
Number (6U, 1/1 × 19", ring ferrule) or 126 (6U, 1/1 × 19", pin ferrule), binary
inputs
2
Fixed pickup voltage and dropout voltage for binary input of MR (Mechanical Relay) contact
On value >77Vdc
Up to 15 (6U, 1/2 × 19", pin ferrule) or 45 (6U, 1/1 × 19", pin ferrule) MR
Number
inputs
Fixed pickup voltage and dropout voltage for binary input of MR contact
On value >87.5Vdc
Up to 15 (6U, 1/2 × 19", pin ferrule) or 45 (6U, 1/1 × 19", pin ferrule) MR
Number
inputs
Fixed pickup voltage and dropout voltage for binary input of MR contact
On value >154Vdc
Up to 15 (6U, 1/2 × 19", pin ferrule) or 45 (6U, 1/1 × 19", pin ferrule) MR
Number
inputs
Tripping/signaling contact
0.5A@48Vdc
0.35A@110Vdc
0.20A@220Vdc
0.15A@250Vdc
0.5A@48Vdc
0.35A@110Vdc
Cyclic Capacity (2.5 cycle/second,
0.30A@125Vdc
L/R=40ms)
0.20A@220Vdc
0.15A@250Vdc
30A@3s
Short duration current
50A@1s
Up to 44 (6U, 1/2 × 19", ring ferrule), 56 (6U, 1/2 × 19", pin ferrule), 122
Number (6U, 1/1 × 19", ring ferrule), or 158 (6U, 1/1 × 19", pin ferrule)
tripping/signal contacts
Date: 2022-01-17
2 Technical Data
10A@48V 2
10A@110V
Breaking capacity (L/R=40ms)
10A@125V
10A@250V
10A@48V L/R=40ms
Cyclic Capacity (4 cycle/second,
10A@110V L/R=40ms
followed by 2 minutes idle for thermal
10A@125V L/R=40ms
dissipation)
10A@250V L/R=20ms
30A@3s
Short duration current
50A@1s
Up to 12 (6U, 1/2 × 19", ring ferrule), or 36 (6U, 1/1 × 19", ring ferrule)
Number
heavy-capacity tripping contacts
Continuous carry 8A
1.00A@48Vdc
0.50A@110Vdc
0.25A@220Vdc
0.20A@250Vdc
12A@3s
15A@1s
Short duration current
[email protected]
Up to 45 (6U, 1/2 × 19", pin ferrule) or 135 (6U, 1/1 × 19", pin ferrule)
Number
MR outputs
Device structure Plug-in modular type @ rear side, integrated front plate
Protection Class
IP52
Front side IP54 (valid for surface mounting mode of 6U 19" × 1/2 case with sealing
strip)
Date: 2022-01-17
2 Technical Data
Pollution degree Ⅱ
Altitude <3000m
Capacity Max. 32
Connector type LC
Type RS-232
Maximum voltage 6V
Isolation 500Vdc
Date: 2022-01-17
2 Technical Data
Isolation 500Vdc
2
Characteristic Glass optical fiber
Connector type ST
Overvoltage category Ⅲ
IEC 60255-26:2013
2 1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Frequency sweep
Radiated amplitude-modulated
Spot frequency
Radiated amplitude-modulated
IEC 60255-26:2013
Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 5kHz, 5/50ns
IEC 60255-26:2013
IEC 60255-26:2013
Date: 2022-01-17
2 Technical Data
IEC 61000-4-9:2016
Pulse magnetic field immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s
IEC 60255-26:2013
Conducted emission 0.15MHz~0.50MHz: 79dB (μV) quasi peak, 66dB (μV) average
IEC 60255-26:2013
peak @3m
Above 1GHz
3GHz~6GHz: 60dB (μV/m) average, 80dB (μV/m)
peak @3m
IEC 60255-26:2013
interruptions configuration)
2.6 Certifications
ISO9001:2015
ISO14001:2015
ISO45001:2018
ISO/IEC27001:2013
CMMI L5
2 WEEE: 2012/19/EU, EN 50419:2006
Type Resolution
2.8 Terminals
Date: 2022-01-17
2 Technical Data
External time synchronization IRIG-B (200-98), PPS, IEEE 1588 or SNTP protocol
There are some symbols mentioned in the following sections and the meaning of them is given
here.
p.u.——per unit value of settings and currents for current differential protection
Id——differential current
Date: 2022-01-17
2 Technical Data
Operating time (without time delay, without 50Hz: ≤30ms (3I0d>2 times current setting, internal fault)
blocking criterion) 60Hz: ≤25ms (3I0d>2 times current setting, internal fault)
Accuracy of time setting ≤1% of setting +30ms (3I0d>2 times current setting)
Accuracy of time setting ≤1% of setting +30ms (3I0d>2 times current setting)
Date: 2022-01-17
2 Technical Data
protection
Date: 2022-01-17
2 Technical Data
Accuracy of operating time delay ≤1%×Setting or 20ms (at 2 times current setting)
Accuracy of operating time delay Definite-time: ≤1%×setting or 35ms (at 1.1 times voltage
setting)
Accuracy of operating time delay ≤1%×setting or 35ms (at 1.1 times voltage setting)
Date: 2022-01-17
2 Technical Data
≤5% (SIR≤30)
Transient overreaching
≤10% (SIR≥30)
2.12.1 GOOSE
Max. 64
Receiving Control Block (RCB)
(Typical configuration: 50×FCD+200×BOOL+16×FLOAT)
Max. 16
Sending Control Block (SCB)
(Typical configuration: 100×BOOL)
2.12.2 SV
3 Protection Functions
Table of Contents
Date: 2022-01-17
3 Protection Functions
Date: 2022-01-17
3 Protection Functions
List of Figures
Figure 3.6-2 Operation characteristic of sensitive biased differential element ............... 3-17
Figure 3.6-3 Operation characteristic of conventional biased differential element ......... 3-18
Figure 3.6-5 Operation characteristic of DPFC biased differential protection ................. 3-22
Figure 3.6-7 Logic of inrush current blocking current differential protection.................. 3-27
Figure 3.6-12 Logic diagram of DPFC biased differential element .................................... 3-35
Figure 3.7-1 Application for two-winding transformer with one CB at one side .............. 3-37
3 Figure 3.7-2 Application for two-winding transformer with two CBs at one side ............ 3-38
Figure 3.7-8 Logic of enabling restricted earth fault protection ........................................ 3-45
Figure 3.7-9 Pickup logic of restricted earth fault protection ............................................ 3-45
Figure 3.7-10 Logic diagram of restricted earth fault protection ....................................... 3-46
Figure 3.8-2 Winding differential protection applied to stub differential protection ....... 3-48
Figure 3.9-4 Operation characteristic of sensitive biased differential element ............... 3-64
Figure 3.9-5 Operation characteristic of conventional biased differential element ......... 3-65
Figure 3.9-7 Operation characteristic of DPFC biased differential element ..................... 3-68
Date: 2022-01-17
3 Protection Functions
Figure 3.9-14 Logic diagram of DPFC biased differential element .................................... 3-75
Figure 3.10-1 Wiring diagram of shunt reactors in power system ..................................... 3-77
Figure 3.12-5 Logic of forward and reverse direction element .......................................... 3-96
Figure 3.12-7 Definite-time operating curve of phase overcurrent protection ................. 3-98
Figure 3.12-10 Inverse-time dropout curve of phase overcurrent protection ................ 3-101
Figure 3.13-4 Logic of forward and reverse direction element ........................................ 3-112
Figure 3.13-6 Definite-time operating curve of earth fault protection ............................. 3-114
3 Figure 3.13-7 Inverse-time operating curve of earth fault protection .............................. 3-115
Figure 3.13-8 Definite-time dropout characteristics of earth fault protection ................ 3-116
Figure 3.13-10 Inverse-time dropout characteristics of earth fault protection .............. 3-118
Figure 3.14-4 Logic of forward and reverse direction element ........................................ 3-126
Figure 3.15-2 Logic diagram of enabling thermal overload protection (method 1) ....... 3-141
Figure 3.15-3 Pickup logic of thermal overload protection (method 1) ........................... 3-142
Figure 3.15-4 Logic diagram of thermal overload protection (method 1, phase A) ....... 3-142
Date: 2022-01-17
3 Protection Functions
Figure 3.15-5 Logic diagram of thermal overload protection (method 1) ....................... 3-142
Figure 3.16-2 Logic of breaker failure initiating signal abnormality ................................ 3-147
Figure 3.17-3 Definite-time operating curve of phase overvoltage protection ............... 3-154
Figure 3.17-4 Inverse-time operating curve of phase overvoltage protection ............... 3-155
Figure 3.18-3 Definite-time operating curve of residual overvoltage protection ........... 3-161
Figure 3.19-3 Definite-time operating curve of phase undervoltage protection ............ 3-167
Figure 3.19-4 Inverse-time operating curve of phase undervoltage protection ............. 3-168
Figure 3.22-3 Definite-time operating curve of frequency rate-of-change protection ... 3-182
Figure 3.23-9 Phase-to-ground operating characteristics for forward fault ................... 3-193
Figure 3.23-10 Phase-to-phase operating characteristics for forward fault ................... 3-194
Figure 3.23-15 Zero-sequence mutual inductance for double-circuit lines .................... 3-197
Figure 3.23-17 Faulty phase selection based on I0 and I2A ............................................... 3-201
Figure 3.23-22 Logic of distance protection operating (zone i, i=1~4) ............................ 3-207
Date: 2022-01-17
3 Protection Functions
List of Tables
Table 3.5-1 Input signals of three-phase current summation element ................................ 3-8
Table 3.5-2 Output signals of three-phase current summation element ............................. 3-8
Date: 2022-01-17
3 Protection Functions
In the chapter, the prefix ”x.” in some signals, settings and measurements,
represents some side or bushing of transformer defined by user through
PCS-Studio software, which may be “HVS”, “MVS”, “LVS”, “HVS2”,
“MVS2”, “LVS2”, “CWS”, “HVB”, “MVB”, “LVB”, etc. If only one protection
element is equipped, the prefix “x.” may disappear.
Three-phase current element is responsible for pre-processing three phase currents and
3
calculating sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is used for protection logic calculation.
When three phase currents are engaged in the calculation of transformer differential protection,
restricted earth fault protection or winding differential protection, CT circuit failure supervision of
each protection is carried out in the corresponding protection element, which can refer to
corresponding sections for details.
When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.
TCUR3P
x.in_ia x.I3P
x.in_ib x.Ia_Sec
x.in_ic x.Ib_Sec
x.Ic_Sec
x.I1_Sec
3 x.I2_Sec
x.3I0_Cal_Sec
x.Ang(Ia-Ib)
x.Ang(Ib-Ic)
x.Ang(Ic-Ia)
x.Ang(Ia)
x.Ang(Ib)
x.Ang(Ic)
x.Ang(3I0_Cal)
x.Flg_OnLoad
x.CTS.Alm
Date: 2022-01-17
3 Protection Functions
3.1.4 Settings
3
Table 3.1-3 Settings of three-phase current element
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is used for the protection logic calculation.
VT circuit failure supervision of three-phase voltage is carried out by the special VTS element,
which can refer to Section 3.22 for details.
TVOL3P
x.in_ua x.U3P
x.in_ub x.Ua_Sec
x.in_uc x.Ub_Sec
x.BI_En_VT x.Uc_Sec
x.Uab_Sec
3 x.Ubc_Sec
x.Uca_Sec
x.U1_Sec
x.U2_Sec
x.3U0_Cal_Sec
x.Ang(Ua-Ub)
x.Ang(Ub-Uc)
x.Ang(Uc-Ua)
x.Ang(Ua)
x.Ang(Ub)
x.Ang(Uc)
x.Ang(3U0_Cal)
x.Ang(U1)
x.Ang(U2)
x.VTS.Alm
Date: 2022-01-17
3 Protection Functions
3.2.4 Settings
Table 3.2-3 Settings of three-phase voltage element
TCUR1P
x.in_ip x.I1P
x.3I0_Ext_Sec
x.Ang(3I0_Ext)
x.Flg_OnLoad
3
3.3.3 I/O Signals
Table 3.3-1 Input signals of single-phase current element
3.3.4 Settings
Table 3.3-3 Settings of single-phase current element
Date: 2022-01-17
3 Protection Functions
TVOL1P
x.in_up x.U1P
x.U_Sec
x.Ang(U)
3
3.4.3 I/O Signals
Table 3.4-1 Input signals of single-phase voltage element
3.4.4 Settings
Table 3.4-3 Settings of single-phase voltage element
Three-phase current summation element is responsible for calculating the sum of multiple current
inputs in one side of transformer. All calculated information of three-phase current summation
element is used for the protection logic calculation.
Three-phase current summation element is used to calculate the sum of several groups of
currents.
When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.
TCUR3P_3SD
x.in_i3p1 x.I3P
x.in_i3p2 x.Ia_Sec
3 x.in_i3p3 x.Ib_Sec
x.Ic_Sec
x.I1_Sec
x.I2_Sec
x.3I0_Cal_Sec
x.Ang(Ia-Ib)
x.Ang(Ib-Ic)
x.Ang(Ic-Ia)
x.Ang(Ia)
x.Ang(Ib)
x.Ang(Ic)
x.Ang(3I0_Cal)
x.Flg_OnLoad
Date: 2022-01-17
3 Protection Functions
In power system, the power transformer is one of most valuable and expensive equipment. If a
fault occurs in the protection zone of a transformer, current differential protection operates quickly
to clear the fault to avoid the transformer from damages or reduce the maintenance cost as low as
possible.
The fault detector can initiate biased differential element, and its operation equation is as follows.
Where:
The fault detector can initiate instantaneous differential element, and its operation equation is as
follows.
Where:
Where:
∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and hence the
element maintains stability.
∆𝐼1̇ , ∆𝐼2̇ , …, ∆𝐼𝑚̇ are DPFC current of each side of transformer representatively.
Regardless of direction of power flow and very sensitive, this fault detector is used to guard DPFC
biased differential protection. The setting is fixed in factory and thus site setting is not required.
During the normal operation, the magnitudes of secondary current of each side of transformer are
different due to the mismatch between the CT ratios and the power transformer ratio. The current
value difference between each side shall be eliminated before calculation for current differential
protection by amplitude compensation.
Sn
I1bBrm Equation 3.6-4
3U1nBrm
Where:
Date: 2022-01-17
3 Protection Functions
U1nBrm is rated primary voltage of side m (i.e., the settings [HVS.U1n_Plate], [MVS.U1n_Plate] or
[LVS.U1n_Plate]).
I 1bBrm
I 2bBrm Equation 3.6-5
CTBrm
Where:
For all differential protections, the secondary currents of each side must follow below criterion.
I 2bBr1 I 2bBr2 I
Max( , ,..., 2bBrm )
I 2nBr1 I 2nBr2 I 2nBrm
128 Equation 3.6-6
I 2bBr1 I 2bBr2 I 2bBrm
Min( , ,..., )
I 2nBr1 I 2nBr2 I 2nBrm
When selecting CT, the ratio between maximum value and minimum value
should be considered. It is recommended that the ratio is smaller than 16.
Theoretically, the ratio is preferred to be as small as it can be.
For DPFC biased differential element, the secondary currents of each side must follow Equation
3.6-7 in addition to Equation 3.6-6. Otherwise, alarm signals [ProtBrd.Fail_Settings] and
[FDBrd.Fail_Settings] are issued and the device will be blocked at the same time unless DPFC
biased differential element is disabled.
I 2bBr1 I 2bBr2 I
Max( , ,..., 2bBrm ) 0.4
I 2nBr1 I 2nBr2 I 2nBrm
Equation 3.6-7
I I I
Min( 2bBr1 , 2bBr2 ,..., 2bBrm ) 0.1
I 2nBr1 I 2nBr2 I 2nBrm
Where:
same time.
3 False differential current is caused by phase shift between the power transformer primary current
and secondary current for delta/wye, so phases of each side secondary current must be
compensated by this phase compensation. Δ→Y and Y→Δ transfer methods by settings can be
selected to adjust phase angle of secondary current on each side of the transformer, and Δ→Y
transfer method is recommended. Zero-sequence current is always eliminated both at Y and Δ
windings by adopting Δ→Y method.
The wiring connection of HV, MV and LV sides may be different, so it is needed to compensate
phase of each side current of transformer for calculation of current differential protection. There
are two transforming methods for phase compensation: Δ→Y and Y→Δ, and different
transforming methods will result in the difference.
2. [Clk_PhComp]: the target o'clock each side current will be shifted to for phase compensation.
For example:
The vector group of a transformer is Y0/Δ11 and the target o'clock ([Clk_PhComp]) is set to LV
side. Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.
1. For HV side, with reference to the set target o'clock, the o'clock of HV side is 1 (i.e. wiring
o'clock 12-target o'clock 11) clock, so the matrix of relative o'clock 1 is adopted to
Date: 2022-01-17
3 Protection Functions
2. For LV side, with reference to the set target o'clock, the o'clock of LV side is 0 (i.e. wiring
o'clock 11- target o'clock 11), so the matrix of relative o'clock 0 is adopted to compensate LV
side current.
If an earthing transformer is connected outside the protection zone of differential protection, the
setting [HVS.En_I0Elim] (or [LVS.En_I0Elim]) could be disabled, i.e. set to 0.
If an earthing transformer is connected within the protection zone of differential protection, then
zero-sequence current must be eliminated and otherwise differential protection may operate
unexpectedly during an external fault. Therefore the setting [HVS.En_I0Elim] (or [LVS.En_I0Elim])
must be enabled, i.e., set to 1. 3
Table 3.6-1 Matrix of phase compensation
1 0 0 2 - 1 - 1
0 0 1 0 1
- 1 2 - 1
(No phase shit) 3
0 0 1 - 1 - 1 2
1 -1 0 1 -1 0
1
0 1 - 1
1
0 1 - 1
1
(Shift 30°leading) 3 3
- 1 0 1 - 1 0 1
0 -1 0 1 -2 1
2 0 0 - 1 1
1 1 - 2
(shift 60°leading) 3
- 1 0 0 - 2 1 1
0 -1 1 0 -1 1
1
1 0 - 1
1
1 0 - 1
3
(Shit 90°leading) 3 3
- 1 1 0 - 1 1 0
0 0 1 - 1 - 1 2
4 1 0 0 1
2 - 1 - 1
(Shit 120°leading) 3
0 1 0 - 1 2 - 1
- 1 0 1 - 1 0 1
1
1 - 1 0
1
1 - 1 0
5
(Shift 150°leading) 3 3
0 1 - 1 0 1 - 1
- 1 0 0 - 2 1 1
6 0 -1 0 1
1 - 2 1
(Shift 180°leading) 3
0 0 - 1 1 1 - 2
- 1 1 0 - 1 1 0
1
0 - 1 1
1
0 - 1 1
7
(Shift 150°lagging) 3 3
1 0 - 1 1 0 - 1
0 1 0 - 1 2 - 1
8 0 0 1 1
- 1 - 1 2
(Shift 120°lagging) 3
1 0 0 2 - 1 - 1
3 1
0 1 - 1 0 1 - 1
- 1 0 1
1
- 1 0 1
S9
(Shift 90°lagging) 3 3
1 - 1 0 1 - 1 0
0 0 - 1 1 1 - 2
10 - 1 0 0 1
- 2 1 1
(Shift 60°lagging) 3
0 - 1 0 1 - 2 1
1 0 - 1 1 0 - 1
1
- 1 1 0
1
- 1 1 0
11
(Shift 30°lagging) 3 3
0 - 1 1 0 - 1 1
Date: 2022-01-17
3 Protection Functions
1
I rA 2 I A1 I A2 I A3 I A4 I A5 I A6
I rB
1
I B1 I B 2 I B 3 I B 4 I B 5 I B 6 Equation 3.6-10
2
1
I rC 2 I C1 I C 2 I C 3 I C 4 I C 5 I C 6
Where:
IAm, IBm, ICm are the secondary current of branch m (m=1, 2, 3, 4, 5, 6).
I'Am, I'Bm, I'Cm are corrected secondary current of branch m (m=1, 2, 3, 4, 5, 6).
M1, M2, M3, M4, M5, M6 are matrixes of phase shifting of each branch of transformer respectively.
Its value is decided according to the vector group of transformer and please refers to “section
3.6.1.2” for details.
I2bBr1, I2bBr2, I2bBr3, I2bBr4, I2bBr5, I2bBr6 are rated secondary values of each branch of transformer
respectively.
Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current (i.e.,
Id=I'_H+I'_L) should be zero during the normal operation of the transformer or an external fault
occurring.
*
*
*
I'_H I'_L
PCS-978S
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)
I''_H I''_L
Where:
“I''_H” and “I''_L” are secondary corrected currents of HV and LV sides respectively.
M1 and M2 are matrixes of phase shifting and zero-sequence current elimination of HV and LV
sides respectively.
I2bBr1 and I2bBr2 are rated secondary currents at HV and LV sides respectively.
The symbol “*” represents the polarity of CT. If current flowing into the
polarity of CT, the current direction is defined as forward direction.
To clarify the situation, three important operation conditions with ideal and matched measurement
I'_H flows into the protected zone, I'_L leaves the protected zone, according to the definition of
signs in above figure, therefore I'_H=–I'_L.
Moreover |I'_H|=|I'_L|
Id=|I'_H+I'_L|=|I'_H-I'_H|=0
Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|
Differential current (Id) is far less than restraint current (Ir), and current differential protection
does not operate.
Id=|I'_H+I'_L|=|I'_H+I'_H|=2|I'_H|
Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|
Differential current (Id) is two times of restraint current (Ir), and current differential protection
operates.
Id=|I'_H+I'_L|=|I'_H+0|=|I'_H|
Ir=(|I'_H |+|I'_L|)/2=(|I'_H|+|0|)/2=|I'_H|/2
Differential current (Id) are two times of restraint current (Ir), and current differential protection
operates.
The currents for following calculation are the products of the actual secondary current of each side
Date: 2022-01-17
3 Protection Functions
multiplying its own correction coefficient. The sensitive biased differential element with low pickup
setting and restraint slope is much more sensitive for a slight internal fault. Four blocking elements,
CT saturation, inrush current, overexcitation and CT circuit failure (optional) have also been
included for the protection in order to prevent it from the unwanted operation during an external
fault.
𝑚 Equation 3.6-11
3
𝐼𝑑 = |∑ 𝐼𝑖̇ |
𝑖=1
𝑚
1
𝐼𝑟 = ∑|𝐼𝑖̇ |
2
𝑖=1
Where:
𝐼𝑑 and 𝐼𝑟 are respectively the differential current and the restraint current.
K=2
[87T.I_Inst]
t
en
m
le
le
6 tia
0. r en
K= ffe
di
d
a se
bi
[87T.Slope1] e [87T.Slope3]
tiv
si
s en
of
ea
ar
n
io
at
er
op
1.2
[87T.Slope2]
Conventional biased differential element with higher setting and restraint coefficient comparing
with sensitive biased differential element is blocked only by an inrush current detection.
Conventional biased differential element provides faster operation for severe internal faults. Its
operation criterion is:
3 Conventional biased differential element can eliminate the influence of CT saturation during an
external fault and ensures reliable operation even if CT is saturated during an internal fault by
means of its biased characteristic.
The slop of conventional biased differential element takes the higher one
between “0.6” and “[87T.Slope3]-0.15”, and the knee point is fixed in
program.
K=2
[87T.I_Inst]
K=max(0.6, [87T.Slope3]-0.15)
1.2
Restraint current
0.8
When the transformer capacity is too small or the CT ratio is too large, the
rated currents will be very small. So, in order to ensuring the reliability, the
Date: 2022-01-17
3 Protection Functions
Instantaneous differential element for transformer is to accelerate the operation speed for
transformer's internal fault. The element has no blocking element but to guard that the setting
must be greater than the maximum inrush current. Instantaneous differential element shall
operate to clear the fault when any phase differential current is higher than its setting. Its
operation criterion is:
3
Id>[87T.I_Inst] Equation 3.6-13
Where:
[87T.I_Inst]
of d
ea se
ar bia ent K=0.6
[87T.Slope1] n
io al m
at n ele e
er ntio ial tiv
p
o ve nt n si ent
n re se em
co iffe of l el [87T.Slope3]
d ea ia
ar ent
n r
tio ffe
e ra d di
E C op ase
bi
D
1.2
[87T.Slope2]
[87T.I_Biased]
0.8 B Restraint current
A [87T.I_Knee2]
[87T.I_Knee1]
The characteristic of internal faults is a straight line with the slope 2 (63.4°) in the operation
diagram (dash-dotted line K=2)
1. Sensitive biased differential element will send tripping signal monitored by CT saturation,
overexcitation, inrush current and CT circuit failure (optional). It can ensure sensitivity and
avoid the unwanted operation when CT is saturated during an external fault. Its operation
area is the tint shadow area in the figure above.
When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the tripping area of sensitive biased differential protection.
When an external fault occurs, the short-circuit current rise strongly, causing a
correspondingly high restraint current (2 times through-flowing current) with little differential
current. After CT reaches saturation (point B), a differential quantity is produced and the
3 restraint quantity is reduced. In consequence, the operating point may moves into the tripping
area of sensitive biased differential protection. Because CT saturation criterion is equipped,
sensitive biased differential protection will not maloperate even the fault point moves into the
operation area.
2. Conventional biased differential element will send tripping signal monitored by inrush current
only. It eliminates the influence of transient and steady saturations of CT during an external
fault and ensures reliable operation even if CT is in saturation condition during an internal
fault by means of its biased characteristic. Its operation area is the deeper shadow area in the
figure above.
When an internal fault occurs, differential current rises greatly and the operating point moves
to E in the tripping area of conventional biased differential protection. (Only the second
harmonic criterion is adapted to distinguishing inrush current for blocking conventional biased
differential protection.)
3. Unrestrained instantaneous differential protection element will send tripping signal without
any blocking if differential current of any phase reaches its setting. Its operation area is over
the above two areas with the deepest dark shadow.
When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.
DPFC biased differential protection is regardless of the load current and is sensitive to small
internal fault current within the transformer. Its performance against current transformer saturation
is also good. DPFC (Deviation of Power Frequency Component) is the power frequency
component of fault component, which is the differential value between the sampling value at this
time point and that at a cycle before.
DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to slight inter-turn fault is maintained during normal operation of transformer. The sensitivity
of transformer differential protection is improved greatly when DPFC biased differential element is
enabled, especially in the situation inter-turn fault during heavy load operation.
Date: 2022-01-17
3 Protection Functions
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
3
0 20 40 60 80 100 120
DPFC current
ΔI=I(K)-I(K-24)
I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.
From above figures, it is concluded that DPFC can reflect the sudden change of fault current at
the initial stage of a fault and has a perfect performance of fault detection. DPFC biased
differential protection reflects variation of load condition to perform a sensitive protection for the
transformer. Lab tests show that it is more sensitive than the biased differential element under the
heavy load condition. DPFC restraint current and differential current are phase-segregated. DPFC
biased differential element can be blocked by inrush current, overexcitation and CT circuit failure.
The operation criterion is as follows:
∆𝐼𝑑 > 0.75 × ∆𝐼𝑟 − 0.3𝑝. 𝑢. (∆𝐼𝑟 > 2𝑝. 𝑢. ) Equation 3.6-14
𝑚 𝑚 𝑚
Where:
∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and hence the
element maintains stability.
∆𝐼𝑑 and ∆𝐼𝑟 are DPFC differential current and DPFC restraint current respectively.
K=m
K=0.75
1.2p.u.
K=0.6
0.2p.u.
Restraint current
0.333p.u. 2p.u.
The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.
DPFC biased differential element can detect a slight inter-turn fault of transformer more
sensitively than biased current differential element. During a slight inter-turn fault, fault current will
flow through transformer whether transformer is fed from one side or from both sides. Therefore,
following two typical situations (an external fault and a slight inter-turn fault) are given to show
differential and restraint current calculation.
During normal operation, Ia_HVS=1A∠0°, Ib_LVS=1A∠180°
Id=|I'a_HVS+I'b_LVS|
=|1.3A∠0°+1.1A∠180°|=0.2A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)
Date: 2022-01-17
3 Protection Functions
=0.5x(|1.3A∠0°|+|1.1A∠180°|)=1.2A
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|
=|(1.3A∠0°-1A∠0°)+(1.1A∠180°-1A∠180°)|=0.2A
ΔIr=max(|I'a_HVS-Ia_HVS|,|I'b_LVS-Ib_LVS|)
=max(|1.3A∠0°-1A∠0°|,|1.1A∠180°-1A∠180°|)=0.3A
Conclusion: DPFC biased differential element is more sensitive than biased differential
element during an internal fault.
3
2. An external fault: I'a_HVS=2A∠0°, I'b_LVS=2A∠180°, other phase are supposed as zero
Id=|I'a_HVS+I'b_LVS|
=|2A∠0°+2A∠180°|=0A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)
=0.5x(|2A∠0°|+|2A∠180°|)=2A
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|
=|(2A∠0°-1A∠0°)+(2A∠180°-1A∠180°)|=0A
ΔIr=max(|I'a_HVS-Ia_HVS|, |I'b-_LVS-Ib_LVS|)
=max(|2A∠0°-1A∠0°|,|2A∠180°-1A∠180°|)=1A
Conclusion: DPFC biased differential element does not operate during an external fault.
The device provides optional inrush current distinguished principles: harmonic principle (second
harmonic and third harmonic) and waveform symmetry principle. The logic setting
[87T.Opt_Inrush_Ident] is used to select distinguished principle, second harmonic principle or
waveform symmetry principle. The discrimination of inrush current by third harmonics is
independent criterion, and is not controlled by the setting [87T.Opt_Inrush_Ident]. When an
internal fault occurs and CT goes to stable saturation, there are great third harmonic component in
CT secondary current. Because sensitive biased differential element has too high sensitivity, the
third harmonic criterion is only used to block sensitive biased differential element to prevent it from
maloperation when both [87T.Opt_Inrush_Ident] and [87T.En_Hm3_Blk] are set as “1”.
The second and third harmonics of differential current can be used to distinguish inrush current.
Its criteria are:
Where:
𝐼𝑑_2𝑛𝑑 and 𝐼𝑑_3𝑟𝑑 are the second and third harmonics of phase differential current respectively.
The differential current is basically the fundamental sinusoidal wave during a fault. When the
transformer is energized, plentiful harmonics will appear, and the waveform will be distorted,
interrupted and unsymmetrical. Wave symmetry principle is used to distinguish inrush current.
CT saturation characteristics make waveform unsymmetrical between the first half cycle and the
second half cycle. During internal faults, current waveform is sinusoidal wave, so two half cycles
of wave are almost symmetrical after a periodic component is eliminated (calculate the differential
of differential current in fact).
As shown in Figure 3.6-6, arc ABC is a cycle of typical waveform of differential current with a
periodic component. Flip the arc BC of second half cycle vertically to get the arc B'C', and then
move it forward half cycle to get the arc B''C''. The degree of symmetry of current wave is shown
as
S
K sym Equation 3.6-16
S
Where:
X: arc AB
Y: arc B''C''
Date: 2022-01-17
3 Protection Functions
Both waveform symmetry principle and second harmonic principle are based on current distortion
due to inrush current, and the only difference is the mathematical method. The second harmonic
principle is to calculate the percentage of second harmonic in differential current, but the
waveform symmetry principle is to calculate the percentage of even harmonic to total differential
current.
There are three optional blocking modes for inrush current, self-adaptive one-phase inrush
blocking one-phase differential element mode (self-adaptive 1Pblk1P mode), two-phase inrush
blocking three-phase differential element mode (2PBlk3P mode) and one-phase inrush blocking
three-phase differential element mode (1Pblk3P mode), by the logic setting
[87T.Opt_BlkMode_Inrush]. Self-adaptive blocking mode can enhance ability of differential
protection to avoid maloperation during transformer energization effectively and ensure high
speed of differential protection for faults under normal operation. The self-adaptive blocking mode
is recommended to be selected in the actual application.
The device has an energizing detection element by current criterion (without additional
breaker position signal) to check whether the transformer is in the process of energization.
Once the transformer in the process of energization is detected, the following criterions are
adopted to improve the stability to avoid mal-operation caused by inrush current.
Criterion 1
waveform characteristics, the device automatically increases those values which shall be
not greater than corresponding values of settings. This feature ensures biased
differential element fast operation for transformer energized on to a fault in addition to the
inrush current blocking.
Criterion 2
3 Criterion 3
If the second harmonic percent of differential current used as auxiliary criteria continues
to rise, then biased differential element is kept being blocked.
When the inrush current is detected in any two-phase current, three-phase current differential
protection will be blocked.
When the inrush current is detected in any phase current, three-phase current differential
protection will be blocked.
It is supposed that three differential currents are Ida, Idb, and Idc.
Date: 2022-01-17
3 Protection Functions
For mode 1 in case 3, when blocking criterion 1, 2 and 3 of inrush current discrimination are all
released to differential element, differential element can operate. Otherwise, differential element
will be blocked if any of three blocking criterions blocks.
Case 4 is usually an internal fault, and blocking mode 2 can ensure differential protection operate
correctly if there is an internal fault in case 4. Case 3 may be an internal fault or inrush current,
and blocking mode 1 can distinguish through its perfect criteria, hence, it is recommended to use
blocking mode 1.
The following figure shows the logic of inrush current blocking differential protection.
3
SET [87T.Opt_BlkMode_Inrush=0]
&
SIG No Inrush (Phase C)
&
>=1
&
SET [87T.Opt_BlkMode_Inrush=2]
SET [87T.Opt_BlkMode_Inrush=1]
>=1
>=1
SIG Transformer energization 100ms 0ms &
SET [87T.Opt_BlkMode_Inrush=0]
Where:
“Flag_NoInrush_Harm” is the internal signal that means no inrush current is detected by the
harmonic principle.
“Flag_NoInrush_Wave” is the internal signal that means no inrush current is detected by the
waveform symmetry principle.
“Flg_NoInrush_Hm3” is the internal signal that means no inrush current is detected by the third
harmonic principle.
There are two kinds of CT saturation, i.e. transient CT saturation and stable CT saturation. If an
3 external fault or an internal fault occurs, CT primary current increases greatly and CT secondary
current consists of fundamental component, DC component and harmonic component. The
decaying DC component results in remanent magnetism in magnetic core, and with the
accumulation of remnant magnetism, CT goes into saturation state which is called transient CT
saturation. With the time passed, the DC component decays to zero almost and CT is still
saturated caused by AC excitation, which is called stable CT saturation.
According to tests in lab, it is found that the second harmonic component is greater than the third
harmonic component at the stage of CT transient saturation and the third harmonic is greater than
the secondary harmonic at the stage of CT stable saturation. Therefore, the second and third
harmonics both can be used to detect CT saturation.
or Equation 3.6-17
Where:
𝐼∅_1𝑠𝑡 is the fundamental component of one phase current, it won’t do CT saturation detection
unless the fundamental component is higher than the corresponding internal setting.
𝐾2𝑛𝑑 and 𝐾3𝑟𝑑 are fixed coefficients of secondary and third harmonics respectively.
If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and biased differential element will be blocked.
Date: 2022-01-17
3 Protection Functions
Internal faults can be distinguished from external faults by differential protection through the
asynchronous method of differential and restraint, and if it is judged as internal fault by this
method, the CT saturation blocking element will not be enabled. Meanwhile, when some-side
measured current is relatively small, the CT saturation criterion of this side will exit automatically.
It is needed that the saturation free time of CT is no less than 4ms to ensure differential protection
operate correctly with the added CT saturation criterion.
When a transformer is overexcited, the exciting current will increase sharply which may result in
an unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. The third or fifth harmonic of differential current can 3
be selected to determinate overexcitation.
Where:
𝑈∗
n= ⁄𝑓 Equation 3.6-19
∗
Where:
The base value for calculating per unit value of voltage is rated secondary voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.
If overexcitation factor is less than 1.4, biased differential element is blocked when the constant of
fifth or third harmonics is greater than [87T.K_Hm3/Hm5_OvExc] and this condition is judged as
overexcitation condition without damages to transformer. If overexcitation factor is greater than
1.4, biased differential element is no longer being blocked by overexcitation because transformer
is damaged in this situation.
1. CT circuit abnormality
If the following operation formula is met for 10s, the differential current abnormality alarm
[87T.Alm_Diff] will be issued, but this alarm will not block the protection 87T.
2. CT circuit failure
The following two cases are considered as CT circuit failure, and the device can discriminate
at which side CT circuit is faulty by unbalanced currents. Differential CT secondary circuit
failure can be judged more accurately and reliably by adopting combined method of voltage
and current.
First case, if none of following four conditions is satisfied after the fault detector of biased
differential current, or biased residual differential current, or biased winding differential
3 current picks up, it will be judged as CT circuit failure and the alarm will be issued.
2) Any phase current at any side increases after fault detector picks up.
3) The maximum phase current is greater than 1.1p.u. after the fault detector picks up.
The alarm of CT circuit failure can be settable to block transformer differential protection,
reactor differential protection, restricted earth-fault protection and winding differential
protection. The alarm of CT circuit failure is latched once issued, it can be reset automatically
after the failure is cleared (under the condition that the setting [En_AutoRecov_Alm_CTS] is
set to be “Enabled”), or it can be reset manually when the setting [En_AutoRecov_Alm_CTS]
is set to be “Disabled”.
Transformer's sensitive biased differential element will be blocked during CT circuit failure
when the logic setting [87T.En_CTS_Blk] set as “1”.
Biased restricted earth-fault element will be blocked during CT circuit failure when the
logic setting [64REF.En_CTS_Blk] is set as “1”.
Biased winding differential protection will be blocked during CT circuit failure when the
logic setting [87W.En_CTS_Blk] is set as “1”.
Date: 2022-01-17
3 Protection Functions
87T
87T.in_I3P1 87T.Ida
3
87T.in_I3P2 87T.Idb
87T.in_I3P3 87T.Idc
87T.in_I3P4 .
87T.in_I3P5 .
87T.in_I3P6 .
87T.Enable 87T.St_DPFC_C
87T.Block 87T.Flg_Inrush
Date: 2022-01-17
3 Protection Functions
EN [87T.En_Inst] &
87T.On_Inst
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_Inst
SIG Fail_Device
&
87T.Valid_Inst
EN [87T.En_Biased] &
87T.On_Biased
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_Biased
SIG Fail_Device
&
87T.Valid_Biased
EN [87T.En_DPFC] &
87T.On_DPFC
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_DPFC
SIG Fail_Device
&
87T.Valid_DPFC
3
Figure 3.6-9 Pickup logic of transformer differential protection
SIG 87T.Pkp_Biased
>=1
SIG Sensitive 87T & 87T.Op_Biased
SIG U*/f*>1.4
SIG 87T.Pkp_Biased
Date: 2022-01-17
3 Protection Functions
SIG U*/f*>1.4
SIG 87T.Pkp_DPFC
SIG 87T.Pkp_Inst
>=1
SIG 87T.Pkp_Biased
SIG 87T.Pkp_DPFC
T 0ms 87T.Alm_CTS
Where:
“T” is an internal time delay parameter, and it is floating and not open for user’s configuration.
3.6.5 Settings
Table 3.6-5 Settings of transformer differential protection
Date: 2022-01-17
3 Protection Functions
Restricted earth fault protection (REF) is meant to protect a single winding of a power transformer,
and the protected winding must be earthed. In the case of delta windings, the winding must be 3
earthed by an earthing transformer, which must be electrically placed between the winding and
the current transformers. REF can be applied to protection of two-winding transformer,
three-winding transformer, auto-transformer and shut reactor.
REF is a kind of differential protection, so it calculates differential current and restrained current.
The differential current is a vector difference of the neutral current (i.e., current flowing in the
neutral conductor) and the residual current from the lines. For internal faults, this difference is
equal to the total earth fault current. REF operates on the fault current only, and is not dependent
on eventual load currents. This makes REF a very sensitive protection.
3.7.1.1 Overview
The difference between current differential protection and REF is that the first one is based on
adjusted phase current balance and the latter is based on balance of calculated residual current
and residual current from neutral CT.
Each side of transformer can be equipped with one set of REF, i.e., for a three-winding
transformer, up to three groups of REF can be equipped. REF is not affected by inrush current
and the tap of transformer. CT transient detection function based on the ratio of residual current to
positive current is adopted to eliminate the influence of difference of transient characteristic to
REF.
*
3I0Cal '_H
Magnitude compensation
Figure 3.7-1 Application for two-winding transformer with one CB at one side
HV side 1
* * *
I_H1
LV side
I_H2
3I0Cal'_H1 * * *
3I0Cal'_H2
HV side 2
Magnitude
compensation
REF at HV side
Magnitude
compensation
3 Magnitude
I_HNP
compensation *
I'_HNP
Figure 3.7-2 Application for two-winding transformer with two CBs at one side
HV side
* * *
I_H
3I0Cal'_H I_M
*
MV side CW side
*
*
3I0Cal'_M
I_CW
Magnitude
LV side
compensation *
REF at HV side
Magnitude
compensation
I'_CW
Magnitude
compensation
The protection function can be provided with up to 4 sets of three-phase current inputs and 1
neutral point current input, and in auto-transformer applications, it can be provided with up to 2
sets of three phases current inputs for high voltage and middle voltage sides respectively.
Before some side REF is put into service on site, polarity of neutral point
CT must have been checked by a primary current injection test. Otherwise
an undesired operation may occur during an external earth fault.
Date: 2022-01-17
3 Protection Functions
Where:
If CTs used for REF have different primary rated values, the device will automatically adjust the
currents with respective correction ratio shown as below.
Klph
I1n
Klb / I 2 n and K lb min(
I1n _ max
,4) Equation 3.7-2
3
I1n _ max I1n _ min
Where:
I1n_min is minimum primary rated value among all CTs for REF.
I1n_max is maximum primary rated value among all CTs for REF.
This calculation method is to take the minimum CT primary rated value of all calculated sides as
the reference side. If the multiple of maximum CT primary rated value to minimum CT primary
rated value is greater than 4, then reference side shall be taken as 4 and other sides shall be
calculated proportionally. Otherwise, the reference side shall be taken as 1, and other sides will be
calculated proportionally.
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (K1ph).
When selecting CT, the primary currents for each side muse follow the
I1n _ max
criterion: 128 , it is recommended that the ratio is smaller than 16.
I1n _ min
Theoretically, the ratio is preferred to be as small as it can be.
3𝐼0𝑑 = 𝐾𝑙𝑝ℎ1 × 3𝐼01 + 𝐾𝑙𝑝ℎ2 × 3𝐼02 + 𝐾𝑙𝑝ℎ3 × 3𝐼03 + 𝐾𝑙𝑝ℎ4 × 3𝐼04 + 𝐾𝑙𝑝ℎ𝑁𝑃 × 𝐼𝑁𝑃
Where:
3I01, 3I02, 3I03, 3I04 are secondary values of calculated residual current at each side.
3I'01, 3I'02, 3I'03, 3I'04 are secondary values of corrected calculated residual current at each side.
K1ph1, K1ph2, K1ph3, K1ph4 are corrected coefficients of amplitude compensation at each side.
Where:
Ia
*
A
Ib
*
B
Ic
*
I_NP
*
3I0Cal' =I'c+I'b+I'a
I'_NP REF
I'_NP flows into the protected zone from ground, 3I0Cal' leaves the protected zone, i.e. I'_NP
is negative according to the definition of signs in above figure, therefore I'_NP= -3I0Cal'.
It indicates there is no differential current in the case, and the restraint current corresponds to
the through-flowing current, hence, REF does not operate.
2. Internal short-circuit:
Date: 2022-01-17
3 Protection Functions
It indicates the differential current are two times of restraint current in internal short-fault,
hence, REF operates.
3𝐼0𝑑 > [𝑥. 64𝑅𝐸𝐹. 𝑆𝑙𝑜𝑝𝑒] × (3𝐼0𝑟 − [𝑥. 64𝑅𝐸𝐹. 𝐼_𝐾𝑛𝑒𝑒]) + [𝑥. 64𝑅𝐸𝐹. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑]
3
Equation 3.7-5
3𝐼0𝑑 = |3𝐼 ̇01 + 3𝐼 ̇02 + 3𝐼 ̇03 + 3𝐼 ̇04 + 𝐼 ̇NP|
3𝐼0𝑟 = Max(|3𝐼̇ 01|, |3𝐼 ̇02|, |3𝐼 ̇03|, |3𝐼 ̇04|, |𝐼 ̇NP|)
Where:
3𝐼0𝑑 and 3𝐼0𝑟 are respectively the differential current and the restraint current at side x of
transformer.
3𝐼̇ 01, 3𝐼̇ 02, 3𝐼 ̇03 and 3𝐼 ̇04 are the calculated residual currents at side x of transformer.
K=m
[x.64REF.Slope]
[x.64REF.I_Biased]
Restraint current
[x.64REF.I_Knee]
The value of m is defined by the branch number for REF calculation. For example, there are two
branches at HV side (wye winding with neutral point earthed), so there are three branches
In order to ensure the selectivity of restricted earth fault protection, direction criterion is also
available. The setting [x.64REF.En_Dir_Blk] is used to enable/disable the function of direction
criterion blocking REF. The direction criterion is based on the different direction characteristic of
neutral-point current I_NP and calculated residual current 3I0Cal at an external earth fault and an
internal earth fault.
For an external earth fault, the neutral-point current I_NP and the calculated residual current
3 3I0Cal have equal magnitude, but they are of approximately opposite directions.
3I0Cal
ROA (Relay Operate Angle)
I_NP
ROA
For an internal earth fault, the magnitudes of the two currents I_NP and 3I0Cal may be different,
but their relative directions are within a certain angle range. The operation angle setting
[x.64REF.ROA] is equipped in the device, it will be judged as an internal earth fault and the
direction criterion will be released when the relative angle of the two currents is lower than the
setting.
ROA
3I0Cal
I_NP
ROA
Or when I_NP>K×3I0Cal (K is an internal setting), it will also be judged as an internal earth fault
and the direction criterion will be released.
Date: 2022-01-17
3 Protection Functions
Non-identical CT characteristics can cause unbalance current. During phase-to-phase faults and
three-phase faults, the unbalance of three-phase CTs results in residual current which may lead to
maloperation of REF. Therefore, positive-sequence current restraint blocking criterion is adopted
to prevent REF from maloperation in above mentioned conditions.
When the residual current of REF at each side is greater than 0 times positive-sequence current,
it is decided that zero-sequence current is caused by a fault and release REF. Positive-sequence
current restraint blocking criterion is showed below. This blocking criterion is ignored when neutral
point current is greater than the internal setting, whichever is greater.
3
3I0>β0×I1 Equation 3.7-6
Where:
CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid maloperation
of REF during an external fault. Please refer to Section 3.6.1.10 for details.
The criterions of CT saturation detection in 64REF are as shown in Equation 3.7-7. If any one of
the criterions is met, it will be considered that it is CT saturation to cause this differential current
and restricted earth fault protection will be blocked.
Where:
𝐼∅_1𝑠𝑡 is the fundamental component of one phase current, it won’t do CT saturation detection
unless the fundamental component is higher than the corresponding internal setting.
𝐾2𝑛𝑑 and 𝐾3𝑟𝑑 are fixed coefficients of secondary and third harmonics respectively.
CT circuit supervision for REF is divided into two kinds: differential CT circuit abnormality without
the pickup of the fault detector and differential CT circuit failure with the pickup of the fault
detector.
3 CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of REF will be issued
without blocking the protection.
CT Circuit Failure
64REF
x.64REF.in_I3P1 x.64REF.3I0d
x.64REF.in_I3P2 x.64REF.3I0r
x.64REF.in_I3P3 x.64REF.I0_Th
x.64REF.in_I3P4 x.64REF.St
x.64REF.in_I1P x.64REF.Op
x.64REF.Enable x.64REF.On
x.64REF.Block x.64REF.Blocked
x.64REF.Valid
x.64REF.Alm_Diff
x.64REF.Alm_CTS
Date: 2022-01-17
3 Protection Functions
3.7.4 Logic
EN [x.64REF.En] &
x.64REF.On
SIG x.64REF.Enable
&
SIG x.64REF.Block >=1 x.64REF.Blocked
SIG Fail_Device
&
x.64REF.Valid
SIG 3I0>β0×I1
&
SIG CT saturation
EN [x.64REF.En_CTS_Blk] x.64REF.St
EN x.64REF.En_Dir_Blk
SIG x.64REF.Pkp
Where:
3.7.5 Settings
Table 3.7-3 Settings of restricted earth fault protection
Date: 2022-01-17
3 Protection Functions
The winding differential protection can be used in auto-transformer when each side and common
winding are equipped with three phases current inputs. Winding differential protection is based on
Kirchhoff's law, so inrush current has no effect on it. Winding differential protection consists of
phase winding differential protection and residual winding differential protection. Residual winding 3
differential protection adopts the calculated residual current of each side and common winding for
the protection calculation and three phases CT polarity is easy to be checked. The operation
principle of which is similar to that of REF, but compared to REF, winding differential protection
can operate not only during internal earth faults but also during phase-to-phase faults. The
protection can be provided with up to 5 sets of three phases current inputs.
3.8.1.1 Overview
Winding differential protection is based on Kirchhoff's first law and calculates differential currents
of electrical connection circuits including phase A, phase B phase C and residual differential
currents. Inrush current and tap change of the transformer have no effect on winding differential
protection. Winding differential protection has high sensitivity to internal earth faults because there
is no load current in the restraint current. Normally, winding differential protection is applied in
following two situations.
HV side
* * *
I_H
I_M
I'_H
*
MV side
*
CW side
*
I'_M
I_CW
Magnitude
LV side
compensation Winding
* * *
differential
Magnitude protection
compensation
Magnitude I'_CW
compensation
HV side 1
* * * I_Bush
*
I_H1
LV side
*
HV side
*
I_H2
* * *
I'_H1
I'_H2 HV side 2
Magnitude
compensation Winding differential
protection
Magnitude
3 compensation
Magnitude
compensation
I'_HBush
Where:
Where:
If CTs used by winding differential protection have differential primary rated value, then the current
compensation is carried out in the program automatically with parameters input. Following gives
the criteria of calculating correction coefficient.
Date: 2022-01-17
3 Protection Functions
I1n
K wph K wb / I 2n
I1n _ max
Equation 3.8-2
I1n _ max
K wb min( ,4)
I1n _ min
Where:
I1n_max is the maximum value among primary values of all CTs for winding differential protection.
This calculation method is to take the minimum CT primary rating of all calculated CT inputs as
the reference. If the multiple of the maximum CT primary ratio to the minimum CT primary rating is
greater than 4, then reference shall be taken as 4 and others shall be calculated proportionally.
Otherwise, the reference shall be taken as 1, and others will be calculated proportionally.
The currents used in the following analysis have been corrected, which means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (Kwph).
When selecting CT, the primary currents for each side muse follow the
I1n _ max
criterion: 128 , it is recommended that the ratio is smaller than 16.
I1n _ min
Theoretically, the ratio is preferred to be as small as it can be.
I wdA I A1 I A2 I A3
I I I
wdB K wph1 B1 K wph 2 B 2 K wph 3 I B 3
I wdC I C1 IC 2 IC 3
I wd 0 I 01 I 02 I 03
1 2 3
Equation 3.8-3
I A4 I A5
I I
K wph 4 B4
K wph 5
B5
IC 4 IC 5
I 04 I 05
3 4 5
Where:
I wdA , I wdB , I wdC , I wd0 are respectively three phase and residual winding differential currents.
I wrA , I wrB , I wrC , I wr0 are secondary values of three phase restraint currents and neutral
I Am , I Bm , I Cm and I 0 m are respectively secondary values of three phase currents and calculated
neutral current of branch m (m=1, 2, 3, 4, 5).
I Am , I B m , I C m and I 0 m are respectively secondary values of corrected three phase currents
Kwph1, Kwph2, Kwph3, Kwph4, Kwph5 are corrected coefficients of each side for magnitude
compensation respectively.
Date: 2022-01-17
3 Protection Functions
The operation criteria of winding differential protection are as follows, and maximum 5 branches
are supported for the calculation.
𝐼𝑤𝑑 > [87𝑊. 𝑆𝑙𝑜𝑝𝑒] × (𝐼𝑤𝑟 − [87𝑊. 𝐼_𝐾𝑛𝑒𝑒]) + [87𝑊. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] (𝐼𝑤𝑟
> [87𝑊. 𝐼_𝐾𝑛𝑒𝑒]) Equation 3.8-6
|𝐼 ̇w1|, |𝐼 ̇w2|, |𝐼 ̇w3|, |𝐼 ̇w4| and |𝐼 ̇w5| are currents of five branches respectively.
K=m
[87W.Slope]
[87W.I_Biased]
Restraint current
[87W.I_Knee]
The value of m is defined by the branch number for winding differential protection. For example,
winding differential protection is applied for protecting an autotransformer including HV side, MV
side and common winding and m is equal to 3.
In order to prevent winding differential protection from undesired operation caused by transient or
steady state saturation of CT during an external fault, the second and third harmonics of
secondary current of individual CTs are used for the device to discriminate saturation of
three-phase CT. If CT saturation is detected, winding differential protection will be blocked. The
criterions of CT saturation detection in 87W are as shown in Equation 3.8-7.
3
1
𝐼∅_2𝑛𝑑 > 𝐾2𝑛𝑑 × 𝐼∅_1𝑠𝑡 & 𝐼∅_𝑤𝑑 > [87𝑊. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑]
2
or Equation 3.8-7
1
𝐼∅_3𝑟𝑑 > 𝐾3𝑟𝑑 × 𝐼∅_1𝑠𝑡 & 𝐼∅_𝑤𝑑 > [87𝑊. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑]
2
Where:
𝐾2𝑛𝑑 and 𝐾3𝑟𝑑 are fixed coefficients of secondary and third harmonics respectively.
If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and winding differential protection will be
blocked.
CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of winding differential
protection will be issued without blocking the protection.
CT Circuit Failure
Date: 2022-01-17
3 Protection Functions
87W
87W.in_I3P1 87W.Ida
87W.in_I3P2 87W.Idb
87W.in_I3P3 87W.Idc
87W.in_I3P4 .
87W.in_I3P5 .
87W.Enable . 3
87W.Block 87W.Alm_Diff
87W.Alm_CTS
3.8.4 Logic
EN [87W.En_PhSeg] &
87W.On_PhSeg
SIG 87W.Enable
&
SIG 87W.Block >=1 87W.Blocked_PhSeg
SIG Fail_Device
&
87W.Valid_PhSeg
Date: 2022-01-17
3 Protection Functions
EN [87T.En_REF] &
87W.On_REF
SIG 87W.Enable
&
SIG 87W.Block >=1 87W.Blocked_REF
SIG Fail_Device
&
87W.Valid_REF
SIG 87W.Flag_DIFF
& &
SIG CT Staturation [87W.t_Op] 0ms 87W.Op_PhSeg
EN [87W.En_CTS_Blk]
SIG 87W.Pkp_PhSeg
SIG 87W.Flag_DIFF
& &
SIG CT Staturation [87W.t_Op] 0ms 87W.Op_REF
EN [87W.En_CTS_Blk]
SIG 87W.Pkp_REF
Where:
“87W.Flag_DIFF” means that the operation criterion of winding differential protection is satisfied.
3.8.5 Settings
Table 3.8-3 Settings of winding differential protection
If an earth fault or phase-to-phase fault of reactor occurs, current differential protection can
operate quickly to clear the fault to avoid the reactor from damages or reduce the maintenance
cost as low as possible. Different to transformer current differential protection based on
electromagnetic balance, reactor current differential protection is based on Kirchhoff's law, so it is
needed to develop current differential protection according to the actual application of reactor not
only to use transformer current differential protection to protect reactors.
Date: 2022-01-17
3 Protection Functions
Unrestrained differential element is to accelerate the operating speed for reactor's severe internal
faults without biased characteristic and blocking elements. DPFC biased differential element
calculated by current variation has high sensitivity to earth faults at ground end of reactor.
Zero-sequence differential element based on calculated residual current of two sides of reactor
has high sensitivity to asymmetric fault. Above four differential protection elements work
coordinately to form the high-speed current differential protection with high sensitivity.
Where:
Where:
Where:
∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and
hence the element maintains stability.
This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC
biased differential protection. The setting is fixed and thus site setting is not required.
It includes biased characteristic and instantaneous characteristic, and its operation equation is as
follows.
3I0d>[87R.I_Biased]
Equation 3.9-4
3I0d>[87R.I_Inst]
Where:
3 3I0d is residual differential current.
Under normal condition, the magnitudes of secondary current of both ends of reactor are different
due to the mismatch between CT ratios. The current value difference shall be eliminated before
calculation for current differential protection by amplitude compensation.
𝑆𝑛
𝐼1𝑏 = ⁄ Equation 3.9-5
√3𝑈𝑛
Where:
𝑆𝑛 is the rated capacity of reactor (i.e., the setting [Sn] in “System Settings” menu).
𝑈𝑛 is rated voltage of reactor. (i.e., the setting [U1n] in “System Settings” menu).
Where:
3. Correction coefficients
Kph2=1
Kph1≤8
Date: 2022-01-17
3 Protection Functions
Kph2=1
Kph1=(I1n_CT1)/(I1n_CT2)
Kph1≤8
Kph3≤8
Where:
3
I1n_CT# is the primary current of CT#. (# =1, 2, 3)
Low-voltage side of the reactor is taken as reference side, so the correction coefficient of
low-voltage side is 1 and that of high-voltage side is equal to the ratio of primary current of CT1 to
primary current of CT2. The maximum ratio of two sides is 8. If the ratio is out of the limit, the
device will be blocked and corresponding alarm messages are issued.
When viewing settings and values of current differential protection in the device, the unit “p.u.”
(per unit value) can be found. The current in differential protection calculation is not actual
secondary value but per unit value which is got by actual secondary value of each side of reactor
divided by reactor secondary rated current of each branch (i.e., I 2b1, I2b2).
1. Differential current
I dA I A1 I A2 I A3
I / I / I / I
dB I B1 2b1 I B 2 2b 2 I B 3 2b3 Equation 3.9-9
I dC I C1 I C 2 I C 3
1 2 3
I dA I A1 I A2 I A3
I dB I B1 I B 2 I B 3 Equation 3.9-10
I dC I C1 I C 2 I C 3
Where:
𝐼𝐴# , 𝐼𝐵# , 𝐼𝐶# are the equation vectors, the secondary current of CT#. (# =1, 2, 3)
′ ′ ′
𝐼𝐴# , 𝐼𝐵# , 𝐼𝐶# are the corrected secondary current. (# =1, 2, 3)
2. Restraint current
𝐼𝑟𝐴 = |𝐼′̇𝐴2 |
{𝐼𝑟𝐵 = |𝐼′̇𝐵2 | Equation 3.9-11
𝐼𝑟𝐶 = |𝐼′̇𝐶2 |
1 ′
𝐼𝑟𝐴 = (|𝐼 ̇ 𝐴1 | + |𝐼 ′̇ 𝐴2 | + |𝐼 ′̇ 𝐴3 |)
2
1
𝐼𝑟𝐵 = (|𝐼 ′̇ 𝐵1 | + |𝐼 ′̇ 𝐵2 | + |𝐼 ′̇ 𝐵3 |) Equation 3.9-12
2
1
{ 𝐼𝑟𝐶 = (|𝐼 ′̇ 𝐶1 | + |𝐼 ′̇ 𝐶2 | + |𝐼 ′̇ 𝐶3 |)
2
Where:
Current compensation process is shown in the flowing figure. In an ideal situation, the differential
current should be zero during normal operation of reactor or an external fault.
Ip1 Ip2
HV side CT1 CT2 LV side
*
* *
I1 I2
PCS-978S
I'1 I'2
Date: 2022-01-17
3 Protection Functions
*
Ip1
CT1
*
*
HV side I1
*
Ip3 * Ip2
CT3 CT2 LV side
*
*
*
*
I3 I2
PCS-978S
3
Magnitude compensation Magnitude compensation Magnitude compensation
(÷I2b3) (÷ I2b1) (÷I2b2)
CT5
CT1
*
IP1
*
*
HV side I1
CT4
Three phases
*
*
I3 I2
PCS-978S
The symbol “*” represents the polarity of CT. If current flowing into the
polarity of CT, the current direction is defined as positive direction.
Where:
𝐼1′ flows into the protected zone, 𝐼2′ leaves the protected zone, i.e. is negative according to
the definition of signs in above figure, therefore 𝐼1′ = −𝐼2′ .
𝐼𝑑 = |𝐼1′ + 𝐼2′ | = 0
𝐼𝑟 = |𝐼1′ | = |𝐼2′ |
No differential current (𝐼𝑑 =0), restraint current (𝐼𝑟 ) corresponds to double the through-flowing
current, and current differential protection does not operate.
1
The following applies 𝐼2′ = 2 𝐼1′
1
𝐼𝑑 = |𝐼1′ + 𝐼2′ | = |𝐼1′ + 𝐼1′ | = 1.5|𝐼1′ |
2
𝐼𝑟 = |𝐼2′ | = 0.5|𝐼1′ |
Differential current (𝐼𝑑 ) are three times of restraint current (𝐼𝑟 ) and corresponding to the total
fault, and current differential protection operates.
Biased differential element with initial restraint slope consists of sensitive and conventional
differential elements as well as independent CT saturation criterion and harmonic blocking.
The currents used in this section analysis and the following analysis have been corrected,
that means the currents for following calculation are the products of the actual secondary
current of each side multiplying its own correction coefficient.
Date: 2022-01-17
3 Protection Functions
The sensitive biased differential element with low pickup setting and restraint slope is much
more sensitive for a slight internal fault. Three blocking elements, CT saturation, inrush
current, CT circuit failure (optional) have also been included in order to prevent it from
unwanted operation during an external fault.
2 Equation 3.9-13
𝐼𝑑 = |∑ 𝐼𝑖̇ | 3
𝑖=1
𝐼𝑟 = |𝐼2̇ |
3
1
𝐼𝑟 = ∑|𝐼𝑖̇ |
2
𝑖=1
Where:
𝐼𝑑 and 𝐼𝑟 are respectively the differential current and the restraint current.
𝐾𝑃 is knee point, and its value is determined by the settings [87R.I_Biased] and [87R.Slope].
In order to improve the sensitivity of differential protection, the LV-side current is taken as
restraint current. When an internal fault occurs, current partly flows into ground through the
short circuit point, so the LV-side current will decrease and therefore the sensitivity of
differential protection is improved. Operation characteristic of sensitive biased differential
element is shown below.
Differential current
K
[87R.I_Inst]
l
tia
r en
ffe
di
ed
as
K=0.6 bi
t ive
si nt
en e
f s elem
e ao
ar
n
a tio
er [87R.Slope]
3 Op
1.2p.u.
[87R.I_Biased]
Restraint current
0 KP 0.8p.u.
Conventional biased differential element with higher setting and restraint coefficient
comparing with sensitive biased differential element, which is blocked only by an inrush
current detection. Conventional biased differential element provides fast operation for severe
internal faults. Operation criterion is:
Parameters of this protection have been fixed in the program and do not
need to be configured by user.
Date: 2022-01-17
3 Protection Functions
Differential current
[87R.I_Inst]
t l
en na
m io
le nt
l e ve
ia n
nt co
re of
ffe a
di are
K=0.6
ed n
as i o
bi rat
pe
O
3
1.2p.u.
Restraint current
0 0.8p.u.
Instantaneous differential element for reactor is to accelerate the operation speed for reactor's
internal fault. The element has no blocking element but to guard that the setting must be greater
than the maximum unbalanced current caused by inrush current. Instantaneous differential
element shall operate to clear the fault when any phase differential current is higher than its
setting. Operation criterion is:
Where:
Differential current
K
Operating area of
F instantaneous differential element
[87R.I_Inst]
t l
en na
K=0.6 l
ia
m io
nt
le nt
re
le e
ffe
ia nv
di
nt co
ed
re of
ias
eb
ffe a
di are
iv
sit nt
ed g
en e
as in
f s elem
3
bi rat
o
pe
e a
O ar
E g
in
at
er
Op
[87R.Slope]
D
1.2p.u.
[87R.I_Biased]
A Restraint current
0 KP 0.8p.u.
Where:
1. Sensitive biased differential element will send tripping signal monitored by criteria of CT
transient characteristic difference, and CT circuit failure (optional). It can ensure sensitivity
and avoid the unwanted operation when CT is saturated during an external fault or caused by
inrush current. Its operation area is the tint shadow area in the figure above.
When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the operation area of sensitive biased differential element.
2. Conventional biased differential element will send tripping signal without blocking criteria. It
eliminates the influence of transient and steady CT saturations during an external fault and
ensures reliable operation even if CT is in saturation condition during an internal fault by
means of its biased characteristic. Its operation area is the deeper shadow area in the figure
above.
When an internal fault occurs, differential current rises greatly and the operating point moves
to E in the operation area of conventional biased differential element.
3. Instantaneous differential element will send tripping signal without any blocking if differential
current of any phase reaches its setting. Its operation area is over the above two areas with
Date: 2022-01-17
3 Protection Functions
When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.
DPFC biased differential element is regardless of load current and is sensitive to small internal
fault current within the reactor. Its performance against CT saturation is also good. Lab tests show
that it is more sensitive than biased differential element under the heavy load condition.
DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to faults with fault resistance and faults close to neutral side is maintained during normal 3
operation of reactor. Floating threshold patent technology is adopted to prevent maloperation of
DPFC differential protection due to system frequency deviation, external faults and CB tripping
process.
The sensitivity of reactor current differential protection is improved greatly when DPFC biased
differential element is enabled, especially in the situation faults with fault resistance and faults
close to neutral point. Operation criteria are:
∆𝐼𝑑 > 0.75 × ∆𝐼𝑟 − 0.3𝑝. 𝑢. (∆𝐼𝑟 > 2𝑝. 𝑢. ) Equation 3.9-17
3 3 3
Where:
∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and hence the
element maintains stability.
∆𝐼𝑑 and ∆𝐼𝑟 are respectively the DPFC differential current and the DPFC restraint current.
The calculation of DPFC restraint current and differential current are phase-segregated. DPFC
biased differential element is blocked by inrush current and CT circuit failure. DPFC biased
differential element has the higher anti-CT saturation characteristic, the sensitivity of which to
slight inter-turn fault is maintained during normal operation of reactor.
Differential current
3
Operation area of DPFC
K=m
biased differential element
K=0.75
1.2p.u.
0.333p.u. 2p.u.
The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.
Where:
3𝐼0𝑑 and 3𝐼0𝑟 are respectively residual differential current and residual restraint current
Date: 2022-01-17
3 Protection Functions
Where:
β0 is a proportional constant. 3
Operation characteristic of zero-sequence differential element is shown below.
Differential current
Operating area of
instantaneous zero-sequence
F
differential element
[87R.I_Inst]
l l
tia na
K=0.6
en tio
ce
t fe r e n
en
en dif nv
qu
o
e
el nc of c
s
o-
er
e z ent
ue a
em e
eq re
iv
-s a
sit m
ro ing
en ele
f s tial
ze r a t
o n
pe
ea ere
ar
O
g diff
a tin
er
Op
[87R.Slope]
1.2p.u.
[87R.I_Biased]
Restraint current
0 KP 0.8p.u.
CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of reactor current
differential protection will be issued without blocking the protection.
CT Circuit Failure
87R.I3P1 87R.Ida
87R.I3P2 87R.Idb
87R.I3P3 87R.Idc
87R.Enable .
87R.Block
.
.
87R.St_DPFC_B
87R.St_DPFC_C
Date: 2022-01-17
3 Protection Functions
3.9.4 Logic
EN [87R.En_Inst] &
87R.On_Inst
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_Inst
SIG Fail_Device
&
87R.Valid_Inst
Date: 2022-01-17
3 Protection Functions
EN [87R.En_Biased] &
87R.On_Biased
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_Biased
SIG Fail_Device
&
87R.Valid_Biased
EN [87R.En_Inst]
3
&
EN [87R.En_REF] 87R.On_InstREF
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_InstREF
SIG Fail_Device
&
87R.Valid_InstREF
EN [87R.En_REF] &
87R.On_REF
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_REF
SIG Fail_Device
&
87R.Valid_REF
EN [87R.En_DPFC] &
87R.On_DPFC
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_DPFC
SIG Fail_Device
&
87R.Valid_DPFC
SIG 87R.Pkp_Biased
>=1
SIG Sensitive 87R & 87R.Op_Biased
SIG CT saturation
&
SIG CT circuit failure & &
EN [87R.En_CTS_Blk]
SIG 87R.Pkp_Biased
Date: 2022-01-17
3 Protection Functions
SIG 87R.Pkp_REF
>=1
SIG Sensitive 87R REF & 87R.Op_REF
SIG CT saturation
&
SIG CT circuit failure & & 3
EN [87R.En_CTS_Blk]
SIG 87R.Pkp_REF
SIG 87R.Pkp_DPFC
3.9.5 Settings
Table 3.9-3 Settings of reactor current differential protection
Inter-turn faults in reactors present a formidable challenge to the protection engineer. The current
and voltage changes encountered during an inter-turn fault can be of similar magnitude as load
variation, and therefore, sensitive, reliable protection schemes should be considered.
Inter-turn fault protection consists of zero-sequence power direction element and zero-sequence
impedance element. They can improve sensitivity and ensure the device against maloperation
during external faults, transient process (such as series compensated lines, LC resonance, power
swing etc.) or abnormal conditions (such as pole disagreement, CT secondary circuit failure, etc.)
Inter-turn fault protection adopts the current from CT at line side of reactor. The amplitude of
residual voltage is compensated to ensure zero-sequence power direction element can
distinguish direction correctly when system impedance is too low. Inter-turn fault protection will be
blocked during CT and VT circuit failure.
DPFC inter-turn fault detector will enable inter-turn fault protection, and its operation equation is
as follows.
I d 1.25 I dt I dth
Equation 3.10-1
I d I 1 I 2
Where:
I dt is the floating threshold varied with the change of load current from time to time. The change
Date: 2022-01-17
3 Protection Functions
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold ( I dt ) is higher than the change of current under these conditions and
I 1 and I 2 are DPFC current of two ends of reactor representatively.
The wiring diagram of shunt reactors in power system is shown as Figure 3.10-1.
F1
AC1 Zs1 ZL Zs2 AC2
* Relay 1 Relay 2 *
Zr1 Zr2 F2
Where:
1. F1: External single-phase earth fault of line (close-up external earth fault)
The fault point is zero-sequence power source, the equivalent zero-sequence network is shown
below.
Zs' U0 Zr2
I0
Fault PS
Where:
3 Zs': equivalent system impedance, Zs'= (Zr1//Zs1+ ZL)//Zs2
It is an external earth fault, so viewing from the device location, zero-sequence current flows to
reactor from reactor grounding point and via transmission line back to the ground at the earth fault
point. Therefore, the equation between U0 and I0 at the relay location is: U0=I0xZr2.
U0
I0
Because of the fault point in reactor, the equivalent zero-sequence network is shown below.
I0 Fault PS
Where:
Date: 2022-01-17
3 Protection Functions
It is an internal inter-turn fault, so viewing from reactor relay location, zero-sequence current flows
from reactor to ground through system reactance. Therefore, the equation between U0 and I0 at
the device location is: U0=-I0xZ's.
U0
The phase angle of residual current leading residual voltage is nearly 90°if an inter-turn fault of
reactor winding occurs. The residual current phase leads the residual voltage phase if an internal
single-phase earth fault occurs, and the residual current phase lags the residual voltage phase if
an external single-phase earth fault occurs. Therefore, the phase angle between residual current
and residual voltage can be used to distinguish internal faults from external faults. The
zero-sequence impedance of system very small compared to reactor impedance, so the residual
voltage detected by the device will not be sensitive to operate and need to be compensated.
( 3 U 0 K [ 21I.Zn_Reac_NP ] 3 I 0 )
- 180 Arg
0 Equation 3.10-2
3I0
Where:
3 U 0 and 3 I 0 are respectively calculated residual voltage and calculated residual current from
VT and CT at the line side of reactor.
K is the floating coefficient adaptive to variation of zero-sequence voltage and current from 0 to
0.8.
Zero-sequence impedance of reactor is usually thousands of ohms which is greater than system
impedance. When an inter-turn fault or internal single-phase earth fault of reactor occurs, the
Operation criterion:
Where:
21IT
21IT.I3P 21IT.St
21IT.U3P 21IT.Op
21IT.Enable 21IT.On
21IT.Block 21IT.Blocked
21IT.Valid
Date: 2022-01-17
3 Protection Functions
EN [21IT.En] &
21IT.On
SIG 21IT.Enable
&
SIG 21IT.Block >=1 21IT.Blocked
SIG Fail_Device
&
21IT.Valid
SET 21IT.Valid
&
SIG Flag_ZSImpedance 0 500ms 21IT.Pkp
FD.Pkp
SIG FwdDir_ROC
SIG AlmL_CTS
SIG 21IT.Pkp_DPFC
Where:
3.10.5 Settings
Table 3.10-3 Settings of inter-turn fault protection
Overexcitation results from excessive applied voltage, possibly in combination with below-normal
frequency. Such condition may occur when a unit is on load, but are more likely to arise when it is
on open circuit, or at a loss of load occurrence. Transformers directly connected to generators are
in particular danger to experience overexcitation condition.
During overexcitation, field current of transformer rises greatly to cause excessive heating and
severe damage. The transformer, working magnetic flux density near the knee point, is subject to
overexcitation. Frequency range for normal operation is 45~55Hz for 50Hz working frequency of
power system and 55~65Hz for 60Hz working frequency of power system.
Overexcitation protection can be configured at any side of transformer through PCS-Studio, and it
is recommended to be equipped at the side without OLTC.
Date: 2022-01-17
3 Protection Functions
Where:
The base value for calculating per unit value of voltage is secondary voltage corresponding to
primary voltage of one side of transformer, and the base value for calculating per unit value of
frequency is rated frequency. Hence, under normal operation, n should be equal to 1.
Several groups of setting point with independent settings can be configured for simulating the
inverse-time operation characteristics curve and this protection can satisfy overexcitation
requirements of various transformers.
U*/f*
n0
n1
n2
n3
n4
n5
n6
n7
n8
n9
3 t0 t1t2 t3 t4 t5 t6 t7 t8 t9
t (s)
0
Inverse-time characteristic curve can be specified by several overexcitation multiple settings, and
the relation among various settings of n and t are:
24Cal
24Cal.in_U3P OvExc
24Cal.in_FREQ U/f
Date: 2022-01-17
3 Protection Functions
24DT1
24DT1.OvExc 24DT1.St
24DT1.Enable 24DT1.Op
24DT1.Block 24DT1.On
24DT1.Blocked
24DT1.Valid
24DT2
3
24DT2.OvExc 24DT2.St
24DT2.Enable 24DT2.Alm
24DT2.Block 24DT2.On
24DT2.Blocked
24DT2.Valid
24IDMT
24IDMT.OvExc 24IDMT.ThermAccu
24IDMT.Enable 24IDMT.St
24IDMT.Block 24IDMT.Op
24IDMT.On
24IDMT.Blocked
24IDMT.Valid
24IDMT.Alm
3 7 24IDMT.Enable
Input signal of enabling inverse-time overexcitation protection. It is triggered from
binary input or programmable logic etc.
Input signal of blocking inverse-time overexcitation protection. It is triggered from
8 24IDMT.Block
binary input or programmable logic etc.
Date: 2022-01-17
3 Protection Functions
3.11.4 Logic
EN [24DT1.En] &
24DT1.On
SIG 24DT1.Enable
&
SIG 24DT1.Block >=1 24DT1.Blocked
SIG Fail_Device
&
24DT1.Valid
3
EN [24DT2.En] &
24DT2.On
SIG 24DT2.Enable
&
SIG 24DT2.Block >=1 24DT2.Blocked
SIG Fail_Device
&
24DT2.Valid
EN [24IDMT.En] &
24IDMT.On
SIG 24IDMT.Enable
&
SIG 24IDMT.Block >=1 24IDMT.Blocked
SIG Fail_Device
&
24IDMT.Valid
SET U*/f*>[24DT1.K_Set]
BI x.BI_En_VT
SET U*/f*>[24DT2.K_Set]
BI x.BI_En_VT
SET U*/f*>[24IDMT.Kn_Set]
BI x.BI_En_VT
24IDMT.St
SIG 24IDMT.Pkp
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT 24IDMT.Op
24IDMT.St
EN [24IDMT.En_Trp]
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT* 24IDMT.Alm
EN [24IDMT.En_Alm]
Where, IDMT* means that the time delay of inverse-time overexcitation protection for alarm
Date: 2022-01-17
3 Protection Functions
purpose equals to [24IDMT.K_Alm] of the time delay of inverse-time overexcitation protection for
trip purpose.
3.11.5 Settings
Table 3.11-3 Settings of overexcitation protection
Date: 2022-01-17
3 Protection Functions
[24IDMT.K9_Set]<[24IDMT.K8_ Set]<…<[24IDMT.K1_Set]<[24IDMT.K0_
Set] 3
[24IDMT.t0_Op]<[ 24IDMT.t1_ Op]<…<[24IDMT.k8_ Op] <[24IDMT.t9_ Op]
Phase overcurrent protection is widely used in power systems. It can be used as main protection
of the feeder, and can also be used as backup protection for power equipment such as
transformers, reactors, and motors. When a fault occurs in the system, a fault current will be
generated and phase overcurrent protection can reflect the increase of the fault current.
The device can provide 6 stages of phase overcurrent protection with independent logic by default.
Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. The dropout characteristics can be set as instantaneous dropout, definite-time
dropout or inverse-time dropout. It can be chosen whether it is blocked by voltage control element
or harmonic control element. The direction control element can be set as no direction, forward
direction and reverse direction. Phase overcurrent protection picks up when the current exceeds
the setting, and operates after a certain time delay. Once the fault disappears, phase overcurrent
protection will dropout.
Phase overcurrent protection can operate to trip or alarm and can be enabled or disabled via the
settings or the signals, for some specific applications, phase overcurrent protection needs to be
blocked by the external signal, so the device provides a function block input signal to be used to
block phase overcurrent protection.
EN [x.50/51Pi.En] &
x.50/51Pi.On
SIG x.50/51Pi.Enable
&
SIG x.50/51Pi.Block >=1 x.50/51Pi.Blocked
SIG Fail_Device
&
x.50/51Pi.Valid
SET x.Ia>0.95×[x.50/51Pi.I_Set]
>=1
SET x.Ib>0.95×[x.50/51Pi.I_Set] &
0 500ms &
SET x.Ic>0.95×[x.50/51Pi.I_Set]
x.50/51Pi.Pkp
SIG x.50/51Pi.On
SIG x.50/51Pi.Valid
&
FD.Pkp
SET [x.50/51Pi.Opt_Trp/Alm]=Alm
When a fault occurs at the remote end of a feeder, the fault current is relatively small, so the
voltage control element can be adopted to increase the sensitivity for this kind of fault. It can be
enabled or disabled via the setting [x.50/51P.VCE.En_VTS_Blk]. If VT circuit supervision is
enabled and the setting [x.50/51P.VCE.En_VTS_Blk] is set as “Enabled”, the device will issue an
alarm signal "VTS.Alm" when VT circuit fails, and voltage control element will be blocked. If
voltage control element is not enabled, phase overcurrent protection will not effected by VT circuit
failure. The corresponding relationship between each phase and voltage control element is as
follows.
Date: 2022-01-17
3 Protection Functions
EN [x.50/51P.VCE.En_VTS_Blk] &
>=1
SIG x.VTS.Alm &
SIG x.Uab, x.Ubc, x.Uca
criterion
Voltage
&
x.50/51P.VCE.Op
SIG x.U2, x.U0_Cal
EN [x.En_VT]
3
Figure 3.12-3 Logic of voltage control element
Ua
[x.50/51P.DIR.phi_Min_Fwd]
Non-operating Ia
area
[x.50/51P.DIR.RCA]
Operating area in
reverse direction
[x.50/51P.DIR.phi_Max_Fwd]
[x.50/51P.DIR.phi_Min_Rev] Non-operating
area
In order to ensure the selectivity of phase overcurrent protection, direction control element is also
available. The setting [x.50/51Pi.Opt_Dir] (i=1~6) is used to select the direction characteristics for
each stage of phase overcurrent protection: no direction, forward direction and reverse direction.
Takes the phase A fault as an example, the setting [x.50/51P.DIR.Opt_PolarizedVolt] is set as
"Up", its operating characteristics is shown in Figure 3.12-4. The principle of phase B and phase C
For the “ACB” system phase sequence, the angle difference under
positive-sequence voltage polarization mode and phase-to-phase voltage
polarization mode is different from that of the “ABC” system phase
sequence, as shown in the following table:
Date: 2022-01-17
3 Protection Functions
The calculation of direction control element needs to judge the voltage threshold and the current
threshold. The direction judgement can be executed only when both the voltage and the current
are greater than the threshold values. For different polarization mode, the selected voltage and
current, and their threshold value are also different, the specific principles are:
The memorized characteristics of direction control element can eliminate the dead zone for
close-in three-phase short-circuit fault. When the polarized voltage is less than the minimum
operating voltage setting [x.50/51P.DIR.U_Min], the 2-cycle pre-fault positive-sequence voltage is
used to judge the direction. The polarized voltage will not be used to judge the direction until it is
greater than [x.50/51P.DIR.U_Min].The logic of forward direction element and reverse direction
element are shown in Figure 3.12-5.
EN [x.50/51P.DIR.En_VTS_Blk] &
Forward direction
x.50/51P.DIR.Fwd
SIG Three-phase voltages
criterion
SIG Memorized U1
SET [x.50/51P.DIR.Opt_PolarizedVolt]
3 BI x.BI_En_VT &
EN [x.En_VT]
SET x.Iop>[x.50/51P.DIR.I_Min]
EN [x.50/51P.DIR.En_VTS_Blk] &
x.50/51P.DIR.Rev
SIG Three-phase voltages
criterion
SIG Memorized U1
SET [x.50/51P.DIR.Opt_PolarizedVolt]
BI x.BI_En_VT &
EN [x.En_VT]
SET x.Iop>[x.50/51P.DIR.I_Min]
Where:
Memorized U1: the positive-sequence memory voltage, it refers to the 2-cycle pre-fault
positive-sequence voltage when the polarized voltage is less than the minimum operating voltage
setting [x.50/51P.DIR.U_Min], and it is calculated from the three-phase voltage.
When the transformer is energized with no-load, the inrush current may be generated, which may
cause the maloperation of phase overcurrent protection. Because secondary harmonic
Date: 2022-01-17
3 Protection Functions
component is high in the inrush current but secondary harmonic component is low in the fault
current, harmonic control element based on secondary harmonic component is added to prevent
phase overcurrent protection from maloperation due to inrush current. For harmonic control
element, the harmonic blocking mode can be selected through the setting [50/51P.HMB.Opt_Blk],
it can support phase blocking, cross blocking, and maximum phase blocking. The corresponding
relationship is shown in the following table.
When the fundamental current is greater than the setting [x.50/51P.HMB.I_Rls], the corresponding
phase will be unblocked by harmonic control element. The logic of harmonic control element is
shown in Figure 3.12-6.
SET Imax>[x.50/51P.HMB.I_Rls]
SET [x.50/51P.HMB.Opt_Blk]
Where:
Phase overcurrent protection can operate instantaneously or with a fixed time delay. It can also
operate with inverse-time characteristics, and its characteristics curve complies with the
standards IEC 60255-3 and ANSI C37.112. Phase overcurrent protection can support
definite-time characteristics, IEC & ANSI standard inverse-time characteristics and user-defined
inverse-time characteristics, which are determined by the setting [x.50/51Pi.Opt_Curve] (i=1~6).
The relationship between the setting and the characteristics curve is shown in the table below.
Instantaneous characteristics
Definite-time characteristics
[x.50/51Pi.t_Op]
I
[x.50/51Pi.I_Set]
Inverse-time characteristics
When I>[x.50/51Pi.I_Set], phase overcurrent protection begins to accumulate, and the operating
Date: 2022-01-17
3 Protection Functions
time is affected by the applied current I. The operating time will decrease with the current
increasing, but the operating time shall not less than the setting [x.50/51Pi.tmin] (i=1~6). The
inverse-time operating characteristics equation is:
K
t={ + C} × TMS
I α
(I ) − 1
P
Where:
[x.50/51Pi.tmin]
I
[x.50/51Pi.I_Set] ID
When the applied current is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overcurrent protection is shown in the following equation.
T0
1
∫ dt = 1
t(I)
0
Where:
Instantaneous characteristics
Definite-time characteristics
When I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection drops out with a time delay
[x.50/51Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among
start signal, operating signal and the counter is as shown in Figure 3.12-9.
Start time
I>[x.50/51Pi.I_Set]
x.50/51Pi.St
x.50/51Pi.Op
Operating counter
[x.50/51Pi.t_DropOut]
[x.50/51Pi.t_DropOut] [x.50/51Pi.t_DropOut]
Dropout time
Dropout time
Inverse-time characteristics
Date: 2022-01-17
3 Protection Functions
tP
1
Itp = ∫ dt
t(I)
0
If I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection begins to drop out, and the dropout
characteristics meets the following equations.
tR
Itp − ∫
1
t R (I)
dt = 0 3
0
tr
t R (I) = { } × TMS
I 2
1 − (I )
P
Where:
tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
phase overcurrent protection operates.
tr
I
[x.50/51Pi.I_Set]
The sequence diagram of inverse-time dropout characteristics among start signal, operating
signal and the counter is shown in Figure 3.12-11.
Start time
I>[x.50/51Pi.I_Set]
x.50/51Pi.St
3
x.50/51Pi.Op
Operating counter
Dropout time
Dropout time
x.50/51P.HMB
x.50/51P.HMB.in_I3P x.50/51P.HMB.Op
x.50/51P.DIR
x.50/51P.DIR.in_I3P x.50/51P.DIR.Fwd
x.50/51P.DIR.in_U3P x.50/51P.DIR.Rev
x.50/51P.VCE
x.50/51P.VCE.in_U3P x.50/51P.VCE.Op
Date: 2022-01-17
3 Protection Functions
x.50/51Pi
x.50/51Pi.in_I3P x.50/51Pi.St
x.50/51Pi.Enable x.50/51Pi.StA
x.50/51Pi.Block x.50/51Pi.StB
x.50/51Pi.VCE x.50/51Pi.StC
x.50/51Pi.FwdDir x.50/51Pi.Op
x.50/51Pi.RevDir x.50/51Pi.Op.PhA
x.50/51Pi.HMB x.50/51Pi.Op.PhB 3
x.50/51Pi.Op.PhC
x.50/51Pi.On
x.50/51Pi.Blocked
x.50/51Pi.Valid
x.50/51Pi.Alm
Date: 2022-01-17
3 Protection Functions
3.12.4 Logic
SET Ia>[x.50/51Pi.I_Set]
EN [x.50/51Pi.En_Volt_Blk]
SIG x.50/51P.DIR.Fwd_A
selection
Direction
SIG x.50/51P.DIR.Rev_A
&
x.50/51Pi.Alm_A
SET [x.50/51Pi.Opt_Trp/Alm]=Alm
SIG x.50/51Pi.StA
>=1
SIG x.50/51Pi.StB x.50/51Pi.St
SIG x.50/51Pi.StC
SIG x.50/51Pi.Op.PhA
>=1
SIG x.50/51Pi.Op.PhB x.50/51Pi.Op
SIG x.50/51Pi.Op.PhC
SIG x.50/51Pi.Alm_A
>=1
SIG x.50/51Pi.Alm_B x.50/51Pi.Alm
SIG x.50/51Pi.Alm_C
3.12.5 Settings
Table 3.12-3 Settings of phase overcurrent protection
Date: 2022-01-17
3 Protection Functions
3 25 x.50/51Pi.Opt_Curve
ANSILT
IECN
-
IECDefTi
me
characteristics curve
stage i of phase overcurrent
for
Date: 2022-01-17
3 Protection Functions
Under normal conditions, three phases of the power system is symmetrical, its zero-sequence
current and voltage are zero theoretically. Most of the faults are asymmetrical, so various 3
protections reflect sequence component principle can be fulfilled based on the fault's
asymmetrical characteristics. Earth fault protection has been widely used in power systems, it can
be applied for the fault as long as there is zero-sequence current, including single-phase earth
fault and phase-to-phase short-circuit earth fault etc.
Earth fault protection can operate to trip or alarm and can be enabled or disabled via the settings
or the signals, for some specific applications, this protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block earth fault
protection.
EN [x.50/51Gi.En] &
x.50/51Gi.On
SIG x.50/51Gi.Enable
&
SIG x.50/51Gi.Block >=1 x.50/51Gi.Blocked
SIG Fail_Device
&
x.50/51Gi.Valid
SET [x.50/51Gi.Opt_Trp/Alm]=Alm
3 In order to ensure the selectivity of earth fault protection, direction control element can be
available. The setting [x.50/51Gi.Opt_Dir] (i=1~4) is used to select the direction characteristics for
each stage of earth fault protection: no direction, forward direction and reverse direction are
selectable. The operation boundary of the forward direction element can be set by
[x.50/51G.DIR.phi_Min_Fwd] and [x.50/51G.DIR.phi_Max_Fwd]. The operation boundary of the
reverse direction element can be set by [x.50/51G.DIR.phi_Min_Rev] and
[x.50/51G.DIR.phi_Max_Rev].
-U0
[x.50/51G.DIR.phi_Min_Fwd]
Non-operating I0
area
Operating area in
[x.50/51G.DIR.phi_Max_Rev] forward direction
[x.50/51G.DIRRCA]
Operating area in
reverse direction
[x.50/51G.DIR.phi_Max_Fwd]
Non-operating
area
[x.50/51G.DIR.phi_Min_Rev]
The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode.
Date: 2022-01-17
3 Protection Functions
Polarization Polarized
Operating current Angle difference
mode voltage
Calculated residual current:
- 3U0 Angle=Angle(-3U0)-Angle(3I0_Cal)-RCA
Zero-sequence 3I0_Cal
voltage polarized Measured residual current:
- 3U0 Angle=Angle(-3U0)-Angle(3I0_Ext)-RCA
3I0_Ext
The direction element calculation needs to judge the current threshold and voltage threshold. The
corresponding operating current must be greater than the minimum operating current setting
[x.50/51G.DIR.3I0_Min], otherwise the direction element can‘t operate. The polarized voltage
must be greater than the minimum operating voltage setting [x.50/51G.DIR.3U0_Min], otherwise
the direction element can’t operate. 3
The logic of forward direction element and reverse direction element are shown in Figure 3.13-4.
EN [x.50/51G.DIR.En_VTS_Blk] &
Forward direction
criterion
3 SIG x.3U0_Cal
BI x.BI_En_VT &
EN [x.En_VT]
SET x.Iop>[x.50/51G.DIR.3I0_Min]
SET x.Upo>[x.50/51G.DIR.3U0_Min]
EN [x.50/51G.DIR.En_VTS_Blk] &
SIG x.3U0_Cal
BI x.BI_En_VT &
EN [x.En_VT]
SET x.Iop>[x.50/51G.DIR.3I0_Min]
SET x.Upo>[x.50/51G.DIR.3U0_Min]
Where:
Date: 2022-01-17
3 Protection Functions
Harmonic control element based on zero-sequence current can be used to prevent earth fault
protection from maloperation due to inrush current. Zero-sequence current can be calculated or
measured. When the percentage of second harmonic component to fundamental component in
residual current is greater than the setting [x.50/51G.HMB.K_Hm2], harmonic control element
operates to block earth fault protection if the corresponding setting [x.50/51Gi.En_Hm_Blk] is set
as "Enabled" (i=1~4). When the fundamental component of zero-sequence current is greater than
the setting [x.50/51G.HMB.I_Rls], earth fault protection will be unblocked by harmonic control
3
element. The logic of harmonic control element is shown in Figure 3.13-5.
SET x.3I0>[x.50/51G.HMB.I_Rls]
SET x.3I0_2nd/3I0>[x.50/51G.HMB.K_Hm2]
Where:
Earth fault protection can operate instantaneously or with a fixed time delay. It can also operate
with inverse-time characteristics, and its characteristics curve complies with the standards IEC
60255-3 and ANSI C37.112. Earth fault protection can support definite-time characteristics, IEC &
ANSI standard inverse-time characteristics and user-defined inverse-time characteristics, which
are determined by the setting [x.50/51Gi.Opt_Curve] (i=1~4). The relationship between the setting
and the characteristics curve is shown in the table below.
Instantaneous characteristics
Definite-time characteristics
[x.50/51Gi.t_Op]
I0
[x.50/51Gi.3I0_Set]
Inverse-time characteristics
When x.3I0>[x.50/51Gi.3I0_Set], earth fault protection begins to accumulate, and the operating
time is affected by the applied current x.3I0. The operating time will decrease with the current
increasing, but the operating time shall not less than the setting [x.50/51Gi.tmin] (i=1~4). The
inverse-time operating characteristics equation is:
Date: 2022-01-17
3 Protection Functions
K
t={ + C} × TMS
x. 3I0 α
( ) −1
I0P
Where:
[x.50/51Gi.tmin]
I0
[x.50/51Gi.3I0_Set] ID
When the applied residual current is not a fixed value, but changes with the time, the operating
behavior of inverse-time earth fault protection is shown in the following equation.
T0
1
∫ dt = 1
t(x. 3I0 )
0
Where:
The supported dropout characteristics of earth fault protection include instantaneous, definite-time
and ANSI inverse-time characteristics. When the operating characteristics curve is selected as
definite-time, IEC inverse-time or user-defined inverse-time characteristics, the dropout
characteristic curve can only be selected as instantaneous or definite-time characteristics, and the
alarm signal "Fail_Settings" will be issued and the device will be blocked if ANSI inverse-time
characteristics is selected. When the operating characteristics curve is selected as ANSI
inverse-time characteristics, the dropout characteristic curve can be selected as instantaneous,
definite-time and ANSI inverse-time characteristics.
3 Instantaneous characteristics
Definite-time characteristics
When x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection drops out with a time delay
[x.50/51Gi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among
start signal, operating signal and the counter is as shown in Figure 3.13-8.
Start time
x.3I0>[x.50/51Gi.3I0_Set]
x.50/51Gi.St
x.50/51Gi.Op
Operating counter
[x.50/51Gi.t_DropOut]
[x.50/51Gi.t_DropOut] [x.50/51Gi.t_DropOut]
Dropout time
Dropout time
Inverse-time characteristics
Date: 2022-01-17
3 Protection Functions
tP
1
Itp = ∫ dt
t(x. 3I0 )
0
If x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection begins to drop out, and the dropout
characteristics meets the following equations.
tR
Itp − ∫
1
t R (x. 3I0 )
dt = 0 3
0
tr
t R (x. 3I0 ) = 2 × TMS
x. 3I0
{1 − ( I0P } )
Where:
tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
earth fault protection operates.
3 tr
I0
[x.50/51Gi.3I0_Set]
The sequence diagram of inverse-time dropout characteristics among start signal, operating
signal and the counter is shown in the following figure.
Start time
x.3I0>[x.50/51Gi.3I0_Set]
x.50/51Gi.St
x.50/51Gi.Op
Operating counter
Dropout time
Dropout time
Date: 2022-01-17
3 Protection Functions
x.50/51G.HMB
x.50/51G.HMB.in_I3P x.50/51G.HMB.Op
x.50/51G.HMB.in_I1P
x.50/51G.DIR
x.50/51G.DIR.in_I3P x.50/51G.DIR.Fwd
x.50/51G.DIR.in_I1P x.50/51G.DIR.Rev
3
x.50/51G.DIR.in_U3P
x.50/51Gi
x.50/51Gi.in_I3p x.50/51Gi.St
x.50/51Gi.in_I1p x.50/51Gi.Op
x.50/51Gi.Enable x.50/51Gi.On
x.50/51Gi.Block x.50/51Gi.Blocked
x.50/51Gi.FwdDir x.50/51Gi.Valid
x.50/51Gi.RevDir x.50/51Gi.Alm
x.50/51Gi.HMB
3.13.4 Logic
SET x.3I0>[x.50/51Gi.3I0_Set]
EN [x.50/51Gi.En_Hm_Blk]
SIG x.50/51Gi.Pkp
&
x.50/51Gi.Op
SET [x.50/51Gi.Opt_Trp/Alm]=Trp
&
x.50/51Gi.Alm
SET [x.50/51Gi.Opt_Trp/Alm]=Alm
3.13.5 Settings
Table 3.13-3 Settings of earth fault overcurrent protection
Date: 2022-01-17
3 Protection Functions
Date: 2022-01-17
3 Protection Functions
When a phase-to-phase fault occurs in the system, the fault current is small, and phase current
criterion may not detect the fault. At this time, negative-sequence overcurrent protection is
sensitive to the fault and can be used. Negative-sequence overcurrent protection can also be
used to detect pole disagreement operation or unbalanced load.
The device can provide two stages of negative-sequence overcurrent protection with independent
Negative-sequence overcurrent protection can operate to trip or alarm and can be enabled or
disabled via the settings or the signals, for some specific applications, negative-sequence
overcurrent protection needs to be blocked by the external signal, so the device provides a
function block input signal to be used to block negative-sequence overcurrent protection.
EN [x.50/51Qi.En] &
x.50/51Qi.On
SIG x.50/51Qi.Enable
&
SIG x.50/51Qi.Block >=1 x.50/51Qi.Blocked
SIG Fail_Device
&
x.50/51Qi.Valid
SET [x.50/51Qi.Opt_Trp/Alm]=Alm
Date: 2022-01-17
3 Protection Functions
-U2
3
[x.50/51Q.DIR.phi_Min_Fwd]
Non-operating I2
area
[x.50/51Q.DIR.phi_Max_Rev]
Operating area in
forward direction
[x.50/51Q.DIR.RCA]
Operating area in
reverse direction
[x.50/51Q.DIR.phi_Max_Fwd]
Non-operating
area
[x.50/51Q.DIR.phi_Min_Rev]
The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode.
Polarized
Polarization mode Operating current Angle difference
voltage
Negative-sequence
Negative-sequence current: I2 -U2 Angle=Angle(-U2)-Angle(I2)-RCA
voltage polarized
The direction element calculation needs to judge the current threshold and voltage threshold. The
corresponding operating current must be greater than the minimum operating current setting
[x.50/51Q.DIR.I2_Min], otherwise the direction element can’t operate. The polarized voltage must
be greater than the minimum operating voltage setting [x.50/51Q.DIR.U2_Min], otherwise the
direction element can’t operate.
The logic of forward direction element and reverse direction element are shown in Figure 3.14-4.
EN [x.50/51Q.DIR.En_VTS_Blk] &
Forward direction
3 criterion
SIG x.U2
EN [x.En_VT]
SET x.Iop>[x.50/51Q.DIR.I2_Min]
SET x.Upo>[x.50/51Q.DIR.U2_Min]
EN [x.50/51Q.DIR.En_VTS_Blk] &
SIG x.U2
EN [x.En_VT]
SET x.Iop>[x.50/51Q.DIR.I2_Min]
SET x.Upo>[x.50/51Q.DIR.U2_Min]
Negative-sequence overcurrent protection can operate instantaneously or with a fixed time delay.
It can also operate with inverse-time characteristics, and its characteristics curve complies with
the standards IEC 60255-3 and ANSI C37.112. Negative-sequence overcurrent protection can
support definite-time characteristics, IEC & ANSI standard inverse-time characteristics and
Date: 2022-01-17
3 Protection Functions
Instantaneous characteristics
Definite-time characteristics
[x.50/51Qi.t_Op]
3
I2
[x.50/51Qi.I2_Set]
Inverse-time characteristics
K
t={ + C} × TMS
x. I2 α
(I ) −1
2P
Where:
Date: 2022-01-17
3 Protection Functions
[x.50/51Qi.tmin]
3
I2
[x.50/51Qi.I2_Set] ID
When the applied negative-sequence current is not a fixed value, but changes with the time, the
operating behavior of inverse-time negative-sequence overcurrent protection is shown in the
following equation.
T0
1
∫ dt = 1
t(x. I2 )
0
Where:
Instantaneous characteristics
Definite-time characteristics
Start time
x.I2>[x.50/51Qi.I2_Set]
3 x.50/51Qi.St
x.50/51Qi.Op
Operating counter
[x.50/51Qi.t_DropOut]
[x.50/51Qi.t_DropOut] [x.50/51Qi.t_DropOut]
Dropout time
Dropout time
Inverse-time characteristics
tP
1
Itp = ∫ dt
t(x. I2 )
0
tR
1
Itp − ∫ dt = 0
t R (x. I2 )
0
Date: 2022-01-17
3 Protection Functions
tr
t R (I2 ) = { } × TMS
x. I2 2
1−( )
I2P
Where:
tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after 3
negative-sequence overcurrent protection operates.
tr
I2
[x.50/51Qi.I2_Set]
The sequence diagram of inverse-time dropout characteristics among start signal, operating
signal and the counter is shown in Figure 3.14-9.
Start time
x.I2>[x.50/51Qi.I2_Set]
x.50/51Qi.St
x.50/51Qi.Op
3 [x.50/51Qi.t_Op]
Negative-sequence overcurrent
protection operating
Operating counter
Dropout time
Dropout time
x.50/51Q.DIR
x.50/51Q.DIR.in_I3P x.50/51Q.DIR.Fwd
x.50/51Q.DIR.in_U3P x.50/51Q.DIR.Rev
x.50/51Qi
x.50/51Qi.in_I3P x.50/51Qi.St
x.50/51Qi.Enable x.50/51Qi.Op
x.50/51Qi.On
x.50/51Qi.Block
x.50/51Qi.Blocked
x.50/51Q.FwdDir
x.50/51Qi.Valid
x.50/51Q.RevDir
x.50/51Qi.Alm
Date: 2022-01-17
3 Protection Functions
4 x.50/51Qi.FwdDir
Input signal of forward direction element of stage i of negative-sequence 3
overcurrent protection (i=1~2)
Input signal of reverse direction element of stage i of negative-sequence
5 x.50/51Qi.RevDir
overcurrent protection (i=1~2)
Three-phase current data input for direction control element of
6 x.50/51Q.DIR.in_I3P
negative-sequence overcurrent protection
Three-phase voltage data input for direction control element of
7 x.50/51Q.DIR.in_U3P
negative-sequence overcurrent protection
3.14.4 Logic
SET x.I2>[x.50/51Qi.I2_Set]
x.50/51Qi.St
SIG x.50/51Q.DIR.Fwd
&
& Timer
selection
Direction
t
SIG x.50/51Q.DIR.Rev
t
SET [x.50/51Qi.Opt_Dir]
SIG x.50/51Qi.Pkp
&
x.50/51Qi.Op
SET [x.50/51Qi.Opt_Trp/Alm]=Trp
3 &
x.50/51Qi.Alm
SET [x.50/51Qi.Opt_Trp/Alm]=Alm
3.14.5 Settings
Table 3.14-3 Settings of negative-sequence overcurrent protection
Date: 2022-01-17
3 Protection Functions
3 negative-sequence
overcurrent
protection operate to
Trp
14 x.50/51Qi.Opt_Trp/Alm - Trp trip or alarm (i=1 or
Alm
2)
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
The option of
ANSILTE
operating
ANSILTV
characteristics curve
ANSILT
15 x.50/51Qi.Opt_Curve - IECDefTime for stage i of
IECN
negative-sequence
IECV
overcurrent
IECI
protection (i=1 or 2)
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
Inst for stage i of
16 x.50/51Qi.Opt_Curve_DropOut DefTime - Inst negative-sequence
IDM overcurrent
protection (i=1 or 2)
Inst: instantaneous
dropout
Date: 2022-01-17
3 Protection Functions
3.15.1 Application
During overload operation of a power equipment, great current results in greater heat to lead
equipment temperature increase and if the temperature reaches too high values, the equipment
might be damaged. The insulation within the equipment will have forced ageing. As a
consequence of this, the risk of internal phase-to-phase or phase-to-ground faults will increase.
For transformers and reactors, high temperature will degrade the quality of the oil.
3 Thermal overload protection estimates the internal heat content of the equipment (temperature)
continuously. This estimation is made by using a thermal model of the equipment with the time
constants, which is based on current measurement.
1. Method 1
Two stages overload protection are available, one stage for alarm purpose and the other stage for
trip purpose. When the temperature increases to the alarm value, thermal overload protection
issues alarm signal to remind the operator for attention, and if the temperature continues to
increase to the trip value, thermal overload protection issues trip command.
There are four thermal overload protection elements at most equipped at each side of transformer.
Thermal overload protection adopts IEC 60255-8 as thermal time characteristic, and fundamental
current or 1st to 11th harmonic current is used for protection calculation.
The device provides a thermal overload model which is based on the IEC60255-8 standard.
t Refer to IEC60255-8
Ip
P=—
IB
P = 0.0
P = 0.6
P = 0.8
P = 0.9
kIB I
Date: 2022-01-17
3 Protection Functions
There are two types of thermal time characteristic, cold start characteristic and hot start
characteristic. The thermal overload formulas are shown as below.
I eq
t ln Equation 3.15-1
I eq (k I B )
t ln
I eq I p
Equation 3.15-2
3
I eq (k I B )
Where:
τ is the thermal time constant of the protected device, i.e. [x.49.Tau]. When the current I eq is lower
than 0.04In, the thermal time constant adopts the value of [x.49.Tau]*[x.49.C_Disspt].
IP is the steady-state load current prior to the overload for a duration which would result in
constant thermal level (duration is greater than several time constant τ), which is memory current.
For cold start characteristic, it is zero.
ln is natural logarithm.
The hot start characteristic is adopted in the device. The calculation is carried out at zero of I P, so
users need not to set the value of IP.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value
is greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclose, will operate.
2. Method 2
The actual windings temperature can be gained by oil temperature, which is measured by external
transducer (Pt100), plus temperature difference between windings temperature and oil
temperature, i.e.,
The temperature difference can be calculated according to the current, and is changed with the
current. When the current is increased from 0 to I, the temperature accumulation complies with
the following equation.
t
I
T _ Diff [ x.49.K _ T _ Diff ] ( ) (1 e )
[ x.49.Ib _ Set ]
I
T _ Diff [ x.49.K _ T _ Diff ] ( )
[ x.49.Ib _ Set ]
3 Where:
t is time.
τ is time constant.
According to the calculated windings temperature, the user can compare it with user-defined
temperature value, and can set stage and time delay to trip or alarm by user-defined logic.
x.49
x.49.in_I3P x.49.Accu_A
x.49.Clr x.49.Accu_B
x.49.Enable .
x.49.Block .
.
x.49.Valid
x.49.Alm
Date: 2022-01-17
3 Protection Functions
3.15.5 Logic
EN [x.49.En_Trp] >=1
EN [x.49.En_Alm] &
x.49.On
SIG x.49.Enable
&
SIG x.49.Block >=1 x.49.Blocked
SIG Fail_Device
&
x.49.Valid
SIG x.49.Pkp
&
3 SIG x.Ia x.49.StA
& Timer
SET [x.49.Ib_Set] t
x.49.Alm.PhA
t
EN [x.49.En_Alm]
& Timer
t
x.49.Op.PhA
t
EN [x.49.En_Trp]
SIG x.49.Clr
SIG x.49.StA
>=1
SIG x.49.StB x.49.St
SIG x.49.StC
SIG x.49.Op.PhA
>=1
SIG x.49.Op.PhB x.49.Op
SIG x.49.Op.PhC
SIG x.49.Alm.PhA
>=1
SIG x.49.Alm.PhB x.49.Alm
SIG x.49.Alm.PhC
3.15.6 Settings
Table 3.15-3 Settings of thermal overload protection
Date: 2022-01-17
3 Protection Functions
When a fault happens to the power system, the device will operate to trip the circuit breaker, and
the fault will be isolated by opening the circuit breaker. If the circuit breaker fails to open within the
certain time due to some abnormalities (for example, low tripping pressure), the fault may cause
system stability being destroyed or electrical equipment being damaged. Breaker failure
protection is adopted to issue a backup tripping command to trip adjacent circuit breakers, and
isolate the fault as requested by the device.
According to the tripping information from the device and the auxiliary information (the current and
the circuit breaker position) of target circuit breaker, breaker failure protection constitutes the
criterion to discriminate whether the target circuit fails to open. If the criterion is confirmed, breaker
failure protection will operate to trip the target circuit breaker with the time delay [x.50BF.t_ReTrp],
trip it again with the time delay [x.50BF.t1_Op] and trip the adjacent circuit breakers with the time
delay [x.50BF.t2_Op]. As a special backup protection, breaker failure protection can quickly
isolate the fault, reduce the affected range by the fault, keep system stability and prevent
generators, transformers and other primary equipments from seriously damaged.
The current check criterion includes three kinds of current elements: phase overcurrent element,
zero-sequence overcurrent element and negative-sequence overcurrent element.
φ = A, B or C
The phase overcurrent element can be enabled or disabled by the setting [x.50BF.En_Ip]. For
single-phase initiating logic, if corresponding phase current is larger than the setting
3 [x.50BF.I_Set], the current check criterion based on phase overcurrent element meets the
condition. For three-phase initiating logic, if any phase current is larger than the setting
[x.50BF.I_Set], the current check criterion based on phase overcurrent element meets the
condition.
I2 is negative-sequence current
For single-phase initiating logic, if corresponding phase circuit breaker is in closed position, the
contact check criterion meets the condition. For three-phase initiating logic, if any phase circuit
breaker is in closed position, the contact check criterion meets the condition.
For breaker failure protection, phase-segregated re-trip, two phases inter-trip three phases,
three-phase re-trip and two time delays are available.
Date: 2022-01-17
3 Protection Functions
1. Phase-segregated re-trip
When the re-tripping is initiated by two-phase failure, two phase inter-trip three-phases
operates to trip three-phase circuit breaker. When the re-tripping is initiated by three-phase
failure, three-phase re-trip operates to trip three-phase circuit breaker.
2. Three-phase re-trip 3
For non phase-segregated tripping system, breaker failure protection provides three-phases
re-trip function. When breaker failure protection receives initiating signal of three-phases
tripping and the current check criterion or the contact check criterion meets the condition, the
device will issue three-phases tripping command to re-trip the target circuit breaker with the
time delay [x.50BF.t_ReTrp].
As similar as three-phase re-trip, the device will operate to re-trip the target circuit breaker
again with the time delay [x.50BF.t1_Op] when the relevant operating criterion is satisfied. It
can be enabled by the setting [x.50BF.En_t1].
As similar as three-phase re-trip, the device will operate to trip the adjacent circuit breakers
with the time delay [x.50BF.t2_Op] when the relevant operating criterion is satisfied. It can be
enabled by the setting [x.50BF.En_t2].
In addition, breaker failure protection provides an independent initiating function via the circuit
breaker position. The input signal "x.50BF.ExTrp_WOI" is energized, normally closed
auxiliary contact of the circuit breaker is chosen to trigger the timer of breaker failure
protection. When the initiating signal of breaker failure protection is energized for longer than
10s, an alarm signal "x.50BF.Alm_Init" will be issued, and will drop out with a time delay of
10s.
x.50BF
x.50BF.in_I3P x.50BF.Op_ReTrpA
x.50BF.Enable x.50BF.Op_ReTrpB
x.50BF.Block x.50BF.Op_ReTrpC
x.50BF.ExTrpA x.50BF.Op_ReTrp3P
x.50BF.ExTrpB x.50BF.Op_t1
3 x.50BF.ExTrpC x.50BF.Op_t2
x.50BF.ExTrp3P x.50BF.On
x.50BF.ExTrp_WOI x.50BF.Blocked
x.50BF.BI_52b_PhsA x.50BF.Valid
x.50BF.BI_52b_PhsB x.50BF.StA
x.50BF.BI_52b_PhsC x.50BF.StB
x.50BF.StC
x.50BF.St
x.50BF.Alm_Init
Date: 2022-01-17
3 Protection Functions
3.16.4 Logic
EN [x.50BF.En] &
x.50BF.On
SIG x.50BF.Enable
&
SIG x.50BF.Block >=1 x.50BF.Blocked
SIG Fail_Device
&
x.50BF.Valid
SIG x.50BF.Valid
EN [x.50BF.En_3I0_1P] >=1
&
SET x.3I0>[x.50BF.3I0_Set]
& >=1
Current/Contact check
EN [x.50BF.En_CBPos]
(A, B, C)
SIG x.IA>[x.50BF.I_Set]
>=1
SIG x.IB>[x.50BF.I_Set]
SIG x.IC>[x.50BF.I_Set]
&
EN [x.50BF.En_Curr]
&
EN [x.50BF.En_CBPos]
SIG x.50BF.BI_52b_PhsA
&
SIG x.50BF.BI_52b_PhsB
SIG x.50BF.BI_52b_PhsC
Date: 2022-01-17
3 Protection Functions
EN [x.50BF.En_ReTrp]
&
SIG Current/Contact check (A) & [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpA
x.50BF.StA
&
SIG Current/Contact check (B) & [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpB
x.50BF.StB
&
SIG Current/Contact check (C) & [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpC
x.50BF.StC
SIG x.50BF.ExTrpA
>=2
>=1
&
[x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrp3P
3
& >=1
SIG x.50BF.ExTrpB
>=1 x.50BF.St
>=1
SIG x.50BF.ExTrpC
&
SIG Current/Contact check
EN [x.50BF.En_Ip]
&
[x.50BF.t1_Op] 0 x.50BF.Op_t1
EN [x.50BF.En_t1]
&
[x.50BF.t2_Op] 0 x.50BF.Op_t2
EN [x.50BF.En_t2]
SIG x.50BF.Alm_Init
&
EN [x.50BF.En_ReTrp] [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrp3P
SIG x.50BF.ExTrp3P
&
SIG Current/Contact check
EN [x.50BF.En_Ip]
SIG x.50BF.ExTrp3P
&
EN [x.50BF.En_3I0_3P] &
SET 3I0>[x.50BF.3I0_Set]
>=1
3 EN [x.50BF.En_I2_3P] &
& >=1 &
[x.50BF.t1_Op] 0 x.50BF.Op_t1
SET I2>[x.50BF.I2_Set]
SIG x.50BF.ExTrp_WOI
& >=1
EN [x.50BF.En_CB_Ctrl] x.50BF.St
SIG x.50BF.BI_52b_PhsA
&
SIG x.50BF.BI_52b_PhsB
SIG x.50BF.BI_52b_PhsC
EN [x.50BF.En_t1]
&
[x.50BF.t2_Op] 0 x.50BF.Op_t2
EN [x.50BF.En_t2]
3.16.5 Settings
Table 3.16-3 Settings of breaker failure protection
Date: 2022-01-17
3 Protection Functions
Disabled
Enabling/disabling zero-sequence 3
13 x.50BF.En_3I0_3P - Disabled overcurrent element of breaker failure
Enabled
protection via three-phases initiating signal
Enabling/disabling negative-sequence
Disabled
14 x.50BF.En_I2_3P - Disabled overcurrent element of breaker failure
Enabled
protection via three-phases initiating signal
Enabling/disabling breaker failure protection
Disabled
15 x.50BF.En_CB_Ctrl - Disabled be initiated by normally closed contact of
Enabled
circuit breaker
Disabled Enabling/disabling abnormality check of
16 x.50BF.En_Alm_Init - Disabled
Enabled breaker failure initiating signal
Disabled Enabling/disabling current check criterion of
17 x.50BF.En_Curr - Enabled
Enabled breaker failure protection
Disabled Enabling/disabling contact check criterion of
18 x.50BF.En_CBPos - Disabled
Enabled breaker failure protection
In the power system, some abnormal conditions can generate high voltage, which may damage
the insulation performance of transformers, capacitors, motors and transmission lines, resulting in
equipment damage. Phase overvoltage protection can effectively detect the overvoltage that may
be generated in the system.
The device can provide two stages of phase overvoltage protection with independent logic. When
a high voltage occurs in the system, phase overvoltage protection will operate to isolate the fault
from the system after a time delay if the voltage is greater than the setting. In addition, phase
overvoltage protection also provides the alarm function to notify that there is the overvoltage in the
system and find the cause timely to prevent from further deterioration of the fault.
Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [x.59Pi.Opt_Up/Upp]. “1-out-of-3” or “3-out-of-3” logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages)
Phase overvoltage protection can be enabled or disabled via the settings or the signals, for some
specific applications, phase overvoltage protection needs to be blocked by the external signal, so
the device provides a function block input signal to be used to block phase overvoltage protection.
In addition, if the local-side VT is out of service, phase overvoltage protection will be disabled.
EN [x.59Pi.En] &
3 x.59Pi.On
SIG x.59Pi.Enable
SIG x.59Pi.Block
&
>=1 x.59Pi.Blocked
SIG Fail_Device
SIG x.BI_En_VT
Date: 2022-01-17
3 Protection Functions
SET [x.59Pi.Opt_Up/Upp]=Upp
SET x.Uab>U_DropOut
>=1
SET x.Ubc>U_DropOut &
SET x.Uca>U_DropOut
SET [x.59Pi.Opt_1P/3P]=1P
&
SET [x.59Pi.Opt_1P/3P]=3P >=1
SET x.Uab>U_DropOut
&
&
SET x.Ubc>U_DropOut
SET x.Uca>U_DropOut
SET x.Ua>U_DropOut
>=1
3
SET x.Ub>U_DropOut &
SET x.Uc>U_DropOut
SET [x.59Pi.Opt_1P/3P]=1P
SIG x.59Pi.On
SIG x.59Pi.Valid
&
FD.Pkp
SET [x.59Pi.Opt_Trp/Alm]=Alm
Phase overvoltage protection can operate with a fixed time delay. It can also operate with
inverse-time characteristics. Phase overvoltage protection can support definite-time
characteristics, IEC & ANSI standard inverse-time characteristics and user-defined inverse-time
characteristics, which are determined by the setting [x.59Pi.Opt_Curve] (i=1 or 2). The
relationship between the setting and the characteristics curve is shown in the table below.
Definite-time characteristics
When x.U>[x.59Pi.U_Set], phase overvoltage protection operates with a time delay [x.59Pi.t_Op],
the operating characteristics curve is as shown in Figure 3.17-3.
[x.59Pi.t_Op]
U
[x.59Pi.U_Set]
Inverse-time characteristics
When x.U>[x.59Pi.U_Set], phase overvoltage protection begins to accumulate, and the operating
time is affected by the applied voltage x.U. The operating time will decrease with the voltage
increasing, but the operating time shall not less than the setting [x.59Pi.tmin] (i=1 or 2). The
inverse-time operating characteristics equation is:
K
t={ α + C} × TMS
x. U
( ) −1
UP
Where:
Date: 2022-01-17
3 Protection Functions
[x.59Pi.tmin]
U
[x.59Pi.U_Set] UD
When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overvoltage protection is shown in the following equation.
T0
1
∫ dt = 1
t(x. U)
0
Where:
The supported dropout characteristics of phase overvoltage protection include instantaneous and
definite-time characteristics.
Instantaneous characteristics
Definite-time characteristics
Start time
x.U>[x.59Pi.U_Set]
x.59Pi.St
3 x.59Pi.Op
Operating counter
[x.59Pi.t_DropOut]
[x.59Pi.t_DropOut] [x.59Pi.t_DropOut]
Dropout time
Dropout time
x.59Pi
x.59Pi.in_U3P x.59Pi.St
x.59Pi.Enable x.59Pi.StA
x.59Pi.Block x.59Pi.StB
x.59Pi.StC
x.59Pi.Op
X.59Pi.Op.PhA
x.59Pi.Op.PhB
x.59Pi.Op.PhC
x.59Pi.On
x.59Pi.Blocked
x.59Pi.Valid
x.59Pi.Alm
Date: 2022-01-17
3 Protection Functions
3.17.4 Logic
SET [x.59Pi.Opt_Up/Upp]=Upp
SET x.Uab>[x.59Pi.U_Set]
>=1
SET x.Ubc>[x.59Pi.U_Set] &
SET x.Uca>[x.59Pi.U_Set]
SET [x.59Pi.Opt_1P/3P]=1P
&
SET [x.59Pi.Opt_1P/3P]=3P >=1 >=1
SET x.Uab>[x.59Pi.U_Set]
&
&
3 SET x.Ubc>[x.59Pi.U_Set]
SET x.Uca>[x.59Pi.U_Set]
SET [x.59Pi.Opt_Up/Upp]=Up
SET x.Ua>[x.59Pi.U_Set]
>=1
SET x.Ub>[x.59Pi.U_Set] &
SET x.Uc>[x.59Pi.U_Set]
SET [x.59Pi.Opt_1P/3P]=1P
&
SET [x.59Pi.Opt_1P/3P]=3P >=1
SET x.Ua>[x.59Pi.U_Set]
&
& x.59Pi.St
SET x.Ub>[x.59Pi.U_Set]
& Timer
SET x.Uc>[x.59Pi.U_Set] t
&
t
SIG x.59Pi.Pkp x.59Pi.Op
SET [x.59Pi.Opt_Trp/Alm]=Trp
&
x.59Pi.Alm
SET [x.59Pi.Opt_Trp/Alm]=Alm
3.17.5 Settings
Table 3.17-3 Settings of phase overvoltage protection
Date: 2022-01-17
3 Protection Functions
3 If an earth fault happens to the feeder in the grounding system via high resistance, the residual
current changes little and is difficult to detect. However, the amplitude of the residual voltage
changes significantly and can be used to detect the earth fault. In addition, the transformer is
grounded via the gap in the neutral point, the residual voltage increases once a fault occurs, so
residual overvoltage protection can also be used as backup protection of the transformer. The
residual voltage can be measured from broken-delta VT, and it can also be calculated internally by
the device using three-phase voltage.
EN [x.59Gi.En] &
x.59Gi.On
SIG x.59Gi.Enable
SIG x.59Gi.Block
&
>=1 x.59Gi.Blocked
SIG Fail_Device
SIG x.BI_En_VT
Date: 2022-01-17
3 Protection Functions
SET [x.59Gi.Opt_3U0]=Ext
0 500ms &
SIG x.59Gi.On
x.59Gi.Pkp
SIG x.59Gi.Valid &
FD.Pkp
3
SET [x.59Gi.Opt_Trp/Alm]=Alm
[x.59Gi.t_Op]
U0
[x.59Gi.3U0_Set]
Instantaneous characteristics
Definite-time characteristics
Start time
3 x.3U0>[x.59Gi.3U0_Set]
x.59Gi.St
x.59Gi.Op
Operating counter
[x.59Gi.t_DropOut]
[x.59Gi.t_DropOut] [x.59Gi.t_DropOut]
Dropout time
Dropout time
59G
x.59Gi.in_U3P x.59Gi.St
x.59Gi.in_U1P x.59Gi.Op
x.59Gi.Enable x.59Gi.On
x.59Gi.Block x.59Gi.Blocked
x.59Gi.Valid
x.59Gi.Alm
Date: 2022-01-17
3 Protection Functions
3.18.4 Logic
SET [x.59Gi.Opt_3U0]=Ext
&
x.59Gi.Alm
SET [x.59Gi.Opt_Trp/Alm]=Alm
3.18.5 Settings
Table 3.18-3 Settings of residual overvoltage protection
3 6 x.59Gi.En
Disabled
- Enabled
Enabling/disabling stage i of residual
Enabled overvoltage protection (i=1 or 2)
Enabling/disabling stage i of residual
overvoltage protection operate to trip or
Trp
7 x.59Gi.Opt_Trp/Alm - Trp alarm (i=1 or 2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose
In the power system, some abnormal conditions will lead to low voltage. Electric equipment such
as motors cannot operate for a long time under the rated voltage and need to be isolated from the
system timely. In addition, the voltage decreasing may be related to the shortage of system
reactive power. Shedding some reactive loads through phase undervoltage protection can
improve the voltage level of the system.
The device can provide two stages of phase undervoltage protection with independent logic.
When the voltage drops in the system and it is lower than the setting, phase undervoltage
protection will operate to isolate the fault from the system after a time delay. In addition, phase
undervoltage protection also provides the alarm function to notify that there is the undervoltage in
the system and find the cause timely to prevent from further deterioration of the fault.
Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [x.27Pi.Opt_Up/Upp]. “1-out-of-3” or “3-out-of-3” logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages). The circuit breaker position with/without the current condition can be as an
auxiliary criterion for phase undervoltage protection, which can be configured via the setting
[x.27Pi.Opt_LogicMode].
Phase undervoltage protection can be enabled or disabled via the settings or the signals, for
Date: 2022-01-17
3 Protection Functions
some specific applications, phase undervoltage protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block phase undervoltage
protection. In addition, if the local-side VT is out of service, phase undervoltage protection will be
disabled.
EN [x.27Pi.En] &
x.27Pi.On
SIG x.27Pi.Enable
SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Upp
SET x.Uab<U_DropOut
&
SET x.Ubc<U_DropOut
SET x.Uca<U_DropOut
>=1
&
SET [x.27Pi.Opt_1P/3P]=1P
SET x.Uab<U_DropOut
>=1
SET x.Ubc<U_DropOut
SET x.Uca<U_DropOut
SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Up
SET x.Ua<U_DropOut
&
SET x.Ub<U_DropOut >=1
>=1 Voltage criterion
SET x.Uc<U_DropOut
&
SET [x.27Pi.Opt_1P/3P]=1P
SET x.Ua<U_DropOut
>=1
SET x.Ub<U_DropOut
SET x.Uc<U_DropOut
SET [x.27Pi.Opt_LogicMode]=None
SET [x.27Pi.Opt_LogicMode]=Curr
SIG x.Ia>0.04In
&
SIG x.Ib>0.04In
& >=1
SIG x.Ic>0.04In
SIG x.27Pi.52a
3 >=1
& >=1
>=1 Auxiliary criterion
SET [x.27Pi.Opt_LogicMode]=CurrOrCBPos
&
&
SET [x.27Pi.Opt_LogicMode]=CurrAndCBPos
SIG x.27Pi.On
SIG x.27Pi.Valid
SET [x.27Pi.Opt_Trp/Alm]=Alm
Phase undervoltage protection can operate with a fixed time delay. It can also operate with
inverse-time characteristics. Phase overvoltage protection can support definite-time
characteristics, IEC & ANSI standard inverse-time characteristics and user-defined inverse-time
characteristics, which are determined by the setting [x.27Pi.Opt_Curve] (i=1 or 2). The
relationship between the setting and the characteristics curve is shown in the table below.
Date: 2022-01-17
3 Protection Functions
Definite-time characteristics 3
When U<[x.27Pi.U_Set], phase undervoltage protection operates with a time delay [x.27Pi.t_Op],
the operating characteristics curve is as shown in Figure 3.19-3.
[x.27Pi.t_Op]
U
[x.27Pi.U_Set]
Inverse-time characteristic
K
t={ + C} × TMS
x. U α
1−(U )
P
Where:
t
3
[x.27Pi.tmin]
U
UD [x.27Pi.U_Set]
When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase undervoltage protection is shown in the following equation.
T0
1
∫ dt = 1
t(x. U)
0
Where:
Instantaneous characteristics
Date: 2022-01-17
3 Protection Functions
Definite-time characteristics
Start time
x.U<[x.27Pi.U_Set]
3
x.27Pi.St
x.27Pi.Op
Operating counter
[x.27Pi.t_DropOut]
[x.27Pi.t_DropOut] [x.27Pi.t_DropOut]
Dropout time
Dropout time
x.27Pi
x.27Pi.in_U3P x.27Pi.St
x.27Pi.Enable x.27Pi.StA
x.27Pi.Block x.27Pi.StB
x.27Pi.52a x.27Pi.StC
x.27Pi.LiveCur x.27Pi.Op
3 X.27Pi.Op.PhA
x.27Pi.Op.PhB
x.27Pi.Op.PhC
x.27Pi.On
x.27Pi.Blocked
x.27Pi.Valid
x.27Pi.Alm
Date: 2022-01-17
3 Protection Functions
3.19.4 Logic
SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Upp
SET x.Uab<[x.27Pi.U_Set]
&
SET x.Ubc<[x.27Pi.U_Set]
SET x.Uca<[x.27Pi.U_Set]
&
>=1
3
SET [x.27Pi.Opt_1P/3P]=1P
SET x.Uab<[x.27Pi.U_Set]
>=1
SET x.Ubc<[x.27Pi.U_Set]
SET x.Uca<[x.27Pi.U_Set]
SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Up
SET x.Ua<[x.27Pi.U_Set]
&
SET x.Ub<[x.27Pi.U_Set] >=1
SET x.Uc<[x.27Pi.U_Set]
>=1
&
SET [x.27Pi.Opt_1P/3P]=1P
SET x.Ua<[x.27Pi.U_Set]
>=1
SET x.Ub<[x.27Pi.U_Set]
SIG x.27Pi.On
SIG x.27Pi.Pkp
&
x.27Pi.Op
SET [x.27Pi.Opt_Trp/Alm]=Trp
&
x.27Pi.Alm
SET [x.27Pi.Opt_Trp/Alm]=Alm
3.19.5 Settings
Table 3.19-3 Settings of phase undervoltage protection
3 Up
by phase undervoltage
protection
2 x.27Pi.Opt_Up/Upp - Upp
Upp Up: phase voltage
Upp: phase-to-phase
voltage
(i=1 or 2)
The option of auxiliary
criterion mode for
phase undervoltage
protection
None: no check
Curr: check current
condition
None
CBPos: check normally
Curr
open auxiliary contact
3 x.27Pi.Opt_LogicMode CBPos - CurrAndCBPos
CurrOrCBPos: check
CurrOrCBPos
current condition or
CurrAndCBPos
normally open auxiliary
contact
CurrAndCBPos: check
current condition and
normally open auxiliary
contact
(i=1 or 2)
The voltage setting for
stage i of phase
4 x.27Pi.U_Set 5.000~120.000 V 80.000
undervoltage protection
(i=1 or 2)
The dropout coefficient
for stage i of phase
5 x.27Pi.K_DropOut 1.000 ~1.200 - 1.030
undervoltage protection
(i=1 or 2)
The operating time
6 x.27Pi.t_Op 0.100~100.000 s 1.000
delay for stage i of
Date: 2022-01-17
3 Protection Functions
8 x.27Pi.En_VTS_Blk
Disabled
Enabled
- Disabled
is blocked by VT circuit
failure when VT circuit
3
supervision is enabled
and VT circuit fails (i=1
or 2)
Enabling/disabling
Disabled stage i of phase
9 x.27Pi.En - Enabled
Enabled undervoltage protection
(i=1 or 2)
Enabling/disabling
stage i of phase
undervoltage protection
Trp
10 x.27Pi.Opt_Trp/Alm - Trp operate to trip or alarm
Alm
(i=1 or 2)
Trp: for tripping purpose
Alm: for alarm purpose
The option of operating
ANSIDefTime
characteristics curve for
IECDefTime
11 x.27Pi.Opt_Curve - IECDefTime stage i of phase
UserDefine
undervoltage protection
InvTime_U
(i=1 or 2)
The option of dropout
characteristics curve for
stage i of phase
undervoltage protection
Inst
12 x.27Pi.Opt_Curve_DropOut - Inst (i=1 or 2)
DefTime
Inst: instantaneous
dropout characteristics
DefTime: definite-time
dropout characteristics
Time multiplier setting
for stage i of
13 x.27Pi.TMS 0.040~20.000 - 1.000
inverse-time phase
undervoltage protection
3 undervoltage protection
(i=1 or 2)
The constant “α” for
stage i of customized
16 x.27Pi.Alpha 0.0100~3.0000 - 0.0200 inverse-time phase
undervoltage protection
(i=1 or 2)
The constant “C” for
stage i of customized
17 x.27Pi.C 0.0000~1.0000 - 0.0000 inverse-time phase
undervoltage protection
(i=1 or 2)
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The increase of frequency indicates that
the output power of the system is much larger than that of the load. When the system frequency is
greater than the predefined setting, the overfrequency protection will operate for removing some
part of active power supplies from the system.
The device can provide four stages of overfrequency protection. If the system frequency is greater
than the setting, overfrequency protection will operate to remove some part of active power
supplies from the system. Overfrequency protection is with independent definite-time
characteristics and with instantaneous dropout characteristics.
Overfrequency protection can be enabled or disabled by the settings and the signals. For some
specific applications, overfrequency protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block overfrequency protection.
Date: 2022-01-17
3 Protection Functions
EN [81Oi.En] &
81Oi.On
SIG 81Oi.Enable
&
SIG 81Oi.Block >=1 81Oi.Blocked
SIG Fail_Device
&
81Oi.Valid
SIG 81Oi.Valid
&
FD.Pkp
SET [81Oi.Opt_Trp/Alm]=Alm
[81Oi.t_Op]
f
[81Oi.f_Set]
FreqCal
FreqCal.in_U3P FreqCal.FREQ
f
3 FreqCal.df/dt
81Oi
81Oi.In_FREQ 81Oi.St
81Oi.In_U3P 81Oi.Op
81Oi.Enable 81Oi.On
81Oi.Block 81Oi.Blocked
81Oi.Valid
81Oi.Alm
Date: 2022-01-17
3 Protection Functions
&
SET Upp_min>[81.Upp_Blk] [81Oi.t_Op] 0
SIG 81Oi.Pkp
&
81Oi.Alm
SET [81Oi.Opt_Trp/Alm]=Alm
&
81Oi.Op
SET [81Oi.Opt_Trp/Alm]=Trp
3.20.5 Settings
Table 3.20-3 Settings of overfrequency protection
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The decrease of frequency indicates that
the output power of the system is much less than that of the load. When the system frequency is
less than the predefined setting, the underfrequency protection will operate for shedding some
part of loads from the system.
3 The device can provide four stages of underfrequency protection. If the system frequency is less
than the setting, underfrequency protection will operate to shedding some part of loads from the
system. Underfrequency protection is with independent definite-time characteristics and with
instantaneous dropout characteristics.
Underfrequency protection can be enabled or disabled by the settings and the signals. For some
specific applications, underfrequency protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block underfrequency protection.
EN [81Ui.En] &
81Ui.On
SIG 81Ui.Enable
&
SIG 81Ui.Block >=1 81Ui.Blocked
SIG Fail_Device
&
81Ui.Valid
SIG 81Ui.Valid
&
FD.Pkp
SET [81Ui.Opt_Trp/Alm]=Alm
Date: 2022-01-17
3 Protection Functions
[81Ui.t_Op].
[81Ui.t_Op]
3
f
[81Ui.f_Set]
FreqCal
FreqCal.in_U3P FreqCal.FREQ
FreqCal.df/dt
81Ui
81Ui.in_FREQ 81Ui.St
81Ui.in_U3P 81Ui.Op
81Ui.Enable 81Ui.On
81Ui.Block 81Ui.Blocked
81Ui.Valid
81Ui.Alm
3.21.4 Logic
&
SET Upp_min>[81.Upp_Blk] [81Ui.t_Op] 0
SIG 81Ui.Pkp
&
81Ui.Alm
SET [81Ui.Opt_Trp/Alm]=Alm
&
81Ui.Op
SET [81Ui.Opt_Trp/Alm]=Trp
Date: 2022-01-17
3 Protection Functions
3.21.5 Settings
Table 3.21-3 Settings of underfrequency protection
4 81Ui.En
Disabled
-
Enable Enabling/disabling stage i of underfrequency 3
Enabled d protection (i=1~4)
Enabling/disabling stage i of underfrequency
81Ui.Opt_Trp/ Trp protection operate to trip or alarm (i=1~4)
5 - Trp
Alm Alm Trp: for tripping purpose
Alm: for alarm purpose
Frequency rate-of-change protection is used to detect the power system frequency changes
(increase and decrease). And the frequency rate-of-change can reflect the balance between the
generated active power and the consumed active power. When the frequency changes too fast, it
is generally considered that the system has a fault, and the frequency rate-of-change protection
can operate in such a situation.
The device can provide two stages of frequency rate-of-change protection. If the system
frequency rate-of-change is greater than the setting, frequency rate-of-change protection will
operate. Frequency rate-of-change protection is with independent definite-time characteristics
and with instantaneous dropout characteristics.
Frequency rate-of-change protection can operate to trip or alarm. For some specific applications,
frequency rate-of-change protection needs to be blocked by the external signal, so the device
provides an input signal to be used to block frequency rate-of-change protection.
EN [81Ri.En] &
81Ri.On
SIG 81Ri.Enable
&
SIG 81Ri.Block >=1 81Ri.Blocked
SIG Fail_Device
&
81Ri.Valid
SIG [81Ri.df/dt_Set]>0
&
SET df/dt>[81Ri.df/dt_Set] >=1
SET Upp_min>[81.Upp_Blk]
SIG [81Ri.df/dt_Set]<0
&
SET df/dt<[81Ri.df/dt_Set]
SET Upp_min>[81.Upp_Blk]
&
0 500ms &
SIG 81Ri.On 81Ri.Pkp
3 SIG 81Ri.Valid
&
FD.Pkp
SET [81Ri.Opt_Trp/Alm]=Alm
[81Ri.t_Op]
-df/dt df/dt
-[81Ri.df/dt_Set] 0 [81Ri.df/dt_Set]
Date: 2022-01-17
3 Protection Functions
FreqCal
FreqCal.in_U3P FreqCal.FREQ
FreqCal.df/dt
81Ri
81Ri.In_FREQ 81Ri.St 3
81Ri.In_U3P 81Ri.Op
81Ri.Enable 81Ri.On
81Ri.Block 81Ri.Blocked
81Ri.Valid
81Ri.Alm
3.22.4 Logic
SIG [81Ri.df/dt_Set]>0
&
SET df/dt>[81Ri.df/dt_Set] &
SET Upp_min>[81.Upp_Blk]
SIG f>[81Ri.f_Pkp]
3 SIG [81Ri.df/dt_Set]<0
& >=1
SET df/dt<[81Ri.df/dt_Set] &
SET Upp_min>[81.Upp_Blk]
81Ri.St
SIG f<[81Ri.f_Pkp]
&
[81Ri.t_Op] 0
SIG 81Ri.Pkp
&
81Ri.Alm
SET [81Ri.Opt_Trp/Alm]=Alm
&
81Ri.Op
SET [81Ri.Opt_Trp/Alm]=Trp
3.22.5 Settings
Table 3.22-3 Settings of frequency rate-of-change protection
Date: 2022-01-17
3 Protection Functions
When phase overcurrent protection and earth fault protection can’t meet the sensitivity
requirement of transformer backup protection, distance protection may be configured. The
operation mode of power system has little effect on impedance protection, so distance protection
cooperates with protections of the adjacent equipment more easily.
Distance protection includes three independent phase-to-phase measuring loops and three
independent phase-to-ground measuring loops. Both mho and quadrilateral characteristics are
available for different application. In addition, load encroachment, power swing blocking and
releasing, and faulty phase selection functions are also provided. 3
3.23.1 Functions Description
Up to 4 distance protection zones are supplied for high- and middle-voltage side of transformer
respectively. Each zone includes three independent phase-to-phase measuring loops and three
independent phase-to-ground measuring loops. Phase-to-ground distance element can be
compensated by zero-sequence current of local line. The distance protection zones can operate,
independent of each other, in forward direction, reverse direction or non-direction.
Load encroachment can distinguish effectively between heavily loaded line and faulty line, and the
risk of encroachment of the load impedance into the tripping characteristics of the distance
protection can be excluded.
Power swing blocking and releasing can prevent distance protection from undesired operation
during power swing, even if measured impedance reaches into the operation area of distance
protection. Moreover, distance protection can operate reliably when a fault occurs during power
swing.
The current amplitude is calculated based on the injected analogue quantities. The fault detector
continuously detects the change of phase-to-phase power frequency current and the calculated
zero-sequence and negative-sequence currents. The fault detector includes:
1. Fault detector based on DPFC current: DPFC current is greater than the setting value
2. Fault detector based on zero-sequence current: Zero-sequence current is greater than the
setting value
If any of the above conditions is satisfied, the fault detector will operate to start distance protection
calculation.
I(k-24) is the value of the sampling point before a cycle, 24 is the sampling points cycle.
3 200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
0 20 40 60 80 100 120
DPFC current
From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection. It is used to determine
whether this pickup condition is met according to Equation 3.23-1.
For multi-phase short-circuit fault, DPFC phase-to-phase current has high sensitivity to
ensure the pickup of protection device. For usual single phase to earth fault, it also has
sufficient sensitivity to pick up except the earth fault with very large fault resistance. Under
this condition, DPFC current may be very small and the sensitivity is reduced, however,
zero-sequence current is used to remedy the reduction of the sensitivity.
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steady under normal or power swing
condition, the adaptive floating threshold with the ΔISet is higher than the change of current
under these conditions and hence maintains the element stability.
Where:
ΔIΦΦMAX: The maximum half-wave integration value of phase-to-phase current (ΦΦ=AB, BC,
CA)
Date: 2022-01-17
3 Protection Functions
The coefficient, 1.25, is an empirical value which ensures that the threshold is always higher
than the unbalance current of the system.
If operation condition are satisfied, the fault detector based on DPFC current will operate. The
pickup signal will maintain 5s after the fault detector based on DPFC current drops off.
The operation condition will be satisfied when zero-sequence current (3I0) is greater than the
setting [x.FD.ROC.3I0_Set]. The fault detector based on zero-sequence current is always in 3
service. (3I0: zero-sequence current is calculated from the vector sum of Ia, Ib and Ic)
If operation condition are satisfied, the fault detector based on zero-sequence current will
operate. The pickup signal will maintain 5s after the fault detector based on zero-sequence
current drops off.
The operation condition will be satisfied when negative-sequence current (I2) is greater than
the setting [x.FD.NOC.I2_Set].
If operation condition are satisfied, the fault detector based on negative-sequence current will
operate. The pickup signal will maintain 5s after the fault detector based on
negative-sequence current drops off.
For forward direction or reverse direction close-in fault, the voltage of faulty phase is 0, the
measured impedance of faulty phase is located in the origin of R-X plane, so it can’t be
distinguished as forward direction or reverse direction fault if not handled.
For solving the problem, the positive-sequence voltage is used as polarized voltage to distinguish
between forward direction fault and reverse direction fault. As shown in Figure 3.23-1 and Figure
3.23-2, line OA and line OE are named direction line which has good direction characteristics with
positive-sequence voltage as the polarized voltage.
U̇1
−β ≤ Arg ≤ 90° + α Equation 3.23-2
İ
U̇1
180° − β ≤ Arg ≤ 270° + α Equation 3.23-3
İ
Where:
jX
B Z_Set
θ D
C
Dꞌ
A
α
φ φ
R
R_Offset O β R_Set
E
jX
E
R_Set β O R_Offset
R
φ φ
α
A
Dꞌ C
θ
B
D Z_Set
Date: 2022-01-17
3 Protection Functions
jX
B Z_Set
D
C
φ φ φ
R
R_Offset R
φ O
3
A
Z_Offset E
Where:
θ is downward offset angle of the reactance line, which is used to prevent distance protection from
overreaching.
For forward direction or reverse direction close-in three-phase fault, positive-sequence voltage is
almost 0, so the dead zone of distance protection for a close-in three-phase fault must be
eliminated. Memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltages adopts 2 cycles pre-fault positive-sequence voltage.
When the memory fades out, the operating characteristics will be shifted toward forward direction
or reverse direction, as shown in Figure 3.23-4 and Figure 3.23-5.
jX
B Z_Set
θ D
C
Dꞌ
A α
φ φ
O R
R_Offset β R_Set
ZShift
3 E
jX
B Z_Set
θ D
C
A
Dꞌ
α ZShift
E φ
R_Offset φ R
β R_Set
O
For reverse direction distance element, the similar treatment as forward direction distance
element can be adopted, by rotating the operation characteristics of forward direction distance
element 180°, the operating characteristics of reverse direction distance element can be gained.
For forward direction or reverse direction close-in fault, the voltage of faulty phase is almost 0, and
the measured impedance of faulty phase is located in the origin of R-X plane. Positive-sequence
voltage is used as polarized voltage to distinguish between forward direction fault and reverse
direction fault.
Phase comparison equation of forward direction distance element and reverse direction distance
element is:
U̇OP∅
−90° ≤ Arg ≤ 90°
U̇P∅
Where:
Date: 2022-01-17
3 Protection Functions
U̇ is phase voltage.
İ is phase-to-phase current.
U̇ is phase voltage.
U̇ is phase-to-phase voltage.
İ is phase-to-phase current.
U̇ is phase voltage.
U̇ is phase-to-phase voltage.
İ is phase-to-phase current.
Non direction distance element adopts offset characteristics and does not use
jX
Z
θ
C
D
3 φ
R
O
jX
φ R
θ
Z
jX
Z_Set
R
φ O
Z_Offset
Date: 2022-01-17
3 Protection Functions
Where:
θ is downward offset angle of the reactance line, which is used to prevent distance protection from
overreaching.
For the fault in forward direction, the operating characteristics of phase-to-ground distance
element is shown in Figure 3.23-9. Operating characteristics on R-X plane is a circle with line 3
connecting ends of Z_Set and -2ZS/3 as the diameter. The origin is enclosed in the circle.
jX
Z_Set
R
O
-2Zs/3
Where:
For the fault in forward direction, the operating characteristics of phase-to-phase distance element
is shown in Figure 3.23-10. Operating characteristics on R-X plane is a circle with line connecting
ends of Z_Set and -ZS/2 as the diameter. The origin is enclosed in the circle.
jX
Z_Set
R
O
-Zs/2
3
Figure 3.23-10 Phase-to-phase operating characteristics for forward fault
For the fault in reverse direction, the operating characteristics is shown in Figure 3.23-11. This
characteristics is a circle with line connecting ends of Z_Set and Z' S as the diameter.
ZꞋs
jX
Z_Set
R
O
Where:
Z'S is total impedance between remote system and protective device location.
For reverse direction distance element, its operating characteristics can be gained by rotating the
operating characteristics of forward direction distance element 180°.
For forward direction or reverse direction close-in three-phase fault, positive-sequence voltage is
also 0, so the dead zone of distance protection for a close-in three-phase fault must be eliminated.
Memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltages adopts 2 cycles pre-fault positive-sequence voltage. When the memory fades out, the
operating characteristics will be shifted toward forward direction or reverse direction.
For the fault in forward direction, as shown in Figure 3.23-12, C1 is the operating characteristics
Date: 2022-01-17
3 Protection Functions
before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is enclosed in the impedance circle.
jX
Z_Set
φ
O
C2
R
3
Zs C1
For the fault in reverse direction, as shown in Figure 3.23-13, C1 is the operating characteristics
before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is not enclosed in the impedance circle.
ZꞋs
jX
C1
Z_Set
C2
φ
O
R
The distance protection with such design thoroughly eliminates the dead zone when three-phase
close-in fault occurs. It also has favorable directivity and will not operate for a reverse three-phase
fault at busbar.
For three-phase transmission line, the faulty phase is affected by the current of non-faulty phase
due to the mutual inductance among phase-to-phase conductors.
ZL
ZM
IA
IB ZM
IC
UC UB UA
Where:
ZL is line impedance
ZL1 = ZL − ZM
ZL0 = ZL + 2ZM
ZL0 − ZL1
ZM =
3
Z −Z ZL0 −ZL1
Hence, U̇A = İA × ZL1 + (İA + İB + İC ) × L0 3 L1 = (İA + 3İ0 × 3×Z ) × ZL1
L1
ZL0 − ZL1
K0 =
3 × ZL1
For parallel double-circuit lines, due to mutual inductance of zero-sequence current from the
adjacent line, phase-to-ground characteristics of distance protection will be affected.
Date: 2022-01-17
3 Protection Functions
ZL1
Z
I
3I0I ZM0
II
3I0II
Where: 3
3I0I is residual current of line I.
Due to mutual inductance of zero-sequence current from the adjacent line, the error item 3İ0II ×
ZM0 is imported. According to the actual application, K 0 and the setting range of distance
protection shall be adjusted reasonably to avoid undesired operation.
When distance protection is used to protect long, heavily loaded lines, the risk of encroachment of
the load impedance into the tripping characteristics of the distance protection may exist. A load
encroachment characteristics for all zones is used to exclude the risk of unwanted fault detected
by distance protection during heavy load flow. As shown in Figure 3.23-16, if the measured
impedance locate in the load area, distance protection will be blocked.
jX
φLoad φLoad
Load Area Load Area
R
O
RLoad RLoad
Two settings are equipped to exclude the encroachment of the load impedance:
When power swing occurs on the power system, the impedance measured by the distance
measuring element may vary from the load impedance area into the operating zone of the
3 distance element. The distance measuring element may operate due to the power swing occurs at
many points of interconnected power systems. To keep the stability of whole power system,
tripping due to operation of the distance measuring element during a power swing is generally not
allowed. Distance protection adopts power swing blocking releasing to avoid maloperation
resulting from power swing. In another word, distance protection is blocked all along under the
normal condition and power swing when the respective logic settings are enabled. Only when fault
(internal fault or power swing with internal fault) is detected, power swing blocking for distance
protection is released by PSBR element.
Power swing blocking for distance element will be released if any of the following PSBR elements
operates. Each distance zone elements has respective setting for selection this function.
If any of the following condition is matched, FD PSBR will operate for 160ms.
Positive sequence current is lower than the setting [x.21T.I_PSBR] before general fault
detector element operates.
As shown in figure below, assuming that normal load impedance locates at position 1 and the
impedance locates at position 2 when positive-sequence current is lower than the setting
[x.21T.I_PSBR], it means FD operates between point 1 and point 2 if operation condition for
FD PSBR mentioned above is fulfilled (point 3 as an example), and then FD PSBR will
operate for 160ms.
[x.21T.I_PSBR]
FD Normal load
impedance
Point 1
Point 2
Point 3
Date: 2022-01-17
3 Protection Functions
I0+I2>m×I1
The “m”, an empirical value, is internal fixed coefficient which can ensure UF PSBR operation
during power swing with internal unsymmetrical fault, while no operation during power swing
or power swing with external fault.
In case of power swing but no fault, I0 and I2 are near zero, but I1 is very large.
Asymmetric fault discriminating element will not operate.
In case of both power swing and external fault, if center of power swing is in scope of
protection, both phase-to-phase and grounding impedance relays may operate. At this
time, selection of value of m is used to ensure no operation of asymmetric fault
discriminating element, blocking of distance protection, and no incorrect operation
without selectivity. If power swing center is not on this line, distance protection will not
operate incorrectly without selectivity due to power swing.
In case of both power swing and internal fault, if at the instant of short circuit, system
electric potential angle is not laid out, asymmetric fault discriminating element will
operate at once. If at the instant of short circuit, system electric potential angle is laid out,
asymmetric fault discriminating element will operate when system angle gradually
decreases, or local side tripping may be activated after immediate operation of opposite
side asymmetric fault discriminating element and releasing of distance protection tripping.
In case of normal internal asymmetric phase-to-phase or grounding fault in the system,
relatively large zero-sequence or negative-sequence component will exist. At this time,
the above equation is true and distance protection will be released.
If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD
PSBR nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is
provided for this case specially. This detection is based on measuring the voltage at power
swing center, during power swing, U1cosΦ will constantly change periodically.
UOS=U1×COSΦ
Where:
As shown in the figure below, assume system connection impedance angle of 90°, current
vector will be perpendicular to the line connecting E M and EN, and have the same phase as
power swing center voltage. During normal operation of system or power swing, U1cosΦ just
reflects positive-sequence voltage of power swing center. In case of 3-phase short circuit,
U1cosΦ is voltage drop on arc resistor, transition resistance is arc resistance, and voltage
drop on arc resistor is less than 5%UN. In actual system, line impedance angle is not 90°.
Through compensation of angle Φ, power swing center voltage can be measured accurately.
I
EM U EN
UOS
During power swing, power swing center voltage U1cosΦ has the following characteristics:
When electric potential phase angle difference between power supplies at two sides is 180 o,
U1cosΦ=0 and change rate dU1cosΦ/dt is the maximum. When this phase angle difference
is near 0o, power swing center voltage change rate dU 1cosΦ/dt is the minimum. During short
circuit, U1cosΦ remains unchanged and dU1cosΦ/dt=0. However, in early stage of short
circuit when normal state enters short circuit state, dU1cosΦ/dt is very large. Therefore, use
of dU1cosΦ/dt solely to differentiate power swing and short circuit is not complete.
For these reasons, the method to release distance protection on condition that power swing
center voltage U1cosΦ is less than a setting and after a short delay can be used as symmetric
fault discriminating element. This element can accurately differentiate power swing and
3-phase short circuit fault, and constitute a complete power swing blocking scheme with other
elements. The element to open distance protection if U 1cosΦ is less than a certain setting
and after a delay is easy to realize and has short delay, and can trip fault more quickly and
accurately trip 3-phase short circuit fault during power swing.
The second criterion is a backup of the first criterion allowing longer monitoring period of
voltage variation.
To reduce the time delay for SF PSBR element during power swing, the change rate of
voltage at power swing center is also used which can release SF PSBR element quickly for
Date: 2022-01-17
3 Protection Functions
the fault occurred during power swing. The typical release time is less than 60ms.
The realization of phase-segregated tripping and fault location depends on the faulty phase
selection. Each zone of distance protection contains three phase-to-ground measuring elements
and three phase-to-phase measuring elements, so non-faulty phase maybe operates when there
is a fault. For example, for near-end phase A fault, phase A distance element operates, while
phase AB and phase CA distance element are also possible to operate. Therefore, the faulty
phase selection of distance protection cannot only depend on the operating phase of distance
protection.
For single-phase fault, three phase-to-ground distance elements, three phase-to-phase distance
3
elements and the angle relation between I0 and I2A can effectively distinguish faulty phase. As
shown in Figure 3.23-17,
I
−60° < 𝐴𝑟𝑔 I 0 < 60° region A is selected
2A
I
60° < 𝐴𝑟𝑔 I 0 < 180° , region B is selected
2A
I
180° < 𝐴𝑟𝑔 I 0 < 300° , region C is selected
2A
Region A
60° -60°
Region B Region C
180°
Zero-sequence current is used to distinguish between earth fault and phase-to-phase fault. For
earth fault, associating the angle relation between I0 and I2A, the operating phase of distance
protection can determine faulty phase. For phase-to-phase fault, the faulty phase is detected by
comparing the relative relationship of distance protection operating.
For each distance protection zone, the three phase-to-ground distance elements share the same
time relay, and the three phase-to-phase distance elements share the same time relay.
When there is a transferring fault, operating time of distance protection with time delay is subject
to the beginning of the first fault. For example:
If the time delay of zone 2 of phase-to-ground distance element is set as 400ms, zone 2 of
phase-to-ground distance element will operate at T=400ms not T=500ms. However, time delay of
each distance protection zone is independent.
x.21T.FD
x.21T.FD.in_U3p x.21T.FD.Pkp
x.21T.FD.in_I3p x.21T.FD.DPFC.Pkp
x.21T.FD.ROC.Pkp
x.21T.FD.NOC.Pkp
x.21T.FD.Alm_Pkp
x.21T
x.21T.Enable x.21T.On
x.21T.Block x.21T.Blocked
x.21T.FwdDir_ZeroSeq x.21T.Valid
x.21T.RevDir_ZeroSeq
x.21T.FwdDir_NegSeq
x.21T.RevDir_NegSeq
Date: 2022-01-17
3 Protection Functions
x.21Ti
x.21Ti.Enable x.21Ti.On
x.21Ti.Block x.21Ti.Op
x.21Ti.ZG.Enable x.21Ti.Op.PhA
x.21Ti.ZG.Block x.21Ti.Op.PhB
x.21Ti.ZP.Enable x.21Ti.Op.PhC
x.21Ti.ZP.Block x.21Ti.ZG.LoadEnch.St
x.21Ti.Enable_PSBR x.21Ti.ZG.LoadEnch.StA 3
x.21Ti.Block_PSBR x.21Ti.ZG.LoadEnch.StB
x.21Ti.ZG.LoadEnch.StC
x.21Ti.ZP.LoadEnch.St
x.21Ti.ZP.LoadEnch.StAB
x.21Ti.ZP.LoadEnch.StBC
x.21Ti.ZP.LoadEnch.StCA
Date: 2022-01-17
3 Protection Functions
3.23.4 Logic
Calculate negative-
sequence current: x.I2
x.I2>[x.21T.FD.NOC.I2_Set] x.21T.FD.NOC.Pkp 3
SIG x.21T.FD.Pkp 50s 10s x.21T.FD.Alm_Pkp
SIG Fail_Device
&
x.21T.Valid
SIG x.21T.Valid
&
SIG x.21Ti.Enable
SIG x.21Ti.Block
EN [x.21Ti.ZG.En]
& &
& x.21Ti.ZG.Enabled
SIG x.21Ti.ZG.Enable
SIG x.21Ti.ZP.Block
SIG x.VTS.Alm
&
>=1 x.21Ti.ZP.Enabled
SIG x.BI_En_VT &
EN [x.En_VT]
SIG x.21Ti.ZG.Enabled
&
SIG x.21T.FD.Pkp x.21Ti.Flag.ZG
EN [x.21Ti.ZG.En_3I0] >=1
SET 3I0>[FD.ROC.3I0_Set]
EN [x.21Ti.ZG.En_NeuDir_Blk]
SET [x.21Ti.DirMode]=Forward
&
& & x.21Ti.Flg_PSBR_ZG
>=1
SIG x.50/51G.DIR.Rev
3 SET [x.21Ti.DirMode]=Reverse &
SIG x.50/51G.DIR.Fwd
EN [x.21Ti.ZG.En_NegDir_Blk]
&
SET [x.21Ti.DirMode]=Forward & &
>=1
SIG x.50/51Q.DIR.Rev
SIG x.50/51Q.DIR.Fwd
SIG x.21Ti.ZG.StA
&
SET x.Ia>0.04In
SIG x.21Ti.LoadEnchPG.StA
SIG x.21Ti.ZG.StB
& >=1
SET x.Ib>0.04In
SIG x.21Ti.LoadEnchPG.StB
SIG x.21Ti.ZG.StC
&
SET x.Ic>0.04In
SIG x.21Ti.LoadEnchPG.StC
Date: 2022-01-17
3 Protection Functions
SIG x.21Ti.ZP.Enabled
&
SIG x.21T.FD.Pkp x.21Ti.Flag.ZP
EN [x.21Ti.ZP.En_NegDir_Blk]
SIG x.50/51Q.DIR.Fwd
SIG x.21Ti.ZP.StAB
3
&
SET x.Iab>0.04In
SIG x.21T.LoadEnchPP.StAB
SIG x.21Ti.ZP.StBC
& >=1
SET x.Ibc>0.04In
SIG x.21T.LoadEnchPP.StBC
SIG x.21Ti.ZP.StCA
&
SET x.Ica>0.04In
SIG x.21T.LoadEnchPP.StCA
"x.21Ti.ZP.StAB" means that zone i of phase-to-phase distance element starts. (phase AB)
"x.21Ti.ZP.StBC" means that zone i of phase-to-phase distance element starts. (phase BC)
"x.21Ti.ZP.StCA" means that zone i of phase-to-phase distance element starts. (phase CA)
&
[x.21Ti.ZP.t_Op] 0 x.21Ti.ZP.Op
SIG x.21Ti.Flag.ZP
SIG x.21Ti.Flg_PSBR
>=1
&
SIG |I0|+|I2|>m×I1
SIG x.21Ti.Flg_PSBR
"x.21Ti.Rls_PSBR" is the releasing signal of power swing blocking element for zone i of distance
protection.
"x.21Ti.Flg_PSBR_ZG" is the operating condition of power swing blocking element for zone i of
phase-to-ground distance element.
"x.21Ti.Flg_PSBR_ZP" is the operating condition of power swing blocking element for zone i of
phase-to-phase distance element.
3.23.5 Settings
Table 3.23-3 Settings of distance protection
Date: 2022-01-17
3 Protection Functions
Date: 2022-01-17
3 Protection Functions
Output map controls tripping outputs of protection elements and programmable logics. Each
protection element has its corresponding tripping logic setting used to configure tripping output
contacts, and 120 tripping outputs of programmable logics are equipped for visual logic
programming.
All tripping output contacts are with a settable dwell time to ensure sufficient time of tripping
command to open the circuit breaker.
Each protection element can control total 32 groups of tripping output contacts by tripping logic
settings. Therefore, the user can configure the tripping output contacts of each protection element
individually though the corresponding tripping logic setting. 32 groups of independent tripping
output contacts can be defined to trip HV side, MV side, and LVS side etc. Each group of tripping
contacts can correspond to certain amount of contacts on binary output plug-in modules.
Tripping logic settings are used to specify which breakers will be tripped when some protection
element operates. This logic setting comprises 32 binary bits as follows and is expressed by a
hexadecimal number of 8 digits from 00000000H to FFFFFFFFH. The tripping logic setting is
specified as follows:
“Output001” just means to drive the 1st group of tripping output contacts and please refer to
Chapter “Hardware”. The tripping outputs are recorded as “Output001_OutMap ~
Output032_OutMap” by the device when they operate, and “Outputxxx” (xxx=001, 002…032)
represents “trip output xxx” (xxx=001, 002…032). The circuit breaker corresponding with bit which
is set as “1” will be tripped. Tripping output logic settings should be set on basis of
application-specific drawings.
The device provides 120 programmable trip output with I/O signals and settings for users used by
visualization programming.
For example, if it is required to set stage 1 of phase overcurrent protection at HV side of the
transformer operate to issue trip command after its operation criterion is satisfied “AND” receiving
a binary input which can be a blocking signal from other device, programmable trip output can
complete the function configuration as following steps.
Date: 2022-01-17
3 Protection Functions
2. Connect final output of programming logic to input signal of programmable trip output.
3. Set corresponding tripping logic setting of programmable trip output to complete the function
configuration.
3.24.3 Settings
3
Table 3.24-2 Settings of programmable trip output
4 Control Functions
Table of Contents
4 List of Figures
Figure 4.2-1 Relationship between reference and synchronous voltages ....................... 4-12
Figure 4.3-1 Voltage wiring diagram of 1 CB with 2 busbars (1-phase bus voltage) ....... 4-21
Figure 4.3-2 Voltage wiring diagram of 1 CB with 2 busbars (3-phase bus voltage) ....... 4-21
Figure 4.3-4 Voltage selection logic diagram of 1 CB with 2 busbars (1-phase bus voltage)
................................................................................................................................................... 4-24
Figure 4.3-5 Voltage selection logic diagram of 1 CB with 2 busbars (3-phase bus voltage)
................................................................................................................................................... 4-25
Figure 4.3-6 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing bus CB)
................................................................................................................................................... 4-25
Date: 2022-01-17
4 Control Functions
Figure 4.3-7 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing tie CB)
................................................................................................................................................... 4-26
Figure 4.4-1 Diagram of conversion from DC analog input to TPI ..................................... 4-27
Figure 4.4-2 Logic diagram of manual control of tap position ........................................... 4-30
Figure 4.4-3 Logic diagram of control operation of tap position changer ........................ 4-30
Figure 4.5-3 IDMT operating characteristic curve of the initial tap change command of
ATCC ......................................................................................................................................... 4-35
Figure 4.5-5 Logic diagram of automatic/manual mode switch of voltage regulation .... 4-36 4
Figure 4.5-6 Logic diagram of under voltage of ATCC ........................................................ 4-37
Figure 4.5-12 Equivalent circuit diagram of line voltage drop ........................................... 4-40
Figure 4.5-13 Vector diagram for compensation of line voltage drop ............................... 4-40
Figure 4.5-14 Logic diagram of ATCC tap change command ............................................. 4-43
Figure 4.6-4 Logic diagram of PVR general blocking signal .............................................. 4-50
List of Tables
Table 4.2-1 Input signals of manual closing synchronism check ...................................... 4-14
Table 4.2-2 Output signals of manual closing synchronism check ................................... 4-14
Table 4.4-1 Input signals of tap position indication and control ........................................ 4-28
Table 4.4-2 Output signals of tap position indication and control..................................... 4-28
4 Table 4.4-3 Settings of tap position indicator ...................................................................... 4-31
Date: 2022-01-17
4 Control Functions
The switchgear control function is mainly used to realize operation of primary equipment such as
circuit breaker (CB), disconnect switch (DS) and earthing switch (ES). This function can be
divided into remote control and local control according to the control source location. A remote
control mainly refers to remote control commands from substation automation system (SAS) or
network control centre (NCC). However, a control triggered manually from the device LCD, by a
terminal contact or by a panel handle is a local control. The switchgear control function is closely
related to interlocking, double point status (DPS), remote/local control mode switching and trip
counter.
A control command can realize various control signals such as the CB/DS/ES opening/closing. In
order to ensure the reliability of the control output, a locking circuit is added to each control object.
The operation is strictly in accordance with the selection, check and execution steps, to ensure
that the control operation can be safely and reliably implemented. In addition, the device has a 4
hardware self-checking and blocking function to prevent hardware damage from maloperation
output.
When the device is in the remote-control mode, the control command may be sent via
communication protocol; when it is in the local control mode, the local operation may be
performed on the device LCD or panel handle.
3. If the selection is successful, the protocol module sends an execution command, otherwise it
sends a cancel command;
When the device is in the maintenance status, it can still respond to local control commands.
The switchgear control function can cooperate with functions such as synchronism check and
interlocking criteria calculation to complete the output of the corresponding operation command. It
can realize the normal control output in one bay and the interlocking and programmable logic
configuration between bays.
Module Description
CSWI Control of circuit breaker (CB), disconnector switch (DS) or earthing switch (ES)
RMTLOC Remote or local control mode
XCBR Synthesis of CB position, three-phase or phase separated
XSWI Synthesis of DS/ES position
Module Description
SXCBR/SCSWI Trip counter of CB/DS/ES
RSYN Synchronism check for CB closing
CILO Interlocking logic for CB/DS/ES control
MCSWI Manual control of CB/DS/ES
CHKPOS Position verification for switchgear control
The initiation of a control command may be sent to the device by the SCADA or the NCC through
communication protocol. It may also be the operation of the device LCD or the manual triggering
through configured signal. The command is sent by the CPU to the control module for processing,
and a control record is made on the CPU module according to the control result.
The remote/local control mode switch function determines whether the device is in the remote or
the local control permission state through the configuration of terminal contact, function key, or
binary signal. Each control object provides a remote/local input, and the control module
determines the current control authority to be remote or local according to the input value. By
default, if the input is not configured, any control operation is blocked.
A double point status (DPS), which usually indicates switchgear status, can be derived from 2
ordinary binary inputs. The signification of a DPS is shown in the following table. For switchgear
status, only the 2 statuses "01" and "10" indicating respectively the positions opening and closing
are valid. The other 2 statuses "00" and "11", i.e. intermediate or bad status, will cause the alarm
"DPS.Alm".
Date: 2022-01-17
4 Control Functions
For the convenient use in user-defined logic programming, this functional module derives four
single-bit outputs to indicate each DPS state.
Indication Signal
DPS_ON DPS_OFF DPS_INT DPS_BAD
DPS State
ON 1 0 0 0
OFF 0 1 0 0
INT 0 0 1 0
BAD 0 0 0 1
This unit also supports the DPS synthesis through switchgear opening and closing positions after
jittering processing. The synthetic DPS contains original SOE timestamp. The CB control function
supports phase-segregated position inputs and can synthesize these inputs into general position.
4
In accordance with the control object, the DPS synthesis function is divided into 2 modules: XCBR
and XSWI. The XCBR is mainly used for CB position synthesis, including phase-segregated
positions, while the XSWI is used DS or ES position synthesis.
The trip counter function takes the DPS of switchgear position as input count the trip times. For
CB, this device supports phase-segregated and general trip counter. The trip counter function is
triggered by DPS change. The counting result is stored in non-volatile memory for power-off
holding.
Use the clear command from the menu in local LCD or customized binary signal to reset trip
counter.
4.1.1.4 Interlocking
The interlocking function will influence the control operation output. When the function is enabled,
the device determines whether the control operation is permitted based on the interlocking logic
result. Each control object is equipped with an independent interlocking logic which supports
unlocking operation through a binary signal.
The interlocking function is very important for the control operation of switchgears. During the
operation of primary equipment, the positions of the relevant equipment must be correct for
operation permission. For remote control, i.e. command from SAS or NCC, this device could
detect the interlocking logic depending on the message within the command; for local control
through device LCD or terminal contact, please use the corresponding logic setting to
enable/disable the interlocking function.
The switchgear control function supports manual control function that can be configured with a
The manual control function supports the control input configuration of selection and open/close
operations. When the control object selection input is configured, the signal "1" indicates that the
current control object has to be selected before a control operation; if the control object selection
input is not configured, the control command can be directly issued without judgment of selection.
The position verification function is provided during switchgear control process. In a control
function block of circuit breaker, disconnector or earthing switch, if the input “in_CheckPos_En” is
set as 1, the CB/DS/ES position shall be verified when receiving a remote or local control
command.
The device shall respond control command failed with the cause of failure when its DPS is
INT, BAD or opposite (i.e. OPEN while opening or CLOSE while closing).
For applications such as signal reset and function enable/disable, the control mode is generally
direct control, i.e. execution without selection before, direct control with normal security in IEC
61850.
The direct control function provides remote/local switch and interlocking configurations. The
control command is usually issued directly by the SAS. It also supports the command triggered by
binary signal.
Date: 2022-01-17
4 Control Functions
The prefix CB** for circuit breaker, DS** for disconnector switch and
DirCtrl** for direct control in the following lists are hidden since their
description (if valid) are similar.
4 12
13
in_Pos_C_NC
in_N_Trp
Phase C normally closed contact input for DPS closing position
Opening command for trip counter
14 in_N_Trp_A Phase A opening command for trip counter
15 in_N_Trp_B Phase B opening command for trip counter
16 in_N_Trp_C Phase C opening command for trip counter
17 in_Clr_Cnt Clear trip counters
18 in_Rsyn Structure pointer of synchronism check element
19 in_EnaOpn Opening permission for interlocking
20 in_EnaCls Closing permission for interlocking
21 in_CILO_Bypass Bypass for interlocking
22 in_Manual_Sel Selection for manual control
23 in_Manual_Opn Opening for manual control
24 in_Manual_Cls Closing for manual control
25 in_CheckPos_En Input signal of enabling of position verification function for switchgear control
Date: 2022-01-17
4 Control Functions
4.1.4 Logics
The prefix CB** for circuit breaker and DS** for disconnector switch in the
following diagrams are hidden since their logics (if valid) are similar.
EN [CB**.En_CILO_Cls] >=1
SIG CB**.Cls_Enabled
&
SIG CB**.25.RSYN_OK
>=1
SIG CB**.25.SynChk_Enabled &
SIG CB**.25.DdChk_Enabled
4
EN [DS**.En_CILO_Cls] >=1
SIG DS**.Cls_Enabled
EN [XXXX.En_CILO_Opn] >=1
SIG XXXX.Opn_Enabled
Date: 2022-01-17
4 Control Functions
SIG XXXX.DPS_A = ON
&
SIG XXXX.DPS_B = ON XXXX.DPS = ON
SIG XXXX.DPS_C = ON
EN [XXXX.DPS.En_Alm]
EN [XXXX.En_CILO_Opn] >=1
EN [XXXX.En_CILO_Cls]
SIG in_Manual_Opn
&
SIG Opn_Enabled Cmd_ManOpn
SIG in_Manual_Cls
>=1
SIG in_Manual_Sel &
SIG in_Manual_Cls
&
SIG Cls_Enabled Cmd_ManCls
4.1.5 Settings
Table 4.1-4 Settings of DPS settings
Date: 2022-01-17
4 Control Functions
The purpose of synchronism check is to ensure two systems are synchronous before they are
going to be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus, closing operation is
applied with the synchronism check to avoid this situation and maintain the system stability. The
synchronism check includes synchro-check and dead charge check.
4.2.1.1 Synchro-check
The comparative relationship between the reference voltage and the synchronization voltage for
synchro-check is as follow. Furthermore, the measured three-phase voltages for synchro-check
should not exceed the overvoltage threshold [25.U_OV] or lag the undervoltage threshold
[25.U_UV].
U_Ref
U_Syn
This figure shows the characteristics of synchro-check element used for CB closing if both
reference and synchronous sides are live. The element operates if the voltage difference,
frequency difference, frequency variation difference and phase angle difference are all within their
setting ranges.
The voltage difference between the reference side and the synchronous side is checked by
the following equations
The frequency difference between the reference side and the synchronous side is checked
by the following equations
|f(U_Ref)-f(U_Syn)| ≤ [25.f_Diff_Set]
df/dt ≤ [25.df/dt_Set]
Date: 2022-01-17
4 Control Functions
The phase difference between the reference voltage and the synchronization voltage is
checked by the following equation
∆δ ≤ [25.phi_Diff_Set]
The dead charge check mode checks either the reference side or the synchronization voltage.
Several dead charge check modes are supported in using the setting [25.Opt_Mode_DdChk]. The
device compares the reference side and the synchronization voltages at both ends of a circuit
breaker with the settings [25.U_LvChk] and [25.U_DdChk]. When the voltage is higher than
[25.U_LvChk], the corresponding side is regarded as live. When the voltage is lower than
[25.U_DdChk], the corresponding side is regarded as dead.
If one of the following conditions is met, the synchro-check for CB closing is enabled. 4
[25.Opt_ValidMode] = Setting, [25.En_SynChk] = Enabled;
If one of the following conditions is met, the dead charge check for CB closing is enabled.
If none of synchro-check and dead charge check is enabled, the synchronism check for CB
closing is disabled.
The synchronism check function is suitable for several applications. According to different
application scenarios, user needs to configure different voltage input channel. For both the
reference side and the synchronous side, the voltage input channel may be single phase or
three-phase.
While configuring through the PCS-Studio software, user can configure three-phase or
single-phase voltage channel for reference and synchronous sides inputs.
In the meantime, the voltage selection logic can be adopted for the synchronism check input
channel, please refer to the corresponding section.
4
4.2.3 I/O Signals
Table 4.2-1 Input signals of manual closing synchronism check
Date: 2022-01-17
4 Control Functions
4.2.4 Logics
EN [25.Opt_ValidMode] = Config
&
SIG 25.in_syn_chk
SIG 25.in_vol_chk
SIG 25.DdChk_Enabled
SIG in_25_Bypass
SIG in_25_Blk
SIG in_SYN_Blk
SET df/dt [25.df/dt_Set]
1
SET [25.En_df/dt_Chk] = Disabled
SET ΔU [25.U_Diff_Set]
SET Δf [25.f_Diff_Set]
1
SET [25.En_f_Diff_Chk] = Disabled
1 25.SynChk_OK
SET Δδ [25.phi_Diff_Set] &
SET U_Ref [25.U_UV]
SET U_Ref [25.U_OV]
1
SET U_Syn [25.U_UV]
SET U_Syn [25.U_OV]
Date: 2022-01-17
4 Control Functions
SET [25.Opt_Mode_DdChk]
criteria selection
Dead check
SIG 25.SynDd
4 SIG in_Lv_Blk
&
SIG 25.SynLv
4.2.5 Settings
Table 4.2-3 Settings of synchronism check
Date: 2022-01-17
4 Control Functions
25.Opt_Mode_DdChk
4 SynDdRefDd Dead check for both the reference and the synchronous sides
SynLvRefDd Live check for synchronous side and dead check for reference side
SynDdRefLv Dead check for synchronous side and live check for reference side
SynLvRefDd/SynDdRefLv Option 2 or 3
AnySideDd Option 1, 2 or 3
The voltage selection function can be used to switch the reference and synchronization voltages
of synchronism check in double busbars and one-and-half circuit breakers application scenarios,
or to switch three-phase voltages of both busbars for the use in protection calculation or
measurement.
By default, this device adopts the principle of proximity in built-in voltage selection logic. Moreover,
it supports customized selection logic. The default voltage selection logic is automatically disabled
if the customized voltage selection logic is correctly configured.
The customized selection result may be derived from any source binary signals, such as binary
inputs, isolators status and programmable logic output signals.
If voltage selection logic fails, the alarm "x.VoltSel.Alm_Invalid_Sel" will be issued and the
selection output remains unchanged.
For single circuit breaker with double busbars, the selection of appropriate voltage from both
busbars for synchronism check is required. Line VT input is taken as reference.
Date: 2022-01-17
4 Control Functions
Bus2
Bus1
DS1 DS2
UB1
UB2
DS1.DPS
CB
DS2.DPS
Ua
UL1 Ub
Line
Uc
Figure 4.3-1 Voltage wiring diagram of 1 CB with 2 busbars (1-phase bus voltage)
4
For single circuit breaker with double busbars, the selection of three-phase voltage from both
busbars is used as reference voltage of synchronism check. Single-phase voltage from line
VT is the synchronization voltage.
Bus2
Bus1
DS1 DS2
Ua
UB1 Ub
Uc
Ua
UB2 Ub
Uc
CB
DS1.DPS
DS2.DPS
UL1
Line
Figure 4.3-2 Voltage wiring diagram of 1 CB with 2 busbars (3-phase bus voltage)
For a bus side CB of one-and-half breakers arrangement in the application scenario of double
circuit breakers, the selection of voltage from Line1_VT, Line2_VT and the other bus side VT
is the synchronization voltage to be synchronized with the reference voltage of local bus side.
For the tie CB of one-and-half breakers arrangement in the application scenario of double
circuit breakers, the selection of voltage from Line1_VT & Bus1_VT and Line2_VT &
Bus2_VT is the reference voltage and synchronization voltage respectively to check
synchronism for the closing operation.
Bus1
UB1
Bus1_CB.DPS Bus1_CB
Line 1
Ua
UL1 Ub
Uc DS1
DS1.DPS
Tie_CB.DPS Tie_CB
Line 2
UL2
4 DS2.DPS
DS2
Bus2_CB.DPS Bus2_CB
UB2
Bus2
Date: 2022-01-17
4 Control Functions
4.3.4 Logics
&
Alm_Invalid_Sel
UB1 U_Syn
Single-phase voltage of busbars for
synchronization side
UB2
Figure 4.3-4 Voltage selection logic diagram of 1 CB with 2 busbars (1-phase bus voltage)
Date: 2022-01-17
4 Control Functions
&
Alm_Invalid_Sel
UB1 U_Ref
Three-phase voltage of busbars for reference side
UB2
Figure 4.3-5 Voltage selection logic diagram of 1 CB with 2 busbars (3-phase bus voltage)
SIG DS2.DPS=ON
SIG DS1.DPS=OFF
&
SIG Tie_CB.DPS=ON UB2_Sel
UL1
UL2 U_Syn
UB2
UB1 U_Ref
Figure 4.3-6 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing bus CB)
UL1 Uref
UB1
4 UL2 Usyn
UB2
&
>=1
& Alm_Invalid_Sel
Figure 4.3-7 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing tie CB)
4.3.5 Settings
Table 4.3-3 Settings of voltage selection
A tap changer is a connection point selection mechanism along a power transformer winding that
allows a variable number of turns to be selected in discrete steps. A transformer with a variable
turn's ratio is produced, enabling stepped voltage regulation of the output. The tap selection may
be made via an automatic or manual tap changer mechanism.
Date: 2022-01-17
4 Control Functions
The Tap Position Indicator (TPI) input could be Binary-Coded Decimal (BCD), independent
contacts, carry inputs or DC analog input.
Binary input
For the BCD and the independent contacts input modes, the indicator supports
phase-segregated inputs “84.in_tap**” and phase discordance alarm(s)
“84.Alm_Invalid_TP**”. Refer to the following I/O signals and settings description for more
detail.
DC analog input
For the DC analog input mode, the indicator adopts a channel of DCAI module as the input.
By parameterization, the DC analog input range could be defined into several step segments
4
which correspond to different tap positions. Thus, the input is converted into three-phase tap
position indication.
TPI
DCAI
R-Δ R R+Δ
The [84.Value_Segment02] = 9 is set to indicate that an input within this second segment,
which is defined in the range (R-Δ, R+Δ), represents the tap position 9.
Similarly, the first segment is defined to present TPI 3 and the third segment is defined to
present TPI 5.
The control of tap changer is treated as binary outputs, including "84CSWI1.Opn" (descend),
"84CSWI1.Cls" (raise) and "84CSWI2.Opn" (emergency stop), in this device.
During a tap position control process, if the situation "tap position runaway" occurs, the power
supply of tap changer's motor mechanism should be cut off. In this device, the runaway situation
means that the tap changer is out of control to step up/down continuously (more than one step) in
one control procedure.
When [84.En_RunawayTrip] is enabled and the device executes a tap command successfully, a
supervision window will be initiated to detect whether the change of TPI is greater than "1" during
20s. If a runaway situation is conformed, the binary output "84.BO_RunawayTrip" will be issued.
4
The countdown of supervision windows starts from the rising edge of a tap
changer control execution indicating signal, i.e. "84CSWI1.Opn_Exec" or
"84CSWI1.Cls_Exec".
Date: 2022-01-17
4 Control Functions
4.4.3 Logic
SIG in_Manual_Opn
&
SIG Opn_Enabled Cmd_ManOpn
4 SIG in_Manual_Cls
>=1
SIG in_Manual_Sel &
SIG in_Manual_Cls
&
SIG Cls_Enabled Cmd_ManCls
EN [84CSWI*.En_CILO_Cls] >=1
SIG 84CSWI*.Cls_Enabled
EN [84CSWI*.En_CILO_Opn] >=1
SIG 84CSWI*.Opn_Enabled
Date: 2022-01-17
4 Control Functions
EN [84.En_RunawayTrip]
SIG 84.in_RunawayTrip
Figure 4.4-4 Logic diagram of runaway trip during tap position control process
4.4.4 Settings
Table 4.4-3 Settings of tap position indicator
4
No. Setting Range Unit Default Description
The option of the input code of tap
position indication (TPI)
Resv: direct input or DC analogue
channel
Resv BCD: 6-bit BCD for max. 39 positions
BCD Carry: 13-bit carry inputs for max. 29
Carry positions
1 84.Opt_Code - BCD
Independent Independent: 26-bit independent
BCD-PhSeg contacts for max. 26 positions
Independent-PhSeg BCD-PhSeq: 18-bit BCD for max. 39
phase-segregated positions
Independent-PhSeq: 24-bit
independent contacts for max. 8
phase-segregated positions
The Delay Pick Up (DPU) time, i.e.
2 84.t_DPU 0~6000 ms 500
debounce time, of TPI
Enabling/disabling the trip of tap
Disabled or
3 84.En_RunawayTrip - Disabled changer motor power supply during
Enabled
the situation "Tap runaway"
The holding time of output signal for
the trip of tap changer motor power
4 84.t_RunawayTrip 0~60000 ms 500
supply during the situation "Tap
runaway"
The number of the defined segment,
5 84.Num_AI_Segment 0~48 - 1 i.e. tap positions, in the DC analog
input range of TPI
The rated value corresponding to the
6 84.Rated_AI_Segment** -220.00~220.00 - 0.00
No.** segment in DC analog input
Voltage regulation function can regulate the object voltage to the pre-set target value by changing
the tap position of transformer. The device provides both automatic and manual modes of
transformer tap changer control.
The Automatic Tap Changer Control (ATCC) function can provide up to four target voltage values.
It regulates voltage by sending a raising or descending command to the tap changer of
transformer after a latency. The initial regulation can be set as definite-time or inverse-time
characteristic. The blocking criteria by limits of voltage, current, tap position, etc. are available. In
addition, the device can regulate voltage at the end of transmission line by compensating the
voltage drop according to line resistance and reactance.
URegulated
Latency3
t3 t4 t5 t6 t7
Bandwidth
UTarget
t1 t2
Latency1
TIME
t2 - t1 = Latency1
The ATCC function is triggered from t1 because the regulated voltage exceeds the bandwidth,
Date: 2022-01-17
4 Control Functions
and the Latency1 of initial tap change command starts. However, during t2-t1, the regulated
voltage returns back to the bandwidth. Thus, no command will be issued.
t4 - t3 = Latency1
The ATCC function is triggered from t3 because the regulated voltage exceeds the bandwidth,
and the Latency1 of initial tap change command starts. During t4-t3, the regulated voltage
remains to be outside of the bandwidth. Then, a step down command is issued from t4.
t5 - t4 = Latency2
The Latency2 of sequential tap change command starts from t4 because the regulated
voltage is still outside of the bandwidth after the initial command. During t5-t4, the regulated
voltage remains to be outside of the bandwidth. Then, a step down command is issued from
t5.
t6 - t5 = Latency2
The Latency2 of sequential tap change command starts from t5 because the regulated
4
voltage is still outside of the bandwidth after the previous commands. However, during t6-t5,
the regulated voltage returns back to the bandwidth. Thus, no command will be issued.
t7 - t3 = Latency3
During t7-t3, the regulated voltage returns back to the bandwidth, the ATCC function
successfully completes the task. Otherwise, the ATCC function will be blocked and the alarm
signal "90V.ReguFail_Blk" will be issued immediately.
Where:
UTarget is the target voltage value of regulation that defined by the setting [90V.U_Target_*], * can
be 1, 2, 3 or 4.
Bandwidth is the acceptable range of target voltage and is defined by the setting
[90V.U_Bandwidth].
Latency1 is the settable interval before the sending of initial command and is defined by the
setting [90V.t1_Intvl].
Latency2 is the settable interval between two times of tap change and is defined by the setting
[90V.t2_Intvl].
Latency3 is the result judgement interval of the whole process of ATCC function and is defined by
the setting [90V.t_ReguFail].
The bandwidth represents the permitted fluctuation range of measured voltage compared to the
target value. If the regulated voltage is inside of the bandwidth, no more control command will be
issued to change the tap. If the voltage exceeds the bandwidth, a tap change command shall be
issued after Latency1. Then the on-load tap-changer will carry out an operation according to the
command.
If the regulated voltage exceeds the target voltage bandwidth, and none of the blocking criteria is
met, the ATCC function initiates step up/down command automatically. The Latency1 before the
initial command is defined by the setting [90V.t1_Intvl]. A serial of commands will be sent
sequentially until the regulated voltage appears within the pre-set target voltage bandwidth. The
following Latency2 between two tap change commands is defined by the setting [90V.t2_Intvl].
TIME
Bandwidth
4
Cmd pulse
Latency2
Cmd pulse
Latency2
Cmd pulse
Latency2
Cmd pulse
Latency1
URegulated
To reduce the delay of Latency1 for the initial tap change command, the inverse-time
characteristics can be put into service by the logic setting [90V.En_IDMT]. The greater the voltage
deviation appears to the bandwidth, the shorter the time delay will be. Thus, the inverse-time
characteristics can react faster to large voltage variation. The time calculation equation is:
Latency1BandwidthU_Target
𝑡=
|ΔU|
Where:
Latency1 is the initial operating time delay of ATCC, which is defined by the setting [90V.t1_Intvl].
Bandwidth is the acceptable range of target voltage and is defined by the setting
[90V.U_Bandwidth] in percentage value.
Date: 2022-01-17
4 Control Functions
|ΔU| is the absolute value of voltage deviation which is calculated by the target voltage
“90V.U_Target” and the regulated voltage “90V.U_Regu”.
180 [90V.t1_Intvl]
120
80
40
U/B
4
Figure 4.5-3 IDMT operating characteristic curve of the initial tap change command of ATCC
This device supports four target voltage values. At a time, only one can be the valid value. The
selection function supports the priority from high (target voltage 1) to low (target voltage 4) of
these four values. It is user-programmable in using the configuration tool PCS-studio. If the four
input terminals are left blank, the selection logic hasn’t been configured. The default selected
target voltage value is then defined by [90V.U_Target_1].
&
90V.U_target_2 is seletced
SIG 90V.in_set_target2
&
90V.U_target_3 is seletced
SIG 90V.in_set_target3
&
90V.U_target_4 is seletced
SIG 90V.in_set_target4
The ATCC function can automatically send command to tap changer according to blocking criteria
in real time. Additionally, this device can switch on the manual mode of voltage regulation in using
of the tap position control function (84). The automatic mode and the manual mode of voltage
User may use the [90V.Link_Auto] setting value or the “90V.in_auto” signal state to switch the
automatic/manual mode. The device provides the input terminal “90V.in_opt_mode” for the
decision of device voltage regulation mode via logic link setting or binary input. The switching logic
is shown in the following figure.
>=1
SIG 90V.in_opt_mode 90V.Auto
&
SIG 90V.in_auto
SIG 90V.in_auto
The ATCC function judges the alarm and blocking criteria listed in the following table. If any of
them is met, the ATCC function will issue the corresponding alarm signal or even be blocked with
the general alarm signal “90V.Total_Blk”.
90V.Alm_UV /
The regulated voltage is under the ATCC function lower limit.
90V.UV_Blk Auto
90V.Alm_OV /
The regulated voltage is under the ATCC function upper limit.
90V.OV_Blk Auto
Date: 2022-01-17
4 Control Functions
The regulated voltage range is defined by the settings [90V.U_UV] and [90V.U_OV]. An
out-of-limit of such range can trigger the alarm “90V.Alm_UV” or “90V.Alm_OV” or even block
the ATCC function depending on the corresponding logic settings [90V.En_Alm_UV],
[90V.En_Alm_OV], [90V.En_UV_Blk] and [90V.En_OV_Blk].
EN 90V.En_Alm_UV &
SET 90V.U_Regu<[90V.U_UV]
10s 1s 90V.Alm_UV
4
EN 90V.En_UV_Blk &
90V.UV_Blk
SET 90V.U_Regu<[90V.U_UV]
EN 90V.En_Alm_OV &
10s 1s 90V.Alm_OV
SET 90V.U_Regu>[90V.U_OV]
EN 90V.En_OV_Blk &
90V.OV_Blk
SET 90V.U_Regu>[90V.U_OV]
90V.Alm_OC, 90V.OC_Blk
The overcurrent limit is defined by the setting [90V.I_OC]. An out-of-limit can trigger the alarm
“90V.Alm_OC” or even block the ATCC function depending on the corresponding logic
settings [90V.En_Alm_OC] and [90V.En_OC_Blk].
EN 90V.En_Alm_OC &
10s 1s 90V.Alm_OC
SET IA>[90V.I_OC]
>=1
SET IB>[90V.I_OC]
&
SET IC>[90V.I_OC]
90V.OC_Blk
EN 90V.En_OC_Blk
90V.ReguFail_Blk
Since the initial ATCC command is issued, if the regulated voltage is still out of the bandwidth
of target voltage after the timeout of the ATCC failure period defined by the setting
[90V.t_ReguFail] (see Latency3=t7-t3 in the Figure 4.5-1), the actual round of ATCC ends. At
the same time, the blocking signal “90V.ReguFail_Blk” is issued and the ATCC function is
4 blocked. The blocking state is maintained until one of the following conditions appears:
manual reset, regulated voltage return within the bandwidth or change of target voltage value.
90V.TP_OvRange_Blk
The tap position range is defined by the settings [90V.TP_Min] and [90V.TP_Max]. An
out-of-limit of such range can block the ATCC function.
90V.Quality_Blk
If there is an abnormal quality alarm of the ATCC related quantities, the ATCC function shall
be blocked. The two kinds of ATCC related quantities are: regulated voltage and current
received from merging unit; and tap position indication that is defined in the Section 4.4.1.1.
90V.N_Regu_OvLmt_Blk
In an ATCC process, if the number of issued commands within the regulation period defined
by the setting [90V.t_Period_Regu] exceeds the limit defined by the setting [90V.Num_Regu],
the actual process ends. At the same time, the blocking signal “90V.N_Regu_OvLmt_Blk” is
issued and the ATCC function is blocked. The blocking is maintained until one of the following
Date: 2022-01-17
4 Control Functions
conditions appears: manual reset, expiration of the regulation period or change of target
voltage value.
90V.ExtBlk1, 90V.ExtBlk2
The device supports the blocking of ATCC function by two external signals “90V.ExtBlk1” and
“90V.ExtBlk2”. For “90V.ExtBlk1”, the ATCC function cannot be automatically unlocked and
the manual reset is mandatory. However, the ATCC function can be automatically unlocked
after the rest of “90V.ExtBlk2”.
The logic of ATCC function general block signal and automatic/manual reset is shown in the
following figure.
Manual Reset
SIG 90V.Runaway_Blk
SIG 90V.ExtBlk1
Automatic Reset
SIG 90V.Manual_Blk
>=1
SIG 90V.Maint_Blk
SIG 90V.OC_Blk
SIG 90V.TP_OvRange_Blk
>=1
SIG 90V.Quality_Blk
SIG 90V.ExtBlk2
When transmitting electric power from transformer to load over a long distance, the load side
voltage at the end of the transmission line will drop due to line resistance and reactance. To
accurately regulate the voltage at the end of the transmission line, the ATCC function can
compensate the voltage drop according to line parameters and total active/reactive power of
transformer.
RL XL
Where:
4
UL: load side voltage
Im
UB
jXLIL Re
O UL
RLIL
Date: 2022-01-17
4 Control Functions
ATCC
in_pqcalc
in_opt_mode
in_auto
in_test
in_sel_target1
in_sel_target2
in_sel_target3
in_sel_target4
in_vts_block
in_runaway_block
in_extern1_block
in_extern2_block 4
in_manual_reset
in_tap_pos
Date: 2022-01-17
4 Control Functions
4.5.4 Logic
SIG 90V.Auto
SIG 90V.Manual
SIG 90V.Auto
SIG 90V.Manual
4.5.5 Settings
Date: 2022-01-17
4 Control Functions
When two transformers run parallel in Master-Follower mode, the follower transformer can
automatically step up/down according to the master transformer tap change command. Thus,
achieving a simultaneous voltage regulation of both transformers.
Generally, when two transformers run in parallel, their characteristics such as capacity and tap
position are the same. The two transformers interact information, such as tap position indication,
tap change blocking signal, tap change command, etc., through the GOOSE network. When the
conditions are met, the follower changes its tap position according to the master tap change
command to regulate the voltage.
When changing tap position in parallel, both the master and the follower will judge whether the tap
position indications are consistent. The judgement can be made according to the actual TPI of 4
both transformers or to the state of the programmable input signal “PVR.in_tap_match”. However,
if “PVR.in_tap_match” has been configured through the configuration tool PCS-Studio, the TPI
consistency judgement will be disabled in PVR function.
Moreover, the tap change function in reverse sequence is available. When the master raises the
tap to step up, the follower can descend its tap to step up, and vice versa. The sequence of tap
change depends on the setting value of [PVR.Opt_Dir_TP]. For example, two transformers
(adjustable tap range 1~15) run in parallel and enable the reverse sequence tap change function.
When the master’s TPI is 3, the TPI of both transformers are consistent if the follower’s TPI is 13.
For a parallel voltage regulation process, the timing coordination between master and follower is
shown in the following figure.
Master Master
[PVR.t_Wait] [PVR.t_Stable]
Master Idle state Wait for tap change Wait for stable state Idle state
operation
Follower Idle state Idle state Wait for stable state Idle state
Follower
[PVR.t_Stable]
t1 t3 t2 t4 t5 t6 t
1. t1
a) The master has successfully sent the tap change command and begins to wait for tap
position change operation during the t2-t1 period defined by the setting [PVR.t_Wait]. Its
output signal “PVR.parallel_Reday” is set as 1.
2. t2
If t3 > t2, the master will reset to idle state and this round of parallel voltage regulation is
aborted.
3. t3
a) The master’s tap change operation has completed. It begins to wait for stable state of
parallel voltage regulation and sends tap change command to the follower via GOOSE
4 communication network.
4. t4
b) The follower receives the tap change command from the master via GOOSE
communication network and begins to wait for stable state.
5. t5
a) The master’s stable state waiting period t5-t3 defined by the setting [PVR.t_Stable] is
exhausted and returns to idle state.
6. t6
b) The follower’s stable state waiting period t5-t4 defined by the setting [PVR.t_Stable] is
exhausted and return to idle state.
Stable state refers that the self BCU has completed the tap change and is
waiting for the peer BCU to complete the tap change. During such period,
the master sends GOOSE step up/down command; the follower proceeds
tap change operation.
The TPI consistency judgement of both transformers will not start until the
Date: 2022-01-17
4 Control Functions
0: Parallel; 1: Standalone.
Every time the rising edge of the input signal is received, the parallel/standalone mode is
switched once.
Every time the rising edge of the input signal is received, the master/follower mode will be
switched.
Rising edge of the input signal “PVR.in_para_master” which is linked to the output signal
“PVR.Master” of the parallel BCU via GOOSE communication to indicate its master/follower
mode.
Every time the rising edge of the input signal is received, the master/follower mode will be
switched.
PVR
in_master
in_standalone
in_para_master
in_self_tap
in_para_tap
in_self_block
in_para_block
in_goose_raise
in_goose_lower
in_inner_raise
in_inner_lower
in_tap_match
Date: 2022-01-17
4 Control Functions
4.6.4 Logic
4
SIG PVR.Standalone &
>=1
PVR.StepUpTP_Self
SIG Manual tap change cmd. PVR.StepDownTP_Self
&
SIG PVR.Master
&
SIG PVR.Total_Blk
&
SIG PVR.Total_Blk
&
SIG PVR.ChCfg_Blk
SIG PVR.Self_Blk
4.6.5 Settings
Date: 2022-01-17
5 Measurement
5 Measurement
Table of Contents
List of Figures
List of Tables
Date: 2022-01-17
5 Measurement
In the chapter, the prefix ”x” in some measurements, represents some side
or bushing of transformer defined by user through PCS-Studio software,
which may be “HVS”, “MVS”, “LVS”, “HVS2”, “MVS2”, “LVS2”, “CWS”,
“HVB”, “MVB”, “LVB”, etc. If only one protection element is equipped, the
prefix “x.” may disappear.
5.1 Overview
This device performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
11 x.Ang (Ia-Ib) Phase angle between phase A and phase B currents deg
12 x.Ang (Ib-Ic) Phase angle between phase B and phase C currents deg
13 x.Ang (Ic-Ia) Phase angle between phase C and phase A currents deg
14 x.Ang (Ua-Ub) Phase angle between phase A and phase B voltages deg
15 x.Ang (Ub-Uc) Phase angle between phase B and phase C voltages deg
16 x.Ang (Uc-Ua) Phase angle between phase C and phase A voltages deg
5
5.2.3 Sequence Components Values
Date: 2022-01-17
5 Measurement
Please find these values in Table 5.6-2 Output signals of DC measuring transducers.
11 x.Ang (Ia-Ib) Phase angle between phase A and phase B currents deg
12 x.Ang (Ib-Ic) Phase angle between phase B and phase C currents deg
13 x.Ang (Ic-Ia) Phase angle between phase C and phase A currents deg
14 x.Ang (Ua-Ub) Phase angle between phase A and phase B voltages deg
15 x.Ang (Ub-Uc) Phase angle between phase B and phase C voltages deg
16 x.Ang (Uc-Ua) Phase angle between phase C and phase A voltages deg
Date: 2022-01-17
5 Measurement
Please find these values in Table 5.6-2 Output signals of DC measuring transducers.
1 f System frequency Hz
5 7 87T.Ia_Th
Threshold value of phase-A restraint current of transformer
p.u.
differential protection.
Date: 2022-01-17
5 Measurement
Date: 2022-01-17
5 Measurement
protection
10 87W.Ib_Th
Threshold of phase-B restraint current of winding differential
protection.
In 5
Threshold of phase-C restraint current of winding differential
11 87W.Ic_Th In
protection.
Date: 2022-01-17
5 Measurement
The DC measuring transducer with an input rated at 0~±20mA or 0~±10V is optional in this device.
8 or 12 (depending on the subtype) inputs are available in one DC AI module, which can be
plugged into a plug-in module slot. Typically, slowly changing process variable such as
temperature or gas pressure are measured by such transducers.
A DC measuring transducer input typically converts a value which represents a physical quantity
such as temperature or pressure. Therefore, a characteristic curve that assigns the physical
quantity to the DC analogue value is necessary. The following figure shows an example.
Temperature (⁰C)
Tmax
P
Tmin Tp
ITransd (mA)
O ip 20
In this example, the setting of the range for the scaled value goes from a usable range of 0mA to
+20mA. The measured value 0mA means a temperature of Tmin which is defined by the setting
[B**.DCAI.Min_Transducer**] and the measured value 20mA signifies a temperature of Tmax
which is defined by the setting [B**.DCAI.Max_Transducer**]. Thus, for the actual point P, the
5 measured transducer current ip can be converted into a value of temperature.
5.6.3 Settings
Table 5.6-3 Settings of DC measuring transducers
Date: 2022-01-17
5 Measurement
6 Supervision
Table of Contents
List of Figures
List of Tables
Date: 2022-01-17
6 Supervision
6.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before
the LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore,
the automatic supervision function, which checks the health of the protection system when startup
and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
All hardware has real-time monitoring functions, such as CPU module monitoring, communication
interface status monitoring, power supply status monitoring. 6
The monitoring function of CPU module also includes processor self-check, memory self-check
and so on. The processor self-check is checked by designing execution instructions and data
operations. Check whether the processor can execute all instructions correctly, and whether it can
correctly calculate complex data operations to determine whether it works normally. For
peripherals, it can monitor the status of the interface module, check the input and output data,
send the communication interface and receive self-loop detection. Memory self-check is used to
detect unexpected memory errors in the running process. It can effectively prevent program logic
abnormality caused by memory errors.
The status monitoring of communication interface also includes Ethernet communication interface
monitoring and differential channel communication interface monitoring. By accessing the status
register of the communication interface, the state of the corresponding interface is obtained, such
as the state of connection, the number of sending frames, the number of frames received, and the
number of wrong frames. According to the statistics of the acquired interface state, it is judged
whether the interface work is abnormal.
The hardware supervision also includes the power supply status monitoring. The voltage
monitoring chip is used by all the power supplies. The reset voltage threshold is preset to the reset
monitoring circuit. When the power supply is abnormal, the voltage monitoring chip will output the
reset signal to control CPU to be in the reset state and avoid the wrong operation.
In the process of operation, the safety allowance should always be kept and no overload
phenomenon is allowed. When the user configures logic components with PCS-Studio, the
PCS-Studio automatically calculates the time required for the theoretical execution of the
configured components. When the security limit is exceeded, the PCS-Studio will indicate that the
configuration error is not allowed to download the current configuration to the device.
During the operation of the device, there is a lot of data exchange between modules. The number
of data exchanges is related to the number of logical components configured by the user. When
the configuration is too large to cause the number of data exchange to exceed the upper limit
supported by the device, the PCS-Studio prompts the configuration error.
The initialization of the device depends on the configuration files of each module. The user
configured logical components will eventually be embodied in the configuration file, limited to the
hardware memory space. When the configuration file size is more than the upper limit, the
PCS-Studio prompts the configuration error.
The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate
unexpected changes in memory caused by electromagnetic interference. The chip memory has
parity function. When an error occurs, the system can detect anomalies immediately, and
eliminate the logic abnormity caused by memory errors.
In addition to the above hardware memory reliability measures, the device software is also
constantly checking the memory during operation, including code, constant data, and so on. Once
the error detection, the system will automatically restart the restore operation. If they detect the
error immediately after the restart, it may be the result of a permanent fault locking device
hardware, only at the moment and not restart.
The reliability of the device is largely determined by the reliability of the export drive. By reading
the driving state of the binary output relay, the alarm signal will be generated and the device is
immediately blocked to prevent the relay from maloperation when the device is not given a
tripping order and the binary output relay driver is detected in the effective state.
The CPU chip needs to be able to ensure long-term stability under the permissible working
temperature of the specification. Therefore, it is necessary to monitor the working temperature
Date: 2022-01-17
6 Supervision
monitored by CPU.
The device is blocked when the actual hardware configuration is not consistent with the hardware
configuration file. Compared with pre configured modules, this device will be blocked if more
module is inserted, fewer module is inserted, and wrong modules is inserted.
1. Each hardware module configuration check code needs to be consistent with CPU module.
The device CPU module stores the configuration check codes of other modules. In initialization
procedure, it checks whether the configuration check code of each module is consistent with the
stored code in CPU module, and if it is not consistent, this device is blocked.
2. The hardware modules and process interface versions need to be consistent with the CPU
module.
If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this
moment, each hardware module and process will be upgraded synchronously, otherwise the
version of the interface will be inconsistent.
The configuration text formed by the device calibration visualization project includes checking
whether the check code is wrong or not. 6
4. Whether any setting is over the range, whether it needs to confirm the settings.
If the setting exceeds the configuration range, the device is blocked; if some settings are added, it
is necessary to confirm the new values through the LCD.
In the operation procedure, the CPU module sends a time synchronization command to other
module, each module repeats heartbeat message to the CPU module, if it does not respond or the
heartbeat is abnormal, then this device is blocked.
2. Check whether the settings of other modules are consistent with the CPU module.
The actual values of all the settings in the CPU module are initialized to send to the corresponding
slave modules. In the process of operation, the setting values stored in the CPU module and the
setting values of other modules will be checked one by one. If they are not consistent, this device
will issue the alarm signal "Fail_Settings".
The sampling circuit of this device is designed as dual-design scheme. Each analog sampling
channel is sampled by two groups of ADC. The sampling data is self checking and inter checking
in real time. If any sampling circuit is abnormal, the device reports the alarm signal "Alm_Sample",
and the protection function related to the sampling channel is disabled at the same time. When
the sampling circuit returns to normal state, the related protection is not blocked after 10s.
The secondary circuit supervision function includes current transformer supervision (CTS),
voltage transformer supervision (VTS), power supply supervision of binary inputs and
tripping/closing circuit supervision.
The purpose of the CTS is to detect whether the current transformer circuit is failed. In some
cases, if the CT is failed (broken-conductor, short-circuit), related protective element should be
blocked for preventing this device from mal-operation.
The CT circuit supervision function is integrated in the protection elements related to current
calculation, such as, 87T, 87W, 64REF, 87R, etc., there is no independent CT circuit supervision
element, so please refer to the corresponding protection in Chapter 3 for the details about the
CTS.
6
6.6 VT Circuit Supervision (VTS)
The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when measurement from VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
2. Only current protection functions are enabled and VT is not connected to the device.
3. The specific current protection has picked up before the satisfaction of conditions of VT circuit
failure alarm.
Date: 2022-01-17
6 Supervision
time delay count-down will be paused until the protection returns to normal state.
Under normal conditions, the device detects residual voltage that is greater than the setting
[x.VTS.3U0_Set] or negative-sequence voltage that is greater than the setting [x.VTS.U2_Set] to
distinguish a single-phase or two-phase VT circuit failure, and detects positive-sequence voltage
that is less than the setting [x.VTS.U1_Set] to distinguish a three-phase VT circuit failure. Upon
detecting abnormality on VT circuit, an alarm will come up after a time delay of [x.VTS.t_DPU] and
drop-off with a time delay of [x.VTS.t_DDO] after that VT is restored to normal. Upon abnormality
detection on VT circuit, an instant alarm will be issued after a time delay of 25ms and drop-off
without time delay.
VT (secondary circuit) MCB auxiliary contact can be connected to the binary input circuit of the
device as a binary signal. If the MCB has been opened (i.e. [x.VTS.MCB_VT] is energized), the
device will consider that the VT circuit is in a bad condition and issue an alarm without a time
delay. If the auxiliary contact is not connected to the device, VT circuit supervision will be issued
with time delay as mentioned in previous paragraph.
When VT is not connected into the device, the alarm shall be not issued if the logic setting
[x.En_VT] is set as "Disabled". However, the alarm is still issued if the binary input
[x.VTS.MCB_VT] is energized, no matter that the logic setting [x.En_VT] is set as "Disabled" or
"Enabled".
VTS 6
x.VTS.in_U3P x.VTS.InstAlm
x.VTS.in_I3P
x.VTS.Enable
x.VTS.Block
x.VTS.MCB_VT
x.VTS.in_52b_a
x.VTS.in_52b_b
x.VTS.in_52b_b
6.6.4 Logic
SET x.3U0>[x.VTS.3U0_Set]
>=1
SET x.U2>[x.VTS.U2_Set]
[x.En_VT]
&
EN x.VTS.Alm
BI x.VTS.MCB_VT
EN [x.VTS.En]
&
x.VTS.Enable
6
SIG
SIG x.VTS.Block
SET x.3U0>[x.VTS.3U0_Set]
>=1
SET x.U2>[x.VTS.U2_Set]
[x.En_VT]
&
EN x.VTS.InstAlm
BI x.VTS.MCB_VT
EN [x.VTS.En]
&
SIG x.VTS.Enable
SIG x.VTS.Block
Where:
x.VTS.Alm is the output signal of three-phase voltage element (TVOL3P), as shown in Section
Date: 2022-01-17
6 Supervision
3.2.3.
In this device, the specific current protection includes phase overcurrent protection, earth fault
protection, current differential protection and breaker failure protection.
If the specific protection picks up firstly and then an abnormality on VT circuit is detected. The
VT circuit failure alarm should not be issued before the specific protection returns to normal
state.
If an abnormality on VT circuit is detected firstly and then the specific protection operates to
pick up. The time delay count-down of VT circuit failure alarm shall be paused until the
protection return to normal state.
If the specific protection operates and VT circuit failure alarm has been issued, the alarm will
be maintained.
6.6.5 Settings
Table 6.6-3 Settings of VT circuit supervision
The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.7-1.
All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the
binary input will be validated and wrote into SOE.
Binary input
state
In order to meet flexible configurable requirement for different project field, all binary inputs
provided by the device are configurable. Through the configuration tool, this device provides two
parameters to setup debounce time of delayed pickup and dropout based on specific binary
signal.
1. Type 1
2. Type 2
Date: 2022-01-17
6 Supervision
Debounce time
The debounce time of delayed pickup and delayed dropout is recommended to set as
15ms, in order to prevent binary signals from maloperation due to mixed connection of
AC system and DC system.
The debounce time of delayed pickup and delayed dropout is recommended to set as
(-t1+ t2+Time delay)≥15ms, in order to prevent binary signals from maloperation due to
mixed connection of AC system and DC system. Where, “t1” is the debounce time of
delayed pickup, and “t2” is the debounce time of delayed dropout.
3. Type 3
This type of binary inputs is usually used as auxiliary input condition, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 5ms.
6
When users have their own reasonable setting principles, they can set the
debounce time related settings according to their own setting principles.
[Num_Blk_Jitter] N, times threshold to block binary input status change due to jitter
[Blk_Window_Jitter] T’, blocking window of binary input status change due to jitter
For a binary input voltage variation, if the jitter processing function is enabled, its handling
principle is:
1. During the T,
a) If the actual jitter times < N, the block will not be initiated and the status change of this
binary input will be considered.
b) If the actual jitter times ≥ N, the T’ is initiated, and the status change of binary input will
be ignored during the T’.
a) If the actual jitter times < N’, the block window will expire. The final status of this binary
input will be compared to the original one before T’, so as to determine whether there is a
change or not.
b) If the actual jitter times ≥ N’, the T’ will be initiated again immediately (i.e. restart the
timer), and the status change of binary input will be ignored during the next T’.
Debounce time
(rising edge)
T
T t7 t8
6 t5 t6
T T T
t1 t2 t3 t4 t9 t10 t
②Green line Blocking signal of binary input status change due to jitter
③Blue line Binary input status after debounce and jitter processing
3. T = t2 - t1
a) n = 6 < N;
4. T = t4 - t3, at t5
Date: 2022-01-17
6 Supervision
a) n = 7 = N;
c) Jitter blocking, no more SOE, ② changes its status to 1 and ③ stops the tracing.
5. T’ = t6 - t5
a) At t7, n = 5 =N’, the processing prolongs the blocking immediately due to jitter;
6. T’ = t8 - t7
a) At t9, n = 5 =N’, the processing prolongs the blocking immediately due to jitter.
7. T’ = t10 - t9
a) n = 2 < N’;
b) At t10, jitter unblocking, ② changes its status to 0, the blocking window expires and ③
restart to trace the voltage variation imeediately. At this point, no debounce time takes
effect and SOE can be created since then.
Because of the long cable and the large coupling capacitance, it is easy to be interfered by
external signals, to cause undesired operation. The device provides two kinds of BI modules,
NR6604 and NR6611, which support the high-power conducting mode of binary inputs through
the setting [En_BICheckInstP] to fulfill mechanical binary input.
When voltage is greater than 95% of the settable ON value of binary input, the high-power
conducting mode is triggered. Under the compensation of a relatively large current, the
instantaneous active power immediately rises to the threshold.
This pulsed current will remain constant for the next 20ms. During which time, as the voltage
rises, the power will also rise.
If the voltage drops below 95% of the settable ON value of binary input, the device turns off
the high-power conducting mode.
However, if the voltage rises and exceeds the 95% threshold again, the high-power
conducting mode will restart.
20ms 20ms
UPickup
0.95UPickup
Interference Signal Valid Signal UDropout
U (In)
BI (Out)
BI debounce time BI debounce time
(rising edge, >20ms) (falling edge, >20ms)
Time
Only the binary inputs whose rated voltage is 110Vdc, 125Vdc, 220Vdc or
6 250Vdc (@50Hz), is capable to apply the high-power conducting mode.
The switchgear trip counter function supports counting of opening operations for circuit breaker
and disconnector. For a phase-segregated circuit breaker, if the position of any phase changes
from close to open, the opening counter increase.
Hardware circuit and operation status of this device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts “BO_Fail” will be given. The
protective device then cannot work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
If the device is blocked or alarm signal is sent during operation, please do find out its reason with
Date: 2022-01-17
6 Supervision
the help of self-diagnostic record. If the reason cannot be found at site, please notify the factory
NR. Please do not simply press button “TARGET RESET” on the protection panel or re-energize
on the device.
In the following table, “ON” means the LED is lit, “OFF” means the LED is
extinguished, “×” means having no influence, “YES” means the LED status
is modifiable, “NO” means the LED status is unmodifiable.
Date: 2022-01-17
6 Supervision
Date: 2022-01-17
6 Supervision
Date: 2022-01-17
6 Supervision
Date: 2022-01-17
6 Supervision
8 Fail_ProcessConfig
View the menu "Initialization Error" to check the detailed reason, and
send the reason to the manufacturer or the agent.
6
9 Fail_BoardRegister Please inform the manufacturer or the agent for repair.
View the menu "Initialization Error" to check the detailed reason, and
10 Fail_BoardInit
send the reason to the manufacturer or the agent.
11 Fail_Settings Please check the settings and set them correctly
12 Fail_Sample Please check the connection of CPU plug-in module.
13 Bxx.Fail_Board Please inform the manufacturer or the agent to deal with it.
14 P1.Fail_Board Please check the connection of PWR plug-in module.
Alarm signals
The signal is issued with other specific alarm signals, and please refer to
15 Alm_Device
the handling suggestion other specific alarm signals.
16 Alm_DeviceInit Please inform the manufacturer or the agent to deal with it.
Users may pay no attention to the alarm signal in the project
commissioning stage, but it is needed to download the latest package file
(including correct version checksum file) provided by R&D engineer to
17 Alm_Version make the alarm signal disappear. Then users get the correct software
version. It is not allowed that the alarm signal is issued on the device
already has been put into service. The devices have been put into service
so that the alarm signal disappears.
18 Alm_CommTest No special treatment is needed, and disable this test function after the
19 Alm_GOOSETest completion of the test.
Date: 2022-01-17
6 Supervision
Date: 2022-01-17
7 System Functions
7 System Functions
Table of Contents
Date: 2022-01-17
7 System Functions
The device supports both hardware-based and software-based clock synchronization modes.
IRIG-B: IRIG-B via serial port (RS-485 or TTL level), female BNC (TTL level) or
ST-connector port
PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), female BNC (TTL
level), ST-connector port or binary input
IEEE 1588: Clock message based on IEEE 1588 via Ethernet network
SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network
Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol
The device provides a priority-based adaptive clock synchronization scheme, which means that
the device can automatically identify multiple clock synchronization sources in the same clock
synchronization mode and choose the highest priority of lock synchronization sources.
The setting [Opt_TimeSyn] is set as "Conventional" and the setting [En_ConvModeSNTP] is set
as "Disabled"
The setting [Opt_TimeSyn] is set as "Conventional" and the setting [En_ConvModeSNTP] is set
as "Enabled"
[IP_Server_SNTP] is the address of SNTP clock synchronization server which sends SNTP timing
messages to the relay or BCU. [IP_StandbyServer_SNTP] is the address of standby SNTP clock
synchronization server.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "0.0.0.0", the device
receives broadcast SNTP synchronization message.
7
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "0.0.0.0", the device
adopts the setting whose value is not equal to "0.0.0.0" as SNTP server address and receives
unicast SNTP synchronization message.
7.2.1 Overview
The device can provide real-time state information, including analog quantities (such primary
Date: 2022-01-17
7 System Functions
measurement value, secondary measurement value, metering value and so on) and status
quantities (supervision status, input status, output status and so on). By check these state
information, operators can know operation state of the protected equipment and whether the
device is healthy.
These state information can be gained via local HMI. The menu path is:
1. Analog quantities
2. Status quantities
Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.
Device's state information can be uploaded into clients through message communication. For
differential protocols, the state information can be gained through corresponding communication
service.
The device can print the current state information, so that the operator can observe and save the
current operation condition. The access path is:
7.3.1 Overview
The device can store the latest 1024 time-stamped disturbance records, 1024 time-stamped
binary events, 1024 time-stamped supervision events, 256 time-stamped control logs and 1024
time-stamped device logs. All the records are stored in non-volatile memory, and when the
available space is exhausted, the oldest record is automatically overwritten by the latest one.
The device provides corresponding menus to view event recorders. The menu path is:
Date: 2022-01-17
7 System Functions
Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.
Event recorders can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).
The device can print event recorders, so that the operator can observe and save the current
operation condition. The access path is:
7.4.1 Overview
Fault recorder can be used to have a better understanding of the behavior of the power network
and related primary and secondary equipment during and after a disturbance. Analysis of the
7
recorded data provides valuable information that can be used to improve existing equipment. This
information can also be used when planning for and designing new installations.
The fault recorder is comprised of the report and the waveform, which can be triggered by pickup
signals, trip signals and configurable binary signal [BI_TrigDFR].
The fault memory of the device is automatically updated with every recording. When the fault
memory is filled completely, the oldest records are overwritten automatically. Thus, the most
recent recordings are always stored safely. The maximum number of recordings is 64.
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
The date and time is recorded when a system fault is detected. The time resolution is 1ms.
An operating time (not including the operating time of output relays) is recorded in the record. The
time resolution is 1ms.
4. Fault information
A fault waveform contains all analog and digital quantities related to protection such as currents,
voltages, differential current, alarm elements, and binary inputs and etc.
The overall duration of a single fault recording comprises the total duration of the configurable
recording criterion, the pre-trigger time and the post-trigger time. With the fault recording
parameter, these components can be individually set. The pre-trigger waveform recorded duration
is configured via the setting [RecDur_PreTrigDFR]. The waveform recorded duration after the fault
disappears is configured via the setting [RecDur_PostFault]. The maximum post-trigger waveform
recorded duration is configured via the setting [MaxRecDur_PostTrigDFR].
4. [MaxRecDur_PostTrigDFR]
Trigger point
7
1. Pre-trigger recording time
The pickup recording time cannot be set. It continues as long as any valid trigger condition, binary
or analog, persists (unless limited by the limit time, which is determined by the setting
[MaxRecDur_PostTrigDFR]).
The recording time begins after all activated triggers are reset. Use the setting [RecDur_PostFault]
to set this time.
Use the setting [MaxRecDur_PostTrigDFR] to set this time. If the summation of pickup recording
time and post-fault recording time is larger than maximal post-trigger recording time, the
post-trigger recording time shall be equal to the setting [MaxRecDur_PostTrigDFR].
Date: 2022-01-17
7 System Functions
The device provides corresponding menus to check fault recording. The menu path is:
Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.
Fault recording can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).
The device can print fault recording, so that the operator can observe and save the current
operation condition. The access path is:
The device provides maintenance state, i.e., the binary input [BI_Maintenance] is energized,
which is convenient for maintenance work. For adopting conventional CT/VT, binary inputs and
binary outputs, maintenance state has no influence on protection logics. For binary inputs and
7
binary outputs by GOOSE connections. During device maintenance, the object will send GOOSE
message with Test quality attribute. The Test quality attribute indicates to the receiver device that
the object received via a GOOSE message was created under test conditions and not operating
conditions. If the Test quality attribute received is different with the object's Test quality attribute,
binary inputs and binary outputs by GOOSE connections will be affected based on different types
of binary inputs and binary outputs. For SV (Sampling Value) message, if the Test quality attribute
received is different with the object's Test quality attribute, the relevant protection functions will be
blocked.
For IEC60870-5-103 protocol, only the messages in link layer maintained, service messages in
the application layer which is uploaded automatically are blocked, and service messages in the
application layer which is issued by the client are rejected. For IEC61850 protocol, all Test quality
attribute set as "1". For DNP3.0 and ModBus protocol, they are not affected.
The device provides Test Mode to allow all protection elements, supervision events and binary
events to fulfill communication test, but to avoid the output contacts to close. During
communication test, protection functions are not affected, the signals generated by
communication test are recorded in relevant reports, and event recording and fault recording will
not stop recording disturbance information. The alarm signal "Alm_CommTest" will be issued to
indicate the operator when activating Test Mode and exiting Test Mode.
Communication test can be gained via local HMI and the virtual HMI, the corresponding content
can be viewed through the following menu paths:
Events Simulation
Forced Measurements
If no input operation is carried out within 60s, this test will exit and return to
the previous menu automatically.
7
7.7 Output Test
The device provides Output Test Mode to test all outputs. Through this mode, there will be real
operations, such as contact closing and GOOSE output value change, triggered by the device to
test output circuits and links. So, protection functions outputs and the connecting primary
equipments are affected. The output signals generated by output test are not recorded, while the
entering and exiting of output test mode will be recorded in Superv Events. During the output test,
the protection functions will not stop, nor will the all recording functions.
Output test can be gained via the local LCD or virtual HMI of a debugging PC, the corresponding
content can be viewed through the following menu paths:
Contacts Outputs
GOOSE Outputs
Date: 2022-01-17
7 System Functions
The device provides target reset which can be used to reset local signals (including magnetic
latching output relays), latched LEDs, and confirm pop-up windows of reports. The function does
not affect the protection logic and communication function. There are several ways to reset.
Press the command pushbutton “ESC”+“ENT” on operation panel of the device under
main interface
Press the command pushbutton " TARGET RESET" on operation panel of the device
For different applications users can save the respective function settings in so-called settings
groups, and if necessary enable them quickly. Up to 20 different settings groups can be saved in
the device. In the process, only one settings group is active at any given time. During operation,
the operator can switch between setting groups.
The device will be temporarily blocked during switching setting groups. During temporary device
blocking, the device will loss protection functions and communication functions. Alarm signals
"Fail_Device" and "Alm_Device" will be issued. There are several ways to switch setting groups.
Press the command push-button "MENU" under main interface (password is required)
The communication protocols IEC 60870-5-103 or IEC 61850 can be used for switching the
setting groups via a communication connection.
The device also provides an available function by configuring associated binary signals via
PCS-Studio to switch setting group, which can be external binary inputs or internal logic
signals. By default, no binary signals are configured, so the function is invalid.
Each input signal is coded with a sequence number that corresponds to a setting group.
When the associated input signal changes, the device scans all input signals and selects the
input with the smallest sequence number as the valid input. The device switches to the
setting range corresponding to the input signal. The device can switch up to 20 setting
groups.
Date: 2022-01-17
8 Hardware
8 Hardware
Table of Contents
8.4.8 Binary Input and Binary Output Module (NR6661) ............................................................ 8-34
8.4.9 Mechanical Relay Input and Output Module (NR6662) ..................................................... 8-36 8
8.4.10 DC Analog Input Module (NR6630/NR6631) ................................................................... 8-38
List of Figures
Figure 8.1-3 Typical rear view of PCS-978S with ring ferrule .................................................. 8-3
Figure 8.1-4 Typical rear view of PCS-978S with pin ferrule .................................................... 8-4
Figure 8.4-13 View of binary input module (NR6610A and NR6610B) ............................... 8-26
Figure 8.4-20 View of binary input and binary output module (NR6661A) ........................ 8-35
8 Figure 8.4-21 View of MR IO plug-in module (NR6662A, NR6662B and NR6662N) .......... 8-37
List of Tables
Table 8.4-1 Terminal definition and description of power supply module NR6305A ............ 8-10
Table 8.4-2 Terminal definition and description of power supply module NR6310A ............ 8-11
Table 8.4-3 Terminal definition and description of power supply module NR6311A............. 8-11
Table 8.4-5 Terminal definition and description of binary input module ............................... 8-23
Date: 2022-01-17
8 Hardware
Table 8.4-6 Terminal definition and description of binary input module (NR6604A) ............. 8-25
Table 8.4-7 Terminal definition and description of binary input module ............................... 8-26
Table 8.4-8 Terminal definition and description of binary input module (NR6611A) ............ 8-28
Table 8.4-9 Terminal definition and description of BIBO module NR6661A .......................... 8-35
Table 8.4-11 Terminal definition and description of DC analog input module NR6630A ...... 8-39
Table 8.4-12 Terminal definition and description of DC analog input module NR6631A ...... 8-41
8.1 Overview
The modular design of this device allows this device to be easily upgraded or repaired by a
qualified service person. The faceplate is hinged to allow easy access to the configurable
modules, and back-plugging structure design makes it easy to repair or replace any module.
This device adopts one 32-bit ARM core in the CPU chip as control core for management and
monitoring function, and adopts another 32-bit ARM core in the CPU chip for all the protection
calculation. The parallel processing of sampled data can be realized in each sampling interval to
ensure ultrahigh reliability and safety of the device.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 8.1-1 for the hardware diagram.
External
Binary Input
Pickup
Electronic/Optic CT/VT Relay
ETHERNET
+E
LCD
Clock SYN
Power
Uaux LED ARM2
Supply
RJ45
Keypad
PRINT
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS S series based on microcomputer
are classified into standard and optional modules.
HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
CPU module provides functions like communication with SAS, event record, setting
management etc., and performs filtering, sampling, protection calculation and fault detector
calculation.
NET-DSP module receives and transmits GOOSE messages, sampled values (SV) from
merging unit by IEC 61850-9-2 protocol.
AC AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
8 BI module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V~250V (configurable).
BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
BIBO module provides both binary inputs (with rating voltage among AC110V/220V or
DC24V~250V) and output contacts for tripping and signal.
MR IO module receives mechanical signals from transformer body and provides several
output contacts.
Following figures show the front and rear views of this device respectively.
Date: 2022-01-17
8 Hardware
8 8
1 1
3 3
9 4 9
4
2 2
5 5
6 7 6 7
3. Push buttons for opening/closing operation and switch of local/remote control mode
1 1
8
4 5 6 4 5 6
2 2
3 3
1 1
4 5 6 4 5 6
2 2
3 3
B01 B02 & B03 B04 & B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 P1
NR6106BA NR6641-6I6U NR6641-12I Option Option Option Option Option Option Option NR6601A NR6651A NR6305A
8 NET
03
05
Ib1
Ic1
Ib2n
Ic1n
04
06
03
05
Ib1
Ic1
Ib2n
Ic1n
04
06
03
05
BI_03
BI_05
BI_04
BI_06
04
06
03
05
BO_02
BO_03
04
06
03
05
BI_02+
BI_COM
BI_02-
BI_03
04
06
CONSOLE
Ground
Date: 2022-01-17
8 Hardware
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0213
0214
Ia1 Ib1 Ic1 Ia2 Ib2 Ic2 Ua1 Ub1 Uc1 Ua2 Ub2 Uc2
BI_01 + 1301
To SCADA
…
BI_25 + 1325
1326 -
BI_01 + P101
- P102
BI_02 + P103
- P104
BI_03 + P106
1A 0101
COM
…
To the screen of other coaxial
2A 0104
COM
Console P121
BO_05 P122
1401 P123
1402 BO_01 BO_Fail P124
1403
1404 BO_02 P125
Power
PWR+
External DC power
8
…
Grounding Bus
Ic4 Ib4 Ia4 Ic3 Ib3 Ia3 Ic2 Ib2 Ia2 Ic1 Ib1 Ia1
0414
0413
0424
0423
0422
0421
0420
0419
0418
0417
0416
0415
0412
0411
0410
0409
0408
0407
0406
0405
0404
0403
0402
0401
8.3 CT Requirements
8.3.1 CT Types
Generally there are three types of CT: high remanence, low remanence and no remanence.
Low remanence: TPY, PR, and the residual magnetism does not exceed 10% of the
saturation flux.
The high residual magnetism CT may have large residual magnetism. When the fault
non-periodic component and residual magnetism are in the same direction, the CT saturation
degree will be more serious. The following CT type checking calculation takes into account
the maximum residual magnetism of CT and the maximum non periodic component on the
site.
8.3.2 CT Requirements
Rated secondary limit e.m.f (volts) formula:
Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn
Esl4′ = k4×Ipcf4×Isn×(Rct+Rb)/Ipn
Maximum fault current through two bridge CB but not transformer when
Ipcf2
out-zone fault (amps)
Date: 2022-01-17
8 Hardware
While: k1=2,k3=30,k4=1.
If both CTs of double CB are low remanence type, and with the same model, then k1=2,
k2=1.5, k3=30, k4=1.
Otherwise: k1=2,k2=2,k3=30,k4=1.
When selecting CTs for 87R, the ratio between maximum rated primary value and
minimum rated primary value should not be greater than 10, and it is recommended to be
6.
If both CTs of double CB are low remanence type, and with the same model, then k2=1.5,
k3=30, k4=1.
Otherwise: k2=2,k3=30,k4=1.
When selecting CTs for 87R, the ratio between maximum rated primary value and
minimum rated primary value should not be greater than 10, and it is recommended to be
6.
8.3.4 Example
= 30×5×(1+60/25)=510V
Esl1′ = k1×Ipcf1×Isn×(Rct+Rb)/Ipn
= 2×Ipcf1 ×Isn×(Rct+(Rr+2×RL))/Ipn
= 2×40000×5×(1+(0.1+2×0.5))/2000=420V
Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn
=30×1500*5*(1+(0.1+2×0.5)) /2000=236.25V
Thus, Esl > Esl1′ and Esl > Esl3′, meeting the requirements.
The device consists of power supply module (PWR), main CPU module (CPU), AI module, BI
module, BO plug-in module and DC analog input plug-in module. Terminal definitions and
application of each plug-in module are introduced as follows.
8 The human machine interface (HMI) module is installed on the front panel of this device. It is used
to observe the running status and event information on the LCD, and configure the protection
settings and device operation mode. It can help the user to know the status of this device and
detailed event information easily, and provide convenient and friendly access interface for the
user.
The power supply module is a DC/DC converter with electrical insulation between input and
output. It has an input voltage range as described in Chapter 2 Technical Data. The standardized
output voltages are +5Vdc and +12Vdc. The tolerances of the output voltages are continuously
monitored.
The +5Vdc output provides power supply for all the electrical elements that need +5Vdc power
supply in this device.
Date: 2022-01-17
8 Hardware
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device
is in cold reserve.
Three types of power supply modules are provided: NR6305A, NR6310A and NR6311A.
The PWR module a grounding screw for device grounding. The grounding
screw shall be connected to grounding screw and then connected to the
earth copper bar of panel via dedicated grounding wire.
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 26-pin connector is fixed on the power supply module. The terminal definition of
the connector is described as below.
Table 8.4-1 Terminal definition and description of power supply module NR6305A
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 22-pin connector and a 4-pin connector are fixed on the power supply module.
The terminal definition of the connector is described as below.
Date: 2022-01-17
8 Hardware
Table 8.4-2 Terminal definition and description of power supply module NR6310A
This power supply module provides 9 binary inputs, 5 binary outputs and a device failure binary
output. A 22-pin connector and a 4-pin connector are fixed on the power supply module. The
terminal definition of the connector is described as below.
Table 8.4-3 Terminal definition and description of power supply module NR6311A
The CPU module is the central part of this device, and contains a multi-core 32-bit powerful
processor and some necessary electronic elements. This powerful processor performs all of the
functions for this device: protection function, communication function, human-machine interface
8 function and so on. There are several A/D conversion circuits on this module, which are used to
convert the AC analog signals to corresponding DC signals for fulfilling the demand of the
electrical level standard. A high-accuracy clock chip is contained in this module, it provide
accurate current time for this device.
The CPU module uses the internal bus to receive the data from other modules of the device. It
comprises 100BaseT Ethernet interfaces, RS-485 communication interfaces, PPS/IRIG-B
differential time synchronization interface and RS-232 printing interface, and supports
independent networking mode and mixed networking mode based on MMS/GOOSE/SV. By the
setting [B01.Opt_NetMode], the network mode of four Ethernet interfaces in CPU module can be
set as "Normal", "PRP" or "HSR" in station level.
The main functional details of the CPU module are listed as below:
Date: 2022-01-17
8 Hardware
The CPU module can calculate protective elements (such as overcurrent element) on the
basis of the analog sampled values (voltages and currents) and binary inputs, then it does
logical judgment function and decides whether the device needs to trip or close.
Communication function
The CPU module can effectively manage all communication procedures, and reliably send
out some useful information through its various communication interfaces. These interfaces
are used to communicate with a SAS or a RTU. It also can communicate with the human
machine interface module. If an event occurs (such as SOE, protective tripping event etc.),
this module will send out the relevant event information through these interfaces, and make it
be easily observed by the user.
Auxiliary calculation
Based on the voltage and current inputs, the CPU module also can calculate out the metering
values, such as active power, reactive power and power factor etc. All these values can be
sent to a SAS or a RTU through the communication interfaces.
This module can respond the commands from the keypad of this device and show the results
on the LCD and LED indicators of this device. It also can show the operation situation and
event information for the users through the LCD and LED indicators.
Time synchronization
This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B
signal. Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on
the IRIG-B signal, this module can synchronize local clock with the standard clock.
Do NOT look into the end of an optical fiber connected to an optical port.
8 The configuration and terminal definition of the CPU modules are listed in following table
Sampling
Module ID Interface Terminal No. Usage Physical Layer
Channel
Twisted-pair
2×RJ45 Ethernet
wire or optic
2×SFP (LC) communication
fibre
01 A
NR6106BA 36 RS-485 02 B To SCADA
03 SGND Twisted-pair
04 A wire
RS-485 05 B To SCADA
06 SGND
Date: 2022-01-17
8 Hardware
Sampling
Module ID Interface Terminal No. Usage Physical Layer
Channel
07 SYN+
RS-485 08 SYN- To clock
09 SGND synchronization
TTL 10 SYN-TTL
RJ45 Debugging
Ethernet
4×SFP (LC)
communication Optic fibre
NR6106BH 36 ST-connector Time synchronization
Twisted-pair
RJ45 Ethernet Debugging
wire
Ethernet
4×SFP (LC) Optic fibre
communication
01 A
RS-485 02 B To SCADA
03 SGND
04 A
NR6106BJ 36 RS-485 05 B To SCADA
Twisted-pair
06 SGND
wire
07 SYN+
RS-485 08 SYN- To clock
09 SGND synchronization
TTL 10 SYN-TTL
RJ45 Ethernet Debugging
Twisted-pair
2×RJ45 Ethernet
wire or optic
2×SFP (LC) communication
fibre
01 A
RS-485 02 B To SCADA 8
03 SGND Twisted-pair
NR6106BP 36 04 A wire
RS-485 05 B To SCADA
06 SGND
To clock
BNC Coaxial cable
synchronization
Twisted-pair
RJ45 Ethernet Debugging
wire
The correct connection is shown in Figure 8.4-3. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface.
COM
B
SGND
Clock SYN
SYN-
SGND
Cable
RTS
PRINT
TXD
SGND
8
The 2nd RS-485 port also can be configured as a printer port through the
jumpers “J10” and “J11”.
Date: 2022-01-17
8 Hardware
Do NOT look into the end of an optical fiber connected to an optical port.
8
Do NOT look into an optical port/connector.
It supports GOOSE and SV by IEC 61850-9-2 protocols and can be used for GOOSE & SV
message transmission by point-to-point connection or via LAN. It can receive and send GOOSE
messages to intelligent control device, and receive SV from MU (merging unit). Each interface can
be dedicated for GOOSE or SV message, it can also be shared by GOOSE & SV message.
For the analog input module, if the plug is not put in the socket, external CT circuit is closed itself.
Just shown as below.
Plug
Socket
In
Out
In
Out
8
Put the plug in the socket
There are two types of analog input modules. The rated current is adaptive (1A/5A). Please
declare which kind of AI module is needed before ordering. Maximum linear range of the current
converter is 40In.
6CT+6VT
8CT+4VT
12CT
Date: 2022-01-17
8 Hardware
8
Each analog input channel can be configured according to practical
application through PCS-Studio.
Some connection examples of the current transformers and voltage transformers which are
supported by this relay are shown in this section. If one of the analog inputs has no input in a
practical engineering, the relevant input terminals should be disconnected.
A B C A B C
Ia Ia
Ian Ian
Ib Ib
Ibn Ibn
Ic Ic
Icn Icn
I01
I01n I01
(1) I01n
A B C (3)
Ia
Ian
Ib I0s
Ibn I0sn
Ic
(4)
Icn
I01 I02
I01n I02n
(2) (5)
Where:
(1) Current connections to three current transformers with a star-point connection for ground
current (zero sequence current or residual current).
(2) Current connections to three current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer).
8 (3) Current connections to two current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer), only
for ungrounded or compensated networks.
(4) Current connection to a core balance neutral current transformer for sensitive ground
fault detection, only for ungrounded or compensated networks.
Date: 2022-01-17
8 Hardware
A B C A B C
Ux
52 52 52 Ux 52 52 52
Uxn
Uxn
Ua Ua
Ub Ub
Uc Uc
Un Un
U0 U0
U0n U0n
(1) (2)
Where:
There are five kinds of BI modules available, NR6601A, NR6604A, NR6610A, NR6610B and
NR6611A. The module NR6601A can provide 25 normal binary inputs (common negative supply,
ring ferrule), NR6610A and NR6610B can provide 32 normal binary inputs (common negative 8
supply, pin ferrule), NR6604A can provide 13 normal or high-power binary inputs (independent
negative supply, ring ferrule), and NR6611A can provide 14 normal or high-power binary inputs
(independent negative supply, pin ferrule).
The rated voltage of binary input is optional: 24Vdc, 30Vdc, 48Vdc, 110Vdc,
125Vdc, 220Vdc, 110Vac or 220Vac (@50Hz), which must be specified
when placed order. It is necessary to check whether the rated voltage of
binary input module complies with site DC power supply rating before put
this device in service.
Voltage
300
157.5
138.6
125
110
78.75
69.3
62.5
55 Operation
30.24
24 Operation uncertain
15.12
12
No operation
0 24V 48V 110V 125V 220V 250V
8.4.6.1 NR6601A
Each BI module is with a 26-pin connector for 25 binary inputs which share one common negative
power input and can be configurable. The pickup voltages and dropout voltages of the binary
8 inputs are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from
50%Un to 80%Un.
Date: 2022-01-17
8 Hardware
01 BI_01 BI_02 02
03 BI_03 BI_04 04
05 BI_05 BI_06 06
07 BI_07 BI_08 08
09 BI_09 BI_10 10
11 BI_11 BI_12 12
13 BI_13 BI_14 14
15 BI_15 BI_16 16
17 BI_17 BI_18 18
19 BI_19 BI_20 20
21 BI_21 BI_22 22
23 BI_23 BI_24 24
25 BI_25 COM- 26
Table 8.4-5 Terminal definition and description of binary input module NR6601A
8.4.6.2 NR6604A
Each BI module is with a 26-pin connector for 13 binary inputs, each binary input has independent
negative power input and is configurable. The pickup voltages and drop-out voltages of the binary
inputs are settable by the setting [U_Pickup_BI] and [U_Dropout_BI], and the range is from
50%Un to 80%Un.
01 BI_01 Opto01- 02
03 BI_02 Opto02- 04
05 BI_03 Opto03- 06
07 BI_04 Opto04- 08
09 BI_05 Opto05- 10
11 BI_06 Opto06- 12
13 BI_07 Opto07- 14
8 15 BI_08 Opto08- 16
17 BI_09 Opto09- 18
19 BI_10 Opto10- 20
21 BI_11 Opto11- 22
23 BI_12 Opto12- 24
25 BI_13 Opto13- 26
Date: 2022-01-17
8 Hardware
Table 8.4-6 Terminal definition and description of binary input module NR6604A
01 BI_01 19 BI_01
02 BI_02 20 BI_02
03 BI_03 21 BI_03
04 BI_04 22 BI_04
05 BI_05 23 BI_05
06 BI_06 24 BI_06
07 BI_07 25 BI_07
08 BI_08 26 BI_08
09 BI_09 27 BI_09
10 BI_10 28 BI_10
11 BI_11 29 BI_11
12 BI_12 30 BI_12
13 BI_13 31 BI_13
14 BI_14 32 BI_14
15 BI_15 33 BI_15
16 BI_16 34 BI_16
17 BI_COM 35 BI_COM
18 BI_COM 36 BI_COM
Table 8.4-7 Terminal definition and description of binary input module NR6610
Date: 2022-01-17
8 Hardware
17 COM-
The common negative connection of the BI_01 to BI_16.
18 (01-16)
19 BI_17 The No.17 programmable binary input
20 BI_18 The No.18 programmable binary input
21 BI_19 The No.19 programmable binary input
22 BI_20 The No.20 programmable binary input
23 BI_21 The No.21 programmable binary input
24 BI_22 The No.22 programmable binary input
25 BI_23 The No.23 programmable binary input
26 BI_24 The No.24 programmable binary input
27 BI_25 The No.25 programmable binary input
18-pin
28 BI_26 The No.26 programmable binary input
29 BI_27 The No.27 programmable binary input
30 BI_28 The No.28 programmable binary input
31 BI_29 The No.29 programmable binary input
32 BI_30 The No.30 programmable binary input
33 BI_31 The No.31 programmable binary input
34 BI_32 The No.32 programmable binary input
35 COM-
The common negative connection of the BI_17 to BI_32.
36 (17-32)
8.4.6.4 NR6611A
Each BI module is with two 18-pin connectors for 14 binary inputs, each binary input has
independent negative power input and is configurable. The pickup voltages and drop-out voltages
of the binary inputs are settable by the setting [U_Pickup_BI] and [U_Dropout_BI], and the range
is from 50%Un to 80%Un.
01 19
02 20
03 BI_01 21 BI_08
04 Opto01- 22 Opto08-
05 BI_02 23 BI_09
06 Opto02- 24 Opto09-
07 BI_03 25 BI_10
08 Opto03- 26 Opto10-
09 BI_04 27 BI_11
10 Opto04- 28 Opto11-
11 BI_05 29 BI_12
12 Opto05- 30 Opto12-
13 BI_06 31 BI_13
14 Opto06- 32 Opto13-
15 BI_07 33 BI_14
16 Opto07- 34 Opto14-
17 35
18 36
Table 8.4-8 Terminal definition and description of binary input module NR6611A
Date: 2022-01-17
8 Hardware
17 Blank -
18 Blank -
19 Blank -
20 Blank -
21 BI_08 Configurable binary input 8
22 Opto08- Negative pole of power supply of configurable binary input 8
23 BI_09 Configurable binary input 9
24 Opto09- Negative pole of power supply of configurable binary input 9
25 BI_10 Configurable binary input 10
26 Opto10- Negative pole of power supply of configurable binary input 10
27 BI_11 Configurable binary input 11
18-pin
28 Opto11- Negative pole of power supply of configurable binary input 11
29 BI_12 Configurable binary input 12
30 Opto12- Negative pole of power supply of configurable binary input 12
31 BI_13 Configurable binary input 13
32 Opto13- Negative pole of power supply of configurable binary input 13
33 BI_14 Configurable binary input 14
34 Opto14- Negative pole of power supply of configurable binary input 14
35 Blank -
36 Blank -
The binary output module consists of some necessary contact outputs, and the binary outputs are
used as tripping and closing (protection, auto-reclosing or remote control) outputs or signal
outputs. It can receive tripping commands or closing commands from the CPU module, and then
executes these commands. It also can output some alarm signals from the CPU module.
The device can provide five types of binary output modules: NR6651A, NR6651B, NR6652A,
NR6660A and NR6663A.
8.4.7.1 NR6651A 8
The NR6651A provides 13 normally open contacts (NOC).
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
8.4.7.2 NR6651B
The NR6651B provides 11 normally open contacts (NOC, the first 11 contacts) and 2 normally
close contacts (NCC, the last 2 contacts).
Date: 2022-01-17
8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
8.4.7.3 NR6652A
The NR6652A provides 4 normally open contacts (NOC, the first 4 contacts) with heavy capacity
for controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the
last 4 contacts).
BO_01 01 02
03 04
BO_02 05 06
07 08
BO_03 09 10
11 12
BO_04 13 14
15 16
17 18
BO_05 19 20
BO_06 21 22
BO_07 23 24
BO_08 25 26
8.4.7.4 NR6660A
The NR6660A provides 15 normally open contacts (NOC) and 2 normally open contacts &
normally close contacts (NOC/NCC).
Date: 2022-01-17
8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
18-pin
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
BO_14 27 28
18-pin
BO_15 29 30
BO_16 32
31
BO_16 33
BO_17 35
34
BO_17 36
8.4.7.5 NR6663A
The NR6663A provides 4 normal open contacts (NOC, the first 4 contacts) with heavy capacity for
controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the last
4 contacts).
01 02
03 04
BO_01
07 08
BO_02
09 10
11 12
BO_03
13 14
15 16
BO_04
17 18
19 20
21 22
25 26
BO_06
27 28
29 30
BO_07
31 32
33 34
BO_08
35 36
Each IO module is with two 18-pin connectors for 16 binary inputs, 6 normally open contacts
(NOC) and 2 normally open contacts & normally close contacts (NOC/NCC). The 16 binary inputs
share one common negative power input. All binary inputs are configurable. The pickup voltages
and dropout voltages of the binary inputs are settable by the setting [U_Pickup_BI] and
[U_Dropoff_BI], and the range is from 50%Un to 80%Un.
Date: 2022-01-17
8 Hardware
01 BI_01
02 BI_02
03 BI_03
04 BI_04
05 BI_05
06 BI_06
07 BI_07
08 BI_08
09 BI_09 BO_01 19 20
10 BI_10 BO _02 21 22
11 BI_11 BO_03 23 24
12 BI_12 BO _04 25 26
13 BI_13 BO_05 27 28
14 BI_14 BO _06 29 30
15 BI_15 BO_07_NO 32
31
16 BI_16 BO_07_NC 33
COM-
17 (01-16) BO_08_NO 35
COM-
34
18 BO_08_NC 36
(01-16)
Figure 8.4-20 View of binary input and binary output module (NR6661A)
8 The mechanical relay input and output module NR6662 can provide five binary inputs and three
groups of normally open contacts for mechanical protection. This module is used to output various
signals, such as, trip signal, alarm signal and disturbance & fault recording signal, etc.
There are three kinds of optional MR IO modules, NR6662A (220Vdc), NR6662B (110Vdc) and
NR6662N (125Vdc).
Date: 2022-01-17
8 Hardware
01 BI_COM 19 BO_COM_ 2
02 BI_COM 20 BO_COM_ 2
03 21 BO_MR1_2
Binary input
04 signals of BI_MR1 22 BO_MR2_2
05 mechanical BI_MR2 23 BO_MR3_2
protection
06 BI_MR3 24 BO_MR4_2
07 BI_MR4 25 BO_MR5_2
08 BI_MR5 26
09 27 BO_COM_ 3
10 BO_COM_ 1 28 BO_COM_ 3
11 BO_COM_ 1 29 BO_MR1_3
12 BO_MR1_1 30 BO_MR2_3
13 BO_MR2_1 31 BO_MR3_3
14 BO_MR3_1 32 BO_MR4_3
15
16
BO_MR4_1
BO_MR5_1
33
34
BO_MR5_3
8
17 35
18 36
8 30
31
BO_MR2_3
BO_MR3_3
NO contact, is closed when binary input [BI_MR2] is energized.
NO contact, is closed when binary input [BI_MR3] is energized.
32 BO_MR4_3 NO contact, is closed when binary input [BI_MR4] is energized.
33 BO_MR5_3 NO contact, is closed when binary input [BI_MR5] is energized.
34 Blank Not used
35 Blank Not used
36 Blank Not used
The DC analog input module can provide 0~±20mA or 0~±10V input channels.
This device provides two types of DC analog input modules: NR6630A and NR6631A.
Date: 2022-01-17
8 Hardware
8.4.10.1 NR6630A
The NR6630A provides 12 channels of 0~±20mA or 0~±10V inputs, and all channels can be set
as 0~±20mA or 0~±10V DC signal inputs respectively through the jumpers on the module and the
related channel type setting.
Two 18-pin connectors are fixed on this DC analog input module. The terminal definition of the 8
connector on the module NR6630A is listed as below.
Table 8.4-11 Terminal definition and description of DC analog input module NR6630A
10 DCAI_04+
The No.4 DC analog input channel
11 DCAI_04-
12 GND The grounding terminal
13 DCAI_05+
The No.5 DC analog input channel
14 DCAI_05-
15 GND The grounding terminal
16 DCAI_06+
The No.6 DC analog input channel
17 DCAI_06-
18 GND The grounding terminal
19 DCAI_07+
The No.7 DC analog input channel
20 DCAI_07-
21 GND The grounding terminal
22 DCAI_08+
The No.8 DC analog input channel
23 DCAI_08-
24 GND The grounding terminal
25 DCAI_09+
The No.9 DC analog input channel
26 DCAI_09-
27 GND The grounding terminal
28 DCAI_10+
The No.10 DC analog input channel
29 DCAI_10-
30 GND The grounding terminal
31 DCAI_11+
The No.11 DC analog input channel
32 DCAI_11-
33 GND The grounding terminal
34 DCAI_12+
The No.12 DC analog input channel
35 DCAI_12-
36 GND The grounding terminal
8 8.4.10.2 NR6631A
The NR6631A provides 8 channels of 0~±20mA or 0~±10V inputs, and all channels can be set as
0~±20mA or 0~±10V DC signal inputs respectively through the jumpers on the module and the
related channel type setting.
Date: 2022-01-17
8 Hardware
The terminal definition of the connector of the module NR6631A is listed as below.
Table 8.4-12 Terminal definition and description of DC analog input module NR6631A
Date: 2022-01-17
9 Settings
9 Settings
Table of Contents
List of Tables
Date: 2022-01-17
9 Settings
In the chapter, the prefix ”x.” in some settings, represents some side or
bushing of transformer defined by user through PCS-Studio software,
which may be “HVS”, “MVS”, “LVS”, “HVS2”, “MVS2”, “LVS2”, “CWS”,
“HVB”, “MVB”, “LVB”, etc. If only one protection element is equipped, the
prefix “x.” may disappear.
Date: 2022-01-17
9 Settings
They are the primary rated voltages at x side of transformer or reactor marked on the
nameplate.
The setting principle of rated phase-to-phase voltages of each side is to take the primary
rated voltage marked on the nameplate of transformer as the primary rated voltage of
corresponding side. For an on-load tap changing transformer, the voltage of transformer with
tap in middle position is taken as the value of this setting.
For one side not used in the device, please set the primary rated voltage
value of the corresponding side as “0”.
[Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]
They are the wiring o′clock of MV/LV side with respect to HV side, is the parameter shown on
transformer nameplate with the range of 0~11, and need not further calculation.
[Clk_PhComp]
It is the target o′clock each side current will be shift to for phase compensation.
For examples:
The vector group of a transformer is Y0/Δ11 and the target o′clock ([Clk_PhComp]) is set to
“11”. Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.
For HV side, the clock of HV side with reference to target o′clock is 1 (i.e. wiring o′clock
12-target o′clock 11) clock, so the matrix of relative o′clock 1 is adopted to compensate
HV side current. Zero-sequence current elimination has no effect on phase
compensation in the condition.
9
For LV side, the clock of LV side with reference to target o′clock is 0 (i.e. wiring o′clock 11-
target o′clock 11), so the matrix of relative o′clock 0 is adopted to compensate LV side
current. Then it is needed to decide whether zero-sequence current is eliminated and
select the corresponding matrix.
protection may operate unexpectedly during an external fault. Therefore the matrix of relative
o′clock 0 with zero-sequence current elimination should be selected.
1 0 0 2 1 1
0
0 1 0 1
1 2 1
3
0 0 1 1 1 2
1 1 0
1
1 0 1 1
3
1 0 1
0 1 0 1 2 1
2
0 0 1 1
1 1 2
3
1 0 0 2 1 1
0 1 1
1
3 1 0 1
3
1 1 0
0 0 1 1 1 2
1
4
1 0 0
2 1 1
3
0 1 0 1 2 1
1 0 1
1
5 1 1 0
3
0 1 1
1 0 0 2 1 1
6
0 1 0 1
1 2 1
3
0 0 1 1 1 2
9
1 1 0
1
7 0 1 1
3
1 0 1
0 1 0 1 2 1
8
0 0 1
1
1 1 2
3
1 0 0 2 1 1
Date: 2022-01-17
9 Settings
0 1 1
1
9 1 0 1
3
1 1 0
0 0 1 1 1 2
10
1 0 0
1
2 1 1
3
0 1 0 1 2 1
1 0 1
1
11 1 1 0
3
0 1 1
[x.En_RevCT]
It is used to adjust the current polarity of CT at x side of transformer, and default value is
Disabled.
When the current polarity of primary CT is different with defined forward direction by
PCS-978S, the setting can be set as “Enabled”. However, it is recommended to change
external wiring of primary CT.
Date: 2022-01-17
9 Settings
Access path: MainMenu Settings Global Settings Comm Settings General Comm
Settings
9 115200
4800
9600
19200 Baud rate of rear RS-485
21 Baud_RS485-2 bps 19200
38400 serial port 2.
57600
115200
Communication address
between the device and
22 Addr_RS485-1 1~254 - 100
the SCADA or RTU via
RS-485 serial port 1.
Date: 2022-01-17
9 Settings
[Cfg_NetPorts_Bond]
The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device support a bond between any
two Ethernet ports, and the bond among three or above Ethernet ports is impermissible.
The devices communicate with SAS by station level network. In order to ensure reliable
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of
Date: 2022-01-17
9 Settings
the device own the same IP address and MAC address, and network 1 and network 2 are
used as hot standby each other. When both network 1 and network 2 are normal, any of them
is used to communicate between the device and SAS. The device will automatically switch to
the other healthy network when one network is abnormal, which will not affect normal
communication.
Taking a CPU module with four Ethernet ports as an example, each bit is corresponding with
an Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet
port 2, Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and
Ethernet 2 is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is
shown as below.
Ethernet port 1
Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value
0 0 1 1 0011 3 1 0 0 1 1001 9
Ethernet port 2
Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value
0 1 0 1 0101 5 0 1 1 0 0110 6
Ethernet port 3
Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value
1 0 1 0 1010 10 1 1 0 0 1100 12
Ethernet port 4
CPU Module
Take the device's Ethernet ports 1 & 2 for example and assume that Port 1 and Port 2 are
bonded, and Port 1 is connected to NET 1 while Port 2 is connected to NET 2.
After the device is powered on, only Port 1 is activated when both NET 1 and NET 2 are
normal.
If NET1 is abnormal, Port 2 cannot be activated if NET 2 is also abnormal. The device will
keep trying on Port 1. 9
If Port 2 is working, the device will maintain this state even if NET 1 has been restored to
normal. It will be switched to Port 1 only if NET 2 is abnormal.
9 Access path: MainMenu Settings Global Settings Comm Settings DNP Settings
Date: 2022-01-17
9 Settings
9 1-AI32Int
2-AI16Int The “OBJ30” default
18 Obj30DefltVar_TCP1_DNP 3-AI32IntWoutF - 3-AI32IntWoutF variation of the No.1
4-AI16IntWoutF network DNP client
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
19 Obj32DefltVar_TCP1_DNP 2-AI16IntEvWoutT - 1-AI32IntEvWoutT variation of the No.1
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
20 Obj40DefltVar_TCP1_DNP 2-AO16Int - 1-AO32Int variation of the No.1
3-AO32Flt network DNP client
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Disabled
enable/disable the UR
(Unsolicited Response)
9
48 En_UR_TCP3_DNP - Disabled
Enabled message function of
the No.3 network DNP
client.
When this setting is
enabled, the master
Disabled station must activate
49 En_MsgCtrlUR_TCP3_DNP - Enabled
Enabled UR reporting by
enabling unsolicited
application function
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Access path: MainMenu Settings Global Settings Comm Settings IEC103 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
9 13 DST.MonthInYear_End
Jun
Jul
- Oct
It is used to set the end
month of DST.
Aug
Sep
Oct
Nov
Dec
1st
2nd It is used to set the end week
14 DST.WeekInMonth_End - 1st
3nd of DST.
4th
Date: 2022-01-17
9 Settings
[Opt_TimeSyn]
There are three selections for clock synchronization of the device, each selection includes
different time clock synchronization signals shown in the following table.
Option Description
IRIG-B: IRIG-B via serial port (RS-485 or TTL level), female BNC (TTL level) or
ST-connector port
Conventional PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), female BNC (TTL
level), ST-connector port or binary input
IEEE 1588: Clock message based on IEEE 1588 via Ethernet network
SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network
SAS
Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol
When the setting [Opt_TimeSyn] is set as "NoTimeSyn", the device will not send time
synchronization alarm signal.
The clock message via IEC103 protocol is INVALID when the device
receives the IRIG-B signal through RC-485 port.
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
Date: 2022-01-17
9 Settings
9 Config)
Percentage threshold of
4 25.U_UV 0.00~100.00 % 80.00 under voltage for CB
closing blocking
Percentage threshold of
5 25.U_OV 100.00~170.00 % 170.00 over voltage for CB closing
blocking
Percentage threshold of
6 25.f_UF 45.000~65.000 Hz 45.000 under frequency for CB
closing blocking
Date: 2022-01-17
9 Settings
25.Opt_Mode_DdChk
1 SynDdRefDd Dead check for both the reference and the synchronization sides
2 SynLvRefDd Live check for synchronization side and dead check for reference side
3 SynDdRefLv Dead check for synchronization side and live check for reference side
6 SynLvRefDd/SynDdRefLv Option 2 or 3
7 AnySideDd Option 1, 2 or 3
Date: 2022-01-17
9 Settings
[84.Opt_Code] = BCD
Only one of the higher 3 bits, which represent units, tens and twenties, appear to be
1;
Only one of the lower 10 bits, which represent decimal numbers, appear to be 1.
9 3 84.in_tap12 1: valid
0: invalid
Validation for decimal number of twenties
4 84.in_tap13 1: valid
0: invalid
Max. 26 positions, Example: 17 = 0000 0000 0100 0000 0000 0000 00 (BI_26 -> BI_01)
Validation condition:
Date: 2022-01-17
9 Settings
[84.Opt_Code] = BCD-PhSeg
Max. 39 positions, Example: 17 = 01 0111 (BI_06 -> BI_01 and BI_12 -> BI_07 and BI_18 ->
BI_13)
Input Signal
No. Description
Phase A Phase B Phase C
1 84.in_tap01 84.in_tap07 84.in_tap13
2 84.in_tap02 84.in_tap08 84.in_tap14
Decimal number 0~9 of units
1 84.in_tap03 84.in_tap09 84.in_tap15
2 84.in_tap04 84.in_tap10 84.in_tap16
3 84.in_tap05 84.in_tap11 84.in_tap17
Decimal number 0~3 of tens
4 84.in_tap06 84.in_tap12 84.in_tap18
Max. 8 positions, Example: 7 = 0100 0000 (BI_08 -> BI_01 and BI_16 -> BI_09 and BI_24 ->
BI_17)
Date: 2022-01-17
9 Settings
21 90V.En_LDCRX
Disabled
- Disabled
Enabling /disabling the line voltage drop 9
Enabled compensation function of ATCC
The line reactance of the line voltage drop
22 90V.X_LDC -100.00~100.00 ohm 0.00
compensation of ATCC
The line resistance of the line voltage drop
23 90V.R_LDC 0.00~100.00 ohm 0.00
compensation of ATCC
24 90V.t_ReguFail 0~3600 s 180 The judging period of ATCC failure
The limit of times of regulation in an ATCC
25 90V.Num_Regu 1~1000 - 48
process
26 90V.t_Period_Regu 1~24 h 24 The regulation period of and ATCC process
9 Disabled
The reception function of
GOOSE message whose
2 GLink_RecvSim - Disabled
Enabled “Simulation”=1 is Disabled or
Enabled
Date: 2022-01-17
9 Settings
Appendix A Glossary
The abbreviations adopted in this manual are listed as below.
ATCC Automatic Tap Changer Control DBDL Dead Bus Dead Line
DC Direct Current
B
DFR Disturbance Fault recorder
"b" Contact Breaker auxiliary contact (ANSI
DLLB Dead Line Live Bus
Standard Device Number 52B) that closes
when the breaker is open and opens when the DNP Distributed Network Protocol as per IEEE
breaker is closed. Std 1815-2012
DPS IEC 61850 data type: Double Point IRIG-B InterRange Instrumentation Group
Status Time code format B
PL Programmable Logic
H
PPM Pulse Per Minute
HMI Human-machine Interface
PPS Pulse Per Second
HSR High-availability Seamless Redundancy
PRP Parallel Redundancy Protocol
HV High-voltage
A PVR Parallel Voltage Regulation
HVDC High-voltage Direct Current
R
Date: 2022-01-17
Appendix A Glossary
RedBox Redundancy box, used for the SOE Sequence of Events–An ordered,
redundant connection of devices with only one time-stamped log of status changes at binary
interface to both network LAN A and LAN B inputs (also referred to as state inputs). SOE is
used to restore or analyze the performance, or
RMS Root Mean Square
an electrical power system itself, over a certain
RSTP Rapid Spanning Tree Protocol period of time.
S T
SCADA Supervision, Control And Data TCP/IP Transmission Control Protocol over
Acquisition Internet Protocol
A list of function numbers used to represent electrical protection and control element. The device
function numbers used in this manual include the following:
37 Undercurrent element
59 Overvoltage element A
64 Restricted earth fault element
46 Phase-balance current element
79 Reclosing element
These numbers are frequently used within a suffix letter to further designate their application. The
suffix letters used in this instruction manual include the following:
P Phase element
G Residual/Ground element
N Neutral/Ground element
Q Negative-sequence element
Date: 2022-01-17