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PCS-978S - X - Technical Manual - EN - Overseas General - X - R1.25

This document provides an overview of documentation for the PCS-978S Transformer Relay, including: - A datasheet that describes control, protection, measurement and supervision functions and hardware. - A technical manual that contains descriptions of functions, logic diagrams, settings and technical data. - An application manual with instructions for engineering the device using configuration software. - Safety information highlighting hazards and requiring disconnecting power before servicing the device.

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andriohead
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
1K views509 pages

PCS-978S - X - Technical Manual - EN - Overseas General - X - R1.25

This document provides an overview of documentation for the PCS-978S Transformer Relay, including: - A datasheet that describes control, protection, measurement and supervision functions and hardware. - A technical manual that contains descriptions of functions, logic diagrams, settings and technical data. - An application manual with instructions for engineering the device using configuration software. - Safety information highlighting hazards and requiring disconnecting power before servicing the device.

Uploaded by

andriohead
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 509

Copyright © 2022 NR. All rights reserved.

NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR
trademarks may be used without written permission. NR products appearing in this document may
be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and
benefits afforded under P.R. China and international copyright and patent laws in its products,
including but not limited to software, firmware and documentation. NR Engineering Co., Ltd. is
licensed to use this document as well as all intellectual property rights owned or held by NR
Electric Co., Ltd, including but not limited to copyright, rights in inventions, patents, know-how,
trade secrets, trademarks and trade names, service marks, design rights, database rights and
rights in data, utility models, domain names and all similar rights.

The information in this document is provided for informational use only and does not constitute a
legal contract between NR and any person or entity unless otherwise specified. Information in this
document is subject to change without prior notice.

To the extent required the products described herein meet applicable IEC and IEEE standards,
but no such assurance is given with respect to local codes and ordinances because they vary
greatly.

Although every reasonable effort is made to present current and accurate information, this
document does not purport to cover all details or variations in equipment nor provide for every
possible contingency to be met in connection with installation, operation, or maintenance. Should
further information be desired or should particular problems arise which are not covered
sufficiently for your purposes, please do not hesitate to contact us.
Preface

Preface

About This Manual

The manual describes the protection, control, measurement and supervision functions with the
information of relevant hardware for PCS-978S Transformer Relay.

Product Documentation Set

The intended use of manuals throughout the product lifecycle is shown in the figure below.

DS SLG TM AM CPM OCM IMM CM STG

Planning

Ordering

Engineering

Installing

Commissioning

Operation

Maintenance

Disposal

The datasheet (DS) contains describes the control, protection, measurement and supervision
functions with the information of relevant hardware for the device.

The selection guide (SLG) contains the explanation about the application option, the firmware
option, the software option, the hardware option and etc., and is instructive about how to order the
device based on expected configurations.

PCS-978S Transformer Relay I


Date: 2022-01-17
Preface

The technical manual (TM) contains operation principle descriptions, and lists function blocks,
logic diagrams, input and output signals, setting parameters and technical data, sorted per
function. The manual can be used as a technical reference during the engineering phase,
installation and commissioning phase, and during normal service.

The application manual (AM) contains application descriptions and instructions on how to
engineer the device using the configuration tool PCS-Studio. The manual can be used to find out
when and for what purpose a typical protection function can be used. The manual also
recommends a sequence for the engineering of protection, control, measurement and supervision
functions, HMI functions as well as communication engineering.

The communication protocol manual (CPM) describes the communication protocols supported
by the device. The manual concentrates on the vendor-specific implementations.

The operation and commissioning manual (OCM) contains instructions on how to operate and
commission the device. The manual describes how to identify disturbances and how to view
calculated and measured power grid data to determine the cause of a fault. The manual also
describes the process of testing the device in a substation which is not in service.

The installation and maintenance manual (IMM) contains instructions on how to install,
maintain and disposal the device. The manual provides procedures for mechanical and electrical
installation, lifecycle maintenance and repairing, and scrap disposal when decommissioning.

The cybersecurity manual (CM) describes the process for handling cyber security when
communicating with the device. Certification, Authorization with role-based access control, and
product engineering for cyber security related events are described and sorted by function. The
guideline can be used as a technical reference during the engineering phase, commissioning
phase, and during normal service.

The settings guide (STG) contains instructions on how to calculate the device's settings of
various functions (including the protection, automation, control, and supervision functions)
according to the different system parameters and fault conditions.

Safety Information

This manual is not a complete index of all safety measures required for operation of the
equipment (module or device). However, it comprises important information that must be followed
for personal safety, as well as to avoid material damage. Information is highlighted and illustrated
as follows according to the degree of danger:

Indicates an imminently hazardous situation that, if not avoided, will

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, could

result in death or serious injury.

II PCS-978S Transformer Relay

Date: 2022-01-17
Preface

Indicates a potentially hazardous situation that, if not avoided, may result

in minor or moderate injury or equipment damage.

Indicates that property damage can result if the measures specified are

not taken.

Important information about the product, please pay attention to avoid


undesired result.

Instructions and Warnings

The following hazard statements apply to this device.

Disconnect or de-energize all external connections BEFORE opening this


device. Contact with hazardous voltages and currents inside this device
can cause electrical shock resulting in injury or death.

Contact with instrument terminals can cause electrical shock that can
result in injury or death.

Use of this equipment in a manner other than specified in this manual can
impair operator safety safeguards provided by this equipment.

Have only qualified personnel service this equipment. If you are not
qualified to service this equipment, you can injure yourself or others, or
cause equipment damage.

This device is shipped with default passwords. Default passwords should


be changed to private passwords at installation. Failure to change each
default password to a private password may allow unauthorized access.
NR shall not be responsible for any damage resulting from unauthorized
access.

PCS-978S Transformer Relay III


Date: 2022-01-17
Preface

DO NOT look into the fiber (laser) ports/connectors.

DO NOT look into the end of an optical cable connected to an optical


output.

DO NOT perform any procedures or adjustments that this instruction


manual does not describe.

During installation, maintenance, or testing of the optical ports, ONLY use


the test equipment qualified for Class 1 laser products!

Incorporated components, such as LEDs, transceivers, and laser emitters,


are NOT user serviceable. Return units to NR for repair or replacement.

Equipment components are SENSITIVE to electrostatic discharge (ESD).


Undetectable permanent damage can result if you do not use proper ESD
procedures. Ground yourself, your work surface, and this equipment
BEFORE removing any cover from this equipment. If your facility is not
equipped to work with these components, contact NR about returning this
device and related NR equipment for service.

Insufficiently rated insulation can deteriorate under abnormal operating


conditions and cause equipment damage. For external circuits, use wiring
of SUFFICIENTLY RATED insulation that will not break down under
abnormal operating conditions.

SEVERE power and ground problems can occur on the communications


ports of this equipment as a result of using non-standard cables. Please

IV PCS-978S Transformer Relay

Date: 2022-01-17
Preface

use the wiring method recommended in the manual for communication


terminals.

DO NOT connect power to the relay until you have completed these
procedures and receive instruction to apply power. Equipment damage
can result otherwise.

Use of controls or adjustments, or performance of procedures other than


those specified herein, may RESULT IN hazardous radiation exposure.

The firmware may be upgraded to add new features or enhance/modify


existing features, please MAKE SURE that the version of this manual is
compatible with the product in your hand.

Document Conventions

 The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The
Glossary also contains definitions of important terms.

 Menu path is connected with the arrow "→" and bold.

For example: the access path of protection settings is: MainMenu→Settings→Protection


Settings

 Settings not in the table should be placed in brackets.

For example: the system setting [Opt_SysFreq]

 Cross-references are presented in italics.

For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1

 Binary input signals, binary output signals, analogs, LED lights, buttons, and other fixed
meanings, should be written in double quotes and bold.

For example: press the button "ENT".

Symbols

 AND Gate

PCS-978S Transformer Relay V


Date: 2022-01-17
Preface

& & &

 OR Gate

>=1 >=1 >=1

 Comparator

 Binary signal Input

BI xxx

 Signal input

SIG xxx

 Setting input

SET xxx

 Enable input

EN xxx

 Timer

Optional definite-time or inverse-time characteristic

Timer
t
t

 Timer

Fixed delay pickup (10ms), fixed delay dropout (2ms)

10ms 2ms

 Timer

VI PCS-978S Transformer Relay

Date: 2022-01-17
Preface

Settable delay pickup, fixed delay dropout

[Tset1] 0ms

 Timer

Fixed delay pickup, settable delay dropout

0ms [Tset2]

 Timer

Settable delay pickup, settable delay dropout

[Tset1] [Tset2]

 Generator

 Transformer

 Reactor

 Motor

 Capacitor

 Busbar

PCS-978S Transformer Relay VII


Date: 2022-01-17
Preface

 Circuit breaker

52

 Current transformer

3CT
*

 Voltage transformer

3VT

 Disconnector

 Earth

Three-phase Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U

Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2

Warranty

VIII PCS-978S Transformer Relay

Date: 2022-01-17
Preface

NR can provide up to 10-year warranty for this product. For warranty details, please consult the
manufacturer or agent for warranty information.

Document Structure

This manual is a comprehensive work covering the theories of protection, control, supervision,
measurement, etc. and the structure & technical data of relevant hardware. Read the sections that
pertain to your application to gain valuable information about using the PCS-978S. To concentrate
on the target sections of this manual as your job needs and responsibilities dictate. An overview of
each manual section and section topics follows.

1 Introduction
Introduces PCS-978S features, summarizes functions and applications of the device.

2 Technical Data
Lists device specifications, type tests, and ratings.

3 Protection Functions
Describes the function of various protection elements, gives detailed specifics on protection
scheme logic, and provides the relevant logic diagrams.

4 Control Functions
Describes the logic for the control of disconnectors and circuit breakers.

5 Measurement
Provides information on viewing fundamental and rms metering quantities for voltages and
currents, as well as power and energy metering data.

6 Supervision
Describes self-supervision technique to help diagnose potential difficulties should these occur and
includes the list of status notification messages. Provides a troubleshooting chart for common
device operation problems.

7 System Functions
Describes how to perform fundamental operations such as clock synchronization, communicating
with the device, switching active setting group, checking relay status, reading event reports and
SER (Sequential Events Recorder) records.

8 Hardware
Describes the hardware of the PCS series device family and provides general information on the
product structure and the modules technical data.

9 Settings
Provides a list of all settings and their ranges, unit, steps, defaults. The organization of the

PCS-978S Transformer Relay IX


Date: 2022-01-17
Preface

settings is similar to the settings organization in the device and in the PCS-Studio software.

Appendix A Glossary
Describes the abbreviations adopted in this manual.

Document Revision History

PN: ZL_PCS-978S_X_Technical Manual_EN_Overseas General_X

Current version: R1.25

Corresponding Version
Date Description of change
Document Software

R1.00 R1.00 2019-01-31  Form the original manual.

 Modification of voltage selection diagram.

 Update of switchgear control function.

 Update of VT circuit supervision.

 Update of technical data.

 Add switchgear position verification

 Add the description about digital substation application

 Add the description about digital interface

R1.10 R1.20 2019-12-09  Add technical data of GOOSE and SV

 Add certifications of IEC 61850, DNP, PRP, HSR, IEEE

1588

 Add alarm signals of GOOSE and SV

 Add NET-DSP plug-in module (NR6112B)

 Add SV communication settings

 Add GOOSE send links and receiving links

 Add SV links

X PCS-978S Transformer Relay

Date: 2022-01-17
Preface

 Add reactor protection application scenario

 Update of technical data

 Add reactor current differential protection function 87R

and inter-turn fault protection function 21IT


R1.20 R1.30 2020-03-05
 Add binary input and binary output module NR6661

 Add mechanical relay input and output module NR6662

 Replace the NET-DSP module NR6112B with NR6113

 Deletion of the DC analogue input module NR6631B

 Added distance protection function 21T

 Improved some description of restricted earth fault

protection

 Modified the manual closing synchronism check logic

R1.21 R1.31 2020-07-07  Added runaway trip description for tap changer control

 Revision of jitter processing principle of binary input

 Added binary output module NR6663A

 Added CPU modules NR6106BH, NR6106BJ and

NR6106BP

 Added one setting in 64REF protection function

R1.22 R1.32 2020-07-29  Deletion of the PWR module NR6305B

 Improved some description

 Added mechanical relay application

 Added automatic voltage regulation (90V) function

 Added parallel voltage regulation (PVR) function

 Added energy metering function


R1.23 R1.34 2020-12-30
 Added PWR module NR6311A

 Added binary input modules NR6604A and NR6611A

 Added Modbus communication settings

 Improved some description

PCS-978S Transformer Relay XI


Date: 2022-01-17
Preface

 Added the section “Product Documentation Set” in

preface part

 Updated the description about the product warranty

 Modified the technical data of mechanical tests

 Modified 87T CT circuit failure alarm logic diagram

 Modified the descriptions and logics of breaker failure

protection

 Modified the logics of overfrequency protection and

underfrequency protection

 Added the settings [81Oi.Opt_Trp/Alm] and

[81Ui.Opt_Trp/Alm]
R1.24 R1.35 2021-08-16
 Added the alarm signal “81Oi.Alm” and “81Ui.Alm”

 Added 81R frequency rate-of-change protection

 Modified the default value of the settings [IP_LAN1],

[IP_LAN2], [IP_LAN3] and [IP_LAN4]

 Modified the default pickup and dropoff time of binary

intputs from 20ms to 10ms

 Deleted PPM

 Revised the range of the setting [B01.Opt_NetMode].

 Added the setting [En_ConvModeSNTP] in Clock

Synchronization Settings

 Improved some description

R1.25 R1.35 2022-01-17  Improved some description

XII PCS-978S Transformer Relay

Date: 2022-01-17
1 Introduction

1 Introduction
1
Table of Contents

1.1 Application ....................................................................................................... 1-1


1.2 Protection Functions ....................................................................................... 1-2
1.3 Control Functions ............................................................................................ 1-5
1.4 Measurement and Metering Functions .......................................................... 1-6
1.5 Supervision Functions .................................................................................... 1-6
1.6 Communication Functions ............................................................................. 1-7
1.7 User Interfaces ................................................................................................. 1-7
1.8 Additional Functions ....................................................................................... 1-7
1.9 Features ............................................................................................................ 1-8

List of Figures

Figure 1.1-1 Typical application of an auto-transformer ....................................................... 1-1

Figure 1.1-2 Typical application of a shunt reactor ............................................................... 1-2

PCS-978S Transformer Relay 1-a


Date: 2022-01-17
1 Introduction

1-b PCS-978S Transformer Relay

Date: 2022-01-17
1 Introduction

1.1 Application
1
PCS-978S transformer relay provides fast and selective protection, control and monitoring for
two-winding transformers, three-winding transformers, auto-transformers, as well as reactors. The
full transformer protections are configurable by user. Ancillary functions of fault diagnostic,
disturbance records, event records and communication function are integrated in the device.

The PCS-978S is applicable not only to conventional substations, but also to digital substations. It
supports IEC 61850 Editions 1 and 2 and provides GOOSE and SV network interfaces with high
real-time performance. The process level network supports peer-to-peer (P2P) mode and
networking mode, including single network mode and dual network mode. The station level
network could also receive and send MMS messages (such as interlocking signals) or process
level GOOSE messages (such as trip signals).

The function diagrams for protecting an auto-transformer and a reactor are respectively shown
below.

HVS

52 3 VT

*
3 CT

64 50B
87T 49 87W 67G 67P 21T
REF F

MVS 50/
*
51P

1 CT
* *
52 50/
* 67Q
3 CT 51G
1 CT
1 CT
*
50/
MR
51Q
1 CT

3 VT

59P 59G 27P 24 81O 81U 81R

3 CT
*

52
3 VT

LVS

Figure 1.1-1 Typical application of an auto-transformer

PCS-978S Transformer Relay 1-1


Date: 2022-01-17
1 Introduction

Bus1

1 52

Line

3VT

52 50/
21IT 49 87R
51P

*
3 CT

50/
Shunt reactor 51G

3 CT
52
*

Bus2

1 CT
*

Neutral earthing reactor

Figure 1.1-2 Typical application of a shunt reactor

1.2 Protection Functions

ANSI Protection Functions Remark


 Biased differential protection with three slopes.
 Biased DPFC differential protection.
 Unrestrained instantaneous differential protection.
 Optional inrush current distinguished principles:
harmonic criterion or waveform distortion.
 Optional harmonic blocking modes: self-adaptive
87T Transformer differential protection
1Pblk1P mode, 2PBlk3P mode, 1Pblk3P mode.
 Overexcitation detection: fifth harmonic or third
harmonic criterion.
 Optional transfer methods: △→Y or Y→△.
 Independent CT saturation criterion.
 Differential CT circuit failure supervision.
 Optional direction element.
 CT transient characteristic difference detection.
64REF Restricted earth-fault protection
 CT saturation detection based on 2nd and 3rd
harmonics.

1-2 PCS-978S Transformer Relay

Date: 2022-01-17
1 Introduction

ANSI Protection Functions Remark


 CT transient characteristic difference detection.

87W Winding differential protection CT saturation detection based on 2nd and 3rd
harmonics.
1
 Biased DPFC differential protection.
 Biased current differential protection.
 Unrestrained instantaneous differential protection.
87R Reactor differential protection
 Independent CT saturation criterion.
 Harmonic blocking criterion.
 Differential CT circuit failure supervision.
 Zero-sequence power directional element and
21IT Inter-turn fault protection zero-sequence impedance element.
 CT and VT circuit failure blocking.
 Two stages definite-time overexcitation protection.
 Stage 1 of definite-time overexcitation protection for
trip purpose.
24 Overexcitation protection  Stage 2 of definite-time overexcitation protection for
alarm purpose.
 One stage inverse-time overexcitation protection for
both alarm purpose and trip purpose.
 Up to 6 stages with independent logic for high-voltage
side, middle-voltage side, low-voltage side 1 and side
2 respectively, up to 3 stages with independent logic
for common winding side.
67P  Voltage control element for each stage.
Phase overcurrent protection
50/51P  Optional direction element for each stage.
 Optional definite-time characteristic and inverse-time
characteristic for each stage.
 Trip purpose or alarm purpose for each stage.
 Harmonic control element for each stage.
 Up to 4 stages with independent logic for high-voltage
side, middle-voltage side, low-voltage side 1 and side
2, and common winding side respectively.
 Optional direction element for each stage.
 Optional measured zero-sequence current or
67G
Earth fault protection calculated zero-sequence current.
50/51G
 Optional definite-time characteristic and inverse-time
characteristic for each stage.
 Selectable trip purpose or alarm purpose for each
stage.
 Harmonic control element for each stage.

PCS-978S Transformer Relay 1-3


Date: 2022-01-17
1 Introduction

ANSI Protection Functions Remark


 Up to 2 stages with independent logic for high-voltage

1 67Q Negative-sequence overcurrent


side, middle-voltage side, low-voltage side 1 and side
2 respectively.
50/51Q protection  Optional direction element for each stage.
 Optional definite-time characteristic and inverse-time
characteristic for each stage.
 Two stages thermal overload protection, and one
49 Thermal overload protection stage for alarm purpose and the other stage for trip
purpose.
 Up to 6 circuit breakers are supported.
 Phase-segregated re-trip and three-phases re-trip.
 Optional current criterion (phase overcurrent element,
50BF Breaker failure protection zero-sequence overcurrent element,
negative-sequence overcurrent element).
 Optional contact check criterion.
 Two time delays.
 Up to 2 stages with independent logic for high-voltage
side, middle-voltage side, low-voltage side 1 and side
2 respectively.
 Optional definite-time characteristic and inverse-time
59P Phase overvoltage protection characteristic for each stage.
 Optional phase voltage or phase-to-phase voltage.
 Optional “1-out-of-3” logic or “3-out-of-3” logic.
 Selectable trip purpose or alarm purpose for each
stage.
 Up to 2 stages with independent logic for high-voltage
side, middle-voltage side, low-voltage side 1 and side
2 respectively.
 Optional definite-time characteristic and inverse-time
characteristic for each stage.
27P Phase undervoltage protection
 Optional phase voltage or phase-to-phase voltage.
 Optional “1-out-of-3” logic or “3-out-of-3” logic.
 Blocked by instantaneous VT circuit failure.
 Selectable trip purpose or alarm purpose for each
stage.

1-4 PCS-978S Transformer Relay

Date: 2022-01-17
1 Introduction

ANSI Protection Functions Remark


 Up to 2 stages with independent logic for high-voltage
side, middle-voltage side, low-voltage side 1 and side
2 respectively.
1
 Optional measured zero-sequence voltage or
59G Residual overvoltage protection calculated zero-sequence voltage.
 Optional definite-time characteristic and inverse-time
characteristic for each stage.
 Selectable trip purpose or alarm purpose for each
stage.
 Up to 4 stages with independent logic.
 Voltage control element.
81O Overfrequency protection
 Selectable trip purpose or alarm purpose for each
stage
 Up to 4 stages with independent logic.
 Voltage control element.
81U Underfrequency protection
 Selectable trip purpose or alarm purpose for each
stage
 Up to 2 stages with independent logic
 Voltage control element
81R Frequency rate-of-change protection
 Selectable trip purpose or alarm purpose for each
stage
 Up to 4 zones for high- and middle-voltage side
respectively.
 3 independent phase-to-ground distance elements for
each zone
 3 independent phase-to-phase distance elements for
each zone
 Selectable quadrilateral characteristics or mho
characteristics
21T Distance protection  Independent impedance settings and time delays for
each zone
 Zero-sequence current compensation for
phase-to-ground distance element
 Selectable forward direction, reverse direction or non
direction
 Load encroachment for each zone
 Power swing blocking and releasing for each zone
 Faulty phase selection for each zone

1.3 Control Functions

 Switchgear control

PCS-978S Transformer Relay 1-5


Date: 2022-01-17
1 Introduction

 Double point status synthesis

 Remote/Local control mode switch


1  Interlocking logic for control

 Direct control

 Closing synchronism check with voltage selection

 Switchgear trip counter

 Tap position indicator and control

 Automatic voltage regulation (90V)

 Parallel voltage regulation (PVR)

1.4 Measurement and Metering Functions

 U, I, P, Q, S, Cos, f

 Positive, negative and zero sequences

 Max.15th harmonics

 Energy metering (active and reactive energies for import and export)

 DC analog inputs (0~±20mA or 0~±10Vdc)

1.5 Supervision Functions

 CT circuit failure supervision (CTS)

 VT circuit failure supervision (VTS)

 Tripping circuit supervision (TCS)

 Self diagnostic

 Powerful faults recording (max. buffer for 10,000 sampled points at 1.2 or 9.6 kHz)

 Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.

 Disturbance recorder including 64 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)

 Single line diagram representation in display

1-6 PCS-978S Transformer Relay

Date: 2022-01-17
1 Introduction

1.6 Communication Functions

 Support of various protocols 1


Modbus, DNP3.0, IEC 60870-5-103, IEC 61850 Ed.1 & Ed.2, IEC 61850 MMS Server, IEC
61850-8-1 GOOSE, IEC 61850-9-2LE SV, IEC 62439 Parallel Redundancy Protocol (PRP),
IEC 62439 High-availability Seamless Ring (HSR) Redundancy Protocol, IEEE 802.1w Rapid
Spanning Tree Protocol (RSTP).

 Up to four 10Base-T/100Base-TX copper Ethernet ports

 Up to fourteen 100Base-FX optical Ethernet ports

 Up to four 1000Base-SX optical Ethernet ports

 Two RS-485 serial ports for communication, the second one could be used as a RS-232 port
for printer

 One RS-485/TTL serial port for clock synchronization

 One BNC port for clock synchronization

 One ST-connector port for clock synchronization

 Two RJ45 debugging ports (front and rear)

1.7 User Interfaces

 Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and set-point
adjustment

 Push buttons for open/close, switch for selection between local and remote control, and user's
login and logout authority management

 4 Programmable operator pushbuttons with user-configurable labels

 Up to 18 programmable target LEDs with user-configurable labels

 1 RS-232 or RS-485 rear ports for printer

 Language switchover—English+ selected language

 Configuration tool—PCS-Studio

1.8 Additional Functions

 User programmable logic

 Switching system phase sequences function (ABC or ACB)

 Clock synchronization

PCS-978S Transformer Relay 1-7


Date: 2022-01-17
1 Introduction

 IRIG-B: IRIG-B via serial port (RS-485 or TTL level), female BNC (TTL level) or
ST-connector port

1  PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), female BNC (TTL
level), ST-connector port or binary input

 IEEE 1588: Clock message based on IEEE 1588 via Ethernet network

 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network

 SNTP (BC): Broadcast SNTP mode via Ethernet network

 Message (IEC103/Modbus/DNP3.0): Clock messages through IEC103 protocol, Modbus


protocol and DNP3.0 protocol

 Cyber security

 NERC CIP

 IEC 62351

 IEC 62443

 IEEE 1686

1.9 Features

 Unified software and hardware platform, comprehensive power grid solutions of protection,
measurement and monitoring, easy to use and maintain.

 High reliability and redundancy design for drive systems of the sampling circuit and the output
circuit ensure that overall reliability of the device is high. Real-time sampling based on dual AD
can mutually check and detect the potential abnormality in the sampling circuit in time. The
control power supply of the output relay is independent with the control circuit of trigger signals,
which can prevent from undesired operation caused by the abnormality of drive circuit of
output relays.

 Various function modules can satisfy various situations according to the different requirements
of users. Flexible and universal logic programming, user-defined configuration of BI/BOs,
buttons and LEDs and powerful analog programming are supported.

 Modularized hardware design makes the device be easily upgraded or repaired by a qualified
service person. It can be mixed with different I/O modules, with online self-check and
monitoring function, and the device can be restored from abnormal operation only need to
replace a single abnormal module.

 Support memory check and error correction function, ensure high reliability and safety.

 Support the internet communication protocol of native PRP/HSR and RSTP.

 Fully compatible with IEC 61850 edition 1 & edition 2, support MMS service, IEC 62351
communication service, GOOSE communication in station level & process level, SV

1-8 PCS-978S Transformer Relay

Date: 2022-01-17
1 Introduction

communication with multi-sampling rate.

 Full comply with cyber security standards, including IEC62443, IEC62351, IEEE1686,
NERC-CIP, support role based access control (RBAC), security audit, security encryption 1
communication and security tool, improve the cyber security capability of devices.

 Powerful COMTRADE fault and disturbance recording function is supported. The whole
recording time is automatically configurable by the fault duration, which is convenient to fault
analysis and replay. The recording sample rate is up to 9.6kHz.

 Settable secondary rated current (1A/5A) and settable voltage threshold of binary input

 Support LCD, control and multifunction button

 Support flush mounting, semi-flush mounting, surface mounting, wall mounting and other
mounting methods.

 Cross screw IO, CT/VT terminals can support AWG12 specification connector and 4mm 2 lead

 Multiple variants with case size 1/1 or 1/2 × 19"

 Protection class of front side is up to IP54

 PCS-Studio is the application software on the user's PC for the interface with PCS S series
devices providing all the related functionality. It ranges from device configuration to full
substation design of bay integration.

 Support IEEE1588, IRIG-B clock synchronization

 Support actual system phase sequence, either ABC or ACB, incorrect connection of actual
phase sequence can automatically be verified and relevant protection functions can be
blocked.

 Equipped with high-speed large capacity output relay, its operation speed is less than 1ms and
its break capacity is up to 10A. The real-time supervision for output drive circuit can detect the
abnormality in advance.

 Support setup up to 40 users and allow each user to own different password and access
authority.

 High degree of functional integration and flexible configuration modes, transformer main
protection and back-up protection can be integrated in one device, or be separated in two
devices.

 Up to 36 analog inputs can be provided and configured flexibly.

 The tripping output contacts can be configured by tripping matrix, which is flexible, convenient
and suitable to any mode of tripping.

 The relay supports at most 6 branches differential protection. The transformer angle can be
adjusted flexibly, and any transformer angle compensation mode is supported and any side
can be chosen as the reference side of differential protection.

PCS-978S Transformer Relay 1-9


Date: 2022-01-17
1 Introduction

 Reliable differential CT circuit failure supervision. The relay can detect multi-phase CT
wire-break, multi-side CT wire-break, short-circuit, and other complex situation. The

1 corresponding logic setting can be used to select blocking differential protection or not, in case
of CT circuit failure.

 Multiple inrush current blocking options are provided. Self-adaptive inrush current blocking
criterion can ensure the relay fast operation for transformer energized on to a slight fault,
meanwhile it will avoid the unwanted operation in the case of the energization inrush current
caused by energizing transformer with no load, the recovery inrush current caused by cutting
off the transformer external fault, and the sympathetic inrush current.

 Biased DPFC differential protection is regardless of load current and is sensitive to small
internal fault current within the transformer. Its anti CT saturation performance is also strong.

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2 Technical Data

2 Technical Data

Table of Contents

2.1 Electrical Specifications ................................................................................. 2-1 2


2.1.1 AC Current Input ................................................................................................................... 2-1

2.1.2 AC Voltage Input ................................................................................................................... 2-1

2.1.3 Power Supply ....................................................................................................................... 2-2

2.1.4 DC Analogue Input ............................................................................................................... 2-3

2.1.5 Binary Input .......................................................................................................................... 2-3

2.1.6 Binary Output........................................................................................................................ 2-6

2.2 Mechanical Specifications .............................................................................. 2-8


2.3 Ambient Temperature and Humidity Range .................................................. 2-8
2.4 Communication Port ....................................................................................... 2-9
2.4.1 EIA-485 Port ......................................................................................................................... 2-9

2.4.2 Copper Ethernet Port ........................................................................................................... 2-9

2.4.3 Optical Ethernet Port ............................................................................................................ 2-9

2.4.4 Print Port ............................................................................................................................. 2-10

2.4.5 Clock Synchronization Port ................................................................................................ 2-10

2.5 Type Tests .......................................................................................................2-11


2.5.1 Environmental Tests ........................................................................................................... 2-11

2.5.2 Mechanical Tests ................................................................................................................ 2-11

2.5.3 Electrical Tests .................................................................................................................... 2-11

2.5.4 Electromagnetic Compatibility ............................................................................................ 2-12

2.6 Certifications .................................................................................................. 2-13


2.7 Liquid Crystal Display (LCD) ........................................................................ 2-14
2.8 Terminals ........................................................................................................ 2-14
2.8.1 Ring Ferrule ........................................................................................................................ 2-14

2.8.2 Pin Ferrule .......................................................................................................................... 2-14

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2 Technical Data

2.9 Measurement Scope and Accuracy ............................................................. 2-15


2.10 Management Function................................................................................. 2-15
2.10.1 Control Performance ........................................................................................................ 2-15

2.10.2 Clock Performance ........................................................................................................... 2-16

2 2.10.3 Fault and Disturbance Recording..................................................................................... 2-16

2.10.4 Binary Input Signal ........................................................................................................... 2-16

2.11 Protective Functions ................................................................................... 2-16


2.11.1 Transformer Current Differential Protection (87T) ............................................................ 2-16

2.11.2 Restricted Earth Fault Protection (64REF) ....................................................................... 2-17

2.11.3 Winding Differential Protection (87W) .............................................................................. 2-18

2.11.4 Reactor Differential Protection (87R) ............................................................................... 2-18

2.11.5 Inter-turn Fault Protection (21IT) ...................................................................................... 2-18

2.11.6 Overexcitation Protection (24) .......................................................................................... 2-18

2.11.7 Phase Overcurrent Protection (50/51P, 67P) ................................................................... 2-19

2.11.8 Earth Fault Overcurrent Protection (50/51G, 67G) .......................................................... 2-20

2.11.9 Negative-sequence Overcurrent Protection (50/51Q, 67Q) ............................................. 2-20

2.11.10 Thermal Overload Protection (49) .................................................................................. 2-21

2.11.11 Breaker Failure Protection (50BF) .................................................................................. 2-21

2.11.12 Overvoltage Protection (59P) ......................................................................................... 2-21

2.11.13 Residual Overvoltage Protection (59G) ......................................................................... 2-22

2.11.14 Undervoltage Protection (27P) ....................................................................................... 2-22

2.11.15 Overfrequency Protection (81O) .................................................................................... 2-22

2.11.16 Underfrequency Protection (81U)................................................................................... 2-22

2.11.17 Frequency Rate-of-change Protection (81R) ................................................................. 2-23

2.11.18 Distance Protection (21T) ............................................................................................... 2-23

2.12 Communication Functions ......................................................................... 2-23


2.12.1 GOOSE ............................................................................................................................ 2-23

2.12.2 SV ..................................................................................................................................... 2-23

2-b PCS-978S Transformer Relay

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2 Technical Data

2.1 Electrical Specifications

“System phase sequence”, which can be set by PCS-Studio, this setting


informs the device of the actual system phase sequence, either ABC or 2
ACB. CT and VT inputs on the device, labeled as A, B and C, must be
connected to system phase A, B and C for correct operation.

2.1.1 AC Current Input

Phase rotation ABC or ACB

Nominal frequency (fn) 50Hz, 60Hz

Rated current (In) 1A/5A (settable)

Linear to 0.05In~40In

Thermal withstand

-continuously 4In

-for 10s 30In

-for 1s 100In

-for half a cycle 250In

Burden <0.05VA/phase @1A, <0.25VA/phase @5A

Number Up to 24 (6U, 1/2 × 19") or 36 (6U, 1/1 × 19") AC current inputs

2.1.2 AC Voltage Input

Phase rotation ABC or ACB

Nominal frequency (fn) 50Hz, 60Hz

Rated voltage (Un) 100V~130V

Linear to 1V~300V

Thermal withstand Phase-to-ground Phase-to-phase

-continuously 300V 519V

-10s 600V 1038V

-1s 660V 1141V

Burden at rated <0.10VA/phase @100V

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Date: 2022-01-17
2 Technical Data

Number Up to 12 (6U, 1/2 × 19") or 18 (6U, 1/1 × 19") AC voltage inputs

2.1.3 Power Supply

100Vac/110Vac/
24Vdc/30Vdc 110Vdc/125Vdc/ 115Vac/120Vac/
Rated voltage
2 48Vdc/60Vdc 220Vdc/250Vdc
127Vac/220Vac/

230Vac/240Vac/250Vac

IEC 61000-4-11:2017

Permissible voltage range IEC 61000-4-29:2000

18~72Vdc 88~300Vdc 80~275Vac

IEC 60255-26-2013
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage

Quiescent condition Max. 15W (default hardware configuration)

Additional for each


Max. 0.35W
energized SFP socket

Quiescent condition Max. 1W

For BI modules with high power


binary inputs (Binary inputs which
provide settable conducting mode
by high power with constant current
drain):
0.014W @24Vdc
0.031W @48Vdc
0.096W @110Vdc
Burden Additional for each plug-in
Additional for each energized 0.115W @125Vdc
binary input (BI) module 0.270W @220Vdc
contact 0.330W @250Vdc
For BI modules without high power
binary inputs:
0.004W @ 24Vdc
0.015W @ 48Vdc
0.080W @ 110Vdc
0.106W @ 125Vdc
0.320W @ 220Vdc
0.410W @ 250Vdc

Additional for each plug-in Quiescent condition Max. 0.1W

binary output (BO) module Additional for each energized Max. 0.44W

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2 Technical Data

relay

Additional for each plug-in

SV sampling (NET-DSP) Max. 7W

module

2.1.4 DC Analogue Input 2


Standard IEC 60255-1: 2009

Input range 0~±20mA 0~±10V

Input resistance 230Ω >1MΩ

Accuracy 0.1% 0.1%

Up to 8 (ring ferrule) or 12 (pin ferrule) channels of DC analogue inputs,


Number
all of the channels can be set as 0~±20mA or 0~±10Vdc.

2.1.5 Binary Input

Settable pickup voltage and dropout voltage

Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc

Rated current drain 0.73mA 0.83mA 1.47mA 1.67mA

On value (default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc

Off value (default set) <55Vdc <62.5Vdc <110Vdc <125Vdc

Maximum permissible voltage 300Vdc

Withstand voltage 2000Vac, 2800Vdc (1min)

Up to 84 (6U, 1/2 × 19", ring ferrule), 105 (6U, 1/2 × 19", pin ferrule), 234
Number (6U, 1/1 × 19", ring ferrule), or 297 (6U, 1/1 × 19", pin ferrule) binary
inputs

Settable pickup voltage and dropout voltage

Rated voltage 110Vac 220Vac

Rated current drain 0.73mA 1.47mA

On value (default set) 69.3~132Vac 138.6~264Vac

Off value (default set) <55Vac <110Vac

Maximum permissible voltage 300Vac

Withstand voltage 2000Vac, 2800Vdc (1min)

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2 Technical Data

Up to 84 (6U, 1/2 × 19", ring ferrule), 105 (6U, 1/2 × 19", pin ferrule), 234
Number (6U, 1/1 × 19", ring ferrule), or 297 (6U, 1/1 × 19", pin ferrule) binary
inputs

Settable pickup voltage and dropout voltage

Rated voltage 24Vdc 48Vdc


2
Rated current drain 0.16mA 0.32mA

On value (default set) 15.12~28.8Vdc 30.24~57.6Vdc

Off value (default set) <12Vdc <24Vdc

Maximum permissible voltage 300Vdc

Withstand voltage 2000Vac, 2800Vdc (1min)

Up to 84 (6U, 1/2 × 19", ring ferrule), 105 (6U, 1/2 × 19", pin ferrule), 234
Number (6U, 1/1 × 19", ring ferrule), or 297 (6U, 1/1 × 19", pin ferrule) binary
inputs

Settable pickup voltage and dropout voltage for high power binary input

Rated voltage 110Vdc 220Vdc

Rated current drain 0.86mA 1.23mA

On value (Default set) 69.3~132Vdc 138.6~264Vdc

Off value (Default set) <55Vdc <110Vdc

Maximum permissible voltage 300Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 39 (6U, 1/2 × 19", ring ferrule), 42 (6U, 1/2 × 19", pin ferrule), 117

Number (6U, 1/1 × 19", ring ferrule) or 126 (6U, 1/1 × 19", pin ferrule), binary

inputs

Settable pickup voltage and dropout voltage for high power binary input

Rated voltage 24Vdc 48Vdc

Rated current drain 0.58mA 0.66mA

On value (Default set) 15.12~28.8Vdc 30.24~57.6Vdc

Off value (Default set) <12Vdc <24Vdc

Maximum permissible voltage 300Vdc

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2 Technical Data

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 39 (6U, 1/2 × 19", ring ferrule), 42 (6U, 1/2 × 19", pin ferrule), 117

Number (6U, 1/1 × 19", ring ferrule) or 126 (6U, 1/1 × 19", pin ferrule), binary

inputs

2
Fixed pickup voltage and dropout voltage for binary input of MR (Mechanical Relay) contact

Rated voltage 110Vdc

Rated current drain 12mA

On value >77Vdc

Off value <60.5Vdc

Maximum permissible voltage 121Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 15 (6U, 1/2 × 19", pin ferrule) or 45 (6U, 1/1 × 19", pin ferrule) MR
Number
inputs

Fixed pickup voltage and dropout voltage for binary input of MR contact

Rated voltage 125Vdc

Rated current drain 12mA

On value >87.5Vdc

Off value <68.75Vdc

Maximum permissible voltage 137.5Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 15 (6U, 1/2 × 19", pin ferrule) or 45 (6U, 1/1 × 19", pin ferrule) MR
Number
inputs

Fixed pickup voltage and dropout voltage for binary input of MR contact

Rated voltage 220Vdc

Rated current drain 6.6mA

On value >154Vdc

Off value <121Vdc

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2 Technical Data

Maximum permissible voltage 242Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 15 (6U, 1/2 × 19", pin ferrule) or 45 (6U, 1/1 × 19", pin ferrule) MR
Number
inputs

2 2.1.6 Binary Output

Tripping/signaling contact

Output mode Potential free contact

Max. system voltage 250Vac, 300Vdc

Continuous carry 10A

Pickup time (Typical value) <5ms

Dropout time (Resistive load) <6ms

0.5A@48Vdc

0.35A@110Vdc

Breaking capacity (L/R=40ms) 0.30A@125Vdc

0.20A@220Vdc

0.15A@250Vdc

0.5A@48Vdc

0.35A@110Vdc
Cyclic Capacity (2.5 cycle/second,
0.30A@125Vdc
L/R=40ms)
0.20A@220Vdc

0.15A@250Vdc

30A@3s
Short duration current
50A@1s

Durability (Loaded contact) 10000 operations

Up to 44 (6U, 1/2 × 19", ring ferrule), 56 (6U, 1/2 × 19", pin ferrule), 122
Number (6U, 1/1 × 19", ring ferrule), or 158 (6U, 1/1 × 19", pin ferrule)
tripping/signal contacts

Heavy-capacity tripping contact

Output mode Potential free contact

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2 Technical Data

MOV Protection (Max. voltage ) 350Vdc, 275Vac

Continuous carry 10A

Pickup time (Typical value) <1ms

Dropout time (Resistive load) <10ms

10A@48V 2
10A@110V
Breaking capacity (L/R=40ms)
10A@125V

10A@250V

10A@48V L/R=40ms
Cyclic Capacity (4 cycle/second,
10A@110V L/R=40ms
followed by 2 minutes idle for thermal
10A@125V L/R=40ms
dissipation)
10A@250V L/R=20ms

30A@3s
Short duration current
50A@1s

Durability (Loaded contact) 10000 operations

Up to 12 (6U, 1/2 × 19", ring ferrule), or 36 (6U, 1/1 × 19", ring ferrule)
Number
heavy-capacity tripping contacts

MR (Mechanical Relay) contact

Output mode Potential free contact

Max. system voltage 380Vac, 250Vdc

Continuous carry 8A

Pickup time (Typical value) <10ms

Dropout time (Resistive load) <10ms

1.00A@48Vdc

0.50A@110Vdc

Breaking capacity (L/R=40ms) 0.40A@125Vdc

0.25A@220Vdc

0.20A@250Vdc

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2 Technical Data

12A@3s

15A@1s
Short duration current
[email protected]

[email protected]

2 Durability (Loaded contact) 10000 operations

Up to 45 (6U, 1/2 × 19", pin ferrule) or 135 (6U, 1/1 × 19", pin ferrule)
Number
MR outputs

2.2 Mechanical Specifications

Chassis color Silver grey

Approx. 8.66kg (6U, 1/2 × 19")


Weight per device
Approx. 15.27kg (6U, 1/1 × 19")

Chassis material Aluminum alloy

Location of terminal Rear panel of the device

Device structure Plug-in modular type @ rear side, integrated front plate

Protection Class

Standard IEC 60529-2013

IP52

Front side IP54 (valid for surface mounting mode of 6U 19" × 1/2 case with sealing

strip)

Other sides IP50

Rear side, connection terminals IP20

2.3 Ambient Temperature and Humidity Range

Standard IEC 60255-1:2009

-40°C to +80°C (Readability of display may be impaired below -20°C


Operating temperature
and above 70℃ )

Transport and storage temperature


-40°C to +80°C
range

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2 Technical Data

Permissible humidity 5%-95%, without condensation

Pollution degree Ⅱ

Altitude <3000m

2.4 Communication Port


2
2.4.1 EIA-485 Port

Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

Protocol IEC 60870-5-103:1997 or Modbus

Capacity Max. 32

Transmission distance Max. 500m

Safety level Isolation to ELV level

Twisted pair Screened twisted pair cable

2.4.2 Copper Ethernet Port

Connector type RJ-45

Transmission rate 100Mbit/s

Transmission standard 100Base-TX

Transmission distance Max.100m

Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850

Safety level Isolation to ELV level

2.4.3 Optical Ethernet Port

Characteristic Glass optical fiber

Connector type LC

Transmission standard 100Base-FX

Fibre type Multi-mode

Transmission distance Max. 2km

Wave length 1310nm

Transmission power 50μm: Min. -24dBm 62.5μm: Min. -20dBm

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2 Technical Data

Receiving power Min. -31dBm

Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850

Safety level Isolation to ELV level

Characteristic Glass optical fiber


2
Connector type LC

Transmission standard 1000Base-SX

Fibre type Multi-mode

Transmission distance Max. 500m

Wave length 1310nm/850nm

Transmission power Min. -9dBm

Receiving power Min. -18dBm

Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850

Safety level Isolation to ELV level

2.4.4 Print Port

Type RS-232

Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

Printer type EPSON® 300K printer

Safety level Isolation to ELV level

2.4.5 Clock Synchronization Port

Type RS-485 differential level (Serial port)

Input Demodulated IRIG-B or PPS

Maximum voltage 6V

Input impedance 12kΩ

Isolation 500Vdc

Type TTL level (Serial port or female BNC port)

Input Demodulated IRIG-B or PPS

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2 Technical Data

Nominal voltage 5Vdc±10%

Maximum voltage 5.5Vdc

Characteristic impedance 50Ω

Isolation 500Vdc

2
Characteristic Glass optical fiber

Input Demodulated IRIG-B or PPS

Connector type ST

Fiber type Multi-mode

Wave length 850nm

Peak optical input power

Logic level HIGH Maximum -40dBm

Logic level LOW Maximum -10dBm, Minimum -24dBm

2.5 Type Tests

2.5.1 Environmental Tests

Dry cold test IEC60068-2-1:2007

Dry heat test IEC60068-2-2:2007

Damp heat test, cyclic IEC60068-2-30:2005

2.5.2 Mechanical Tests

Vibration IEC 60255-21-1:1988 Class Ⅱ

Shock IEC 60255-21-2:1988 Class Ⅱ

Bump IEC 60255-21-2:1988 Class Ⅰ

Seismic IEC 60255-21-3:1988 Class Ⅱ

2.5.3 Electrical Tests

Standard IEC 60255-27:2013

Dielectric tests Test voltage 2kV, 50Hz, 1min

Impulse voltage tests Test voltage 5kV

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2 Technical Data

Overvoltage category Ⅲ

Insulation resistance measurements Isolation resistance >100MΩ@500VDC

2.5.4 Electromagnetic Compatibility

IEC 60255-26:2013
2 1MHz burst disturbance test Common mode: class Ⅲ 2.5kV

Differential mode: class Ⅲ 1.0kV

IEC 61000-4-2-2008 class Ⅳ

Electrostatic discharge test For contact discharge: 8kV

For air discharge: 15kV

IEC 60255-26:2013 class Ⅲ

Frequency sweep

Radiated amplitude-modulated

Radio frequency interference tests 10V/m (rms), f=80~1000MHz, 1400~2700MHz

Spot frequency

Radiated amplitude-modulated

10V/m (rms), f=80MHz/160MHz/450MHz/900MHz

IEC 60255-26:2013

Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 5kHz, 5/50ns

Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns

IEC 60255-26:2013

Power supply, AC input, I/O port: class Ⅳ, 1.2/50us


Surge immunity test
Common mode: 4kV

Differential mode: 2kV

IEC 60255-26:2013

Power supply, AC, I/O, Comm. Terminal: Class Ⅲ , 10V (rms),


Conducted RF electromagnetic
150kHz~80MHz
disturbance
Spot frequency

10V (rms), f=27MHz/68MHz

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2 Technical Data

Power frequency magnetic field IEC 61000-4-8: 2009

Immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s

IEC 61000-4-9:2016
Pulse magnetic field immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s

Damped oscillatory magnetic field IEC 61000-4-10:2016 2


immunity class Ⅴ, 100kHz & 1MHz–100A/m

IEC 60255-26:2013

Conducted emission 0.15MHz~0.50MHz: 79dB (μV) quasi peak, 66dB (μV) average

0.50MHz~30MHz: 73dB (μV) quasi peak, 60dB (μV) average

IEC 60255-26:2013

30MHz~230MHz: 40dB (μV/m) quasi peak @10m,

50dB (μV/m) quasi peak @3m


Below 1GHz
230MHz~1000MHz: 47dB (μV/m) quasi peak @10m,

Radiated emission 57dB (μV/m) quasi peak @3m

1GHz~3GHz: 56dB (μV/m) average, 76dB (μV/m)

peak @3m
Above 1GHz
3GHz~6GHz: 60dB (μV/m) average, 80dB (μV/m)

peak @3m

IEC 60255-26:2013

Up to 200ms for dips to 40% of rated voltage without


Voltage dips
Auxiliary power supply performance
reset

Voltage short 50ms for interruption without rebooting (Typical

interruptions configuration)

2.6 Certifications

 ISO9001:2015

 ISO14001:2015

 ISO45001:2018

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2 Technical Data

 ISO/IEC27001:2013

 CMMI L5

 EMC: 2014/30/EU, EN60255-26:2013

 Products safety (LVD): 2014/35/EU, EN60255-27:2014


2 WEEE: 2012/19/EU, EN 50419:2006

 RoHS: 2011/65/EU, IEC 62321-4:2013, IEC 62321-5:2013, IEC 62321-6:2015, IEC


62321-7-1:2015, IEC 62321-7-2:2017

 RoHS: (EU) 2015/863, IEC 62321-8:2015

 IEC 61850: Edition 2, Parts 6, 7-1, 7-2, 7-3,7-4 and 8-1

 IEC 61850: Edition 2, GOOSE Performance Class P1 (3ms)

 IEEE 1588: IEEE Std C37.238TM-2017

 DNP: DNP 3.0

 PRP: IEC 62439-3 Ed.3 (IS 2016)

 HSR: IEC 62439-3 Ed.3 (IS 2016)

2.7 Liquid Crystal Display (LCD)

Type Resolution

Size 320x240 pixels

2.8 Terminals

2.8.1 Ring Ferrule

Connection Type Wire Size Screw Type Torque

AC current Screw terminals, 1.5~4mm2 lead M4 1.6~1.8 N·m

AC voltage Screw terminals, 0.8~4mm2 lead M4 1.6~1.8 N·m

Power supply Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N·m

Contact I/O Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N·m

Grounding (Earthing) Connection BVR type, 0.8~4mm2 lead M3 0.6~0.8 N·m

2.8.2 Pin Ferrule

Connection Type Wire Size Screw Type Torque

2-14 PCS-978S Transformer Relay

Date: 2022-01-17
2 Technical Data

Connection Type Wire Size Screw Type Torque

Power supply Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N·m

Contact I/O Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N·m

2.9 Measurement Scope and Accuracy


2
Item Range Accuracy

Phase range 0°~ 360° ≤±1°

Frequency fn±3 Hz ≤ 0.01Hz

≤ 1.0% of rating (0.05~1.00In)


Current 0.05~4.00In
≤ 0.5% of applied quantities (1.00~4.00In)

≤ 1.0% of rating (0.05~1.00Un)


Voltage 0.05~1.50Un
≤ 0.5% of applied quantities (1.00~1.50Un)

±0.5% of P, @Un, at 0.1In<I<4.0In


Active power (W) 0.06~4.00In
±1% of P, @Un, at 0.06In<I<0.1In

±0.5% of Q, @Un, at 0.1In<I<4.0In


Reactive power (VAr) 0.06~4.00In
±1% of Q, @Un, at 0.06In<I<0.1In

±0.5% of S, @Un, at 0.1In<I<4.0In


Apparent power (VA) 0.06~4.00In
±1% of S, @Un, at 0.06In<I<0.1In

±0.5% of Wh at Un and 0.1In<I<4.0In


Energy (Wh) 0.06~4.00In
±1% of Wh at Un and 0.06In<I<0.1In

±0.5% of VArh at Un and 0.1In<I<4.0In


Energy (VArh) 0.06~4.00In
±1% of VArh at Un and 0.06In<I<0.1In

2.10 Management Function

2.10.1 Control Performance

Control mode Local or remote

Response time of local control ≤1s

Response time of remote control ≤3s

PCS-978S Transformer Relay 2-15


Date: 2022-01-17
2 Technical Data

2.10.2 Clock Performance

Real time clock accuracy ≤1s/day

Accuracy of GPS synchronization ≤1ms

External time synchronization IRIG-B (200-98), PPS, IEEE 1588 or SNTP protocol

2 2.10.3 Fault and Disturbance Recording

Settable pre-disturbance, post-disturbance and maximum recorded


Duration & Recording position
duration

Sampling rate Up to 9.6kHz

2.10.4 Binary Input Signal

Resolution of binary input signal ≤1ms

Binary input mode Potential-free contact

2.11 Protective Functions

There are some symbols mentioned in the following sections and the meaning of them is given
here.

Un——VT rated secondary voltage

In——CT rated secondary current

p.u.——per unit value of settings and currents for current differential protection

Id——differential current

3I0d——residual differential current

Iwd——winding differential current

ΔId——DPFC differential current

U*/f*——the overexcitation multiple

2.11.1 Transformer Current Differential Protection (87T)

2.11.1.1 Biased Differential Protection

Accuracy of the 2nd and 3rd harmonic settings ≤0.01

Accuracy of the 5th harmonic setting ≤0.02

2-16 PCS-978S Transformer Relay

Date: 2022-01-17
2 Technical Data

≤5% of operating current setting or 0.02p.u., whichever is


Accuracy of operating current
greater

Dropout ratio ≥95%

50Hz: ≤ 30ms (Id>2 times current setting, internal fault)


Operating time (without blocking criteria)
60Hz: ≤ 25ms (Id>2 times current setting, internal fault)
2
Dropout time ≤30ms

2.11.1.2 Instantaneous Differential Protection

Accuracy of current setting ≤2.5% of setting or 0.02p.u., whichever is greater

Dropout ratio ≥95%

50Hz: ≤ 20ms (Id>2 times current setting, internal fault)


Operating time
60Hz: ≤ 20ms (Id>2 times current setting, internal fault)

Dropout time ≤30ms

2.11.1.3 DPFC Current Differential Protection

Accuracy of operating current ≤10%

Dropout ratio ≥95%

50Hz: ≤30ms (ΔId >3 times current setting (the current

setting is fixed as 0.2p.u. in program), internal fault)


Operating time
60Hz: ≤30ms (ΔId >3 times current setting (the current

setting is fixed as 0.2p.u. in program), internal fault)

Dropout time ≤30ms

2.11.2 Restricted Earth Fault Protection (64REF)

Accuracy of operating current ≤5% of operating current or 0.02×In, whichever is greater

Dropout ratio ≥95%

Operating time (without time delay, without 50Hz: ≤30ms (3I0d>2 times current setting, internal fault)

blocking criterion) 60Hz: ≤25ms (3I0d>2 times current setting, internal fault)

PCS-978S Transformer Relay 2-17


Date: 2022-01-17
2 Technical Data

Accuracy of time setting ≤1% of setting +30ms (3I0d>2 times current setting)

Dropout time ≤30ms

2.11.3 Winding Differential Protection (87W)

≤5% or 0.02×In, whichever is greater


2 Accuracy of operating current

Dropout ratio ≥95%

50Hz: ≤30ms (Iwd>2 times current setting, internal fault)


Operating time (without blocking criterion)
60Hz: ≤25ms (Iwd>2 times current setting, internal fault)

Accuracy of time setting ≤1% of setting +30ms (3I0d>2 times current setting)

Dropout time ≤30ms

2.11.4 Reactor Differential Protection (87R)

2.11.4.1 Biased Differential Protection

≤5% of operating current setting or 0.02p.u., whichever is


Accuracy of operating current
greater

Dropout ratio ≥95%

50Hz: ≤30ms( Id>2 times current setting)


Operating time (without blocking criterion)
60Hz: ≤25ms( Id>2 times current setting)

Dropout time ≤30ms

2.11.4.2 Instantaneous Differential Protection

Accuracy of current setting ≤2.5% of setting or 0.02p.u., whichever is greater

Dropout ratio ≥95%

50Hz: ≤ 20ms( Id>1.5 times current setting)


Operating time
60Hz: ≤ 20ms( Id>1.5 times current setting)

Dropout time ≤30ms

2.11.5 Inter-turn Fault Protection (21IT)

Operating time without delay ≤60ms((3U0>0.02p.u, without harmonic current))

2.11.6 Overexcitation Protection (24)

Accuracy of relative overexcitation (U*/f*) ≤0.01

Dropout ratio of definite-time overexcitation ≥97%

2-18 PCS-978S Transformer Relay

Date: 2022-01-17
2 Technical Data

protection

Accuracy of operating time delay of definite-time


≤1% of setting +100ms (at 1.5 times U*/f* setting)
overexcitation protection

Accuracy of operating time delay of inverse-time


≤2.5% of setting +100ms
overexcitation protection

Dropout time of definite-time overexcitation


protection
≤30ms 2
2.11.7 Phase Overcurrent Protection (50/51P, 67P)

2.11.7.1 Without Direction Control Element

Pickup current 1.0×setting

Accuracy of current setting ≤1%×setting or 0.01×In, whichever is greater

Accuracy of voltage setting ≤1%×setting or 0.1V, whichever is greater

Pickup time ≤25ms (at 2 times current setting)

Definite-time: ≤1%×setting or 25ms (at 2 times current


setting)
Accuracy of operating time delay
Inverse-time: ≤5% of the calculated value + 1% of current
tolerance, or 35ms (1.2≤I/Ip≤30)

Definite-time: ≤1%×setting or 30ms


Accuracy of dropout time
Inverse-time: ≤5% of the calculated value or 30ms

Dropout ratio 0.95

2.11.7.2 With Direction Control Element

Pickup current 1.0×setting

Accuracy of current setting ≤1%×setting or 0.01×In, whichever is greater

Accuracy of voltage setting ≤1%×setting or 0.1V, whichever is greater

Pickup time ≤40ms (at 2 times current setting)

Definite-time: ≤ 1%×setting or 40ms (at 2 times current


setting)
Accuracy of operating time delay
Inverse-time: ≤5% of the calculated value + 1% of current
tolerance, or 35ms (1.2≤I/Ip≤30)

Definite-time: ≤1%×setting or 30ms


Accuracy of dropout time
Inverse-time: ≤5% of the calculated value or 30ms

Dropout ratio 0.95

Accuracy of angle ≤3°

PCS-978S Transformer Relay 2-19


Date: 2022-01-17
2 Technical Data

2.11.8 Earth Fault Overcurrent Protection (50/51G, 67G)

2.11.8.1 Without Direction Control Element

Pickup current 1.0×setting

Accuracy of current setting ≤1%×setting or 0.01×In, whichever is greater

2 Pickup time ≤25ms (at 2 times current setting)

Definite-time: ≤1%×setting or 25ms (at 2 times current


setting)
Accuracy of operating time delay
Inverse-time: ≤5% of the calculated value + 1% of current
tolerance, or 35ms(1.2≤I/Ip≤30)

Definite-time: ≤1%×setting or 30ms


Accuracy of dropout time
Inverse-time: ≤5% of the calculated value or 30ms

Dropout ratio 0.95

2.11.8.2 With Direction Control Element

Pickup current 1.0×setting

Accuracy of current setting ≤1%×setting or 0.01×In, whichever is greater

Accuracy of voltage setting ≤1%×setting or 0.1V, whichever is greater

Pickup time ≤40ms (at 2 times current setting)

Definite-time: ≤1%×setting or 40ms (at 2 times current


setting)
Accuracy of operating time delay
Inverse-time: ≤5% of the calculated value + 1% of current
tolerance, or 35ms (1.2≤I/Ip≤30)

Definite-time: ≤1%×setting or 30ms


Accuracy of dropout time
Inverse-time: ≤5%× the calculated value or 30ms

Dropout ratio 0.95

Accuracy of angle ≤3°

2.11.9 Negative-sequence Overcurrent Protection (50/51Q, 67Q)

2.11.9.1 Without Direction Control Element

Pickup current 1.0×setting

Accuracy of current setting ≤1%×setting or 0.01×In, whichever is greater

Pickup time ≤25ms (at 2 times current setting)

Definite-time:≤1%×setting or 25ms (at 2 times current setting)


Accuracy of operating time delay Inverse-time: ≤5% of the calculated value + 1% of current
tolerance, or 35ms(1.2≤I/Ip≤30)

Accuracy of dropout time Definite-time: ≤1%×setting or 30ms

2-20 PCS-978S Transformer Relay

Date: 2022-01-17
2 Technical Data

Inverse-time: ≤5%× the calculated value or 30ms

Dropout ratio 0.95

2.11.9.2 With Direction Control Element

Pickup current 1.0×setting

Accuracy of current setting ≤1%×setting or 0.01×In, whichever is greater 2


Accuracy of voltage setting ≤1%×setting or 0.1V, whichever is greater

Pickup time ≤40ms (at 2 times current setting)

Definite-time: ≤1%×setting or 40ms (at 2 times current


setting)
Accuracy of operating time delay
Inverse-time: ≤5% of the calculated value + 1% of current
tolerance, or 35ms (1.2≤I/Ip≤30)

Definite-time: ≤1%×setting or 30ms


Accuracy of dropout time
Inverse-time: ≤5%× the calculated value or 30ms

Dropout ratio 0.95

Accuracy of angle ≤3°

2.11.10 Thermal Overload Protection (49)

Accuracy of current setting ≤1%×setting or 0.01×In, whichever is greater

≤5% of the calculated value + 1% of current tolerance, or


Accuracy of operating time delay
35ms(1.2≤I/Ip≤30)

Dropout time ≤30ms

2.11.11 Breaker Failure Protection (50BF)

Pickup current 1.0×Setting

Accuracy of current setting ≤1%×Setting or 0.01In, whichever is greater

Accuracy of operating time delay ≤1%×Setting or 20ms (at 2 times current setting)

Pickup time ≤20ms (at 2 times current setting)

Dropout time <20ms (at 2 times current setting)

Dropout ratio 0.95

2.11.12 Overvoltage Protection (59P)

Pickup voltage 1.0×setting

Accuracy of voltage setting ≤1%×setting or 0.1V, whichever is greater

Pickup time ≤35ms (at 1.1 times voltage setting)

Accuracy of operating time delay Definite-time: ≤1%×setting or 35ms (at 1.1 times voltage

PCS-978S Transformer Relay 2-21


Date: 2022-01-17
2 Technical Data

setting)

Inverse-time: ≤5% of the calculated value + 1% of voltage


tolerance, or 40ms (1.1≤U/Up≤2)

Accuracy of dropout time ≤1%×setting or 30ms

Dropout ratio 0.93~1.00 (settable), 0.98 by default

2 2.11.13 Residual Overvoltage Protection (59G)

Pickup voltage 1.0×setting

Accuracy of voltage setting ≤1%×setting or 0.1V, whichever is greater

Pickup time ≤35ms (at 1.1 times voltage setting)

Accuracy of operating time delay ≤1%×setting or 35ms (at 1.1 times voltage setting)

Accuracy of dropout time ≤1%×setting or 30ms

Dropout ratio 0.93~1.00 (settable), 0.98 by default

2.11.14 Undervoltage Protection (27P)

Pickup voltage 1.0×setting

Accuracy of voltage setting ≤1%×setting or 0.1V, whichever is greater

Pickup time ≤35m (at 0.9 times voltage setting)

Definite-time: ≤1%×setting or 35ms (at 0.9 times voltage


setting)
Accuracy of operating time delay
Inverse-time: ≤5% of the calculated value + 1% of voltage
tolerance, or 50ms (U/Up≤0.9)

Accuracy of dropout time ≤1%×setting or 30ms

Dropout ratio 1.00~1.2 (settable), 1.03 by default

2.11.15 Overfrequency Protection (81O)

Pickup frequency 1.0×setting

Accuracy of frequency setting ≤0.01Hz

Pickup time ≤70ms

Accuracy of operating time delay ≤1%×setting or 70ms

Accuracy of dropout time ≤40ms

Dropout frequency 1.0×setting

2.11.16 Underfrequency Protection (81U)

Pickup frequency 1.0×setting

Accuracy of frequency setting ≤0.01Hz

Pickup time ≤70ms

Accuracy of operating time delay ≤1%×setting or 70ms

2-22 PCS-978S Transformer Relay

Date: 2022-01-17
2 Technical Data

Accuracy of dropout time ≤40ms

Dropout frequency 1.0×setting

2.11.17 Frequency Rate-of-change Protection (81R)


Pickup frequency 1.0×Setting
Accuracy of frequency rate-of-change setting ≤ 0.02Hz
Pickup time ≤70ms 2
Accuracy of operating time delay ≤1%×Setting+70ms
Accuracy of dropout time ≤40ms
Dropout frequency 1.0×Setting

2.11.18 Distance Protection (21T)

Impedance setting accuracy ≤2.5%×Setting or 0.1Ω, whichever is greater

Resetting ratio 1.05

Operating time accuracy ≤1%×Setting+30ms

≤5% (SIR≤30)
Transient overreaching
≤10% (SIR≥30)

2.12 Communication Functions

2.12.1 GOOSE
Max. 64
Receiving Control Block (RCB)
(Typical configuration: 50×FCD+200×BOOL+16×FLOAT)
Max. 16
Sending Control Block (SCB)
(Typical configuration: 100×BOOL)

Receiving route delay Max. 2ms

Sending route delay Max. 3ms

2.12.2 SV

Receiving Control Block (RCB) Max. 12

Receiving route delay Max. 2ms

PCS-978S Transformer Relay 2-23


Date: 2022-01-17
3 Protection Functions

3 Protection Functions

Table of Contents

3.1 Three-phase Current Element (TCUR3P) ....................................................... 3-1


3.1.1 Function Description............................................................................................................. 3-1

3.1.2 Function Block Diagram ....................................................................................................... 3-2

3.1.3 I/O Signals ............................................................................................................................ 3-2 3


3.1.4 Settings ................................................................................................................................. 3-3

3.2 Three-phase Voltage Element (TVOL3P)........................................................ 3-3


3.2.1 Function Description............................................................................................................. 3-3

3.2.2 Function Block Diagram ....................................................................................................... 3-4

3.2.3 I/O Signals ............................................................................................................................ 3-4

3.2.4 Settings ................................................................................................................................. 3-5

3.3 Single-phase Current Element (TCUR1P) ...................................................... 3-5


3.3.1 Function Description............................................................................................................. 3-5

3.3.2 Function Block Diagram ....................................................................................................... 3-6

3.3.3 I/O Signals ............................................................................................................................ 3-6

3.3.4 Settings ................................................................................................................................. 3-6

3.4 Single-phase Voltage Element (TVOL1P) ...................................................... 3-6


3.4.1 Function Description............................................................................................................. 3-6

3.4.2 Function Block Diagram ....................................................................................................... 3-7

3.4.3 I/O Signals ............................................................................................................................ 3-7

3.4.4 Settings ................................................................................................................................. 3-7

3.5 Three-phase Current Summation Element (TCUR3P_3SD).......................... 3-7


3.5.1 Function Description............................................................................................................. 3-7

3.5.2 Function Block Diagram ....................................................................................................... 3-8

3.5.3 I/O Signals ............................................................................................................................ 3-8

3.6 Transformer Current Differential Protection (87T) ........................................ 3-9


3.6.1 Function Description............................................................................................................. 3-9

PCS-978S Transformer Relay 3-a


Date: 2022-01-17
3 Protection Functions

3.6.2 Function Block Diagram ..................................................................................................... 3-31

3.6.3 I/O Signals .......................................................................................................................... 3-31

3.6.4 Logic ................................................................................................................................... 3-33

3.6.5 Settings ............................................................................................................................... 3-35

3.7 Restricted Earth Fault Protection (64REF) .................................................. 3-37


3.7.1 Function Description........................................................................................................... 3-37

3.7.2 Function Block Diagram ..................................................................................................... 3-44

3 3.7.3 I/O Signals .......................................................................................................................... 3-44

3.7.4 Logic ................................................................................................................................... 3-45

3.7.5 Settings ............................................................................................................................... 3-46

3.8 Winding Differential Protection (87W) ......................................................... 3-47


3.8.1 Function Description........................................................................................................... 3-47

3.8.2 Function Block Diagram ..................................................................................................... 3-53

3.8.3 I/O Signals .......................................................................................................................... 3-53

3.8.4 Logic ................................................................................................................................... 3-54

3.8.5 Settings ............................................................................................................................... 3-56

3.9 Reactor Current Differential Protection (87R) ............................................. 3-56


3.9.1 Function Description........................................................................................................... 3-56

3.9.2 Function Block Diagram ..................................................................................................... 3-70

3.9.3 I/O Signals .......................................................................................................................... 3-70

3.9.4 Logic ................................................................................................................................... 3-72

3.9.5 Settings ............................................................................................................................... 3-75

3.10 Inter-turn Fault Protection (21IT) ................................................................ 3-76


3.10.1 Function Description......................................................................................................... 3-76

3.10.2 Function Block Diagram ................................................................................................... 3-80

3.10.3 I/O Signals ........................................................................................................................ 3-80

3.10.4 Logic ................................................................................................................................. 3-81

3.10.5 Settings ............................................................................................................................. 3-82

3.11 Overexcitation Protection (24) .................................................................... 3-82


3.11.1 Function Description ......................................................................................................... 3-82

3-b PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

3.11.2 Function Block Diagram ................................................................................................... 3-84

3.11.3 I/O Signals ........................................................................................................................ 3-85

3.11.4 Logic ................................................................................................................................. 3-87

3.11.5 Settings ............................................................................................................................. 3-89

3.12 Phase Overcurrent Protection (50/51P) ..................................................... 3-91


3.12.1 Function Description......................................................................................................... 3-91

3.12.2 Function Block Diagram ................................................................................................. 3-102

3.12.3 I/O Signal ........................................................................................................................ 3-103 3


3.12.4 Logic ............................................................................................................................... 3-105

3.12.5 Settings ........................................................................................................................... 3-105

3.13 Earth Fault Overcurrent Protection (50/51G) ........................................... 3-109


3.13.1 Function Description....................................................................................................... 3-109

3.13.2 Function Block Diagram ................................................................................................. 3-119

3.13.3 I/O Signal ........................................................................................................................ 3-119

3.13.4 Logic ............................................................................................................................... 3-120

3.13.5 Settings ........................................................................................................................... 3-120

3.14 Negative-sequence Overcurrent Protection (50/51Q) ............................. 3-124


3.14.1 Function Description....................................................................................................... 3-124

3.14.2 Function Block Diagram ................................................................................................. 3-132

3.14.3 I/O Signal ........................................................................................................................ 3-133

3.14.4 Logic ............................................................................................................................... 3-134

3.14.5 Settings ........................................................................................................................... 3-134

3.15 Thermal Overload Protection (49) ............................................................ 3-138


3.15.1 Application ...................................................................................................................... 3-138

3.15.2 Function Description....................................................................................................... 3-138

3.15.3 Function Block Diagram ................................................................................................. 3-140

3.15.4 I/O Signals ...................................................................................................................... 3-140

3.15.5 Logic ............................................................................................................................... 3-141

3.15.6 Settings ........................................................................................................................... 3-142

3.16 Breaker Failure Protection (50BF) ............................................................ 3-143

PCS-978S Transformer Relay 3-c


Date: 2022-01-17
3 Protection Functions

3.16.1 Function Description....................................................................................................... 3-143

3.16.2 Function Block Diagram ................................................................................................. 3-146

3.16.3 I/O Signals ...................................................................................................................... 3-146

3.16.4 Logic ............................................................................................................................... 3-147

3.16.5 Settings ........................................................................................................................... 3-150

3.17 Phase Overvoltage Protection (59P) ........................................................ 3-151


3.17.1 Function Description....................................................................................................... 3-151

3 3.17.2 Function Block Diagram ................................................................................................. 3-156

3.17.3 I/O Signal ........................................................................................................................ 3-157

3.17.4 Logic ............................................................................................................................... 3-158

3.17.5 Settings ........................................................................................................................... 3-158

3.18 Residual Overvoltage Protection (59G) ................................................... 3-160


3.18.1 Function Description....................................................................................................... 3-160

3.18.2 Function Block Diagram ................................................................................................. 3-162

3.18.3 I/O Signal ........................................................................................................................ 3-163

3.18.4 Logic ............................................................................................................................... 3-163

3.18.5 Settings ........................................................................................................................... 3-163

3.19 Phase Undervoltage Protection (27P) ...................................................... 3-164


3.19.1 Function Description....................................................................................................... 3-164

3.19.2 Function Block Diagram ................................................................................................. 3-170

3.19.3 I/O Signal ........................................................................................................................ 3-170

3.19.4 Logic ............................................................................................................................... 3-171

3.19.5 Settings ........................................................................................................................... 3-171

3.20 Overfrequency Protection (81O)............................................................... 3-174


3.20.1 Function Description....................................................................................................... 3-174

3.20.2 Function Block Diagram ................................................................................................. 3-176

3.20.3 I/O Signals ...................................................................................................................... 3-176

3.20.4 Logic ............................................................................................................................... 3-177

3.20.5 Settings ........................................................................................................................... 3-177

3.21 Underfrequency Protection (81U)............................................................. 3-178

3-d PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

3.21.1 Function Description....................................................................................................... 3-178

3.21.2 Function Block Diagram ................................................................................................. 3-179

3.21.3 I/O Signals ...................................................................................................................... 3-180

3.21.4 Logic ............................................................................................................................... 3-180

3.21.5 Settings ........................................................................................................................... 3-181

3.22 Frequency Rate-of-change Protection (81R) ........................................... 3-181


3.22.1 Function Description....................................................................................................... 3-181

3.22.2 Function Block Diagram ................................................................................................. 3-183 3


3.22.3 I/O Signals ...................................................................................................................... 3-183

3.22.4 Logic ............................................................................................................................... 3-184

3.22.5 Settings ........................................................................................................................... 3-184

3.23 Distance Protection (21T) ......................................................................... 3-185


3.23.1 Functions Description ..................................................................................................... 3-185

3.23.2 Function Block Diagram ................................................................................................. 3-202

3.23.3 I/O Signals ...................................................................................................................... 3-203

3.23.4 Logic ............................................................................................................................... 3-205

3.23.5 Settings ........................................................................................................................... 3-208

3.24 Output Map (OutMap) .................................................................................3-211


3.24.1 Function Description....................................................................................................... 3-211

3.24.2 I/O Signals ...................................................................................................................... 3-213

3.24.3 Settings ........................................................................................................................... 3-213

List of Figures

Figure 3.6-1 Current compensation calculation process.................................................... 3-15

Figure 3.6-2 Operation characteristic of sensitive biased differential element ............... 3-17

Figure 3.6-3 Operation characteristic of conventional biased differential element ......... 3-18

Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements .... 3-19

Figure 3.6-5 Operation characteristic of DPFC biased differential protection ................. 3-22

Figure 3.6-6 Schematic of waveform symmetry principle .................................................. 3-25

Figure 3.6-7 Logic of inrush current blocking current differential protection.................. 3-27

PCS-978S Transformer Relay 3-e


Date: 2022-01-17
3 Protection Functions

Figure 3.6-8 Logic of enabling transformer differential protection ................................... 3-33

Figure 3.6-9 Pickup logic of transformer differential protection........................................ 3-34

Figure 3.6-10 Logic diagram of instantaneous differential element .................................. 3-34

Figure 3.6-11 Logic diagram of biased differential element ............................................... 3-34

Figure 3.6-12 Logic diagram of DPFC biased differential element .................................... 3-35

Figure 3.6-13 Logic diagram of CT circuit failure alarm...................................................... 3-35

Figure 3.7-1 Application for two-winding transformer with one CB at one side .............. 3-37

3 Figure 3.7-2 Application for two-winding transformer with two CBs at one side ............ 3-38

Figure 3.7-3 Application for auto-transformer...................................................................... 3-38

Figure 3.7-4 REF principle ...................................................................................................... 3-40

Figure 3.7-5 Operation characteristic of REF ....................................................................... 3-41

Figure 3.7-6 Currents at an external earth fault ................................................................... 3-42

Figure 3.7-7 Currents at an internal earth fault .................................................................... 3-42

Figure 3.7-8 Logic of enabling restricted earth fault protection ........................................ 3-45

Figure 3.7-9 Pickup logic of restricted earth fault protection ............................................ 3-45

Figure 3.7-10 Logic diagram of restricted earth fault protection ....................................... 3-46

Figure 3.8-1 Winding differential protection applied to auto-transformer ........................ 3-47

Figure 3.8-2 Winding differential protection applied to stub differential protection ....... 3-48

Figure 3.8-3 Operating characteristic of winding differential protection .......................... 3-51

Figure 3.8-4 Logic of enabling winding differential protection .......................................... 3-55

Figure 3.8-5 Pickup logic of transformer differential protection........................................ 3-55

Figure 3.8-6 Logic diagram of winding differential protection ........................................... 3-55

Figure 3.9-1 Current compensation calculation process.................................................... 3-60

Figure 3.9-2 Current compensation calculation process.................................................... 3-61

Figure 3.9-3 Current compensation calculation process.................................................... 3-61

Figure 3.9-4 Operation characteristic of sensitive biased differential element ............... 3-64

Figure 3.9-5 Operation characteristic of conventional biased differential element ......... 3-65

Figure 3.9-6 Operation characteristic of biased and Instantaneous differential element3-66

Figure 3.9-7 Operation characteristic of DPFC biased differential element ..................... 3-68

Figure 3.9-8 Operation characteristic of zero-sequence differential element .................. 3-69

3-f PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

Figure 3.9-9 Logic of enabling reactor differential protection ........................................... 3-73

Figure 3.9-10 Pickup logic of reactor differential protection .............................................. 3-74

Figure 3.9-11 Logic diagram of instantaneous differential element .................................. 3-74

Figure 3.9-12 Logic diagram of biased differential element ............................................... 3-74

Figure 3.9-13 Logic diagram of Residual differential element ........................................... 3-75

Figure 3.9-14 Logic diagram of DPFC biased differential element .................................... 3-75

Figure 3.10-1 Wiring diagram of shunt reactors in power system ..................................... 3-77

Figure 3.10-2 Equivalent zero-sequence network for F1 .................................................... 3-78 3


Figure 3.10-3 Vector relation for F1 ....................................................................................... 3-78

Figure 3.10-4 Equivalent zero-sequence network for F2 .................................................... 3-78

Figure 3.10-5 Vector relation for F2 ....................................................................................... 3-79

Figure 3.10-6 Logic of enabling inter-turn fault protection................................................. 3-81

Figure 3.10-7 Pickup logic of inter-turn fault protection ..................................................... 3-81

Figure 3.10-8 Logic diagram of inter-turn fault protection ................................................. 3-81

Figure 3.11-1 Inverse-time characteristic of overexcitation protection ............................ 3-84

Figure 3.11-2 Logic of enabling overexcitation protection ................................................. 3-87

Figure 3.11-3 Pickup logic of overexcitation protection ..................................................... 3-88

Figure 3.11-4 Logic diagram of definite-time overexcitation protection ........................... 3-88

Figure 3.11-5 Logic diagram of inverse-time overexcitation protection ........................... 3-88

Figure 3.12-1 Logic of enabling phase overcurrent protection.......................................... 3-92

Figure 3.12-2 Pickup logic of phase overcurrent protection .............................................. 3-92

Figure 3.12-3 Logic of voltage control element ................................................................... 3-93

Figure 3.12-4 Operating characteristics of the direction element ..................................... 3-93

Figure 3.12-5 Logic of forward and reverse direction element .......................................... 3-96

Figure 3.12-6 Logic of harmonic control element ................................................................ 3-97

Figure 3.12-7 Definite-time operating curve of phase overcurrent protection ................. 3-98

Figure 3.12-8 Inverse-time operating curve of phase overcurrent protection.................. 3-99

Figure 3.12-9 Definite-time dropout characteristics of phase overcurrent protection .. 3-100

Figure 3.12-10 Inverse-time dropout curve of phase overcurrent protection ................ 3-101

Figure 3.12-11 Inverse-time dropout characteristics of phase overcurrent protection. 3-102

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Date: 2022-01-17
3 Protection Functions

Figure 3.12-12 Logic of phase overcurrent protection...................................................... 3-105

Figure 3.13-1 Logic of enabling earth fault protection ...................................................... 3-109

Figure 3.13-2 Pickup logic of earth fault protection .......................................................... 3-110

Figure 3.13-3 Operating characteristics of direction control element............................. 3-110

Figure 3.13-4 Logic of forward and reverse direction element ........................................ 3-112

Figure 3.13-5 Logic of harmonic control element .............................................................. 3-113

Figure 3.13-6 Definite-time operating curve of earth fault protection ............................. 3-114

3 Figure 3.13-7 Inverse-time operating curve of earth fault protection .............................. 3-115

Figure 3.13-8 Definite-time dropout characteristics of earth fault protection ................ 3-116

Figure 3.13-9 Inverse-time dropout curve of earth fault protection................................. 3-118

Figure 3.13-10 Inverse-time dropout characteristics of earth fault protection .............. 3-118

Figure 3.13-11 Logic diagram of earth fault overcurrent protection................................ 3-120

Figure 3.14-1 Logic of enabling negative-sequence overcurrent protection ................. 3-124

Figure 3.14-2 Pickup logic of negative-sequence protection ........................................... 3-124

Figure 3.14-3 Operating characteristics of direction control element............................. 3-125

Figure 3.14-4 Logic of forward and reverse direction element ........................................ 3-126

Figure 3.14-5 Definite-time operating curve of negative-sequence overcurrent protection


................................................................................................................................................. 3-128

Figure 3.14-6 Inverse-time operating curve of negative-sequence overcurrent protection


................................................................................................................................................. 3-129

Figure 3.14-7 Definite-time dropout characteristics of negative-sequence overcurrent


protection ............................................................................................................................... 3-130

Figure 3.14-8 Inverse-time dropout curve of negative-sequence overcurrent protection


................................................................................................................................................. 3-131

Figure 3.14-9 Inverse-time dropout characteristics of negative-sequence overcurrent


protection ............................................................................................................................... 3-132

Figure 3.14-10 Logic of negative-sequence overcurrent protection ............................... 3-134

Figure 3.15-1 Characteristic curve of thermal overload protection ................................. 3-138

Figure 3.15-2 Logic diagram of enabling thermal overload protection (method 1) ....... 3-141

Figure 3.15-3 Pickup logic of thermal overload protection (method 1) ........................... 3-142

Figure 3.15-4 Logic diagram of thermal overload protection (method 1, phase A) ....... 3-142

3-h PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

Figure 3.15-5 Logic diagram of thermal overload protection (method 1) ....................... 3-142

Figure 3.16-1 Logic of enabling breaker failure protection .............................................. 3-147

Figure 3.16-2 Logic of breaker failure initiating signal abnormality ................................ 3-147

Figure 3.16-3 Logic of current/contact check (phase-segregated) .................................. 3-148

Figure 3.16-4 Logic of current/contact check (three-phase) ............................................ 3-148

Figure 3.16-5 Logic of breaker failure protection (phase-segregated) ............................ 3-149

Figure 3.16-6 Logic of breaker failure protection (three-phase) ...................................... 3-150

Figure 3.17-1 Logic of enabling phase overvoltage protection ....................................... 3-152 3


Figure 3.17-2 Pickup logic of phase overvoltage protection............................................ 3-153

Figure 3.17-3 Definite-time operating curve of phase overvoltage protection ............... 3-154

Figure 3.17-4 Inverse-time operating curve of phase overvoltage protection ............... 3-155

Figure 3.17-5 Definite-time dropout characteristics of phase overvoltage protection.. 3-156

Figure 3.17-6 Logic of phase overvoltage protection ....................................................... 3-158

Figure 3.18-1 Logic of enabling residual overvoltage protection .................................... 3-160

Figure 3.18-2 Pickup logic of residual overvoltage protection ........................................ 3-161

Figure 3.18-3 Definite-time operating curve of residual overvoltage protection ........... 3-161

Figure 3.18-4 Definite-time dropout characteristics of residual overvoltage protection3-162

Figure 3.18-5 Logic of residual overvoltage protection .................................................... 3-163

Figure 3.19-1 Logic of enabling phase undervoltage protection ..................................... 3-165

Figure 3.19-2 Pickup logic of phase undervoltage protection ......................................... 3-166

Figure 3.19-3 Definite-time operating curve of phase undervoltage protection ............ 3-167

Figure 3.19-4 Inverse-time operating curve of phase undervoltage protection ............. 3-168

Figure 3.19-5 Definite-time dropout characteristics of phase undervoltage protection3-169

Figure 3.19-6 Logic of phase undervoltage protection ..................................................... 3-171

Figure 3.20-1 Logic of enabling overfrequency protection .............................................. 3-175

Figure 3.20-2 Pickup logic of overfrequency protection................................................... 3-175

Figure 3.20-3 Definite-time operating curve of overfrequency protection...................... 3-175

Figure 3.20-4 Function block diagram of overfrequency protection ............................... 3-176

Figure 3.20-5 Logic of overfrequency protection .............................................................. 3-177

Figure 3.21-1 Logic of enabling underfrequency protection ............................................ 3-178

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Date: 2022-01-17
3 Protection Functions

Figure 3.21-2 Pickup logic of underfrequency protection ................................................ 3-178

Figure 3.21-3 Definite-time operating curve of underfrequency protection ................... 3-179

Figure 3.21-4 Function block diagram of underfrequency protection............................. 3-179

Figure 3.21-5 Logic of underfrequency protection ............................................................ 3-180

Figure 3.22-1 Logic of enabling frequency rate-of-change protection............................ 3-181

Figure 3.22-2 Pickup logic of frequency rate-of-change protection ................................ 3-182

Figure 3.22-3 Definite-time operating curve of frequency rate-of-change protection ... 3-182

3 Figure 3.22-4 Logic of frequency rate-of-change protection ............................................ 3-184

Figure 3.23-1 Quadrilateral forward direction distance element ...................................... 3-188

Figure 3.23-2 Quadrilateral reverse direction distance element ...................................... 3-188

Figure 3.23-3 Quadrilateral non direction distance element ............................................ 3-189

Figure 3.23-4 Shift impedance characteristics of forward direction ............................... 3-190

Figure 3.23-5 Shift impedance characteristics of reverse direction ................................ 3-190

Figure 3.23-6 Mho forward direction distance element..................................................... 3-192

Figure 3.23-7 Mho reverse direction distance element ..................................................... 3-192

Figure 3.23-8 Mho non direction distance element ........................................................... 3-192

Figure 3.23-9 Phase-to-ground operating characteristics for forward fault ................... 3-193

Figure 3.23-10 Phase-to-phase operating characteristics for forward fault ................... 3-194

Figure 3.23-11 Operating characteristics for reverse fault ............................................... 3-194

Figure 3.23-12 Operating characteristics of three-phase close-in fault .......................... 3-195

Figure 3.23-13 Operating characteristics of three-phase close-in fault .......................... 3-195

Figure 3.23-14 Phase-to-phase mutual inductance ........................................................... 3-196

Figure 3.23-15 Zero-sequence mutual inductance for double-circuit lines .................... 3-197

Figure 3.23-16 Distance element with load encroachment ............................................... 3-197

Figure 3.23-17 Faulty phase selection based on I0 and I2A ............................................... 3-201

Figure 3.23-18 Logic of fault detector ................................................................................. 3-205

Figure 3.23-19 Logic of enabling distance protection (i=1~4) .......................................... 3-205

Figure 3.23-20 Logic of distance protection (phase-to-ground, i=1~4) ........................... 3-206

Figure 3.23-21 Logic of distance protection (phase-to-phase, i=1~4) ............................. 3-207

Figure 3.23-22 Logic of distance protection operating (zone i, i=1~4) ............................ 3-207

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Date: 2022-01-17
3 Protection Functions

Figure 3.23-23 Logic of PSBR (i=1~4) ................................................................................. 3-208

List of Tables

Table 3.1-1 Input signals of three-phase current element .................................................... 3-2

Table 3.1-2 Output signals of three-phase current element ................................................. 3-2

Table 3.1-3 Settings of three-phase current element............................................................. 3-3

Table 3.2-1 Input signals of three-phase voltage element .................................................... 3-4

Table 3.2-2 Output signals of three-phase voltage element ................................................. 3-4


3
Table 3.2-3 Settings of three-phase voltage element ............................................................ 3-5

Table 3.3-1 Input signals of single-phase current element ................................................... 3-6

Table 3.3-2 Output signals of single-phase current element ................................................ 3-6

Table 3.3-3 Settings of single-phase current element ........................................................... 3-6

Table 3.4-1 Input signals of single-phase voltage element................................................... 3-7

Table 3.4-2 Output signals of single-phase voltage element................................................ 3-7

Table 3.4-3 Settings of single-phase voltage element ........................................................... 3-7

Table 3.5-1 Input signals of three-phase current summation element ................................ 3-8

Table 3.5-2 Output signals of three-phase current summation element ............................. 3-8

Table 3.6-1 Matrix of phase compensation ........................................................................... 3-13

Table 3.6-2 Comparison of different blocking modes ......................................................... 3-26

Table 3.6-3 Input signals of transformer differential protection......................................... 3-31

Table 3.6-4 Output signals of transformer differential protection ..................................... 3-31

Table 3.6-5 Settings of transformer differential protection ................................................ 3-35

Table 3.7-1 Input signals of restricted earth-fault protection ............................................. 3-44

Table 3.7-2 Output signals of restricted earth-fault protection .......................................... 3-45

Table 3.7-3 Settings of restricted earth fault protection ..................................................... 3-46

Table 3.8-1 Input signals of winding differential protection ............................................... 3-53

Table 3.8-2 Output signals of winding differential protection ............................................ 3-53

Table 3.8-3 Settings of winding differential protection ....................................................... 3-56

Table 3.9-1 Input signals of reactor differential protection................................................. 3-70

Table 3.9-2 Output signals of reactor differential protection.............................................. 3-71

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Date: 2022-01-17
3 Protection Functions

Table 3.9-3 Settings of reactor current differential protection ........................................... 3-75

Table 3.10-1 Input signals of inter-turn protection .............................................................. 3-80

Table 3.10-2 Output signals of inter-turn protection ........................................................... 3-81

Table 3.10-3 Settings of inter-turn fault protection .............................................................. 3-82

Table 3.11-1 Input signals of overexcitation protection ...................................................... 3-85

Table 3.11-2 Output signals of overexcitation protection ................................................... 3-86

Table 3.11-3 Settings of overexcitation protection .............................................................. 3-89

3 Table 3.12-1 Input signals of phase overcurrent protection ............................................. 3-103

Table 3.12-2 Output signals of phase overcurrent protection .......................................... 3-104

Table 3.12-3 Settings of phase overcurrent protection ..................................................... 3-105

Table 3.13-1 Input signals of earth fault protection ........................................................... 3-119

Table 3.13-2 Output signals of earth fault protection ........................................................ 3-120

Table 3.13-3 Settings of earth fault overcurrent protection .............................................. 3-120

Table 3.14-1 Input signals of negative-sequence overcurrent protection ...................... 3-133

Table 3.14-2 Output signals of negative-sequence overcurrent protection ................... 3-133

Table 3.14-3 Settings of negative-sequence overcurrent protection............................... 3-134

Table 3.15-1 Input signals of thermal overload protection ............................................... 3-140

Table 3.15-2 Output signals of thermal overload protection ............................................ 3-141

Table 3.15-3 Settings of thermal overload protection ....................................................... 3-142

Table 3.16-1 Input signals of breaker failure protection ................................................... 3-146

Table 3.16-2 Output signals of breaker failure protection ................................................ 3-146

Table 3.16-3 Settings of breaker failure protection............................................................ 3-150

Table 3.17-1 Input signals of phase overvoltage protection............................................. 3-157

Table 3.17-2 Output signals of phase overvoltage protection.......................................... 3-157

Table 3.17-3 Settings of phase overvoltage protection ..................................................... 3-158

Table 3.18-1 Input signals of residual overvoltage protection ......................................... 3-163

Table 3.18-2 Output signals of residual overvoltage protection ...................................... 3-163

Table 3.18-3 Settings of residual overvoltage protection ................................................. 3-163

Table 3.19-1 Input signals of phase undervoltage protection .......................................... 3-170

Table 3.19-2 Output signals of phase undervoltage protection ....................................... 3-170

3-l PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

Table 3.19-3 Settings of phase undervoltage protection .................................................. 3-171

Table 3.20-1 Input signals of overfrequency protection ................................................... 3-176

Table 3.20-2 Output signals of overfrequency protection ................................................ 3-177

Table 3.20-3 Settings of overfrequency protection............................................................ 3-177

Table 3.21-1 Input signals of underfrequency protection ................................................. 3-180

Table 3.21-2 Output signals of underfrequency protection .............................................. 3-180

Table 3.21-3 Settings of underfrequency protection ......................................................... 3-181

Table 3.22-1 Input signals of distance protection .............................................................. 3-203 3


Table 3.22-2 Output signals of distance protection ........................................................... 3-204

Table 3.22-3 Settings of distance protection ...................................................................... 3-208

Table 3.23-1 Output signals of programmable trip output ................................................ 3-213

Table 3.23-2 Settings of programmable trip output ........................................................... 3-213

PCS-978S Transformer Relay 3-m


Date: 2022-01-17
3 Protection Functions

In the chapter, the prefix ”x.” in some signals, settings and measurements,
represents some side or bushing of transformer defined by user through
PCS-Studio software, which may be “HVS”, “MVS”, “LVS”, “HVS2”,
“MVS2”, “LVS2”, “CWS”, “HVB”, “MVB”, “LVB”, etc. If only one protection
element is equipped, the prefix “x.” may disappear.

3.1 Three-phase Current Element (TCUR3P)

Three-phase current element is responsible for pre-processing three phase currents and
3
calculating sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is used for protection logic calculation.

3.1.1 Function Description


Three-phase current element has following functions:

1. Pre-process three phase currents

2. Calculate information related to three-phase current

3.1.1.1 CT Circuit Failure Supervision

When three phase currents are engaged in the calculation of transformer differential protection,
restricted earth fault protection or winding differential protection, CT circuit failure supervision of
each protection is carried out in the corresponding protection element, which can refer to
corresponding sections for details.

3.1.1.2 Current Detection

When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.

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Date: 2022-01-17
3 Protection Functions

3.1.2 Function Block Diagram

TCUR3P

x.in_ia x.I3P

x.in_ib x.Ia_Sec

x.in_ic x.Ib_Sec

x.Ic_Sec

x.I1_Sec

3 x.I2_Sec

x.3I0_Cal_Sec

x.Ang(Ia-Ib)

x.Ang(Ib-Ic)

x.Ang(Ic-Ia)

x.Ang(Ia)

x.Ang(Ib)

x.Ang(Ic)

x.Ang(3I0_Cal)

x.Flg_OnLoad

x.CTS.Alm

3.1.3 I/O Signals


Table 3.1-1 Input signals of three-phase current element

No. Input Signal Description


1 x.in_ia Sampled value of phase-A current at x side of transformer
2 x.in_ib Sampled value of phase-B current at x side of transformer
3 x.in_ic Sampled value of phase-C current at x side of transformer

Table 3.1-2 Output signals of three-phase current element

No. Output Signal Description


1 x.I3P A current data set at x side of transformer
2 x.Ia_Sec Amplitude of phase-A secondary current at x side of transformer
3 x.Ib_Sec Amplitude of phase-B secondary current at x side of transformer
4 x.Ic_Sec Amplitude of phase-C secondary current at x side of transformer
5 x.I1_Sec Amplitude of positive sequence secondary current at x side of transformer
6 x.I2_Sec Amplitude of negative sequence secondary current at x side of transformer
7 x.3I0_Cal_Sec Amplitude of calculated residual secondary current at x side of transformer

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No. Output Signal Description


8 x.Ang(Ia-Ib) Phase angle between phase A and phase B currents at x side of transformer
9 x.Ang(Ib-Ic) Phase angle between phase B and phase C currents at x side of transformer
10 x.Ang(Ic-Ia) Phase angle between phase C and phase A currents at x side of transformer
11 x.Ang(Ia) Phase angle of phase-A current at x side of transformer
12 x.Ang(Ib) Phase angle of phase-B current at x side of transformer
13 x.Ang(Ic) Phase angle of phase-C current at x side of transformer
14 x.Ang(3I0_Cal) Phase angle of calculated residual current at x side of transformer
15 x.Flg_OnLoad A flag indicating there is load current detected at x side of transformer
16 x.CTS.Alm CT secondary circuit failure at x side of transformer

3.1.4 Settings
3
Table 3.1-3 Settings of three-phase current element

No. Item Range Unit Default Description


1 x.I1n 0~9999 A 1000 Primary current value at x side of transformer
2 x.I2n 1 or 5 A 1 Secondary current value at x side of transformer
Enabled, Logic setting of enabling/disabling the current polarity of
3 x.En_RevCT - Disabled
Disabled CT reversed at x side of transformer

3.2 Three-phase Voltage Element (TVOL3P)

Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is used for the protection logic calculation.

3.2.1 Function Description

Three-phase voltage element has following functions:

1. Pre-process three phase voltages

2. Calculate information related to three phase voltages

3.2.1.1 VT Circuit Failure Supervision

VT circuit failure supervision of three-phase voltage is carried out by the special VTS element,
which can refer to Section 3.22 for details.

PCS-978S Transformer Relay 3-3


Date: 2022-01-17
3 Protection Functions

3.2.2 Function Block Diagram

TVOL3P

x.in_ua x.U3P

x.in_ub x.Ua_Sec

x.in_uc x.Ub_Sec

x.BI_En_VT x.Uc_Sec

x.Uab_Sec

3 x.Ubc_Sec

x.Uca_Sec

x.U1_Sec

x.U2_Sec

x.3U0_Cal_Sec

x.Ang(Ua-Ub)

x.Ang(Ub-Uc)

x.Ang(Uc-Ua)

x.Ang(Ua)

x.Ang(Ub)

x.Ang(Uc)

x.Ang(3U0_Cal)

x.Ang(U1)

x.Ang(U2)

x.VTS.Alm

3.2.3 I/O Signals


Table 3.2-1 Input signals of three-phase voltage element

No. Input signal Description


1 x.in_ua Sampled value of phase-A voltage at x side of transformer
2 x.in_ub Sampled value of phase-B voltage at x side of transformer
3 x.in_uc Sampled value of phase-C voltage at x side of transformer
4 x.BI_En_VT Input signal of indicating VT in service at x side of transformer

Table 3.2-2 Output signals of three-phase voltage element

No. Output signal Description


1 x.U3P A voltage data set at x side of transformer

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3 Protection Functions

No. Output signal Description


2 x.Ua_Sec Amplitude of phase-A secondary voltage at x side of transformer
3 x.Ub_Sec Amplitude of phase-B secondary voltage at x side of transformer
4 x.Uc_Sec Amplitude of phase-C secondary voltage at x side of transformer
5 x.Uab_Sec Amplitude of phase-AB secondary voltage at x side of transformer
6 x.Ubc_Sec Amplitude of phase-BC secondary voltage at x side of transformer
7 x.Uca_Sec Amplitude of phase-CA secondary voltage at x side of transformer
8 x.U1_Sec Amplitude of positive sequence secondary voltage at x side of transformer
9 x.U2_Sec Amplitude of negative sequence secondary voltage at x side of transformer
10 x.3U0_Cal_Sec Amplitude of calculated residual secondary voltage at x side of transformer
11 x.Ang(Ua-Ub) Phase angle between phase A and phase B voltages at x side of transformer 3
12 x.Ang(Ub-Uc) Phase angle between phase B and phase C voltages at x side of transformer
13 x.Ang(Uc-Ua) Phase angle between phase C and phase A voltages at x side of transformer
14 x.Ang(Ua) Phase angle of phase-A voltage at x side of transformer
15 x.Ang(Ub) Phase angle of phase-B voltage at x side of transformer
16 x.Ang(Uc) Phase angle of phase-C voltage at x side of transformer
17 x.Ang(3U0_Cal) Phase angle of calculated residual voltage at x side of transformer
18 x.Ang(U1) Phase angle of positive sequence voltage at x side of transformer
19 x.Ang(U2) Phase angle of negative sequence voltage at x side of transformer
VT secondary circuit abnormality at x side of transformer
20 x.VTS.Alm
For the logic of signal “x.VTS.Alm”, please refer to Section 6.6.

3.2.4 Settings
Table 3.2-3 Settings of three-phase voltage element

No. Item Range Unit Default Description


Rated primary voltage value of VT at x side of
1 x.U1n 1.000~1100.000 kV -
transformer
Rated secondary voltage value of VT at x side of
2 x.U2n 1.000~120.000 V -
transformer
Enabled,
3 x.En_VT - Enabled Logic setting to put VT into service
Disabled

3.3 Single-phase Current Element (TCUR1P)

Single-phase current element is responsible for pre-processing measured single-phase current


and calculating the magnitude and the phase angle of the single-phase current, etc. All calculated
information of single-phase current element is used for the protection logic calculation.

3.3.1 Function Description


Single-phase current element has following functions:

1. Pre-process measured single-phase current

PCS-978S Transformer Relay 3-5


Date: 2022-01-17
3 Protection Functions

2. Calculate information related to the single-phase current

3.3.2 Function Block Diagram

TCUR1P

x.in_ip x.I1P

x.3I0_Ext_Sec

x.Ang(3I0_Ext)

x.Flg_OnLoad
3
3.3.3 I/O Signals
Table 3.3-1 Input signals of single-phase current element

No. Input signal Description


1 x.in_ip Sampled single-phase current at x side of transformer

Table 3.3-2 Output signals of single-phase current element

No. Output signal Description


1 x.I1P A current data set at x side of transformer
2 x.3I0_Ext_Sec Amplitude of external residual secondary current at x side of transformer
3 x.Ang(3I0_Ext) Phase angle of external residual current at x side of transformer
4 x.Flg_OnLoad A flag indicating that the load current is detected at x side of transformer

3.3.4 Settings
Table 3.3-3 Settings of single-phase current element

No. Item Range Unit Default Description


Primary rated current of neutral CT at x side of
1 x.Neu.I1n 0~9999 A 1000
transformer
Secondary rated current of neutral CT at x side of
2 x.Neu.I2n 1 or 5 A 1
transformer
Enabled, Logic setting of enabling/disabling the current polarity
3 x.Neu.En_RevCT - Disabled
Disabled of neutral CT reversed at x side of transformer

3.4 Single-phase Voltage Element (TVOL1P)

Single-phase voltage element is responsible for pre-processing single-phase voltage and


calculating the magnitude and the phase angle of the single-phase voltage, etc. All calculated
information of single-phase voltage element is used for the protection logic calculation.

3.4.1 Function Description

Single-phase voltage element has following functions:

3-6 PCS-978S Transformer Relay

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3 Protection Functions

1. Pre-process measured single-phase voltage

2. Calculate information related to single-phase voltage

3.4.2 Function Block Diagram

TVOL1P

x.in_up x.U1P

x.U_Sec

x.Ang(U)
3
3.4.3 I/O Signals
Table 3.4-1 Input signals of single-phase voltage element

No. Input signal Description


1 x.in_up Sampled single-phase voltage at x side of transformer

Table 3.4-2 Output signals of single-phase voltage element

No. Output signal Description


1 x.U1P A voltage data set at x side of transformer
2 x.U_Sec Amplitude of single-phase secondary voltage at x side of transformer
3 x.Ang(U) Phase angle of single-phase voltage at x side of transformer

3.4.4 Settings
Table 3.4-3 Settings of single-phase voltage element

No. Item Range Unit Default Description


Primary rated voltage of broken-delta VT at x side of
1 x.Neu.U1n 0.000~1100.000 kV -
transformer
Secondary rated voltage of broken-delta VT at x side
2 x.Neu.U2n 1.000~200.000 V -
of transformer

3.5 Three-phase Current Summation Element (TCUR3P_3SD)

Three-phase current summation element is responsible for calculating the sum of multiple current
inputs in one side of transformer. All calculated information of three-phase current summation
element is used for the protection logic calculation.

3.5.1 Function Description

Three-phase current summation element is used to calculate the sum of several groups of
currents.

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3 Protection Functions

3.5.1.1 Current Detection

When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.

3.5.2 Function Block Diagram

TCUR3P_3SD

x.in_i3p1 x.I3P

x.in_i3p2 x.Ia_Sec
3 x.in_i3p3 x.Ib_Sec

x.Ic_Sec

x.I1_Sec

x.I2_Sec

x.3I0_Cal_Sec

x.Ang(Ia-Ib)

x.Ang(Ib-Ic)

x.Ang(Ic-Ia)

x.Ang(Ia)

x.Ang(Ib)

x.Ang(Ic)

x.Ang(3I0_Cal)

x.Flg_OnLoad

3.5.3 I/O Signals


Table 3.5-1 Input signals of three-phase current summation element

No. Input signal Description


st
1 x.in_i3p1 Sampled value of the 1 group of three-phase current at x side of transformer
2 x.in_i3p2 Sampled value of the 2nd group of three-phase current at x side of transformer
3 x.in_i3p3 Sampled value of the 3rd group of three-phase current at x side of transformer

Table 3.5-2 Output signals of three-phase current summation element

No. Output signal Description


1 x.I3P A current data set at x side of transformer
2 x.Ia_Sec Amplitude of phase-A secondary current at x side of transformer
3 x.Ib_Sec Amplitude of phase-B secondary current at x side of transformer
4 x.Ic_Sec Amplitude of phase-C secondary current at x side of transformer

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No. Output signal Description


5 x.I1_Sec Amplitude of positive sequence secondary current at x side of transformer
6 x.I2_Sec Amplitude of negative sequence secondary current at x side of transformer
7 x.3I0_Cal_Sec Amplitude of calculated residual secondary current at x side of transformer
8 x.Ang(Ia-Ib) Phase angle between phase A and phase B currents at x side of transformer
9 x.Ang(Ib-Ic) Phase angle between phase B and phase C currents at x side of transformer
10 x.Ang(Ic-Ia) Phase angle between phase C and phase A currents at x side of transformer
11 x.Ang(Ia) Phase angle of phase-A current at x side of transformer
12 x.Ang(Ib) Phase angle of phase-B current at x side of transformer
13 x.Ang(Ic) Phase angle of phase-C current at x side of transformer
14 x.Ang(3I0_Cal) Phase angle of calculated residual current at x side of transformer 3
15 x.Flg_OnLoad A flag indicating there is load current detected at x side of transformer

3.6 Transformer Current Differential Protection (87T)

In power system, the power transformer is one of most valuable and expensive equipment. If a
fault occurs in the protection zone of a transformer, current differential protection operates quickly
to clear the fault to avoid the transformer from damages or reduce the maintenance cost as low as
possible.

3.6.1 Function Description


Transformer differential protection can be provided with up to 6 sets of three-phase current inputs,
and can be used for 2-winding, 3-winding transformer and auto-transformer. There are 24 vector
groups available for 2-winding transformer and 288 vector groups available for 3-winding
transformer.

Transformer differential protection includes biased differential element, instantaneous differential


element, DPFC biased differential element. Biased differential element is biased characteristic
with three slopes. Instantaneous differential element is without biased characteristic and blocking
logic and can accelerate to operate for transformer's severe internal faults. DPFC biased
differential element calculated by current variation has high sensitivity to inter-turn faults and
high-impedance fault under heavy load. Three differential elements mentioned above work
coordinately to form the high-speed current differential protection with high sensitivity.

3.6.1.1 Fault Detector

 Fault detector based on biased differential current

The fault detector can initiate biased differential element, and its operation equation is as follows.

Id>[87T.I_Biased] Equation 3.6-1

Where:

Id is the differential current of any phase.

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Date: 2022-01-17
3 Protection Functions

 Fault detector based on instantaneous differential current

The fault detector can initiate instantaneous differential element, and its operation equation is as
follows.

Id>0.5x[87T.I_Inst] Equation 3.6-2

Where:

Id is the differential current of any phase.

 Fault Detector based on DPFC differential current


3 The fault detector can initiate DPFC biased differential element, and its operation equation is as
follows.

∆𝐼𝑑 > 1.25 × ∆𝐼𝑑𝑡 + 𝐼𝑑𝑡ℎ


Equation 3.6-3
∆𝐼𝑑 = ⌈∆𝐼1̇ + ∆𝐼2̇ + ⋯ + ∆𝐼𝑚̇ ⌉

Where:

∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and hence the
element maintains stability.

𝐼𝑑𝑡ℎ is fixed threshold internally.

∆𝐼𝑑 is DPFC differential current.

∆𝐼1̇ , ∆𝐼2̇ , …, ∆𝐼𝑚̇ are DPFC current of each side of transformer representatively.

Regardless of direction of power flow and very sensitive, this fault detector is used to guard DPFC
biased differential protection. The setting is fixed in factory and thus site setting is not required.

3.6.1.2 Amplitude Compensation

During the normal operation, the magnitudes of secondary current of each side of transformer are
different due to the mismatch between the CT ratios and the power transformer ratio. The current
value difference between each side shall be eliminated before calculation for current differential
protection by amplitude compensation.

 Calculate rated primary current at each side

Sn
I1bBrm  Equation 3.6-4
3U1nBrm

Where:

Sn is the maximum rated capacity (i.e., the setting [Sn]).

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U1nBrm is rated primary voltage of side m (i.e., the settings [HVS.U1n_Plate], [MVS.U1n_Plate] or
[LVS.U1n_Plate]).

I1bBrm is rated primary current of side m.

 Calculate rated secondary current at each side

I 1bBrm
I 2bBrm  Equation 3.6-5
CTBrm

Where:

I2bBrm is rated secondary current of side m.

CTBrm is the CT ratio of side m.


3
 Limitation of secondary current

For all differential protections, the secondary currents of each side must follow below criterion.

I 2bBr1 I 2bBr2 I
Max( , ,..., 2bBrm )
I 2nBr1 I 2nBr2 I 2nBrm
 128 Equation 3.6-6
I 2bBr1 I 2bBr2 I 2bBrm
Min( , ,..., )
I 2nBr1 I 2nBr2 I 2nBrm

When selecting CT, the ratio between maximum value and minimum value
should be considered. It is recommended that the ratio is smaller than 16.
Theoretically, the ratio is preferred to be as small as it can be.

For DPFC biased differential element, the secondary currents of each side must follow Equation
3.6-7 in addition to Equation 3.6-6. Otherwise, alarm signals [ProtBrd.Fail_Settings] and
[FDBrd.Fail_Settings] are issued and the device will be blocked at the same time unless DPFC
biased differential element is disabled.

I 2bBr1 I 2bBr2 I
Max( , ,..., 2bBrm )  0.4
I 2nBr1 I 2nBr2 I 2nBrm
Equation 3.6-7
I I I
Min( 2bBr1 , 2bBr2 ,..., 2bBrm )  0.1
I 2nBr1 I 2nBr2 I 2nBrm

Where:

I2bBr1, I2bBr2… I2bBrm are rated secondary current of branch 1, 2 … m of transformer.

I2nBr1, I2nBr2…I2nBrm are CT rated secondary current of branch 1, 2 … m of transformer.

If Equation 3.6-6 is not met, alarm signals [ProtBrd.Fail_Settings] and


[FDBrd.Fail_Settings] are issued and the device will be blocked at the

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3 Protection Functions

same time.

When viewing settings and values of conventional current differential


protection in the device, p.u. (per unit value) is provided. The current in
differential protection calculation is not actual secondary value but per unit
value which is got by actual secondary value of each branch of transformer
divided by transformer secondary rated current of each side (i.e., I2bBrm).

3.6.1.3 Phase Compensation

 Phase compensation principle

3 False differential current is caused by phase shift between the power transformer primary current
and secondary current for delta/wye, so phases of each side secondary current must be
compensated by this phase compensation. Δ→Y and Y→Δ transfer methods by settings can be
selected to adjust phase angle of secondary current on each side of the transformer, and Δ→Y
transfer method is recommended. Zero-sequence current is always eliminated both at Y and Δ
windings by adopting Δ→Y method.

The following transforming method is based on the assumptions listed here:

1. Each side three-phase CT of transformer shall be connected in star type.

2. The positive polarity of each side three-phase CT shall be at busbar side.

The wiring connection of HV, MV and LV sides may be different, so it is needed to compensate
phase of each side current of transformer for calculation of current differential protection. There
are two transforming methods for phase compensation: Δ→Y and Y→Δ, and different
transforming methods will result in the difference.

Phase compensation is controlled by the following settings:

1. [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]: the wiring o’clock of MV/LV side with respect


to HV side, is the parameter shown on transformer nameplate with the range of 0~11, and
need no further calculation.

2. [Clk_PhComp]: the target o'clock each side current will be shifted to for phase compensation.

3. [HVS.En_I0Elim], [MVS.En_I0Elim] and [LVS.En_I0Elim]: logic settings to enable


zero-sequence current elimination for phase compensation of each side of transformer. The
setting is recommended to be set to “1” in general condition, and only if one side of
transformer, without earthing transformer being connected to, is not grounded, the setting of
corresponding side is recommended to be set to “0”.

For example:

The vector group of a transformer is Y0/Δ11 and the target o'clock ([Clk_PhComp]) is set to LV
side. Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.

1. For HV side, with reference to the set target o'clock, the o'clock of HV side is 1 (i.e. wiring
o'clock 12-target o'clock 11) clock, so the matrix of relative o'clock 1 is adopted to

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compensate HV side current.

2. For LV side, with reference to the set target o'clock, the o'clock of LV side is 0 (i.e. wiring
o'clock 11- target o'clock 11), so the matrix of relative o'clock 0 is adopted to compensate LV
side current.

If an earthing transformer is connected outside the protection zone of differential protection, the
setting [HVS.En_I0Elim] (or [LVS.En_I0Elim]) could be disabled, i.e. set to 0.

If an earthing transformer is connected within the protection zone of differential protection, then
zero-sequence current must be eliminated and otherwise differential protection may operate
unexpectedly during an external fault. Therefore the setting [HVS.En_I0Elim] (or [LVS.En_I0Elim])
must be enabled, i.e., set to 1. 3
Table 3.6-1 Matrix of phase compensation

Matrix without zero-sequence current Matrix with zero-sequence current


Relative o'clock
elimination elimination

1 0 0   2 - 1 - 1
0 0 1 0  1
- 1 2 - 1
(No phase shit)   3 
0 0 1 - 1 - 1 2 

 1 -1 0   1 -1 0 
1 
0 1 - 1
1 
0 1 - 1
1
(Shift 30°leading) 3  3 
- 1 0 1  - 1 0 1 

 0 -1 0   1 -2 1 
2  0 0 - 1 1
1 1 - 2
(shift 60°leading)   3 
- 1 0 0  - 2 1 1 

 0 -1 1   0 -1 1 
1 
1 0 - 1
1 
1 0 - 1
3
(Shit 90°leading) 3  3 
- 1 1 0  - 1 1 0 

0 0 1 - 1 - 1 2 
4 1 0 0  1
2 - 1 - 1
(Shit 120°leading)   3 
0 1 0  - 1 2 - 1

- 1 0 1  - 1 0 1 
1 
1 - 1 0 
1 
1 - 1 0 
5
(Shift 150°leading) 3  3 
 0 1 - 1  0 1 - 1

- 1 0 0  - 2 1 1 
6  0 -1 0  1
1 - 2 1 
(Shift 180°leading)   3
 0 0 - 1  1 1 - 2

PCS-978S Transformer Relay 3-13


Date: 2022-01-17
3 Protection Functions

Matrix without zero-sequence current Matrix with zero-sequence current


Relative o'clock
elimination elimination

- 1 1 0  - 1 1 0 
1 
0 - 1 1 
1 
0 - 1 1 
7
(Shift 150°lagging) 3  3 
 1 0 - 1  1 0 - 1
0 1 0  - 1 2 - 1
8 0 0 1 1
- 1 - 1 2 
(Shift 120°lagging)   3 
1 0 0   2 - 1 - 1

3 1 
 0 1 - 1  0 1 - 1
- 1 0 1 
1 
- 1 0 1 
S9
(Shift 90°lagging) 3  3 
 1 - 1 0   1 - 1 0 

 0 0 - 1  1 1 - 2
10 - 1 0 0  1
- 2 1 1 
(Shift 60°lagging)   3 
 0 - 1 0   1 - 2 1 

 1 0 - 1  1 0 - 1
1 
- 1 1 0 
1 
- 1 1 0 
11
(Shift 30°lagging) 3  3 
 0 - 1 1   0 - 1 1 

3.6.1.4 Calculations of Differential and Restraint Currents

The equation of calculating differential current is:


 I dA   I A1  I A2   I A3  I A4 
         
 dB  M 1  I B1 2bBr1 M 2  I B 2  2bBr 2 M 3  I B3 2bBr 3 M 4  I B 4  / I 2bBr 4 
I   / I   / I   / I  
 I dC   I C1  I C 2  I C 3 I C 4 
          
1 2 3 4
Equation 3.6-8
 I A5   I A6 
   
M 5   I B5  / I 2bBr 5  M 6   I B6  / I 2bBr 6
I C5  I C6 
     
5 6

The above equation can be simplified to the following:

 I dA  I  A1  I  A2  I  A3  I A4  I A5  I A6



 I dB  I  B1  I  B 2  I  B 3  I B 4  I B 5  I B 6 Equation 3.6-9

 I dC  I C1  I C 2  I C 3  I C 4  I C 5  I C 6

The equation of calculating restraint current is:

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 1
 
 I rA  2 I  A1  I  A2  I  A3  I  A4  I  A5  I  A6


 I rB 
1

I B1  I B 2  I B 3  I B 4  I B 5  I B 6  Equation 3.6-10
 2
 1

 I rC  2 I C1  I C 2  I C 3  I C 4  I C 5  I C 6 

Where:

IAm, IBm, ICm are the secondary current of branch m (m=1, 2, 3, 4, 5, 6).

I'Am, I'Bm, I'Cm are corrected secondary current of branch m (m=1, 2, 3, 4, 5, 6).

IdA, IdB, IdC are differential currents.


3
IrA, IrB, IrC are restraint currents.

M1, M2, M3, M4, M5, M6 are matrixes of phase shifting of each branch of transformer respectively.
Its value is decided according to the vector group of transformer and please refers to “section
3.6.1.2” for details.

I2bBr1, I2bBr2, I2bBr3, I2bBr4, I2bBr5, I2bBr6 are rated secondary values of each branch of transformer
respectively.

Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current (i.e.,
Id=I'_H+I'_L) should be zero during the normal operation of the transformer or an external fault
occurring.
*

HV side I_H I_L LV side


*

*
*

I'_H I'_L

PCS-978S
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)

Magnitude compensation Magnitude compensation


(/I2bBr1) (/I2bBr2)

I''_H I''_L

Calculate differential current and restraint current

Figure 3.6-1 Current compensation calculation process

Where:

“I_H” and “I_L” are primary currents of HV and LV sides respectively.

“I'_H” and “I'_L” are secondary currents of HV and LV sides respectively.

“I''_H” and “I''_L” are secondary corrected currents of HV and LV sides respectively.

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3 Protection Functions

M1 and M2 are matrixes of phase shifting and zero-sequence current elimination of HV and LV
sides respectively.

I2bBr1 and I2bBr2 are rated secondary currents at HV and LV sides respectively.

The symbol “*” represents the polarity of CT. If current flowing into the
polarity of CT, the current direction is defined as forward direction.

To clarify the situation, three important operation conditions with ideal and matched measurement

3 quantities are considered.

1. Through-flowing current under undisturbed conditions or external fault:

I'_H flows into the protected zone, I'_L leaves the protected zone, according to the definition of
signs in above figure, therefore I'_H=–I'_L.

Moreover |I'_H|=|I'_L|

Id=|I'_H+I'_L|=|I'_H-I'_H|=0

Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|

Differential current (Id) is far less than restraint current (Ir), and current differential protection
does not operate.

2. Internal short-circuit fault, infeed with equal currents each side:

The following applies I'_L=I'_H, moreover |I'_L|=|I'_H|

Id=|I'_H+I'_L|=|I'_H+I'_H|=2|I'_H|

Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|

Differential current (Id) is two times of restraint current (Ir), and current differential protection
operates.

3. Internal short-circuit fault, infeed from one side only:

The following applies I'_L=0

Id=|I'_H+I'_L|=|I'_H+0|=|I'_H|

Ir=(|I'_H |+|I'_L|)/2=(|I'_H|+|0|)/2=|I'_H|/2

Differential current (Id) are two times of restraint current (Ir), and current differential protection
operates.

3.6.1.5 Biased Differential Element

1. Sensitive biased differential element

The currents for following calculation are the products of the actual secondary current of each side

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multiplying its own correction coefficient. The sensitive biased differential element with low pickup
setting and restraint slope is much more sensitive for a slight internal fault. Four blocking elements,
CT saturation, inrush current, overexcitation and CT circuit failure (optional) have also been
included for the protection in order to prevent it from the unwanted operation during an external
fault.

𝐼𝑑 > 𝐾1 × 𝐼𝑟 + 𝐼𝑝𝑘𝑝 (𝐼𝑟 < 𝐾𝑛𝑒𝑒1)

𝐼𝑑 > 𝐾2 × (𝐼𝑟 − 𝐾𝑛𝑒𝑒1) + 𝐾1 × 𝐾𝑛𝑒𝑒1 + 𝐼𝑝𝑘𝑝 (𝐾𝑛𝑒𝑒1 ≤ 𝐼𝑟 ≤ 𝐾𝑛𝑒𝑒2)

𝐼𝑑 > 𝐾3 × (𝐼𝑟 − 𝐾𝑛𝑒𝑒2) + 𝐾2 × (𝐾𝑛𝑒𝑒2 − 𝐾𝑛𝑒𝑒1) + 𝐾1 × 𝐾𝑛𝑒𝑒1 + 𝐼𝑝𝑘𝑝 (𝐼𝑟


> 𝐾𝑛𝑒𝑒2)

𝑚 Equation 3.6-11
3
𝐼𝑑 = |∑ 𝐼𝑖̇ |
𝑖=1

𝑚
1
𝐼𝑟 = ∑|𝐼𝑖̇ |
2
𝑖=1

Where:

𝐼𝑑 and 𝐼𝑟 are respectively the differential current and the restraint current.

𝐼𝑝𝑘𝑝 is the pickup setting of biased differential protection (i.e., [87T.I_Biased]).


“Knee1” and “Knee2” are respectively current settings of knee point 1 and knee point 2 (i.e.,
[87T.I_Knee1] and [87T.I_Knee2]). “K1”, “K2” and “K3” are three slopes of biased differential
protection. (i.e., [87T.Slope1], [87T.Slope2], [87T.Slope3], recommended values: [87T.Slope1]=0.2,
[87T.Slope2]=0.5 and [87T.Slope3]=0.75.)

Operation characteristic of sensitive biased differential element is shown below.


Differential current

K=2

[87T.I_Inst]

t
en
m
le
le
6 tia
0. r en
K= ffe
di
d
a se
bi
[87T.Slope1] e [87T.Slope3]
tiv
si
s en
of
ea
ar
n
io
at
er
op
1.2
[87T.Slope2]

[87T.I_Biased] Restraint current


0.8
[87T.I_Knee1] [87T.I_Knee2]

Figure 3.6-2 Operation characteristic of sensitive biased differential element

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2. Conventional biased differential element

Conventional biased differential element with higher setting and restraint coefficient comparing
with sensitive biased differential element is blocked only by an inrush current detection.
Conventional biased differential element provides faster operation for severe internal faults. Its
operation criterion is:

𝐼𝑑 > 1.2𝑝. 𝑢. (𝐼𝑟 ≤ 0.8𝑝. 𝑢. )


Equation 3.6-12
𝐼𝑑 > 𝑚𝑎𝑥(0.6, [87𝑇. 𝑆𝑙𝑜𝑝3] − 0.15) × (𝐼𝑟 − 0.8𝑝. 𝑢. ) + 1.2𝑝. 𝑢. (𝐼𝑟 > 0.8𝑝. 𝑢. )

3 Conventional biased differential element can eliminate the influence of CT saturation during an
external fault and ensures reliable operation even if CT is saturated during an internal fault by
means of its biased characteristic.

The slop of conventional biased differential element takes the higher one
between “0.6” and “[87T.Slope3]-0.15”, and the knee point is fixed in
program.

Operation characteristic of conventional biased differential element is shown below.


Differential current

K=2

[87T.I_Inst]

K=max(0.6, [87T.Slope3]-0.15)

1.2

Restraint current
0.8

Figure 3.6-3 Operation characteristic of conventional biased differential element

When the transformer capacity is too small or the CT ratio is too large, the
rated currents will be very small. So, in order to ensuring the reliability, the

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pickup current of differential element will be raised adaptively,

The actual pickup current = Max ([87T.I_Biased], 0.04/Min (I2bBr1/I2nBr1,


I2bBr2/I2nBr2, ……, I2bBrm/I2nBrm))

3.6.1.6 Instantaneous Differential Element

Instantaneous differential element for transformer is to accelerate the operation speed for
transformer's internal fault. The element has no blocking element but to guard that the setting
must be greater than the maximum inrush current. Instantaneous differential element shall
operate to clear the fault when any phase differential current is higher than its setting. Its
operation criterion is:
3
Id>[87T.I_Inst] Equation 3.6-13

Where:

Id is the maximum value of three phase differential currents.


Differential current

F operation area of instantaneous


K=2 differential element

[87T.I_Inst]

of d
ea se
ar bia ent K=0.6
[87T.Slope1] n
io al m
at n ele e
er ntio ial tiv
p
o ve nt n si ent
n re se em
co iffe of l el [87T.Slope3]
d ea ia
ar ent
n r
tio ffe
e ra d di
E C op ase
bi

D
1.2

[87T.Slope2]

[87T.I_Biased]
0.8 B Restraint current
A [87T.I_Knee2]
[87T.I_Knee1]

Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements

The characteristic of internal faults is a straight line with the slope 2 (63.4°) in the operation
diagram (dash-dotted line K=2)

Point A shows normal operation of transformer.

Point B shows CT saturation.

Point C, D, E, and F indicate internal faults or external fault of transformer.

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3 Protection Functions

1. Sensitive biased differential element will send tripping signal monitored by CT saturation,
overexcitation, inrush current and CT circuit failure (optional). It can ensure sensitivity and
avoid the unwanted operation when CT is saturated during an external fault. Its operation
area is the tint shadow area in the figure above.

When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the tripping area of sensitive biased differential protection.

When an external fault occurs, the short-circuit current rise strongly, causing a
correspondingly high restraint current (2 times through-flowing current) with little differential
current. After CT reaches saturation (point B), a differential quantity is produced and the

3 restraint quantity is reduced. In consequence, the operating point may moves into the tripping
area of sensitive biased differential protection. Because CT saturation criterion is equipped,
sensitive biased differential protection will not maloperate even the fault point moves into the
operation area.

2. Conventional biased differential element will send tripping signal monitored by inrush current
only. It eliminates the influence of transient and steady saturations of CT during an external
fault and ensures reliable operation even if CT is in saturation condition during an internal
fault by means of its biased characteristic. Its operation area is the deeper shadow area in the
figure above.

When an internal fault occurs, differential current rises greatly and the operating point moves
to E in the tripping area of conventional biased differential protection. (Only the second
harmonic criterion is adapted to distinguishing inrush current for blocking conventional biased
differential protection.)

3. Unrestrained instantaneous differential protection element will send tripping signal without
any blocking if differential current of any phase reaches its setting. Its operation area is over
the above two areas with the deepest dark shadow.

When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.

3.6.1.7 DPFC Biased Differential Element

DPFC biased differential protection is regardless of the load current and is sensitive to small
internal fault current within the transformer. Its performance against current transformer saturation
is also good. DPFC (Deviation of Power Frequency Component) is the power frequency
component of fault component, which is the differential value between the sampling value at this
time point and that at a cycle before.

DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to slight inter-turn fault is maintained during normal operation of transformer. The sensitivity
of transformer differential protection is improved greatly when DPFC biased differential element is
enabled, especially in the situation inter-turn fault during heavy load operation.

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200

100

-100

-200
0 20 40 60 80 100 120
Original Current
100

50

-50

-100
3
0 20 40 60 80 100 120
DPFC current

ΔI=I(K)-I(K-24)

I(k) is the sampling value at a point.

I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.

From above figures, it is concluded that DPFC can reflect the sudden change of fault current at
the initial stage of a fault and has a perfect performance of fault detection. DPFC biased
differential protection reflects variation of load condition to perform a sensitive protection for the
transformer. Lab tests show that it is more sensitive than the biased differential element under the
heavy load condition. DPFC restraint current and differential current are phase-segregated. DPFC
biased differential element can be blocked by inrush current, overexcitation and CT circuit failure.
The operation criterion is as follows:

∆𝐼𝑑 > 0.2𝑝. 𝑢.

∆𝐼𝑑 > 1.25 × ∆𝐼𝑑𝑡 + 𝐼𝑑𝑡ℎ

∆𝐼𝑑 > 0.6 × ∆𝐼𝑟 (∆𝐼𝑟 < 2𝑝. 𝑢. )

∆𝐼𝑑 > 0.75 × ∆𝐼𝑟 − 0.3𝑝. 𝑢. (∆𝐼𝑟 > 2𝑝. 𝑢. ) Equation 3.6-14

∆𝐼𝑑 = |∆𝐼 ̇1 + ∆𝐼 ̇2 + ⋯ + ∆𝐼 ̇m|

𝑚 𝑚 𝑚

∆𝐼𝑟 = Max {∑|∆𝐼 ̇ak|, ∑|∆𝐼 ̇bk|, ∑|∆𝐼 ̇ck|}


𝑘=1 𝑘=1 𝑘=1

Where:

∆𝐼 ̇ak, ∆𝐼 ̇bk, ∆𝐼 ̇ck are DPFC current of branch k of the transformer.

∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and hence the
element maintains stability.

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𝐼𝑑𝑡ℎ is fixed threshold internally.

∆𝐼𝑑 and ∆𝐼𝑟 are DPFC differential current and DPFC restraint current respectively.

Because the calculation of restraint current is different between DPFC


biased differential element and biased differential protection, it is difficult to
test the characteristic at site, so we recommend qualitative function test
only at site.

3 Operation characteristic of DPFC biased differential element is shown below.


Differential current

K=m

K=0.75

1.2p.u.

K=0.6
0.2p.u.
Restraint current
0.333p.u. 2p.u.

Figure 3.6-5 Operation characteristic of DPFC biased differential protection

The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.

DPFC biased differential element can detect a slight inter-turn fault of transformer more
sensitively than biased current differential element. During a slight inter-turn fault, fault current will
flow through transformer whether transformer is fed from one side or from both sides. Therefore,
following two typical situations (an external fault and a slight inter-turn fault) are given to show
differential and restraint current calculation.
During normal operation, Ia_HVS=1A∠0°, Ib_LVS=1A∠180°

1. A slight inter-turn fault: I'a_HVS=1.3A∠0°, I'b_LVS=1.1A∠180°, other phase are supposed


as zero

1) Biased differential element:

Id=|I'a_HVS+I'b_LVS|

=|1.3A∠0°+1.1A∠180°|=0.2A

Ir=0.5x(|I'a_HVS|+|I'b_LVS|)

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=0.5x(|1.3A∠0°|+|1.1A∠180°|)=1.2A

2) DPFC biased differential element:

ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|

=|(1.3A∠0°-1A∠0°)+(1.1A∠180°-1A∠180°)|=0.2A

ΔIr=max(|I'a_HVS-Ia_HVS|,|I'b_LVS-Ib_LVS|)

=max(|1.3A∠0°-1A∠0°|,|1.1A∠180°-1A∠180°|)=0.3A

Conclusion: DPFC biased differential element is more sensitive than biased differential
element during an internal fault.
3
2. An external fault: I'a_HVS=2A∠0°, I'b_LVS=2A∠180°, other phase are supposed as zero

1) Biased differential element:

Id=|I'a_HVS+I'b_LVS|

=|2A∠0°+2A∠180°|=0A

Ir=0.5x(|I'a_HVS|+|I'b_LVS|)

=0.5x(|2A∠0°|+|2A∠180°|)=2A

2) DPFC biased differential element:

ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|

=|(2A∠0°-1A∠0°)+(2A∠180°-1A∠180°)|=0A

ΔIr=max(|I'a_HVS-Ia_HVS|, |I'b-_LVS-Ib_LVS|)

=max(|2A∠0°-1A∠0°|,|2A∠180°-1A∠180°|)=1A

Conclusion: DPFC biased differential element does not operate during an external fault.

3.6.1.8 Inrush Current Discrimination

The device provides optional inrush current distinguished principles: harmonic principle (second
harmonic and third harmonic) and waveform symmetry principle. The logic setting
[87T.Opt_Inrush_Ident] is used to select distinguished principle, second harmonic principle or
waveform symmetry principle. The discrimination of inrush current by third harmonics is
independent criterion, and is not controlled by the setting [87T.Opt_Inrush_Ident]. When an
internal fault occurs and CT goes to stable saturation, there are great third harmonic component in
CT secondary current. Because sensitive biased differential element has too high sensitivity, the
third harmonic criterion is only used to block sensitive biased differential element to prevent it from
maloperation when both [87T.Opt_Inrush_Ident] and [87T.En_Hm3_Blk] are set as “1”.

1. Inrush current discrimination based on harmonics

The second and third harmonics of differential current can be used to distinguish inrush current.
Its criteria are:

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3 Protection Functions

𝐼𝑑_2𝑛𝑑 > [87𝑇. 𝐾_𝐻𝑚2_𝐼𝑛𝑟𝑢𝑠ℎ] × 𝐼𝑑_1𝑠𝑡


Equation 3.6-15
𝐼𝑑_3𝑟𝑑 > [87𝑇. 𝐾_𝐻𝑚3_𝐼𝑛𝑟𝑢𝑠ℎ] × 𝐼𝑑_1𝑠𝑡

Where:

𝐼𝑑_2𝑛𝑑 and 𝐼𝑑_3𝑟𝑑 are the second and third harmonics of phase differential current respectively.

𝐼𝑑_1𝑠𝑡 is the fundamental component of corresponding phase differential current.

It is recommended to set [87T.K_Hm2_Inrush] as 0.15 and [87T.K_Hm3_Inrush] as 0.2.

3 2. Inrush current discrimination based on waveform symmetry principle

The differential current is basically the fundamental sinusoidal wave during a fault. When the
transformer is energized, plentiful harmonics will appear, and the waveform will be distorted,
interrupted and unsymmetrical. Wave symmetry principle is used to distinguish inrush current.

CT saturation characteristics make waveform unsymmetrical between the first half cycle and the
second half cycle. During internal faults, current waveform is sinusoidal wave, so two half cycles
of wave are almost symmetrical after a periodic component is eliminated (calculate the differential
of differential current in fact).

As shown in Figure 3.6-6, arc ABC is a cycle of typical waveform of differential current with a
periodic component. Flip the arc BC of second half cycle vertically to get the arc B'C', and then
move it forward half cycle to get the arc B''C''. The degree of symmetry of current wave is shown
as

S
K sym  Equation 3.6-16
S

Where:

X: arc AB

Y: arc B''C''

S+: are of X-Y

S-: are of X+Y

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Figure 3.6-6 Schematic of waveform symmetry principle 3


For a differential current waveform, the area of X is almost equal to that of Y and the value of K sym
is almost 0. For an unsymmetrical waveform, the area of X is not equal to that of Y, so the value of
Ksym is a great value. Therefore, waveform of inrush current can be distinguished from the
waveform of internal fault according to the value of K sym.

Both waveform symmetry principle and second harmonic principle are based on current distortion
due to inrush current, and the only difference is the mathematical method. The second harmonic
principle is to calculate the percentage of second harmonic in differential current, but the
waveform symmetry principle is to calculate the percentage of even harmonic to total differential
current.

3.6.1.9 Inrush Blocking Mode

There are three optional blocking modes for inrush current, self-adaptive one-phase inrush
blocking one-phase differential element mode (self-adaptive 1Pblk1P mode), two-phase inrush
blocking three-phase differential element mode (2PBlk3P mode) and one-phase inrush blocking
three-phase differential element mode (1Pblk3P mode), by the logic setting
[87T.Opt_BlkMode_Inrush]. Self-adaptive blocking mode can enhance ability of differential
protection to avoid maloperation during transformer energization effectively and ensure high
speed of differential protection for faults under normal operation. The self-adaptive blocking mode
is recommended to be selected in the actual application.

1. Self-adaptive one-phase inrush blocking one-phase differential element mode (self-adaptive


1Pblk1P mode)

The device has an energizing detection element by current criterion (without additional
breaker position signal) to check whether the transformer is in the process of energization.
Once the transformer in the process of energization is detected, the following criterions are
adopted to improve the stability to avoid mal-operation caused by inrush current.

 Criterion 1

According to the waveform characteristics, the device automatically decreases the


restraint coefficient values of second harmonics and wave distortion during the initial
stage of transformer energization, and with the passage of time and the change of

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3 Protection Functions

waveform characteristics, the device automatically increases those values which shall be
not greater than corresponding values of settings. This feature ensures biased
differential element fast operation for transformer energized on to a fault in addition to the
inrush current blocking.

 Criterion 2

The device can be self-adaptive to enable “2PBlk3P” mode according to the


comprehensive characteristics of three-phase differential current. If inrush current is
distinguished, then enables “2PBlk3P” mode for short time, and then switches to
phase-segregated blocking mode after a period.

3  Criterion 3

If the second harmonic percent of differential current used as auxiliary criteria continues
to rise, then biased differential element is kept being blocked.

2. Two-phase inrush blocking three-phase differential element mode (2PBlk3P mode)

When the inrush current is detected in any two-phase current, three-phase current differential
protection will be blocked.

3. One-phase inrush blocking three-phase differential element mode (1Pblk3P mode)

When the inrush current is detected in any phase current, three-phase current differential
protection will be blocked.

A list is given below to compare operation of differential protection in following situations.

It is supposed that three differential currents are Ida, Idb, and Idc.

Table 3.6-2 Comparison of different blocking modes

Case Harmonic current Mode 1 Mode 2 Mode 3


High harmonic component in Ida
1 High harmonic component in Idb Not operate Not operate Not operate
High harmonic component in Idc
Normal harmonic component in Ida
2 Normal harmonic component in Idb Operate Operate Operate
Normal harmonic component in Idc
High harmonic component in Ida Operate or not operate
3 High harmonic component in Idb according to differential Not operate Not operate
Normal harmonic component in Idc current waveform
High harmonic component in Ida
4 Normal harmonic component in Idb Operate Operate Not operate
Normal harmonic component in Idc

Mode 1: self-adaptive one-phase inrush blocking one-phase differential element mode

Mode 2: Two-phase inrush blocking three-phase differential element mode

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Mode 3: One-phase inrush blocking three-phase differential element mode

For mode 1 in case 3, when blocking criterion 1, 2 and 3 of inrush current discrimination are all
released to differential element, differential element can operate. Otherwise, differential element
will be blocked if any of three blocking criterions blocks.

Case 4 is usually an internal fault, and blocking mode 2 can ensure differential protection operate
correctly if there is an internal fault in case 4. Case 3 may be an internal fault or inrush current,
and blocking mode 1 can distinguish through its perfect criteria, hence, it is recommended to use
blocking mode 1.

The following figure shows the logic of inrush current blocking differential protection.
3
SET [87T.Opt_BlkMode_Inrush=0]

SIG Transformer energization >=1


SIG Blocking criterion 1
&
&

SIG Blocking criterion 3

SIG Flag_NoInrush_Harm &


>=1
SET [87T.Opt_Inrush_Ident]

& No Inrush (Phase A)


&
SIG Flag_NoInrush_Wave No Inrush (Phase B)

SIG 87T.TrigDFR No Inrush (Phase C)

SIG Flag_NoInrush_Hm3 >=1


Only valid for sensitive biased
EN [87T.En_Hm3_Blk]
differential element

SIG No Inrush (Phase A) &


& >=1

SIG No Inrush (Phase B)


& >=1
Not block 87T
&

&
SIG No Inrush (Phase C)

&

>=1

&

SET [87T.Opt_BlkMode_Inrush=2]

SET [87T.Opt_BlkMode_Inrush=1]
>=1
>=1
SIG Transformer energization 100ms 0ms &

SIG Blocking criterion 2

SET [87T.Opt_BlkMode_Inrush=0]

Figure 3.6-7 Logic of inrush current blocking current differential protection

Where:

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“Flag_NoInrush_Harm” is the internal signal that means no inrush current is detected by the
harmonic principle.

“Flag_NoInrush_Wave” is the internal signal that means no inrush current is detected by the
waveform symmetry principle.

“Flg_NoInrush_Hm3” is the internal signal that means no inrush current is detected by the third
harmonic principle.

3.6.1.10 CT Saturation Detection

There are two kinds of CT saturation, i.e. transient CT saturation and stable CT saturation. If an
3 external fault or an internal fault occurs, CT primary current increases greatly and CT secondary
current consists of fundamental component, DC component and harmonic component. The
decaying DC component results in remanent magnetism in magnetic core, and with the
accumulation of remnant magnetism, CT goes into saturation state which is called transient CT
saturation. With the time passed, the DC component decays to zero almost and CT is still
saturated caused by AC excitation, which is called stable CT saturation.

According to tests in lab, it is found that the second harmonic component is greater than the third
harmonic component at the stage of CT transient saturation and the third harmonic is greater than
the secondary harmonic at the stage of CT stable saturation. Therefore, the second and third
harmonics both can be used to detect CT saturation.

In order to prevent an unwanted operation of biased differential element caused by transient or


steady state saturation of CT during an external fault, the second and third harmonics of
secondary current of individual CTs are used for the device to discriminate saturation of
three-phase CT. If CT saturation is detected, biased differential element will be blocked.

The criterions of CT saturation detection in 87T are as shown in Equation 3.6-17.

𝐼∅_2𝑛𝑑 > 𝐾2𝑛𝑑 × 𝐼∅_1𝑠𝑡

or Equation 3.6-17

𝐼∅_3𝑟𝑑 > 𝐾3𝑟𝑑 × 𝐼∅_1𝑠𝑡

Where:

𝐼∅_1𝑠𝑡 is the fundamental component of one phase current, it won’t do CT saturation detection
unless the fundamental component is higher than the corresponding internal setting.

𝐼∅_2𝑛𝑑 is the secondary harmonic of the same phase current.

𝐼∅_3𝑟𝑑 is the third harmonic of the same phase current.

𝐾2𝑛𝑑 and 𝐾3𝑟𝑑 are fixed coefficients of secondary and third harmonics respectively.

If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and biased differential element will be blocked.

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Internal faults can be distinguished from external faults by differential protection through the
asynchronous method of differential and restraint, and if it is judged as internal fault by this
method, the CT saturation blocking element will not be enabled. Meanwhile, when some-side
measured current is relatively small, the CT saturation criterion of this side will exit automatically.
It is needed that the saturation free time of CT is no less than 4ms to ensure differential protection
operate correctly with the added CT saturation criterion.

3.6.1.11 Overexcitation Detection

When a transformer is overexcited, the exciting current will increase sharply which may result in
an unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. The third or fifth harmonic of differential current can 3
be selected to determinate overexcitation.

Id_3rd/5th>[87T.K_Hm3/Hm5_OvExc]×Id_1st Equation 3.6-18

Where:

Id_1st is the fundamental component of differential current.

Id_3rd/5th is the third or fifth harmonic of differential current.

The fifth harmonic is recommended to be selected for overexcitation calculation.

The degree of overexcitation (overexcitation factor n) can is evaluated as follows:

𝑈∗
n= ⁄𝑓 Equation 3.6-19

Where:

𝑈∗ and 𝑓∗ are per unit value of voltage and frequency respectively.

The base value for calculating per unit value of voltage is rated secondary voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.

If overexcitation factor is less than 1.4, biased differential element is blocked when the constant of
fifth or third harmonics is greater than [87T.K_Hm3/Hm5_OvExc] and this condition is judged as
overexcitation condition without damages to transformer. If overexcitation factor is greater than
1.4, biased differential element is no longer being blocked by overexcitation because transformer
is damaged in this situation.

3.6.1.12 CT Circuit Supervision

1. CT circuit abnormality

If the following operation formula is met for 10s, the differential current abnormality alarm
[87T.Alm_Diff] will be issued, but this alarm will not block the protection 87T.

The operation formula is as follows:

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Id>max(Ir×[87T.Slope]×0.9, [87T.I_Alm]) Equation 3.6-20

2. CT circuit failure

The following two cases are considered as CT circuit failure, and the device can discriminate
at which side CT circuit is faulty by unbalanced currents. Differential CT secondary circuit
failure can be judged more accurately and reliably by adopting combined method of voltage
and current.

 First case, if none of following four conditions is satisfied after the fault detector of biased
differential current, or biased residual differential current, or biased winding differential
3 current picks up, it will be judged as CT circuit failure and the alarm will be issued.

1) Negative-sequence voltage at any side is greater than 2%Upp (Upp is the


secondary phase-to-phase rated voltage).

2) Any phase current at any side increases after fault detector picks up.

3) The maximum phase current is greater than 1.1p.u. after the fault detector picks up.

4) DPFC element of any phase-to-phase voltage at any side picks up.

 If the alarm of differential CT circuit abnormality (i.e. [87T.Alm_Diff]) is issued and


negative-sequence current at one side is greater than 0.067 times maximum phase
current at the same side or greater than 0.03In, and then CT circuit failure will be judged.

3. Influence of CT circuit failure on differential protection

The alarm of CT circuit failure can be settable to block transformer differential protection,
reactor differential protection, restricted earth-fault protection and winding differential
protection. The alarm of CT circuit failure is latched once issued, it can be reset automatically
after the failure is cleared (under the condition that the setting [En_AutoRecov_Alm_CTS] is
set to be “Enabled”), or it can be reset manually when the setting [En_AutoRecov_Alm_CTS]
is set to be “Disabled”.

 Transformer's conventional biased differential element and instantaneous differential


element are always not blocked during CT circuit failure.

 Transformer's DPFC biased differential element is always blocked during CT circuit


failure.

 Transformer's sensitive biased differential element will be blocked during CT circuit failure
when the logic setting [87T.En_CTS_Blk] set as “1”.

 Biased restricted earth-fault element will be blocked during CT circuit failure when the
logic setting [64REF.En_CTS_Blk] is set as “1”.

 Biased winding differential protection will be blocked during CT circuit failure when the
logic setting [87W.En_CTS_Blk] is set as “1”.

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The operation time of biased differential element controlled by CT circuit


failure has additional 50ms delay than that of biased differential protection
not controlled by CT circuit failure.

3.6.2 Function Block Diagram

87T

87T.in_I3P1 87T.Ida
3
87T.in_I3P2 87T.Idb

87T.in_I3P3 87T.Idc

87T.in_I3P4 .
87T.in_I3P5 .
87T.in_I3P6 .
87T.Enable 87T.St_DPFC_C

87T.Block 87T.Flg_Inrush

3.6.3 I/O Signals


Table 3.6-3 Input signals of transformer differential protection

No. Input signal Description


1 87T.in_I3P1 Three-phase current data input 1 for transformer current differential protection.
2 87T.in_I3P2 Three-phase current data input 2 for transformer current differential protection.
3 87T.in_I3P3 Three-phase current data input 3 for transformer current differential protection.
4 87T.in_I3P4 Three-phase current data input 4 for transformer current differential protection.
5 87T.in_I3P5 Three-phase current data input 5 for transformer current differential protection.
6 87T.in_I3P6 Three-phase current data input 6 for transformer current differential protection.
Input signal of enabling transformer current differential protection. It is triggered
7 87T.Enable
from binary input or programmable logic etc.
Input signal of blocking transformer current differential protection. It is triggered
8 87T.Block
from binary input or programmable logic etc.

Table 3.6-4 Output signals of transformer differential protection

No. Output signal Description


1 87T.Ida Phase-A differential current of transformer differential protection.
2 87T.Idb Phase-B differential current of transformer differential protection.
3 87T.Idc Phase-C differential current of transformer differential protection.
4 87T.Ira Phase-A restraint current of transformer differential protection.

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No. Output signal Description


5 87T.Irb Phase-B restraint current of transformer differential protection.
6 87T.Irc Phase-C restraint current of transformer differential protection.
7 87T.Ia_Th Threshold value of phase-A restraint current of transformer differential protection.
8 87T.Ib_Th Threshold value of phase-B restraint current of transformer differential protection.
9 87T.Ic_Th Threshold value of phase-C restraint current of transformer differential protection.
10 87T.St Transformer differential protection starts.
11 87T.Op Transformer differential protection operates.
12 87T.Op.PhA Phase-A transformer differential protection operates.
13 87T.Op.PhB Phase-B transformer differential protection operates.
3 14 87T.Op.PhC Phase-C transformer differential protection operates.
15 87T.Op_Inst Instantaneous differential element of transformer differential protection operates.
Phase-A instantaneous differential element of transformer differential protection
16 87T.Op_Inst_A
operates.
Phase-B instantaneous differential element of transformer differential protection
17 87T.Op_Inst_B
operates.
Phase-C instantaneous differential element of transformer differential protection
18 87T.Op_Inst_C
operates.
19 87T.Op_Biased Biased differential element of transformer differential protection operates.
20 87T.Op_Biased_A Phase-A biased differential element of transformer differential protection operates.
21 87T.Op_Biased_B Phase-B biased differential element of transformer differential protection operates.
22 87T.Op_Biased_C Phase-C biased differential element of transformer differential protection operates.
23 87T.Op_DPFC DPFC differential element of transformer differential protection operates.
24 87T.Op_DPFC_A Phase-A DPFC differential element of transformer differential protection operates.
25 87T.Op_DPFC_B Phase-B DPFC differential element of transformer differential protection operates.
26 87T.Op_DPFC_C Phase-C DPFC differential element of transformer differential protection operates.
27 87T.On_Inst Instantaneous differential element of transformer differential protection is enabled.
28 87T.On_Biased Biased differential element of transformer differential protection is enabled.
29 87T.On_DPFC DPFC differential element of transformer differential protection is enabled.
30 87T.Blocked_Inst Instantaneous differential element of transformer differential protection is blocked.
31 87T.Blocked_Biased Biased differential element of transformer differential protection is blocked.
32 87T.Blocked_DPFC DPFC differential element of transformer differential protection is blocked.
33 87T.Valid_Inst Instantaneous differential element of transformer differential protection is valid.
34 87T.Valid_Biased Biased differential element of transformer differential protection is valid.
35 87T.Valid_DPFC DPFC differential element of transformer differential protection is valid.
36 87T.Alm_Diff Differential current of transformer differential protection is abnormal.
37 87T.Alm_CTS CT secondary circuit of transformer differential protection is abnormal.
38 87T.St_Inst Instantaneous differential element of transformer differential protection starts.
Phase-A instantaneous differential element of transformer differential protection
39 87T.St_Inst_A
starts.
Phase-B instantaneous differential element of transformer differential protection
40 87T.St_Inst_B
starts.
41 87T.St_Inst_C Phase-C instantaneous differential element of transformer differential protection

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No. Output signal Description


starts.
42 87T.St_Biased Biased differential element of transformer differential protection starts.
43 87T.St_Biased_A Phase-A biased differential element of transformer differential protection starts.
44 87T.St_Biased_B Phase-B biased differential element of transformer differential protection starts.
45 87T.St_Biased_C Phase-C biased differential element of transformer differential protection starts.
46 87T.St_DPFC DPFC differential element of transformer differential protection starts.
47 87T.St_DPFC_A Phase-A DPFC differential element of transformer differential protection starts.
48 87T.St_DPFC_B Phase-B DPFC differential element of transformer differential protection starts.
49 87T.St_DPFC_C Phase-C DPFC differential element of transformer differential protection starts.
50 87T.Flg_Inrush A flag indicating there is inrush current detected. 3
3.6.4 Logic

EN [87T.En_Inst] &
87T.On_Inst
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_Inst

SIG Fail_Device
&
87T.Valid_Inst

EN [87T.En_Biased] &
87T.On_Biased
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_Biased

SIG Fail_Device
&
87T.Valid_Biased

EN [87T.En_DPFC] &
87T.On_DPFC
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_DPFC

SIG Fail_Device
&
87T.Valid_DPFC

Figure 3.6-8 Logic of enabling transformer differential protection

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SET Idmax>[87T.I_Inst] &


0 500ms 87T.Pkp_Inst
FD.Pkp
SIG 87T.Valid_Inst

SET Idmax>[87T.I_Biased] &


0 500ms 87T.Pkp_Biased
FD.Pkp
SIG 87T.Valid_Biased

SET ΔId>1.25ΔIdt+Idth &


0 500ms 87T.Pkp_DPFC
FD.Pkp
SIG 87T.Valid_DPFC

3
Figure 3.6-9 Pickup logic of transformer differential protection

SET Idmax>[87T.I_Inst] &


87T.Op_Inst
SIG 87T.Pkp_Inst

Figure 3.6-10 Logic diagram of instantaneous differential element

SIG Conventional 87T &


&
SIG Inrush current

SIG 87T.Pkp_Biased
>=1
SIG Sensitive 87T & 87T.Op_Biased

SIG CT saturation >=1

SIG Inrush current

SIG CT circuit failure & &


&
EN [87T.En_CTS_Blk]

SIG Overexcitation >=1

SIG U*/f*>1.4

SIG 87T.Pkp_Biased

Figure 3.6-11 Logic diagram of biased differential element

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SIG DPFC 87T

SIG Inrush current


& &
SIG CT circuit failure 87T.Op_DPFC

SIG Overexcitation >=1

SIG U*/f*>1.4

SIG 87T.Pkp_DPFC

Figure 3.6-12 Logic diagram of DPFC biased differential element


3
SIG U2>2%Upp >=1

SIG DPFC line voltage pickup


>=1
>=1 &
SIG Any phase current increase >=1 &
CT circuit failure
SIG Ipmax >1.1p.u.

SIG 87T.Pkp_Inst
>=1
SIG 87T.Pkp_Biased

SIG 87T.Pkp_DPFC

SIG CT circuit failure &


T 0ms x.CTS.Alm
SIG I2>0.04Ipmax or I 2>0.1In

T 0ms 87T.Alm_CTS

Figure 3.6-13 Logic diagram of CT circuit failure alarm

Where:

Idmax is the maximum value of three phase differential currents.

“Upp” is phase-to-phase secondary rated voltage.

“T” is an internal time delay parameter, and it is floating and not open for user’s configuration.

3.6.5 Settings
Table 3.6-5 Settings of transformer differential protection

No. Name Range Unit Default Description


Pickup setting of biased differential
1 87T.I_Biased 0.050~5.000 p.u. 0.500
element
2 87T.I_Inst 0.050~20.000 p.u. 4.000 Current setting of instantaneous

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No. Name Range Unit Default Description


differential element
Current setting of differential circuit
3 87T.I_Alm 0.050~1.500 p.u. 0.200
abnormality alarm
Current setting of knee point 1 for
4 87T.I_Knee1 0.100~3.500 p.u. 0.500
transformer differential protection
Current setting of knee point 2 for
5 87T.I_Knee2 4.000~8.000 p.u. 6.000
transformer differential protection
6 87T.Slope1 0.000~0.900 - 0.200 Slope 1 of biased differential element
7 87T.Slope2 0.100~1.900 - 0.500 Slope 2 of biased differential element

3 8 87T.Slope3 0.100~1.900 - 0.750 Slope 3 of biased differential element


Coefficient of second harmonics
9 87T.K_Hm2_Inrush 0.050~0.800 - 0.150
for inrush current detection
Coefficient of third harmonics for
10 87T.K_Hm3_Inrush 0.050~0.800 - 0.200
inrush current detection
Coefficient of third or fifth harmonic
11 87T.K_Hm3/Hm5_OvExc 0.050~0.800 - 0.250 for overexcitation detection
The recommended value is 0.25.
Enabled, Logic setting for enabling/disabling
12 87T.En_Inst - Disabled
Disabled instantaneous differential element
Logic setting for enabling/disabling
Enabled,
13 87T.En_Biased - Disabled conventional biased differential
Disabled
element
Enabled, Logic setting for enabling/disabling
14 87T.En_DPFC - Disabled
Disabled DPFC biased differential element
Option of inrush current
WaveSym discrimination principle:
15 87T.Opt_Inrush_Ident - Hm2
Hm2 WaveSym: waveform symmetry
Hm2: second harmonic principle
Option of inrush blocking mode
Adaptive: self-adaptive one-phase
inrush blocking one-phase
differential element
Adaptive,
2PBlk3P: two-phase inrush
16 87T.Opt_BlkMode_Inrush 2PBlk3P, - Adaptive
blocking three-phase differential
1PBlk3P
element
1PBlk3P: one-phase inrush
blocking three-phase differential
element
Logic setting for enabling/disabling
Enabled,
17 87T.En_Hm3_Blk - Enabled the third harmonic blocking for
Disabled
inrush current
Option of third or fifth harmonic for
18 87T.Opt_Hm3/Hm5_OvExc Hm3, Hm5 - Hm5
overexcitation criterion

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No. Name Range Unit Default Description


Hm3: third harmonic
Hm5: fifth harmonic
Logic setting for enabling/disabling
Enabled,
19 87T.En_CTS_Blk - Enabled blocking biased differential element
Disabled
during CT circuit failure

3.7 Restricted Earth Fault Protection (64REF)

Restricted earth fault protection (REF) is meant to protect a single winding of a power transformer,
and the protected winding must be earthed. In the case of delta windings, the winding must be 3
earthed by an earthing transformer, which must be electrically placed between the winding and
the current transformers. REF can be applied to protection of two-winding transformer,
three-winding transformer, auto-transformer and shut reactor.

REF is a kind of differential protection, so it calculates differential current and restrained current.
The differential current is a vector difference of the neutral current (i.e., current flowing in the
neutral conductor) and the residual current from the lines. For internal faults, this difference is
equal to the total earth fault current. REF operates on the fault current only, and is not dependent
on eventual load currents. This makes REF a very sensitive protection.

3.7.1 Function Description

3.7.1.1 Overview

The difference between current differential protection and REF is that the first one is based on
adjusted phase current balance and the latter is based on balance of calculated residual current
and residual current from neutral CT.

Each side of transformer can be equipped with one set of REF, i.e., for a three-winding
transformer, up to three groups of REF can be equipped. REF is not affected by inrush current
and the tap of transformer. CT transient detection function based on the ratio of residual current to
positive current is adopted to eliminate the influence of difference of transient characteristic to
REF.
*

HV side I_H LV side


* *

3I0Cal '_H

Magnitude compensation

REF at HV side I_HNP


I'_HNP
*

Figure 3.7-1 Application for two-winding transformer with one CB at one side

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HV side 1

* * *

I_H1
LV side

I_H2
3I0Cal'_H1 * * *

3I0Cal'_H2
HV side 2

Magnitude
compensation
REF at HV side
Magnitude
compensation
3 Magnitude
I_HNP
compensation *
I'_HNP

Figure 3.7-2 Application for two-winding transformer with two CBs at one side

HV side
* * *
I_H

3I0Cal'_H I_M
*

MV side CW side
*
*

3I0Cal'_M

I_CW
Magnitude
LV side

compensation *
REF at HV side
Magnitude
compensation

I'_CW
Magnitude
compensation

Figure 3.7-3 Application for auto-transformer

The protection function can be provided with up to 4 sets of three-phase current inputs and 1
neutral point current input, and in auto-transformer applications, it can be provided with up to 2
sets of three phases current inputs for high voltage and middle voltage sides respectively.

Before some side REF is put into service on site, polarity of neutral point
CT must have been checked by a primary current injection test. Otherwise
an undesired operation may occur during an external earth fault.

3.7.1.2 Fault Detector

REF's pickup criterion is:

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3I0d>[x.64REF.I_Biased] Equation 3.7-1

Where:

3I0d is the residual differential current of some side.

3.7.1.3 Amplitude Compensation

If CTs used for REF have different primary rated values, the device will automatically adjust the
currents with respective correction ratio shown as below.

Klph 
I1n
 Klb / I 2 n and K lb  min(
I1n _ max
,4) Equation 3.7-2
3
I1n _ max I1n _ min

Where:

K1ph is the correction coefficient of the calculated side.

I1n is CT primary rated value at calculated side.

I2n is CT second rated value at calculated side.

I1n_min is minimum primary rated value among all CTs for REF.

I1n_max is maximum primary rated value among all CTs for REF.

This calculation method is to take the minimum CT primary rated value of all calculated sides as
the reference side. If the multiple of maximum CT primary rated value to minimum CT primary
rated value is greater than 4, then reference side shall be taken as 4 and other sides shall be
calculated proportionally. Otherwise, the reference side shall be taken as 1, and other sides will be
calculated proportionally.

The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (K1ph).

When selecting CT, the primary currents for each side muse follow the
I1n _ max
criterion:  128 , it is recommended that the ratio is smaller than 16.
I1n _ min
Theoretically, the ratio is preferred to be as small as it can be.

3.7.1.4 Calculation of Differential and Restraint Currents

The equation of calculating residual differential current is:

3𝐼0𝑑 = 𝐾𝑙𝑝ℎ1 × 3𝐼01 + 𝐾𝑙𝑝ℎ2 × 3𝐼02 + 𝐾𝑙𝑝ℎ3 × 3𝐼03 + 𝐾𝑙𝑝ℎ4 × 3𝐼04 + 𝐾𝑙𝑝ℎ𝑁𝑃 × 𝐼𝑁𝑃

The above equation can be simplified to the following:

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3𝐼0𝑑 = 3𝐼′01 + 3𝐼′02 + 3𝐼′03 + 3𝐼′04 + 𝐼′𝑁𝑃 Equation 3.7-3

Where:

3I0d is the residual differential current.

3I01, 3I02, 3I03, 3I04 are secondary values of calculated residual current at each side.

INP is secondary current at neutral point.

3I'01, 3I'02, 3I'03, 3I'04 are secondary values of corrected calculated residual current at each side.

3 I'NP is the secondary corrected current at neutral point.

K1ph1, K1ph2, K1ph3, K1ph4 are corrected coefficients of amplitude compensation at each side.

K1phNP is corrected coefficient of amplitude compensation at neutral point.

The equation of calculating residual restraint current is:


′ ′ ′ ′ ′
3𝐼0𝑟 = 𝑀𝑎𝑥(3𝐼01 , 3𝐼02 , 3𝐼03 , 3𝐼04 , 𝐼𝑁𝑃 ) Equation 3.7-4

Where:

3𝐼0𝑟 is the residual restraint current.

Ia
*

A
Ib
*

B
Ic
*

I_NP
*

3I0Cal' =I'c+I'b+I'a

I'_NP REF

Figure 3.7-4 REF principle

1. Through-flowing current under undisturbed conditions or external fault:

I'_NP flows into the protected zone from ground, 3I0Cal' leaves the protected zone, i.e. I'_NP
is negative according to the definition of signs in above figure, therefore I'_NP= -3I0Cal'.

3I0d= |3I0Cal'+ I'_NP|= |3I0Cal'–3I0Cal'|= 0

3I0r= Max(|3I0Cal'|, |I'_NP|)= |3I0Cal'|

It indicates there is no differential current in the case, and the restraint current corresponds to
the through-flowing current, hence, REF does not operate.

2. Internal short-circuit:

Assume that I'_NP= 3I0Cal'

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3I0d= |3I0Cal'+ I'_NP|= 2x|3I0Cal'|

3I0r= Max(|3I0Cal'|, |I'_NP)= |3I0Cal'|

It indicates the differential current are two times of restraint current in internal short-fault,
hence, REF operates.

3.7.1.5 Operation Criterion

The operation criteria of REF protection are as follows:

3𝐼0𝑑 > [𝑥. 64𝑅𝐸𝐹. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] (3𝐼0𝑟 ≤ [𝑥. 64𝑅𝐸𝐹. 𝐼_𝐾𝑛𝑒𝑒])

3𝐼0𝑑 > [𝑥. 64𝑅𝐸𝐹. 𝑆𝑙𝑜𝑝𝑒] × (3𝐼0𝑟 − [𝑥. 64𝑅𝐸𝐹. 𝐼_𝐾𝑛𝑒𝑒]) + [𝑥. 64𝑅𝐸𝐹. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑]
3
Equation 3.7-5
3𝐼0𝑑 = |3𝐼 ̇01 + 3𝐼 ̇02 + 3𝐼 ̇03 + 3𝐼 ̇04 + 𝐼 ̇NP|

3𝐼0𝑟 = Max(|3𝐼̇ 01|, |3𝐼 ̇02|, |3𝐼 ̇03|, |3𝐼 ̇04|, |𝐼 ̇NP|)

Where:

3𝐼0𝑑 and 3𝐼0𝑟 are respectively the differential current and the restraint current at side x of
transformer.

3𝐼̇ 01, 3𝐼̇ 02, 3𝐼 ̇03 and 3𝐼 ̇04 are the calculated residual currents at side x of transformer.

𝐼 ̇NP is the residual current from neutral point CT at side x of transformer.

3.7.1.6 Operation Characteristic


Differential current

K=m

[x.64REF.Slope]

[x.64REF.I_Biased]
Restraint current

[x.64REF.I_Knee]

Figure 3.7-5 Operation characteristic of REF

The value of m is defined by the branch number for REF calculation. For example, there are two
branches at HV side (wye winding with neutral point earthed), so there are three branches

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constitute REF of HV side and m is equal to 3.

3.7.1.7 Direction Criterion

In order to ensure the selectivity of restricted earth fault protection, direction criterion is also
available. The setting [x.64REF.En_Dir_Blk] is used to enable/disable the function of direction
criterion blocking REF. The direction criterion is based on the different direction characteristic of
neutral-point current I_NP and calculated residual current 3I0Cal at an external earth fault and an
internal earth fault.

For an external earth fault, the neutral-point current I_NP and the calculated residual current

3 3I0Cal have equal magnitude, but they are of approximately opposite directions.

For external fault

3I0Cal
ROA (Relay Operate Angle)

I_NP

ROA

Figure 3.7-6 Currents at an external earth fault

For an internal earth fault, the magnitudes of the two currents I_NP and 3I0Cal may be different,
but their relative directions are within a certain angle range. The operation angle setting
[x.64REF.ROA] is equipped in the device, it will be judged as an internal earth fault and the
direction criterion will be released when the relative angle of the two currents is lower than the
setting.

For internal fault

ROA
3I0Cal

I_NP

ROA

Figure 3.7-7 Currents at an internal earth fault

Or when I_NP>K×3I0Cal (K is an internal setting), it will also be judged as an internal earth fault
and the direction criterion will be released.

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3.7.1.8 CT Transient Characteristic Difference Detection

Non-identical CT characteristics can cause unbalance current. During phase-to-phase faults and
three-phase faults, the unbalance of three-phase CTs results in residual current which may lead to
maloperation of REF. Therefore, positive-sequence current restraint blocking criterion is adopted
to prevent REF from maloperation in above mentioned conditions.

When the residual current of REF at each side is greater than 0 times positive-sequence current,
it is decided that zero-sequence current is caused by a fault and release REF. Positive-sequence
current restraint blocking criterion is showed below. This blocking criterion is ignored when neutral
point current is greater than the internal setting, whichever is greater.
3
3I0>β0×I1 Equation 3.7-6

Where:

3I0 is the zero-sequence current at a side.

I1 is its corresponding positive-sequence current.

β0 is a proportional constant and the value is 0.6

3.7.1.9 CT Saturation Detection

CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid maloperation
of REF during an external fault. Please refer to Section 3.6.1.10 for details.

The criterions of CT saturation detection in 64REF are as shown in Equation 3.7-7. If any one of
the criterions is met, it will be considered that it is CT saturation to cause this differential current
and restricted earth fault protection will be blocked.

𝐼∅_2𝑛𝑑 > 𝐾2𝑛𝑑 × 𝐼∅_1𝑠𝑡

3𝐼0𝐶𝑎𝑙2𝑛𝑑 > 𝐾2𝑛𝑑 × 3𝐼0𝐶𝑎𝑙1𝑠𝑡


Equation 3.7-7
𝐼∅_3𝑟𝑑 > 𝐾3𝑟𝑑 × 𝐼∅_1𝑠𝑡

3𝐼0𝐶𝑎𝑙3𝑟𝑑 > 𝐾3𝑟𝑑 × 3𝐼0𝐶𝑎𝑙1𝑠𝑡

Where:

𝐼∅_1𝑠𝑡 is the fundamental component of one phase current, it won’t do CT saturation detection
unless the fundamental component is higher than the corresponding internal setting.

3𝐼0𝐶𝑎𝑙1𝑠𝑡 is the fundamental component of calculated residual current, it won’t do CT saturation


detection unless this fundamental component is higher than the corresponding internal setting.

𝐼∅_2𝑛𝑑 is the secondary harmonic of the same phase current.

3𝐼0𝐶𝑎𝑙2𝑛𝑑 is the secondary harmonic of calculated residual current.

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𝐼∅_3𝑟𝑑 is the third harmonic of the same phase current.

3𝐼0𝐶𝑎𝑙3𝑟𝑑 is the third harmonic of calculated residual current.

𝐾2𝑛𝑑 and 𝐾3𝑟𝑑 are fixed coefficients of secondary and third harmonics respectively.

3.7.1.10 CT Circuit Supervision

CT circuit supervision for REF is divided into two kinds: differential CT circuit abnormality without
the pickup of the fault detector and differential CT circuit failure with the pickup of the fault
detector.

3  CT Circuit Abnormality

If the following operation formula is met for 10s, CT circuit abnormality alarm of REF will be issued
without blocking the protection.

The operation formula is as follows:

3I0d>max(0.1×3I0r, [x.64REF.I_Alm]) Equation 3.7-8

 CT Circuit Failure

Please refer to Section 3.6.1.12 for details.

3.7.2 Function Block Diagram

64REF

x.64REF.in_I3P1 x.64REF.3I0d

x.64REF.in_I3P2 x.64REF.3I0r

x.64REF.in_I3P3 x.64REF.I0_Th

x.64REF.in_I3P4 x.64REF.St

x.64REF.in_I1P x.64REF.Op

x.64REF.Enable x.64REF.On

x.64REF.Block x.64REF.Blocked

x.64REF.Valid

x.64REF.Alm_Diff

x.64REF.Alm_CTS

3.7.3 I/O Signals


Table 3.7-1 Input signals of restricted earth-fault protection

No. Input signal Description


1 x.64REF.in_I3P1 Three-phase current data input 1 for REF protection at x side of transformer.

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No. Input signal Description


2 x.64REF.in_I3P2 Three-phase current data input 2 for REF protection at x side of transformer.
3 x.64REF.in_I3P3 Three-phase current data input 3 for REF protection at x side of transformer.
4 x.64REF.in_I3P4 Three-phase current data input 4 for REF protection at x side of transformer.
5 x.64REF.in_I1P Residual current data input for REF protection at x side of transformer.
Input signal of enabling REF protection at x side of transformer. It is triggered from
6 x.64REF.Enable
binary input or programmable logic etc.
Input signal of blocking REF protection at x side of transformer. It is triggered from
7 x.64REF.Block
binary input or programmable logic etc.

Table 3.7-2 Output signals of restricted earth-fault protection


3
No. Output signal Description
1 x.64REF.3I0d Residual differential current of REF protection at x side of transformer.
2 x.64REF.3I0r Residual restraint current of REF protection at x side of transformer.
3 x.64REF.3I0_Th Threshold of residual restraint current of REF protection at x side of transformer.
4 x.64REF.St REF protection at x side of transformer starts.
5 x.64REF.Op REF protection at x side of transformer operates.
6 x.64REF.On REF protection at x side of transformer is enabled.
7 x.64REF.Blocked REF protection at x side of transformer is blocked.
8 x.64REF.Valid REF protection at x side of transformer is valid.
9 x.64REF.Alm_Diff Differential current of REF protection at x side of transformer is abnormal.
10 x.64REF.Alm_CTS CT secondary circuit of REF at x side of transformer is abnormal.

3.7.4 Logic

EN [x.64REF.En] &
x.64REF.On
SIG x.64REF.Enable
&
SIG x.64REF.Block >=1 x.64REF.Blocked

SIG Fail_Device
&
x.64REF.Valid

Figure 3.7-8 Logic of enabling restricted earth fault protection

SET 3I0d>[x.64REF.I_Biased] &


0 500ms &
x.64REF.Pkp
SIG x.64REF.On
FD.Pkp
SIG x.64REF.Valid

Figure 3.7-9 Pickup logic of restricted earth fault protection

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3 Protection Functions

SIG Flag_x.64REF &

SIG 3I0>β0×I1
&
SIG CT saturation

SIG CT circuit failure &

EN [x.64REF.En_CTS_Blk] x.64REF.St

SIG x.3I0Ext>[x.64REF.I_NP_OnLoad] >=1 &


[x.64REF.t_Op] 0ms x.64REF.Op
EN [x.64REF.En_NPCurr]
3 SIG x.64REF.Dir_op >=1

EN x.64REF.En_Dir_Blk

SIG x.64REF.Pkp

Figure 3.7-10 Logic diagram of restricted earth fault protection

Where:

“Flag_x.64REF” means that operation criterion of REF at side x is satisfied.

x.3I0Ext is the measured residual current at side x.

3.7.5 Settings
Table 3.7-3 Settings of restricted earth fault protection

No. Name Range Unit Default Description


1 x.64REF.I_Biased 0.050~5.000 In 0.500 Pickup setting of REF
2 x.64REF.I_Alm 0.050~1.500 In 0.200 Current setting of REF abnormality alarm
Knee point setting of REF
3 x.64REF.I_Knee 0.100~4.000 In 0.500
0.5In is recommended.
Percentage restraint coefficient of REF
4 x.64REF.Slope 0.200~0.750 - 0.500
0.5 is recommended.
5 x.64REF.ROA 45.000~90.000 deg 60.000 Operation angle setting
Current setting of neutral-point on-load
6 x.64REF.I_NP_OnLoad 0.040~40.000 A 0.200
criterion.
Time delay for REF
7 x.64REF.t_Op 0.000~20.000 s 0.000
Recommended value is zero.
Enabled, Logic setting for enabling/disabling
8 x.64REF.En - Disabled
Disabled REF
Enabled, Logic setting for enabling/disabling
9 x.64REF.En_NPCurr - Disabled
Disabled neutral current criterion
Enabled, Logic setting for enabling/disabling
10 x.64REF.En_CTS_Blk - Enabled
Disabled blocking REF during CT circuit failure

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No. Name Range Unit Default Description


Logic setting for enabling/disabling the
Enabled,
11 x.64REF.En_Dir_Blk - Disabled function of direction criterion blocking
Disabled
REF

3.8 Winding Differential Protection (87W)

The winding differential protection can be used in auto-transformer when each side and common
winding are equipped with three phases current inputs. Winding differential protection is based on
Kirchhoff's law, so inrush current has no effect on it. Winding differential protection consists of
phase winding differential protection and residual winding differential protection. Residual winding 3
differential protection adopts the calculated residual current of each side and common winding for
the protection calculation and three phases CT polarity is easy to be checked. The operation
principle of which is similar to that of REF, but compared to REF, winding differential protection
can operate not only during internal earth faults but also during phase-to-phase faults. The
protection can be provided with up to 5 sets of three phases current inputs.

3.8.1 Function Description

3.8.1.1 Overview

Winding differential protection is based on Kirchhoff's first law and calculates differential currents
of electrical connection circuits including phase A, phase B phase C and residual differential
currents. Inrush current and tap change of the transformer have no effect on winding differential
protection. Winding differential protection has high sensitivity to internal earth faults because there
is no load current in the restraint current. Normally, winding differential protection is applied in
following two situations.
HV side

* * *
I_H

I_M
I'_H
*

MV side
*

CW side
*

I'_M
I_CW
Magnitude
LV side

compensation Winding
* * *
differential
Magnitude protection
compensation

Magnitude I'_CW
compensation

Figure 3.8-1 Winding differential protection applied to auto-transformer

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3 Protection Functions

HV side 1
* * * I_Bush

*
I_H1
LV side

*
HV side

*
I_H2
* * *
I'_H1
I'_H2 HV side 2

Magnitude
compensation Winding differential
protection
Magnitude
3 compensation

Magnitude
compensation
I'_HBush

Figure 3.8-2 Winding differential protection applied to stub differential protection

Where:

I_HBush is primary current value of bushing CT at HV side

I'_HBush is secondary current value of bushing CT at HV side

When winding differential protection is used as stub differential protection,


CT polarity must be checked. If the circuit breaker CT polarity and the
transformer bushing CT polarity are both at busbar side, either of them
must be reversed via the tool PCS-Studio.

3.8.1.2 Fault Detector

The criterion of fault detector of winding differential protection is as follows.

Iwd>[87W.I_Biased] Equation 3.8-1

Where:

Iwd is winding differential current.

3.8.1.3 Amplitude Compensation

If CTs used by winding differential protection have differential primary rated value, then the current
compensation is carried out in the program automatically with parameters input. Following gives
the criteria of calculating correction coefficient.

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I1n
K wph   K wb / I 2n
I1n _ max
Equation 3.8-2
I1n _ max
K wb  min( ,4)
I1n _ min

Where:

Kwph is the correction coefficient of the calculated CT input.

I1n is the primary value of CT at calculated CT input.

I2n is the second value of CT at calculated CT input.


3
I1n_min is the minimum value among primary values of all CTs for winding differential protection.

I1n_max is the maximum value among primary values of all CTs for winding differential protection.

This calculation method is to take the minimum CT primary rating of all calculated CT inputs as
the reference. If the multiple of the maximum CT primary ratio to the minimum CT primary rating is
greater than 4, then reference shall be taken as 4 and others shall be calculated proportionally.
Otherwise, the reference shall be taken as 1, and others will be calculated proportionally.

The currents used in the following analysis have been corrected, which means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (Kwph).

When selecting CT, the primary currents for each side muse follow the
I1n _ max
criterion:  128 , it is recommended that the ratio is smaller than 16.
I1n _ min
Theoretically, the ratio is preferred to be as small as it can be.

3.8.1.4 Calculate Differential and Restraint Current

The differential current is as follows.

PCS-978S Transformer Relay 3-49


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3 Protection Functions

 I wdA   I A1   I A2   I A3 
I  I  I   
 wdB   K wph1   B1   K wph 2   B 2   K wph 3   I B 3  
 I wdC   I C1   IC 2   IC 3 
       
 I wd 0   I 01   I 02   I 03 
1 2 3
Equation 3.8-3
 I A4   I A5 
I  I 
K wph 4   B4 
 K wph 5  
 B5

 IC 4   IC 5 
   
 I 04   I 05 
3 4 5

The above equation can be simplified to the following:

I wdA  I A1  I A2  I A3  I A4  I A5


I wdB  I B 1  I B 2  I B 3  I B 4  I B 5
Equation 3.8-4
I wdC  I C 1  I C 2  I C 3  I C 4  I C 5
  I 02
I wd0  I 01   I 03   I 04  I 05 

The restraint current is:

I wrA  Max( I A1 , I A2 , I A3 , I A4 , I A5 )


I wrB  Max( I B 1 , I B 2 , I B 3 , I B 4 , I B 5 )
Equation 3.8-5
I wrC  Max( I C 1 , I C 2 , I C 3 , I C 4 , I C 5 )
 , I 02
I wr 0  Max( I 01  , I 03 , I 04 , I 05 )

Where:

I wdA , I wdB , I wdC , I wd0 are respectively three phase and residual winding differential currents.

I wrA , I wrB , I wrC , I wr0 are secondary values of three phase restraint currents and neutral

restraint current respectively.

I Am , I Bm , I Cm and I 0 m are respectively secondary values of three phase currents and calculated
neutral current of branch m (m=1, 2, 3, 4, 5).

I Am , I B m , I C m and I 0 m are respectively secondary values of corrected three phase currents

and calculated residual current of branch m (m=1, 2, 3, 4, 5).

Kwph1, Kwph2, Kwph3, Kwph4, Kwph5 are corrected coefficients of each side for magnitude
compensation respectively.

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3.8.1.5 Operation Criterion

The operation criteria of winding differential protection are as follows, and maximum 5 branches
are supported for the calculation.

𝐼𝑤𝑑 > [87𝑊. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] (𝐼𝑤𝑟 ≤ [87𝑊. 𝐼_𝐾𝑛𝑒𝑒])

𝐼𝑤𝑑 > [87𝑊. 𝑆𝑙𝑜𝑝𝑒] × (𝐼𝑤𝑟 − [87𝑊. 𝐼_𝐾𝑛𝑒𝑒]) + [87𝑊. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] (𝐼𝑤𝑟
> [87𝑊. 𝐼_𝐾𝑛𝑒𝑒]) Equation 3.8-6

𝐼𝑤𝑑 = |𝐼 ̇w1 + 𝐼 ̇w2 + 𝐼 ̇w3 + 𝐼 ̇w4 + 𝐼 ̇w5|

𝐼𝑤𝑟 = Max(|𝐼 ̇w1|, |𝐼 ̇w2|, |𝐼 ̇w3|, |𝐼 ̇w4|, |𝐼 ̇w5|) 3


Where:

|𝐼 ̇w1|, |𝐼 ̇w2|, |𝐼 ̇w3|, |𝐼 ̇w4| and |𝐼 ̇w5| are currents of five branches respectively.

𝐼𝑤𝑑 is winding differential current.

𝐼𝑤𝑟 is winding restraint current.

For protecting an autotransformer, a winding differential protection is


composed of three-phase currents of HV side, LV side and common
winding. When calculated residual currents of each branch are used for the
calculation, the winding differential protection (87W) becomes neutral
differential protection (87N) also called residual differential protection in the
following description.

3.8.1.6 Operation Characteristic


Differential current

K=m

[87W.Slope]

[87W.I_Biased]
Restraint current
[87W.I_Knee]

Figure 3.8-3 Operating characteristic of winding differential protection

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3 Protection Functions

The value of m is defined by the branch number for winding differential protection. For example,
winding differential protection is applied for protecting an autotransformer including HV side, MV
side and common winding and m is equal to 3.

3.8.1.7 CT Saturation Detection

In order to prevent winding differential protection from undesired operation caused by transient or
steady state saturation of CT during an external fault, the second and third harmonics of
secondary current of individual CTs are used for the device to discriminate saturation of
three-phase CT. If CT saturation is detected, winding differential protection will be blocked. The
criterions of CT saturation detection in 87W are as shown in Equation 3.8-7.
3
1
𝐼∅_2𝑛𝑑 > 𝐾2𝑛𝑑 × 𝐼∅_1𝑠𝑡 & 𝐼∅_𝑤𝑑 > [87𝑊. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑]
2

or Equation 3.8-7

1
𝐼∅_3𝑟𝑑 > 𝐾3𝑟𝑑 × 𝐼∅_1𝑠𝑡 & 𝐼∅_𝑤𝑑 > [87𝑊. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑]
2

Where:

𝐼∅_1𝑠𝑡 is the fundamental component of one phase current.

𝐼∅_2𝑛𝑑 is the secondary harmonic of the same phase current.

𝐼∅_3𝑟𝑑 is the third harmonic of the same phase current.

𝐾2𝑛𝑑 and 𝐾3𝑟𝑑 are fixed coefficients of secondary and third harmonics respectively.

If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and winding differential protection will be
blocked.

3.8.1.8 CT Circuit Supervision

 CT Circuit Abnormality

If the following operation formula is met for 10s, CT circuit abnormality alarm of winding differential
protection will be issued without blocking the protection.

The operation criterion is as follows:

Iwd>max(0.1×Iwr, [87W.I_Alm]) Equation 3.8-8

 CT Circuit Failure

Please refer to Section 3.6.1.12 for details.

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3.8.2 Function Block Diagram

87W

87W.in_I3P1 87W.Ida

87W.in_I3P2 87W.Idb

87W.in_I3P3 87W.Idc

87W.in_I3P4 .
87W.in_I3P5 .
87W.Enable . 3
87W.Block 87W.Alm_Diff

87W.Alm_CTS

3.8.3 I/O Signals


Table 3.8-1 Input signals of winding differential protection

No. Input signal Description


1 87W.in_I3P1 Three-phase current data input 1 for winding differential protection.
2 87W.in_I3P2 Three-phase current data input 2 for winding differential protection.
3 87W.in_I3P3 Three-phase current data input 3 for winding differential protection.
4 87W.in_I3P4 Three-phase current data input 4 for winding differential protection.
5 87W.in_I3P5 Three-phase current data input 5 for winding differential protection.
Input signal of enabling winding differential protection. It is triggered from binary input
6 87W.Enable
or programmable logic etc.
Input signal of blocking winding differential protection. It is triggered from binary input
7 87W.Block
or programmable logic etc.

Table 3.8-2 Output signals of winding differential protection

No. Output signal Description


1 87W.Ida Phase-A differential current of winding differential protection.
2 87W.Idb Phase-B differential current of winding differential protection.
3 87W.Idc Phase-C differential current of winding differential protection.
4 87W.3I0d Residual differential current of winding differential protection.
5 87W.Ira Phase-A restraint current of winding differential protection.
6 87W.Irb Phase-B restraint current of winding differential protection.
7 87W.Irc Phase-C restraint current of winding differential protection.
8 87W.3I0r Residual restraint current of winding differential protection.
9 87W.Ia_Th Threshold of phase-A restraint current of winding differential protection.
10 87W.Ib_Th Threshold of phase-B restraint current of winding differential protection.
11 87W.Ic_Th Threshold of phase-C restraint current of winding differential protection.

PCS-978S Transformer Relay 3-53


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3 Protection Functions

No. Output signal Description


12 87W.3I0_Th Threshold of residual restraint current of winding differential protection.
13 87W.St Winding differential protection starts.
14 87W.St_PhSeg Phase-segregated winding differential protection starts.
15 87W.St_REF Restricted earth-fault element of winding differential protection starts.
16 87W.St_PhSeg_A Phase-A winding differential protection starts.
17 87W.St_PhSeg_B Phase-B winding differential protection starts.
18 87W.St_PhSeg_C Phase-C winding differential protection starts.
19 87W.Op Winding differential protection operates.
20 87W.Op_PhSeg Phase-segregated winding differential protection operates.
3 21 87W.Op_PhSeg_A Phase-A winding differential protection operates.
22 87W.Op_PhSeg_B Phase-B winding differential protection operates.
23 87W.Op_PhSeg_C Phase-C winding differential protection operates.
24 87W.Op_REF Restricted earth-fault element of winding differential protection operates.
25 87W.On_PhSeg Phase-segregated winding differential protection is enabled.
26 87W.On_REF Restricted earth-fault element of winding differential protection is enabled.
27 87W.Blocked_PhSeg Phase-segregated winding differential protection is blocked.
28 87W.Blocked_REF Restricted earth-fault element of winding differential protection is blocked.
29 87W.Valid_PhSeg Phase-segregated winding differential protection is valid.
30 87W.Valid_REF Restricted earth-fault element of winding differential protection is valid.
31 87W.Alm_Diff Differential current of winding differential protection is abnormal.
32 87W.Alm_CTS CT secondary circuit of winding differential protection is abnormal.

3.8.4 Logic

EN [87W.En_PhSeg] &
87W.On_PhSeg
SIG 87W.Enable
&
SIG 87W.Block >=1 87W.Blocked_PhSeg

SIG Fail_Device
&
87W.Valid_PhSeg

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EN [87T.En_REF] &
87W.On_REF
SIG 87W.Enable
&
SIG 87W.Block >=1 87W.Blocked_REF

SIG Fail_Device
&
87W.Valid_REF

Figure 3.8-4 Logic of enabling winding differential protection 3


SET Iwd>[87W.I_Biased] &
0 500ms 87W.Pkp_PhSeg
FD.Pkp
SIG 87W.Valid_PhSeg

SET 3I0d>[87W.I_Biased] &


0 500ms 87W.Pkp_REF
FD.Pkp
SIG 87W.Valid_REF

Figure 3.8-5 Pickup logic of transformer differential protection

SIG 87W.Flag_DIFF
& &
SIG CT Staturation [87W.t_Op] 0ms 87W.Op_PhSeg

SIG CT circuit failure &

EN [87W.En_CTS_Blk]

SIG 87W.Pkp_PhSeg

SIG 3I0>β0×I1 &

SIG 87W.Flag_DIFF
& &
SIG CT Staturation [87W.t_Op] 0ms 87W.Op_REF

SIG CT circuit failure &

EN [87W.En_CTS_Blk]

SIG 87W.Pkp_REF

Figure 3.8-6 Logic diagram of winding differential protection

Where:

“87W.Flag_DIFF” means that the operation criterion of winding differential protection is satisfied.

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3 Protection Functions

3.8.5 Settings
Table 3.8-3 Settings of winding differential protection

No. Name Range Unit Default Description


Pickup setting of biased winding differential
1 87W.I_Biased 0.100~5.000 In 0.500
protection
Current setting of winding differential protection
2 87W.I_Alm 0.050~1.500 In 0.200
abnormality alarm
Knee point setting of biased winding
3 87W.I_Knee 0.100~4.000 In 0.500
differential protection.

3 4 87W.Slope 0.100~0.900 - 0.500


Percentage restraint coefficient of biased
winding differential protection
5 87W.t_Op 0.000~20.000 s 0.000 Time delay for winding differential protection
Logic setting for enabling/disabling
Enabled,
6 87W.En_PhSeg - Disabled phase-segregated winding differential
Disabled
protection
Enabled, Logic setting for enabling/disabling residual
7 87W.En_REF - Disabled
Disabled winding differential protection
Logic setting for enabling/disabling blocking
Enabled,
8 87W.En_CTS_Blk - Enabled winding differential protection during CT circuit
Disabled
failure

3.9 Reactor Current Differential Protection (87R)

If an earth fault or phase-to-phase fault of reactor occurs, current differential protection can
operate quickly to clear the fault to avoid the reactor from damages or reduce the maintenance
cost as low as possible. Different to transformer current differential protection based on
electromagnetic balance, reactor current differential protection is based on Kirchhoff's law, so it is
needed to develop current differential protection according to the actual application of reactor not
only to use transformer current differential protection to protect reactors.

In the section, the suffix ”#” (# =1, 2, 3) in some measurements and


calculated quantities refers to the side (& branch) of the reactor, the suffix
“1” means the branch 1 of high-voltage side (head-end) of reactor, “2”
means the low-voltage side (tail-end) of reactor, “3” means the branch 2 of
high-voltage side (head-end) of reactor.

3.9.1 Function Description

Reactor current differential protection consists of biased differential element, instantaneous


differential element, DPFC biased differential element and zero-sequence differential element.
Biased differential element is two-slope differential element with biased characteristic.

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Unrestrained differential element is to accelerate the operating speed for reactor's severe internal
faults without biased characteristic and blocking elements. DPFC biased differential element
calculated by current variation has high sensitivity to earth faults at ground end of reactor.
Zero-sequence differential element based on calculated residual current of two sides of reactor
has high sensitivity to asymmetric fault. Above four differential protection elements work
coordinately to form the high-speed current differential protection with high sensitivity.

3.9.1.1 Fault Detector

1. Fault detector based on biased differential current

Its operation equation is as follows.


3
Id>[87R.I_Biased] Equation 3.9-1

Where:

Id is the differential current of any phase.

2. Fault detector based on instantaneous differential current

Its operation equation is as follows.

Id>0.9x[87R.I_Inst] Equation 3.9-2

Where:

Id is the differential current of any phase.

3. Fault detector based on DPFC differential current

Its operation equation is as follows.

∆𝐼𝑑 > 1.25 × ∆𝐼𝑑𝑡 + 𝐼𝑑𝑡ℎ


Equation 3.9-3
∆𝐼𝑑 = ⌈∆𝐼1̇ + ∆𝐼2̇ + ∆𝐼3̇ ⌉

Where:

∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and
hence the element maintains stability.

∆𝐼#̇ is DPFC current. (# =1, 2, 3)

∆𝐼𝑑 is DPFC differential current.

𝐼𝑑𝑡ℎ is the fixed threshold internally.

This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC

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biased differential protection. The setting is fixed and thus site setting is not required.

4. Fault detector of residual differential current

It includes biased characteristic and instantaneous characteristic, and its operation equation is as
follows.

3I0d>[87R.I_Biased]
Equation 3.9-4
3I0d>[87R.I_Inst]

Where:
3 3I0d is residual differential current.

3.9.1.2 Amplitude Compensation

Under normal condition, the magnitudes of secondary current of both ends of reactor are different
due to the mismatch between CT ratios. The current value difference shall be eliminated before
calculation for current differential protection by amplitude compensation.

1. Calculate rated primary current at each side

𝑆𝑛
𝐼1𝑏 = ⁄ Equation 3.9-5
√3𝑈𝑛

Where:

𝑆𝑛 is the rated capacity of reactor (i.e., the setting [Sn] in “System Settings” menu).

𝑈𝑛 is rated voltage of reactor. (i.e., the setting [U1n] in “System Settings” menu).

𝐼1𝑏 is the reference primary current of reactor.

2. Calculate rated secondary current at each side

𝐼2𝑏# = 𝐼1𝑏 ⁄𝐶𝑇# Equation 3.9-6

Where:

𝐼2𝑏# is rated secondary current of reactor. (# =1, 2, 3)

𝐶𝑇# is 𝐶𝑇# ratio. (# =1, 2, 3)

3. Correction coefficients

 For single branch application

Kph2=1

Kph1=(I1n_CT1)/(I1n_CT2) Equation 3.9-7

Kph1≤8

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 For double branches application

Kph2=1

Kph1=(I1n_CT1)/(I1n_CT2)

Kph3=(I1n_CT3)/(I1n_CT2) Equation 3.9-8

Kph1≤8

Kph3≤8

Where:
3
I1n_CT# is the primary current of CT#. (# =1, 2, 3)

Kph# is the correction coefficient of CT#. (# =1, 2, 3)

Low-voltage side of the reactor is taken as reference side, so the correction coefficient of
low-voltage side is 1 and that of high-voltage side is equal to the ratio of primary current of CT1 to
primary current of CT2. The maximum ratio of two sides is 8. If the ratio is out of the limit, the
device will be blocked and corresponding alarm messages are issued.

When viewing settings and values of current differential protection in the device, the unit “p.u.”
(per unit value) can be found. The current in differential protection calculation is not actual
secondary value but per unit value which is got by actual secondary value of each side of reactor
divided by reactor secondary rated current of each branch (i.e., I 2b1, I2b2).

3.9.1.3 Calculations of Differential and Restraint Currents

1. Differential current

 I dA   I A1  I A2   I A3 
I     / I    / I    / I
 dB   I B1 2b1  I B 2  2b 2  I B 3  2b3 Equation 3.9-9
 I dC   I C1  I C 2  I C 3
     
1 2 3

The above equation can be simplified to the following:

 I dA  I  A1  I  A2  I  A3

 I dB  I B1  I B 2  I B 3 Equation 3.9-10
      
 I dC I C1 I C 2 I C 3

Where:

𝐼𝑑𝐴 , 𝐼𝑑𝐵 , 𝐼𝑑𝐶 are differential currents.

𝐼2𝑏# is the CT rated secondary value. (# =1, 2, 3)

𝐼𝐴# , 𝐼𝐵# , 𝐼𝐶# are the equation vectors, the secondary current of CT#. (# =1, 2, 3)

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′ ′ ′
𝐼𝐴# , 𝐼𝐵# , 𝐼𝐶# are the corrected secondary current. (# =1, 2, 3)

2. Restraint current

1) For single branch application

𝐼𝑟𝐴 = |𝐼′̇𝐴2 |
{𝐼𝑟𝐵 = |𝐼′̇𝐵2 | Equation 3.9-11
𝐼𝑟𝐶 = |𝐼′̇𝐶2 |

3 2) For double branches application

1 ′
𝐼𝑟𝐴 = (|𝐼 ̇ 𝐴1 | + |𝐼 ′̇ 𝐴2 | + |𝐼 ′̇ 𝐴3 |)
2
1
𝐼𝑟𝐵 = (|𝐼 ′̇ 𝐵1 | + |𝐼 ′̇ 𝐵2 | + |𝐼 ′̇ 𝐵3 |) Equation 3.9-12
2
1
{ 𝐼𝑟𝐶 = (|𝐼 ′̇ 𝐶1 | + |𝐼 ′̇ 𝐶2 | + |𝐼 ′̇ 𝐶3 |)
2

Where:

𝐼𝑟𝐴 , 𝐼𝑟𝐵 , 𝐼𝑟𝐶 are restraint currents.

Current compensation process is shown in the flowing figure. In an ideal situation, the differential
current should be zero during normal operation of reactor or an external fault.

 For single branch application


*
*

Ip1 Ip2
HV side CT1 CT2 LV side
*
* *

I1 I2

PCS-978S

Magnitude compensation (÷I2b1) Magnitude compensation (÷I2b2)

I'1 I'2

Calculate differential current and restraint current

Figure 3.9-1 Current compensation calculation process

 For double branches application

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*
Ip1
CT1

*
*
HV side I1

*
Ip3 * Ip2
CT3 CT2 LV side

*
*
*

*
I3 I2

PCS-978S

3
Magnitude compensation Magnitude compensation Magnitude compensation
(÷I2b3) (÷ I2b1) (÷I2b2)

I'3 I'1 I'2

Calculate differential current and restraint current

Figure 3.9-2 Current compensation calculation process

 For double branches application with pumping reactor

CT5
CT1
*

IP1
*
*

HV side I1
CT4
Three phases
*
*

IP3 Single phase IP2 LV side


CT3 CT2
*
*
*

I3 I2

PCS-978S

Magnitude compensation Magnitude compensation Magnitude compensation


(÷ I2b3) (÷I2b1) (÷I2b2)

I'3 I'1 I'2

Calculate differential current and restraint current

Figure 3.9-3 Current compensation calculation process

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3 Protection Functions

The symbol “*” represents the polarity of CT. If current flowing into the
polarity of CT, the current direction is defined as positive direction.

Where:

“Ip#” is the primary current.

“I#” is the secondary current.

“I'#” is the corrected secondary current.


3 To clarify the situation, two important operation conditions with ideal and matched measurement
quantities are considered. Taking single branch application as an example:

1. Through-flowing current under undisturbed conditions or external fault:

𝐼1′ flows into the protected zone, 𝐼2′ leaves the protected zone, i.e. is negative according to
the definition of signs in above figure, therefore 𝐼1′ = −𝐼2′ .

Moreover |𝐼1′ | = |𝐼2′ |

𝐼𝑑 = |𝐼1′ + 𝐼2′ | = 0

𝐼𝑟 = |𝐼1′ | = |𝐼2′ |

No differential current (𝐼𝑑 =0), restraint current (𝐼𝑟 ) corresponds to double the through-flowing
current, and current differential protection does not operate.

2. Internal short-circuit,|𝐼1′ | > |𝐼2′ |

1
The following applies 𝐼2′ = 2 𝐼1′

1
𝐼𝑑 = |𝐼1′ + 𝐼2′ | = |𝐼1′ + 𝐼1′ | = 1.5|𝐼1′ |
2

𝐼𝑟 = |𝐼2′ | = 0.5|𝐼1′ |

Differential current (𝐼𝑑 ) are three times of restraint current (𝐼𝑟 ) and corresponding to the total
fault, and current differential protection operates.

3.9.1.4 Biased Differential Element

Biased differential element with initial restraint slope consists of sensitive and conventional
differential elements as well as independent CT saturation criterion and harmonic blocking.

1. Sensitive biased differential element

The currents used in this section analysis and the following analysis have been corrected,
that means the currents for following calculation are the products of the actual secondary
current of each side multiplying its own correction coefficient.

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The sensitive biased differential element with low pickup setting and restraint slope is much
more sensitive for a slight internal fault. Three blocking elements, CT saturation, inrush
current, CT circuit failure (optional) have also been included in order to prevent it from
unwanted operation during an external fault.

 For single branch application

𝐼𝑑 > [87𝑅. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] (𝐼𝑟 ≤ 𝐾𝑃)

𝐼𝑑 > [87𝑅. 𝑆𝑙𝑜𝑝𝑒] × 𝐼𝑟 (𝐼𝑟 > 𝐾𝑃)

2 Equation 3.9-13
𝐼𝑑 = |∑ 𝐼𝑖̇ | 3
𝑖=1

𝐼𝑟 = |𝐼2̇ |

 For double branches application

𝐼𝑑 > [87𝑅. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] (𝐼𝑟 ≤ 𝐾𝑃)

𝐼𝑑 > [87𝑅. 𝑆𝑙𝑜𝑝𝑒] × 𝐼𝑟 (𝐼𝑟 > 𝐾𝑃)

𝐼𝑑 = |∑ 𝐼𝑖̇ | Equation 3.9-14


𝑖=1

3
1
𝐼𝑟 = ∑|𝐼𝑖̇ |
2
𝑖=1

Where:

𝐼#̇ is the phase current at side # of reactor. (# =1, 2, 3)

𝐼𝑑 and 𝐼𝑟 are respectively the differential current and the restraint current.

𝐾𝑃 is knee point, and its value is determined by the settings [87R.I_Biased] and [87R.Slope].

In order to improve the sensitivity of differential protection, the LV-side current is taken as
restraint current. When an internal fault occurs, current partly flows into ground through the
short circuit point, so the LV-side current will decrease and therefore the sensitivity of
differential protection is improved. Operation characteristic of sensitive biased differential
element is shown below.

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Differential current

K
[87R.I_Inst]

l
tia
r en
ffe
di
ed
as
K=0.6 bi
t ive
si nt
en e
f s elem
e ao
ar
n
a tio
er [87R.Slope]

3 Op

1.2p.u.

[87R.I_Biased]
Restraint current

0 KP 0.8p.u.

Figure 3.9-4 Operation characteristic of sensitive biased differential element

2. Conventional biased differential element

Conventional biased differential element with higher setting and restraint coefficient
comparing with sensitive biased differential element, which is blocked only by an inrush
current detection. Conventional biased differential element provides fast operation for severe
internal faults. Operation criterion is:

𝐼𝑑 > 1.2𝑝. 𝑢. (𝐼𝑟 ≤ 0.8𝑝. 𝑢. )


Equation 3.9-15
𝐼𝑑 > 0.6 × (𝐼𝑟 − 0.8𝑝. 𝑢. ) + 1.2𝑝. 𝑢. (𝐼𝑟 > 0.8𝑝. 𝑢. )

Parameters of this protection have been fixed in the program and do not
need to be configured by user.

Operation characteristic of conventional biased differential element is shown below.

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Differential current
[87R.I_Inst]

t l
en na
m io
le nt
l e ve
ia n
nt co
re of
ffe a
di are
K=0.6

ed n
as i o
bi rat
pe
O
3
1.2p.u.

Restraint current

0 0.8p.u.

Figure 3.9-5 Operation characteristic of conventional biased differential element

3.9.1.5 Instantaneous Differential Element

Instantaneous differential element for reactor is to accelerate the operation speed for reactor's
internal fault. The element has no blocking element but to guard that the setting must be greater
than the maximum unbalanced current caused by inrush current. Instantaneous differential
element shall operate to clear the fault when any phase differential current is higher than its
setting. Operation criterion is:

Id>[87R.I_Inst] Equation 3.9-16

Where:

Id is the maximum value of three phase differential currents.

Operation characteristic of instantaneous differential element is shown below.

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Differential current
K

Operating area of
F instantaneous differential element

[87R.I_Inst]

t l
en na
K=0.6 l
ia

m io
nt

le nt
re

le e
ffe

ia nv
di

nt co
ed

re of
ias
eb

ffe a
di are
iv
sit nt

ed g
en e

as in
f s elem
3
bi rat
o
pe
e a
O ar
E g
in
at
er
Op
[87R.Slope]
D

1.2p.u.

[87R.I_Biased]
A Restraint current

0 KP 0.8p.u.

Figure 3.9-6 Operation characteristic of biased and Instantaneous differential element

Where:

The value of K is not more than 1.

A is the point shows normal operation of reactor.

D, E, and F are points show internal faults of reactor.

1. Sensitive biased differential element will send tripping signal monitored by criteria of CT
transient characteristic difference, and CT circuit failure (optional). It can ensure sensitivity
and avoid the unwanted operation when CT is saturated during an external fault or caused by
inrush current. Its operation area is the tint shadow area in the figure above.

When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the operation area of sensitive biased differential element.

2. Conventional biased differential element will send tripping signal without blocking criteria. It
eliminates the influence of transient and steady CT saturations during an external fault and
ensures reliable operation even if CT is in saturation condition during an internal fault by
means of its biased characteristic. Its operation area is the deeper shadow area in the figure
above.

When an internal fault occurs, differential current rises greatly and the operating point moves
to E in the operation area of conventional biased differential element.

3. Instantaneous differential element will send tripping signal without any blocking if differential
current of any phase reaches its setting. Its operation area is over the above two areas with

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the deepest dark shadow.

When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.

3.9.1.6 DPFC Biased Differential Element

DPFC biased differential element is regardless of load current and is sensitive to small internal
fault current within the reactor. Its performance against CT saturation is also good. Lab tests show
that it is more sensitive than biased differential element under the heavy load condition.

DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to faults with fault resistance and faults close to neutral side is maintained during normal 3
operation of reactor. Floating threshold patent technology is adopted to prevent maloperation of
DPFC differential protection due to system frequency deviation, external faults and CB tripping
process.

The sensitivity of reactor current differential protection is improved greatly when DPFC biased
differential element is enabled, especially in the situation faults with fault resistance and faults
close to neutral point. Operation criteria are:

∆𝐼𝑑 > 0.2𝑝. 𝑢.

∆𝐼𝑑 > 1.25 × ∆𝐼𝑑𝑡 + 𝐼𝑑𝑡ℎ

∆𝐼𝑑 > 0.6 × ∆𝐼𝑟 (∆𝐼𝑟 < 2𝑝. 𝑢. )

∆𝐼𝑑 > 0.75 × ∆𝐼𝑟 − 0.3𝑝. 𝑢. (∆𝐼𝑟 > 2𝑝. 𝑢. ) Equation 3.9-17

∆𝐼𝑑 = |∆𝐼 ̇1 + ∆𝐼 ̇2 + ∆𝐼 ̇3|

3 3 3

∆𝐼𝑟 = Max {∑|∆𝐼 ̇ak|, ∑|∆𝐼 ̇bk|, ∑|∆𝐼 ̇ck|}


𝑘=1 𝑘=1 𝑘=1

Where:

∆𝐼𝑑𝑡 is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold (∆𝐼𝑑𝑡 ) is higher than the change of current under these conditions and hence the
element maintains stability.

𝐼𝑑𝑡ℎ is fixed threshold internally.

∆𝐼 ̇a#, ∆𝐼 ̇b# and ∆𝐼 ̇c# are the DPFC current of reactor.

∆𝐼𝑑 and ∆𝐼𝑟 are respectively the DPFC differential current and the DPFC restraint current.

Calculation of restraint current of DPFC biased differential element is

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different to the biased differential element, it is difficult to test the


characteristic at site, so we recommend qualitative function test only at
site.

The calculation of DPFC restraint current and differential current are phase-segregated. DPFC
biased differential element is blocked by inrush current and CT circuit failure. DPFC biased
differential element has the higher anti-CT saturation characteristic, the sensitivity of which to
slight inter-turn fault is maintained during normal operation of reactor.
Differential current

3
Operation area of DPFC
K=m
biased differential element

K=0.75

1.2p.u.

0.2p.u. K=0.6 Restraint current

0.333p.u. 2p.u.

Figure 3.9-7 Operation characteristic of DPFC biased differential element

The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.

3.9.1.7 Zero-sequence Differential Element

Operation criteria are:

3𝐼0𝑑 = |3𝐼̇ 01 + 3𝐼 ̇02 + 3𝐼̇ 03|

3𝐼0𝑟 = Max(|3𝐼 ̇01|, |3𝐼̇ 02|, |3𝐼 ̇03|)


3𝐼0𝑑 > [87𝑅. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] (3𝐼0𝑟 ≤ 𝐾𝑃)
Equation 3.9-18
3𝐼0𝑑 > [87𝑅. 𝐼_𝑆𝑙𝑜𝑝𝑒] × 3𝐼0𝑟 (3𝐼0𝑟 > 𝐾𝑃)
3𝐼0𝑑 > 0.6 × (3𝐼0𝑟 − 0.8𝑝. 𝑢. ) + 1.2𝑝. 𝑢.
3𝐼0𝑟 > 0.8𝑝. 𝑢.
3𝐼0𝑑 > [87𝑅. 𝐼_𝐼𝑛𝑠𝑡]

Where:

3𝐼̇ 0# is the calculated residual current. (# =1, 2, 3)

3𝐼0𝑑 and 3𝐼0𝑟 are respectively residual differential current and residual restraint current

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In order to prevent zero-sequence differential element from being affected by non-identical CT


transient characteristic and CT saturation, positive-sequence current restraint blocking criterion is
adopted and its criterion is showed below.

3I0>β0×I1 Equation 3.9-19

Where:

3I0 is the zero-sequence current at a side.

I1 is its corresponding positive-sequence current.

β0 is a proportional constant. 3
Operation characteristic of zero-sequence differential element is shown below.
Differential current

Operating area of
instantaneous zero-sequence
F
differential element

[87R.I_Inst]
l l
tia na

K=0.6
en tio

ce
t fe r e n

en
en dif nv

qu
o

e
el nc of c

s
o-
er
e z ent
ue a
em e
eq re

iv
-s a

sit m
ro ing

en ele
f s tial
ze r a t

o n
pe

ea ere
ar
O

g diff
a tin
er
Op
[87R.Slope]

1.2p.u.

[87R.I_Biased]
Restraint current

0 KP 0.8p.u.

Figure 3.9-8 Operation characteristic of zero-sequence differential element

3.9.1.8 Inrush Current Discrimination

Please refer to Section 3.6.1.8 for details.

3.9.1.9 CT Saturation Detection

Please refer to Section 3.6.1.10 for details.

3.9.1.10 CT Circuit Supervision

 CT Circuit Abnormality

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If the following operation formula is met for 10s, CT circuit abnormality alarm of reactor current
differential protection will be issued without blocking the protection.

The operation criterion is as follows:

Id>max(0.18×Ir, [87R.I_Alm]) Equation 3.9-20

 CT Circuit Failure

Please refer to Section 3.6.1.12 for details.

3.9.2 Function Block Diagram


3
87R

87R.I3P1 87R.Ida

87R.I3P2 87R.Idb

87R.I3P3 87R.Idc

87R.Enable .
87R.Block
.
.
87R.St_DPFC_B

87R.St_DPFC_C

3.9.3 I/O Signals


Table 3.9-1 Input signals of reactor differential protection

No. Input signal Description


Three-phase current data input 1 for reactor differential protection.
 For single branch application
This terminal is fixed for the input of high-voltage side current of reactor.
1 87R.I3P1
 For double branches application
This terminal is fixed for the input of branch 1 current of high-voltage side of
reactor.
Three-phase current data input 2 for reactor differential protection.
 For single branch application
This terminal is unused.
2 87R.I3P2
 For double branches application
This terminal is fixed for the input of branch 2 current of high-voltage side of
reactor.
Three-phase current data input 3 for reactor differential protection.
3 87R.I3P3
This terminal is fixed for the input of low-voltage side current of reactor.

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No. Input signal Description


Input signal of enabling reactor differential protection. It is triggered from binary
4 87R.Enable
input or programmable logic etc.
Input signal of blocking reactor differential protection. It is triggered from binary
5 87R.Block
input or programmable logic etc.

Table 3.9-2 Output signals of reactor differential protection

No. Output signal Description


1 87R.Ida Phase-A differential current of reactor differential protection.
2 87R.Idb Phase-B differential current of reactor differential protection.
3 87R.Idc Phase-C differential current of reactor differential protection. 3
4 87R.3I0d Residual differential current of reactor differential protection.
5 87R.Ira Phase-A restraint current of reactor differential protection.
6 87R.Irb Phase-B restraint current of reactor differential protection.
7 87R.Irc Phase-C restraint current of reactor differential protection.
8 87R.3I0r Residual restraint current of reactor differential protection.
9 87R.Ia_Th Threshold value of phase-A restraint current of reactor differential protection.
10 87R.Ib_Th Threshold value of phase-B restraint current of reactor differential protection.
11 87R.Ic_Th Threshold value of phase-C restraint current of reactor differential protection.
12 87R.3I0_Th Threshold value of residual restraint current of reactor differential protection.
13 87R.St Reactor differential protection starts.
14 87R.Op Reactor differential protection operates.
15 87R.Op.PhA Phase-A reactor differential protection operates.
16 87R.Op.PhB Phase-B reactor differential protection operates.
17 87R.Op.PhC Phase-C reactor differential protection operates.
18 87R.St_REF Residual differential element of reactor differential protection starts.
Phase-A instantaneous differential element of reactor differential protection
19 87R.Op_Inst_A
operates.
Phase-B instantaneous differential element of reactor differential protection
20 87R.Op_Inst_B
operates.
Phase-C instantaneous differential element of reactor differential protection
21 87R.Op_Inst_C
operates.
22 87R.St_DPFC DPFC differential element of reactor differential protection starts.
23 87R.St_Inst Instantaneous differential element of reactor differential protection starts.
24 87R.Op_Biased_A Phase-A biased differential element of reactor differential protection operates.
25 87R.Op_Biased_B Phase-B biased differential element of reactor differential protection operates.
26 87R.Op_Biased_C Phase-C biased differential element of reactor differential protection operates.
27 87R.St_InstREF Instantaneous residual differential element of reactor differential protection starts.
28 87R.Op_DPFC_A Phase-A DPFC differential element of reactor differential protection operates.
29 87R.Op_DPFC_B Phase-B DPFC differential element of reactor differential protection operates.
30 87R.Op_DPFC_C Phase-C DPFC differential element of reactor differential protection operates.
31 87R.Alm_Diff Differential current of reactor differential protection is abnormal.
32 87R.Alm_CTS CT secondary circuit of reactor differential protection is abnormal.

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No. Output signal Description


33 87R.Op_Inst Instantaneous differential element of reactor differential protection operates.
Instantaneous residual differential element of reactor differential protection
34 87R.Op_InstREF
operates.
35 87R.Op_Biased Biased differential element of reactor differential protection operates.
36 87R.Op_DPFC DPFC differential element of reactor differential protection operates.
37 87R.Op_REF Residual differential element of reactor differential protection operates.
38 87R.On_Inst Instantaneous differential element of reactor differential protection is enabled.
39 87R.On_Biased Biased differential element of reactor differential protection is enabled.
40 87R.On_DPFC DPFC differential element of reactor differential protection is enabled.
3 41 87R.On_REF Residual differential element of reactor differential protection is enabled.
42 87R.Blocked_Inst Instantaneous differential element of reactor differential protection is blocked.
43 87R.Blocked_Biased Biased differential element of reactor differential protection is blocked.
44 87R.Blocked_DPFC DPFC differential element of reactor differential protection is blocked.
45 87R.Blocked_REF Residual differential element of reactor differential protection is blocked.
46 87R.Valid_Inst Instantaneous differential element of reactor differential protection is valid.
47 87R.St_Inst_A Phase-A instantaneous differential element of reactor differential protection starts.
48 87R.St_Inst_B Phase-B instantaneous differential element of reactor differential protection starts.
49 87R.St_Inst_C Phase-C instantaneous differential element of reactor differential protection starts.
50 87R.Valid_Biased Biased differential element of reactor differential protection is valid.
51 87R.Valid_DPFC DPFC differential element of reactor differential protection is valid.
52 87R.St_Biased Biased differential element of reactor differential protection starts.
53 87R.St_Biased_A Phase-A biased differential element of reactor differential protection starts.
54 87R.St_Biased_B Phase-B biased differential element of reactor differential protection starts.
55 87R.St_Biased_C Phase-C biased differential element of reactor differential protection starts.
56 87R.Valid_REF Residual differential element of reactor differential protection is valid.
57 87R.St_DPFC_A Phase-A DPFC differential element of reactor differential protection starts.
58 87R.St_DPFC_B Phase-B DPFC differential element of reactor differential protection starts.
59 87R.St_DPFC_C Phase-C DPFC differential element of reactor differential protection starts.

3.9.4 Logic

EN [87R.En_Inst] &
87R.On_Inst
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_Inst

SIG Fail_Device
&
87R.Valid_Inst

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EN [87R.En_Biased] &
87R.On_Biased
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_Biased

SIG Fail_Device
&
87R.Valid_Biased

EN [87R.En_Inst]
3
&
EN [87R.En_REF] 87R.On_InstREF

SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_InstREF

SIG Fail_Device
&
87R.Valid_InstREF

EN [87R.En_REF] &
87R.On_REF
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_REF

SIG Fail_Device
&
87R.Valid_REF

EN [87R.En_DPFC] &
87R.On_DPFC
SIG 87R.Enable
&
SIG 87R.Block >=1 87R.Blocked_DPFC

SIG Fail_Device
&
87R.Valid_DPFC

Figure 3.9-9 Logic of enabling reactor differential protection

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SET Idmax>[87R.I_Inst] &


0 500ms 87R.Pkp_Inst
FD.Pkp
SIG 87R.Valid_Inst

SET Idmax>[87R.I_Biased] &


0 500ms 87R.Pkp_Biased
FD.Pkp
SIG 87R.Valid_Biased

SET 3I0d>[87R.I_Inst] &


0 500ms 87R.Pkp_InstREF
FD.Pkp
SIG 87R.Valid_InstREF

3 SET 3I0d>[87R.I_Biased] &


0 500ms 87R.Pkp_REF
FD.Pkp
SIG 87R.Valid_Biased

SET ΔId>1.25ΔIdt+ΔIdh &


0 500ms 87R.Pkp_DPFC
FD.Pkp
SIG 87R.Valid_DPFC

Figure 3.9-10 Pickup logic of reactor differential protection

SET Idmax>[87R.I_Inst] &


87R.Op_Inst
SIG 87R.Pkp_Inst

Figure 3.9-11 Logic diagram of instantaneous differential element

SIG Conventional 87R &

SIG 87R.Pkp_Biased
>=1
SIG Sensitive 87R & 87R.Op_Biased

SIG CT saturation
&
SIG CT circuit failure & &

EN [87R.En_CTS_Blk]

SIG 87R.Pkp_Biased

Figure 3.9-12 Logic diagram of biased differential element

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SET 3I0d>[87R.I_Inst] &


87R.Op_InstREF
SIG 87R.Pkp_InstREF

SIG Conventional 87R REF &

SIG 87R.Pkp_REF
>=1
SIG Sensitive 87R REF & 87R.Op_REF

SIG CT saturation
&
SIG CT circuit failure & & 3
EN [87R.En_CTS_Blk]

SIG 87R.Pkp_REF

Figure 3.9-13 Logic diagram of Residual differential element

SIG DPFC 87R &


&
SIG CT circuit failure & 87R.Op_DPFC

SIG Inrush current

SIG 87R.Pkp_DPFC

Figure 3.9-14 Logic diagram of DPFC biased differential element

3.9.5 Settings
Table 3.9-3 Settings of reactor current differential protection

No. Item Range Unit Default Description


1 87R.I_Biased 0.050~5.000 p.u. 0.500 Pickup setting of biased differential element
Current setting of instantaneous differential
2 87R.I_Inst 0.050~20.000 p.u. 4.000
element
Current setting of differential current abnormality
3 87R.I_Alm 0.050~1.500 p.u. 0.200
alarm
4 87R.Slope 0.100~0.900 - 0.400 Slope of biased differential element
Coefficient of second harmonics for inrush
5 87R.K_Hm2_Inrush 0.050~0.800 - 0.150
current detection
Coefficient of third harmonics for inrush current
6 87R.K_Hm3_Inrush 0.050~0.800 - 0.200
detection
Enabled, Logic setting of enabling/disabling
7 87R.En_Inst - Disabled
Disabled instantaneous differential element
8 87R.En_Biased Enabled, - Disabled Logic setting of enabling/disabling conventional

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No. Item Range Unit Default Description


Disabled biased differential element
Enabled, Logic setting of enabling/disabling DPFC biased
9 87R.En_DPFC - Disabled
Disabled differential element
Enabled, Logic setting of enabling/disabling
10 87R.En_REF - Disabled
Disabled zero-sequence differential element
Enabled, Logic setting of enabling/disabling block biased
11 87R.En_CTS_Blk - Enabled
Disabled differential element during CT circuit failure

3.10 Inter-turn Fault Protection (21IT)


3
Shunt reactors as the key equipment are widely applied in extra-high voltage and ultra-high
voltage level power system, which has a dominate effect on safe operation of the power system.
The inter-turn fault is a common internal fault occurred in reactor, but current differential protection
cannot operate during inter-turn faults. Considering earth fault protection cannot be taken as the
fast protection for inter-turn faults, a dedicated protection for inter-turn protection of reactor is
needed to be equipped.

Inter-turn faults in reactors present a formidable challenge to the protection engineer. The current
and voltage changes encountered during an inter-turn fault can be of similar magnitude as load
variation, and therefore, sensitive, reliable protection schemes should be considered.

3.10.1 Function Description

Inter-turn fault protection consists of zero-sequence power direction element and zero-sequence
impedance element. They can improve sensitivity and ensure the device against maloperation
during external faults, transient process (such as series compensated lines, LC resonance, power
swing etc.) or abnormal conditions (such as pole disagreement, CT secondary circuit failure, etc.)

Inter-turn fault protection adopts the current from CT at line side of reactor. The amplitude of
residual voltage is compensated to ensure zero-sequence power direction element can
distinguish direction correctly when system impedance is too low. Inter-turn fault protection will be
blocked during CT and VT circuit failure.

3.10.1.1 Fault Detector

DPFC inter-turn fault detector will enable inter-turn fault protection, and its operation equation is
as follows.

I d  1.25  I dt  I dth
Equation 3.10-1
 
I d   I 1   I 2

Where:

I dt is the floating threshold varied with the change of load current from time to time. The change

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of load current is small and gradually under normal or even power swing condition, and the

adaptive floating threshold ( I dt ) is higher than the change of current under these conditions and

hence the element maintains stability.

 
 I 1 and  I 2 are DPFC current of two ends of reactor representatively.

I d is DPFC differential current.

I dth is the fixed threshold internally.


3
3.10.1.2 Residual Power Direction Element

The wiring diagram of shunt reactors in power system is shown as Figure 3.10-1.

F1
AC1 Zs1 ZL Zs2 AC2

* Relay 1 Relay 2 *

Zr1 Zr2 F2

Shunt reactor 1 Shunt reactor 2

Figure 3.10-1 Wiring diagram of shunt reactors in power system

Where:

AC1, AC2: equivalent voltage source

Zs1, Zs2: equivalent system impedance

Zr1, Zr2: impedance of shunt reactor

ZL: line impedance

F1: fault point 1

F2: fault point 2

1. F1: External single-phase earth fault of line (close-up external earth fault)

The fault point is zero-sequence power source, the equivalent zero-sequence network is shown
below.

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Zs' U0 Zr2

I0
Fault PS

Figure 3.10-2 Equivalent zero-sequence network for F1

Where:
3 Zs': equivalent system impedance, Zs'= (Zr1//Zs1+ ZL)//Zs2

U0: relay detected zero sequence voltage

I0: relay detected zero sequence current

FaultPS: fault power source

It is an external earth fault, so viewing from the device location, zero-sequence current flows to
reactor from reactor grounding point and via transmission line back to the ground at the earth fault
point. Therefore, the equation between U0 and I0 at the relay location is: U0=I0xZr2.

Vector relation between U0 and I0 is:

U0

I0

Figure 3.10-3 Vector relation for F1

2. F2: Internal inter-turn fault

Because of the fault point in reactor, the equivalent zero-sequence network is shown below.

Z's Zr2-1 Zr2-2


U0

I0 Fault PS

Figure 3.10-4 Equivalent zero-sequence network for F2

Where:

Z's: equivalent system impedance, Z's = (Zr2//Zs2+ ZL)//Zs2

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Zr2-1: impedance of Zr2 part 1

Zr2-2: impedance of Zr2 part 2

U0: detected zero-sequence voltage by the device

I0: detected zero-sequence current by the device

Fault PS: fault power source

It is an internal inter-turn fault, so viewing from reactor relay location, zero-sequence current flows
from reactor to ground through system reactance. Therefore, the equation between U0 and I0 at
the device location is: U0=-I0xZ's.

Vector relation between U0 and I0 is


3
I0

U0

Figure 3.10-5 Vector relation for F2

The phase angle of residual current leading residual voltage is nearly 90°if an inter-turn fault of
reactor winding occurs. The residual current phase leads the residual voltage phase if an internal
single-phase earth fault occurs, and the residual current phase lags the residual voltage phase if
an external single-phase earth fault occurs. Therefore, the phase angle between residual current
and residual voltage can be used to distinguish internal faults from external faults. The
zero-sequence impedance of system very small compared to reactor impedance, so the residual
voltage detected by the device will not be sensitive to operate and need to be compensated.

The operation criterion of residual power direction element is:

 
( 3 U 0  K  [ 21I.Zn_Reac_NP ]  3 I 0 )
- 180  Arg


 0 Equation 3.10-2
3I0

Where:

 
3 U 0 and 3 I 0 are respectively calculated residual voltage and calculated residual current from
VT and CT at the line side of reactor.

K is the floating coefficient adaptive to variation of zero-sequence voltage and current from 0 to
0.8.

3.10.1.3 Zero-sequence Impedance Element

Zero-sequence impedance of reactor is usually thousands of ohms which is greater than system
impedance. When an inter-turn fault or internal single-phase earth fault of reactor occurs, the

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impedance detected by the device is exactly the zero-sequence impedance of system. If an


external single-phase fault of reactor occurs, the impedance detected by the device is the
zero-sequence impedance of reactor. According to different values of measured impedances,
inter-turn faults (or internal fault) and external earth faults can be distinguished.

Operation criterion:

Zm<0.5 × Z0 Equation 3.10-3

Where:

3 Zm is measured zero-sequence impedance.

Z0 is zero-sequence impedance of reactor.

When VT abnormality (including star line of VT is not connected) is


detected, the operation criteria of residual power direction element and
zero-sequence impedance element are not satisfied, which implies that
inter-turn fault protection is out of service.

When CT abnormality at line side is detected, the operation criteria of


residual power direction element and zero-sequence impedance element
are not satisfied, which implies that inter-turn fault protection is out of
service.

3.10.2 Function Block Diagram

21IT

21IT.I3P 21IT.St

21IT.U3P 21IT.Op

21IT.Enable 21IT.On

21IT.Block 21IT.Blocked

21IT.Valid

3.10.3 I/O Signals


Table 3.10-1 Input signals of inter-turn protection

No. Input signal Description


1 21IT.I3P Three-phase current data input for inter-turn fault protection.
2 21IT.U3P Three-phase voltage data input for inter-turn fault protection.
Input signal of enabling inter-turn fault protection. It is triggered from binary input or
3 21IT.Enable
programmable logic etc.

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No. Input signal Description


Input signal of blocking inter-turn fault protection. It is triggered from binary input or
4 21IT.Block
programmable logic etc.

Table 3.10-2 Output signals of inter-turn protection

No. Output signal Description


1 21IT.St Inter-turn fault protection starts.
2 21IT.Op Inter-turn fault protection operates.
3 21IT.On Inter-turn fault protection is enabled.
4 21IT.Blocked Inter-turn fault protection is blocked.
5 21IT.Valid Inter-turn fault protection is valid. 3
3.10.4 Logic

EN [21IT.En] &
21IT.On
SIG 21IT.Enable
&
SIG 21IT.Block >=1 21IT.Blocked

SIG Fail_Device
&
21IT.Valid

Figure 3.10-6 Logic of enabling inter-turn fault protection

SET 21IT.Valid
&
SIG Flag_ZSImpedance 0 500ms 21IT.Pkp
FD.Pkp

SIG FwdDir_ROC

Figure 3.10-7 Pickup logic of inter-turn fault protection

SIG Flag_ZSImpedance &


&
SIG FwdDir_ROC &
21IT.Op
SIG Alm_VTS &

SIG AlmL_CTS

SIG 21IT.Pkp_DPFC

Figure 3.10-8 Logic diagram of inter-turn fault protection

Where:

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“Flag_ZSImpedance” means that zero-sequence impedance element operates.

“FwdDir_ROC” means that zero-sequence power direction element operates.

3.10.5 Settings
Table 3.10-3 Settings of inter-turn fault protection

No. Item Range Unit Default Description


Enabling/disabling inter-turn fault
1 21IT.En Enabled, Disabled - Disabled
protection.
Enabling/disabling the LV-side current as

3 the input current of 21IT.


This setting should be set according to the
input current actually configured in 21IT.
When the HV–side (head-end) current is
2 21IT.En_Curr_LVS Enabled, Disabled - Disabled
configured as the input current of 21IT, this
setting should be set as “0”; when the
LV–side (tail-end) current is configured as
the input current of 21IT, this setting should
be set as “1”.

3.11 Overexcitation Protection (24)

Overexcitation results from excessive applied voltage, possibly in combination with below-normal
frequency. Such condition may occur when a unit is on load, but are more likely to arise when it is
on open circuit, or at a loss of load occurrence. Transformers directly connected to generators are
in particular danger to experience overexcitation condition.

During overexcitation, field current of transformer rises greatly to cause excessive heating and
severe damage. The transformer, working magnetic flux density near the knee point, is subject to
overexcitation. Frequency range for normal operation is 45~55Hz for 50Hz working frequency of
power system and 55~65Hz for 60Hz working frequency of power system.

Overexcitation protection can be configured at any side of transformer through PCS-Studio, and it
is recommended to be equipped at the side without OLTC.

3.11.1 Function Description


Overexcitation protection consists of two stages definite-time overexcitation protection and one
stage inverse-time overexcitation protection for trip purpose or alarm purpose. The voltage for
protection calculation is RMS of three phase voltages and not affected by frequency fluctuation.
Overexcitation inverse-time curve is sectional linear curve, which has high adaptability.

The overexcitation degree can be reflected by overexcitation multiple which is calculated by


voltage and frequency, according to the following equation.

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n=U*/f* Equation 3.11-1

Where:

U* and f* are per unit value of voltage and frequency respectively.

The base value for calculating per unit value of voltage is secondary voltage corresponding to
primary voltage of one side of transformer, and the base value for calculating per unit value of
frequency is rated frequency. Hence, under normal operation, n should be equal to 1.

For example, overexcitation protection is equipped at HV side, primary voltage of HV side is


525kV (i.e., [HVS.U1n_Tr]=525kV) and voltage transformer ratio is 500kV/100V. The base value
for calculating per unit value of voltage is equal to:
3
525
 62.62V
500
3
100
This base voltage calculation is carried out in the device and users need not calculate VT ratio
when configure settings.

1. Definite-time operation criterion:

U*/f*>[24DTn.K_Set] Equation 3.11-2

Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on


given inverse-time operation characteristic, obtaining overexcitation multiple by calculation, and
getting the corresponding time delay by sectional linear insertion. It reflects the heat accumulation
and radiation.

Several groups of setting point with independent settings can be configured for simulating the
inverse-time operation characteristics curve and this protection can satisfy overexcitation
requirements of various transformers.

Following figure shows inverse-time characteristic of overexcitation protection.

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U*/f*

n0

n1
n2
n3
n4
n5
n6
n7
n8
n9

3 t0 t1t2 t3 t4 t5 t6 t7 t8 t9
t (s)
0

Figure 3.11-1 Inverse-time characteristic of overexcitation protection

The main harm of overexcitation to transformer is overheat, so accumulation method is adopted


and accumulate the time delay according to curve time corresponding to calculated overexcitation
multiple. When accumulated time delay is greater than the operating time delay, inverse-time
overexcitation protection operates. Dissipating process is also simulated, when overexcitation
multiple is less than the minimum overexcitation multiple setting, the accumulated value
decreases to 0 gradually. If overexcitation protection operates and overexcitation condition
disappears, thermal accumulation value decreases to 0 in 10s.

Overexcitation multiple comprises overexcitation information at current instant and also


overexcitation information integrated over various time intervals from its beginning.

Inverse-time characteristic curve can be specified by several overexcitation multiple settings, and
the relation among various settings of n and t are:

n0 > n1 > n2 >n3 > n4 > n5 > n6 > n7 > n8 > n9

t0 < t1 < t2 < t3 < t4 < t5 < t6 < t7 < t8 < t9

3.11.2 Function Block Diagram

24Cal

24Cal.in_U3P OvExc

24Cal.in_FREQ U/f

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24DT1

24DT1.OvExc 24DT1.St

24DT1.Enable 24DT1.Op

24DT1.Block 24DT1.On

24DT1.Blocked

24DT1.Valid

24DT2
3
24DT2.OvExc 24DT2.St

24DT2.Enable 24DT2.Alm

24DT2.Block 24DT2.On

24DT2.Blocked

24DT2.Valid

24IDMT

24IDMT.OvExc 24IDMT.ThermAccu

24IDMT.Enable 24IDMT.St

24IDMT.Block 24IDMT.Op

24IDMT.On

24IDMT.Blocked

24IDMT.Valid

24IDMT.Alm

“24Cal” is the overexcitation calculation element.

“24DT1” is the stage 1 of definite-time overexcitation element.

“24DT2” is the stage 2 of definite-time overexcitation element.

“24IDMT” is the inverse-time overexcitation element.

3.11.3 I/O Signals


Table 3.11-1 Input signals of overexcitation protection

No. Input signal Description


1 24Cal.in_U3P Three-phase voltage data input for overexcitation protection calculation.

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No. Input signal Description


2 24Cal.in_FREQ Frequency data input for overexcitation protection calculation.
Measurement data (including frequency and voltage) required by stage i of
3 24DTi.OvExc
definite-time overexcitation protection. (i=1, 2)
Input signal of enabling stage i of definite-time overexcitation protection. It is
4 24DTi.Enable
triggered from binary input or programmable logic etc. (i=1, 2)
Input signal of blocking stage i of definite-time overexcitation protection. It is
5 24DTi.Block
triggered from binary input or programmable logic etc. (i=1, 2)
Measurement data (including frequency and voltage) required by inverse-time
6 24IDMT.OvExc
overexcitation protection.

3 7 24IDMT.Enable
Input signal of enabling inverse-time overexcitation protection. It is triggered from
binary input or programmable logic etc.
Input signal of blocking inverse-time overexcitation protection. It is triggered from
8 24IDMT.Block
binary input or programmable logic etc.

Table 3.11-2 Output signals of overexcitation protection

No. Output signal Description


An overexcitation data set, mainly used for the inputs of elements “24DTi”,
1 OvExc
“24IDMT”.
2 U/f The calcaulated relative overexcitation value
3 24DTi.St Stage i of definite-time overexcitation protection starts. (i=1, 2)
4 24DT1.Op Stage 1 of definite-time overexcitation protection operates to trip.
5 24DTi.On Stage i of definite-time overexcitation protection is enabled. (i=1, 2)
6 24DTi.Blocked Stage i of definite-time overexcitation protection is blocked. (i=1, 2)
7 24DTi.Valid Stage i of definite-time overexcitation protection is valid. (i=1, 2)
8 24DT2.Alm Stage 2 of definite-time overexcitation protection operates to alarm.
Thermal state of inverse-time overexcitation protection. When the value is “100%”,
9 24IDMT.ThermAccu
inverse-time overexcitation protection operates.
10 24IDMT.St Inverse-time overexcitation protection starts
11 24IDMT.Op Inverse-time overexcitation protection operates to trip.
12 24IDMT.On Inverse-time overexcitation protection is enabled.
13 24IDMT.Blocked Inverse-time overexcitation protection is blocked.
14 24IDMT.Valid Inverse-time overexcitation protection is valid.
15 24IDMT.Alm Inverse-time overexcitation protection operates to alarm.

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3.11.4 Logic

EN [24DT1.En] &
24DT1.On
SIG 24DT1.Enable
&
SIG 24DT1.Block >=1 24DT1.Blocked

SIG Fail_Device
&
24DT1.Valid

3
EN [24DT2.En] &
24DT2.On
SIG 24DT2.Enable
&
SIG 24DT2.Block >=1 24DT2.Blocked

SIG Fail_Device
&
24DT2.Valid

EN [24IDMT.En] &
24IDMT.On
SIG 24IDMT.Enable
&
SIG 24IDMT.Block >=1 24IDMT.Blocked

SIG Fail_Device
&
24IDMT.Valid

Figure 3.11-2 Logic of enabling overexcitation protection

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SET U*/f*>[24DT1.K_Set]

SIG 24DT1.Valid &


0 500ms 24DT1.Pkp
FD.Pkp
EN x.En_VT

BI x.BI_En_VT

SET U*/f*>[24DT2.K_Set]

SIG 24DT2.Valid &


3 EN x.En_VT
0 500ms 24DT2.Pkp

BI x.BI_En_VT

SET U*/f*>[24IDMT.Kn_Set]

SIG 24IDMT.Valid &


0 500ms 24IDMT.Pkp
FD.Pkp
EN x.En_VT

BI x.BI_En_VT

Figure 3.11-3 Pickup logic of overexcitation protection

SIG 24DT1.Pkp &


[24DT1.t_Op] 0ms 24DT1.Op
SET U*/f*>[24DT1.K_Set]
24DT1.St

SIG 24DT2.Pkp &


[24DT2.t_Alm] 0ms 24DT2.Alm
SET U*/f*>[24DT2.K_Set]
24DT2.St

Figure 3.11-4 Logic diagram of definite-time overexcitation protection

24IDMT.St
SIG 24IDMT.Pkp
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT 24IDMT.Op

24IDMT.St
EN [24IDMT.En_Trp]
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT* 24IDMT.Alm

EN [24IDMT.En_Alm]

Figure 3.11-5 Logic diagram of inverse-time overexcitation protection

Where, IDMT* means that the time delay of inverse-time overexcitation protection for alarm

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purpose equals to [24IDMT.K_Alm] of the time delay of inverse-time overexcitation protection for
trip purpose.

3.11.5 Settings
Table 3.11-3 Settings of overexcitation protection

No. Name Range Unit Default Description


It is used to set reference voltage of
overexcitation calculation, and it is usually
1 24Cal.U1n 0.000~2000.000 kV 220.000
set as primary rated voltage at calculated
side of transformer
Voltage option between phase voltage
3
and phase-to-phase voltage for
2 24Cal.Opt_Up/Upp Up, Upp - Up calculation of overexcitation protection
Up: phase voltage
Upp: phase-to-phase voltage
Multiple setting of stage 1 of definite-time
3 24DT1.K_Set 1.000~1.600 - 1.300
overexcitation protection for trip purpose
Time delay setting of stage 1 of
4 24DT1.t_Op 0.100~9999.000 s 1.000 definite-time overexcitation protection for
trip purpose
Logic setting for enabling/disabling stage
Enabled,
5 24DT1.En - Disabled 1 of definite-time overexcitation protection
Disabled
for trip purpose
Multiple setting of stage 2 of definite-time
6 24DT2.K_Set 1.000~1.600 - 1.300 overexcitation protection for alarm
purpose
Time delay setting of stage 2 of
7 24DT2.t_Alm 0.100~9999.000 s 1.000 definite-time overexcitation protection for
alarm purpose
Logic setting of enabling/disabling stage 2
Enabled,
8 24DT2.En - Disabled of definite-time overexcitation protection
Disabled
for alarm purpose
Highest-limit multiple setting of
9 24IDMT.K0_Set 1.000~1.700 - 1.700
inverse-time overexcitation protection: n0
Time delay setting corresponding to
10 24IDMT.t0_Op 0.100~9999.000 s 1.000
highest-limit setting: t0
Multiple setting 1 of inverse-time
11 24IDMT.K1_Set 1.000~1.700 - 1.650
overexcitation protection: n1
Time delay setting corresponding to
12 24IDMT.t1_Op 0.100~9999.000 s 2.000
multiple setting 1: t1
Multiple setting 2 of inverse-time
13 24IDMT.K2_Set 1.000~1.700 - 1.600
overexcitation protection: n2
14 24IDMT.t2_Op 0.100~9999.000 s 5.000 Time delay setting corresponding to

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No. Name Range Unit Default Description


multiple setting 2: t2
Multiple setting 3 of inverse-time
15 24IDMT.K3_Set 1.000~1.700 - 1.500
overexcitation protection: n3
Time delay setting corresponding to
16 24IDMT.t3_Op 0.100~9999.000 s 10.000
multiple setting 3: t3
Multiple setting 4 of inverse-time
17 24IDMT.K4_Set 1.000~1.700 - 1.400
overexcitation protection: n4
Time delay setting corresponding to
18 24IDMT.t4_Op 0.100~9999.000 s 20.000
multiple setting 4: t4

3 19 24IDMT.K5_Set 1.000~1.700 - 1.300


Multiple setting 5 of inverse-time
overexcitation protection: n5
Time delay setting corresponding to
20 24IDMT.t5_Op 0.100~9999.000 s 50.000
multiple setting 5: t5
Multiple setting 6 of inverse-time
21 24IDMT.K6_Set 1.000~1.700 - 1.250
overexcitation protection: n6
Time delay setting corresponding to
22 24IDMT.t6_Op 0.100~9999.000 s 100.000
multiple setting 6: t6
Multiple setting 7 of inverse-time
23 24IDMT.K7_Set 1.000~1.700 - 1.200
overexcitation protection: n7
Time delay setting corresponding to
24 24IDMT.t7_Op 0.100~9999.000 s 300.000
multiple setting 7: t7
Multiple setting 8 of inverse-time
25 24IDMT.K8_Set 1.000~1.700 - 1.150
overexcitation protection: n8
Time delay setting corresponding to
26 24IDMT.t8_Op 0.100~9999.000 s 600.000
multiple setting 8: t8
Lowest-limit multiple setting of
27 24IDMT.K9_Set 1.000~1.700 - 1.130
inverse-time overexcitation: n9
Time delay setting corresponding to
28 24IDMT.t9_Op 0.100~9999.000 s 1000.000
lowest-limit multiple setting: t9
Coefficient of time delay of inverse-time
29 24IDMT.K_Alm 0.500~1.000 - 0.700 overexcitation protection for alarm
purpose
Cooling time of inverse-time
30 24IDMT.t_Cooling 0.100~9999.000 s 10.000
overexcitation protection
Logic setting for enabling/disabling
Enabled,
31 24IDMT.En_Trp - Disabled inverse-time overexcitation protection for
Disabled
trip purpose
Logic setting for enabling/disabling
Enabled,
32 24IDMT.En_Alm - Disabled inverse-time overexcitation protection for
Disabled
alarm purpose

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Please input the corresponding values of selected 10 points of


overexcitation curve of transformer to the device and the values of 10
points are distributed averagely.

Inverse-time overexcitation protection is set with reference to the curve


given by the transformer manufactory. The relation among all settings of
inverse-time overexcitation protection is:

[24IDMT.K9_Set]<[24IDMT.K8_ Set]<…<[24IDMT.K1_Set]<[24IDMT.K0_
Set] 3
[24IDMT.t0_Op]<[ 24IDMT.t1_ Op]<…<[24IDMT.k8_ Op] <[24IDMT.t9_ Op]

3.12 Phase Overcurrent Protection (50/51P)

Phase overcurrent protection is widely used in power systems. It can be used as main protection
of the feeder, and can also be used as backup protection for power equipment such as
transformers, reactors, and motors. When a fault occurs in the system, a fault current will be
generated and phase overcurrent protection can reflect the increase of the fault current.

3.12.1 Function Description

The device can provide 6 stages of phase overcurrent protection with independent logic by default.
Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. The dropout characteristics can be set as instantaneous dropout, definite-time
dropout or inverse-time dropout. It can be chosen whether it is blocked by voltage control element
or harmonic control element. The direction control element can be set as no direction, forward
direction and reverse direction. Phase overcurrent protection picks up when the current exceeds
the setting, and operates after a certain time delay. Once the fault disappears, phase overcurrent
protection will dropout.

Phase overcurrent protection can operate to trip or alarm and can be enabled or disabled via the
settings or the signals, for some specific applications, phase overcurrent protection needs to be
blocked by the external signal, so the device provides a function block input signal to be used to
block phase overcurrent protection.

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EN [x.50/51Pi.En] &
x.50/51Pi.On
SIG x.50/51Pi.Enable

&
SIG x.50/51Pi.Block >=1 x.50/51Pi.Blocked

SIG Fail_Device
&
x.50/51Pi.Valid

3 Figure 3.12-1 Logic of enabling phase overcurrent protection

The pickup logic of phase overcurrent protection is shown in Figure 3.12-2:

SET x.Ia>0.95×[x.50/51Pi.I_Set]
>=1
SET x.Ib>0.95×[x.50/51Pi.I_Set] &
0 500ms &
SET x.Ic>0.95×[x.50/51Pi.I_Set]
x.50/51Pi.Pkp
SIG x.50/51Pi.On

SIG x.50/51Pi.Valid
&
FD.Pkp
SET [x.50/51Pi.Opt_Trp/Alm]=Alm

Figure 3.12-2 Pickup logic of phase overcurrent protection

3.12.1.1 Voltage Control Element

When a fault occurs at the remote end of a feeder, the fault current is relatively small, so the
voltage control element can be adopted to increase the sensitivity for this kind of fault. It can be
enabled or disabled via the setting [x.50/51P.VCE.En_VTS_Blk]. If VT circuit supervision is
enabled and the setting [x.50/51P.VCE.En_VTS_Blk] is set as “Enabled”, the device will issue an
alarm signal "VTS.Alm" when VT circuit fails, and voltage control element will be blocked. If
voltage control element is not enabled, phase overcurrent protection will not effected by VT circuit
failure. The corresponding relationship between each phase and voltage control element is as
follows.

Voltage criterion Phase A Phase B Phase C


x.Uab<[x.50/51P.VCE.Upp] x.Uab<[x.50/51P.VCE.Upp] x.Ubc<[ x.50/51P.VCE.Upp]
Phase-to-phase
x.Uca<[x.50/51P.VCE.Upp] x.Ubc<[x.50/51P.VCE.Upp] x.Uca<[ x.50/51P.VCE.Upp]
Negative-sequence x.U2>[x.50/51P.VCE.U2] x.U2>[x.50/51P.VCE.U2] x.U2>[x.50/51P.VCE.U2]
x.U0_Cal>[x.50/51P.VCE.3 x.U0_Cal>[x.50/51P.VCE.3 x.U0_Cal>[x.50/51P.VCE.3
Zero-sequence
U0] U0] U0]

The relationship among phase-to-phase criterion, negative-sequence criterion and zero-sequence


criterion is "OR". The logic of voltage control element is shown in Figure 3.12-3.

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EN [x.50/51P.VCE.En_VTS_Blk] &

>=1
SIG x.VTS.Alm &
SIG x.Uab, x.Ubc, x.Uca

criterion
Voltage
&
x.50/51P.VCE.Op
SIG x.U2, x.U0_Cal

SIG x.BI_En_VT &

EN [x.En_VT]
3
Figure 3.12-3 Logic of voltage control element

3.12.1.2 Direction Control Element

Ua

[x.50/51P.DIR.phi_Min_Fwd]

Non-operating Ia
area

[x.50/51P.DIR.phi_Max_Rev] Operating area in


forward direction

[x.50/51P.DIR.RCA]

Operating area in
reverse direction

[x.50/51P.DIR.phi_Max_Fwd]

[x.50/51P.DIR.phi_Min_Rev] Non-operating
area

Figure 3.12-4 Operating characteristics of the direction element

In order to ensure the selectivity of phase overcurrent protection, direction control element is also
available. The setting [x.50/51Pi.Opt_Dir] (i=1~6) is used to select the direction characteristics for
each stage of phase overcurrent protection: no direction, forward direction and reverse direction.
Takes the phase A fault as an example, the setting [x.50/51P.DIR.Opt_PolarizedVolt] is set as
"Up", its operating characteristics is shown in Figure 3.12-4. The principle of phase B and phase C

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is the same. If positive-sequence voltage or phase-to-phase voltage is used as polarized voltage,


the operating characteristics are the same.

The operation boundary of the forward direction element can be set by


[x.50/51P.DIR.phi_Min_Fwd] and [x.50/51P.DIR.phi_Max_Fwd]. The operation boundary of the
reverse direction element can be set by [x.50/51P.DIR.phi_Min_Rev] and
[x.50/51P.DIR.phi_Max_Rev].

The polarized voltage is selectable by the setting [x.50/51P.DIR.Opt_PolarizedVolt]. The following


table shows the relationship among the operating current, the polarized voltage and the
polarization mode.

3 Direction criterion (for “ABC” system phase sequence)


Polarization Faulty Operating
Polarized voltage Angle difference
mode phase current
Phase-A Positive-sequence
Phase A Angle_A=Angle(U1)-Angle(Ia)-RCA
current Ia voltage
Positive-sequence Phase-B Positive-sequence
Phase B Angle_B=Angle(U1)-Angle(Ib)-RCA-120º
voltage polarized current Ib voltage
Phase-C Positive-sequence
Phase C Angle_C=Angle(U1)-Angle(Ic)-RCA+120º
current Ic voltage
Phase-A Phase-to-phase
Phase A Angle_A=Angle(Ubc)-Angle(Ia)-RCA+90º
current Ia voltage Ubc
Phase-to-phase Phase-B Phase-to-phase
Phase B Angle_B=Angle(Uca)-Angle(Ib)-RCA+90º
voltage polarized current Ib voltage Uca
Phase-C Phase-to-phase
Phase C Angle_C=Angle(Uab)-Angle(Ic)-RCA+90º
current Ic voltage Uab
Phase-A Phase-to-ground
Phase A Angle_A=Angle(Ua)-Angle(Ia)-RCA
current Ia voltage Ua
Phase-to-ground Phase-B Phase-to-ground
Phase B Angle_B=Angle(Ub)-Angle(Ib)-RCA
voltage polarized current Ib voltage Ub
Phase-C Phase-to-ground
Phase C Angle_C=Angle(Uc)-Angle(Ic)-RCA
current Ic voltage Uc

For the “ACB” system phase sequence, the angle difference under
positive-sequence voltage polarization mode and phase-to-phase voltage
polarization mode is different from that of the “ABC” system phase
sequence, as shown in the following table:

Direction criterion (for “ACB” system phase sequence)


Polarization Faulty Operating
Polarized voltage Angle difference
mode phase current
Positive-sequence Phase Phase-A Positive-sequence
Angle_A=Angle(U1)-Angle(Ia)-RCA
voltage polarized A current Ia voltage

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Phase Phase-B Positive-sequence


Angle_B=Angle(U1)-Angle(Ib)-RCA+120º
B current Ib voltage
Phase Phase-C Positive-sequence
Angle_C=Angle(U1)-Angle(Ic)-RCA-120º
C current Ic voltage
Phase Phase-A Phase-to-phase
Angle_A=Angle(Ubc)-Angle(Ia)-RCA+270º
A current Ia voltage Ubc
Phase-to-phase Phase Phase-B Phase-to-phase
Angle_B=Angle(Uca)-Angle(Ib)-RCA+270º
voltage polarized B current Ib voltage Uca
Phase Phase-C Phase-to-phase
Angle_C=Angle(Uab)-Angle(Ic)-RCA+270º
C current Ic voltage Uab

Therefore, the criteria of three-phase direction control element are as follows: 3


Direction control element
Direction element Operating condition
Phase A forward direction Angle_A forward direction operates.
Phase A reverse direction Angle_A reverse direction operates.
Phase B forward direction Angle_B forward direction operates.
Phase B reverse direction Angle_B reverse direction operates.
Phase C forward direction Angle_C forward direction operates.
Phase C reverse direction Angle_C reverse direction operates.

The calculation of direction control element needs to judge the voltage threshold and the current
threshold. The direction judgement can be executed only when both the voltage and the current
are greater than the threshold values. For different polarization mode, the selected voltage and
current, and their threshold value are also different, the specific principles are:

Polarized voltage Operating current


Phase-to-phase voltage Phase current
Phase-to-ground voltage Phase current
Positive-sequence voltage Phase current

The memorized characteristics of direction control element can eliminate the dead zone for
close-in three-phase short-circuit fault. When the polarized voltage is less than the minimum
operating voltage setting [x.50/51P.DIR.U_Min], the 2-cycle pre-fault positive-sequence voltage is
used to judge the direction. The polarized voltage will not be used to judge the direction until it is
greater than [x.50/51P.DIR.U_Min].The logic of forward direction element and reverse direction
element are shown in Figure 3.12-5.

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EN [x.50/51P.DIR.En_VTS_Blk] &

SIG x.VTS.Alm & >=1


SIG Three-phase currents
&

Forward direction
x.50/51P.DIR.Fwd
SIG Three-phase voltages

criterion
SIG Memorized U1

SET [x.50/51P.DIR.Opt_PolarizedVolt]
3 BI x.BI_En_VT &

EN [x.En_VT]

SET x.Iop>[x.50/51P.DIR.I_Min]

EN [x.50/51P.DIR.En_VTS_Blk] &

SIG x.VTS.Alm & >=1


SIG Three-phase currents
&
Reverse direction

x.50/51P.DIR.Rev
SIG Three-phase voltages
criterion

SIG Memorized U1

SET [x.50/51P.DIR.Opt_PolarizedVolt]

BI x.BI_En_VT &

EN [x.En_VT]

SET x.Iop>[x.50/51P.DIR.I_Min]

Figure 3.12-5 Logic of forward and reverse direction element

Where:

Memorized U1: the positive-sequence memory voltage, it refers to the 2-cycle pre-fault
positive-sequence voltage when the polarized voltage is less than the minimum operating voltage
setting [x.50/51P.DIR.U_Min], and it is calculated from the three-phase voltage.

x.Iop: the operating current.

3.12.1.3 Harmonic Control Element

When the transformer is energized with no-load, the inrush current may be generated, which may
cause the maloperation of phase overcurrent protection. Because secondary harmonic

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component is high in the inrush current but secondary harmonic component is low in the fault
current, harmonic control element based on secondary harmonic component is added to prevent
phase overcurrent protection from maloperation due to inrush current. For harmonic control
element, the harmonic blocking mode can be selected through the setting [50/51P.HMB.Opt_Blk],
it can support phase blocking, cross blocking, and maximum phase blocking. The corresponding
relationship is shown in the following table.

Harmonic blocking criterion


Harmonic blocking mode
Phase A Phase B Phase C
PhaseBlk (phase Ia2/Ia1> Ib2/Ib1> Ic2/Ic1>
1
blocking) x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2
2 CrossBlk (cross blocking) (Ia2/Ia1) or (Ib2/Ib1) or (Ic2/Ic1)> x.50/51P.HMB.K_Hm2 3
MaxPhaseBlk (maximum Max(Ia2, Ib2, Ic2)/Ia1> Max(Ia2, Ib2, Ic2)/Ib1> Max(Ia2, Ib2, Ic2)/Ic1>
3
phase blocking) x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2

When the fundamental current is greater than the setting [x.50/51P.HMB.I_Rls], the corresponding
phase will be unblocked by harmonic control element. The logic of harmonic control element is
shown in Figure 3.12-6.

SET Imax>[x.50/51P.HMB.I_Rls]

SIG x.Ia1, x.Ib1, x.Ic1


&
x.50/51P.HMB.Op
Harmonic
criterion

SIG x.Ia2, x.Ib2, x.Ic2

SET [x.50/51P.HMB.Opt_Blk]

Figure 3.12-6 Logic of harmonic control element

Where:

x.Ia1, x.Ib1, x.Ic1 are the fundamental current.

x.Ia2, x.Ib2, x.Ic2 are the secondary harmonic current.

x.Imax is the maximum phase current.

3.12.1.4 Operating Characteristics

Phase overcurrent protection can operate instantaneously or with a fixed time delay. It can also
operate with inverse-time characteristics, and its characteristics curve complies with the
standards IEC 60255-3 and ANSI C37.112. Phase overcurrent protection can support
definite-time characteristics, IEC & ANSI standard inverse-time characteristics and user-defined
inverse-time characteristics, which are determined by the setting [x.50/51Pi.Opt_Curve] (i=1~6).
The relationship between the setting and the characteristics curve is shown in the table below.

50/51Pi.Opt_Curve Time Characteristics k α c tr


ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal inverse 0.0086 0.02 0.0185 0.46

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50/51Pi.Opt_Curve Time Characteristics k α c tr


ANSIM ANSI Moderately inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite time - - - -
ANSILTE ANSI Long time extremely inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long time very inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long time inverse 0.086 0.02 0.185 4.6
IECN IEC Normal inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -
IECI IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
3 IECST IEC Short time inverse 0.05 0.04 0 -
IECLT IEC Long time inverse 120.0 1.0 0 -
IECDefTime IEC Definite time - - - -
UserDefine Programmable

When the setting [x.50/51Pi.Opt_Curve] is set as "UserDefine", it means that user-defined


inverse-time characteristics is selected. These settings [x.50/51Pi.K], [x.50/51Pi.C] and
[x.50/51Pi.Alpha] are valid, and the inverse-time operating curve is determined by the three
settings.

 Instantaneous characteristics

When I>[x.50/51Pi.I_Set], phase overcurrent protection operates instantaneously.

 Definite-time characteristics

When I>[x.50/51Pi.I_Set], phase overcurrent protection operates with a time delay


[x.50/51Pi.t_Op], and the operating characteristics curve is as shown in Figure 3.12-7.

[x.50/51Pi.t_Op]

I
[x.50/51Pi.I_Set]

Figure 3.12-7 Definite-time operating curve of phase overcurrent protection

 Inverse-time characteristics

When I>[x.50/51Pi.I_Set], phase overcurrent protection begins to accumulate, and the operating

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time is affected by the applied current I. The operating time will decrease with the current
increasing, but the operating time shall not less than the setting [x.50/51Pi.tmin] (i=1~6). The
inverse-time operating characteristics equation is:

K
t={ + C} × TMS
I α
(I ) − 1
P

Where:

IP is the current setting [x.50/51Pi.I_Set].

TMS is the inverse-time time multiplier, i.e. the setting [x.50/51Pi.TMS].


3
K is the inverse-time coefficient, i.e. the setting [x.50/51Pi.K].

C is the inverse-time coefficient, i.e. the setting [x.50/51Pi.C].

α is the inverse-time coefficient, i.e. the setting [x.50/51Pi.Alpha].

I is the measured current.

The inverse-time operating characteristics curve is shown Figure 3.12-8.

[x.50/51Pi.tmin]

I
[x.50/51Pi.I_Set] ID

Figure 3.12-8 Inverse-time operating curve of phase overcurrent protection

When the applied current is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overcurrent protection is shown in the following equation.

T0
1
∫ dt = 1
t(I)
0

Where:

T0 is the operating time of the protection element.

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t(I) is the theoretical operating time when the current is I.

3.12.1.5 Dropout Characteristics

The supported dropout characteristics of phase overcurrent protection include instantaneous,


definite-time and ANSI inverse-time characteristics. When the operating characteristics curve is
selected as definite-time, IEC inverse-time or user-defined inverse-time characteristics, the
dropout characteristic curve can only be selected as instantaneous or definite-time characteristics,
and the alarm signal "Fail_Settings" will be issued and the device will be blocked if ANSI
inverse-time characteristics is selected. When the operating characteristics curve is selected as
ANSI inverse-time characteristics, the dropout characteristic curve can be selected as
3 instantaneous, definite-time and ANSI inverse-time characteristics.

 Instantaneous characteristics

When I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection drops out instantaneously.

 Definite-time characteristics

When I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection drops out with a time delay
[x.50/51Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among
start signal, operating signal and the counter is as shown in Figure 3.12-9.

Start time

I>[x.50/51Pi.I_Set]

x.50/51Pi.St

x.50/51Pi.Op

[x.50/51Pi.t_Op] Phase overcurrent


protection operating

Operating counter

[x.50/51Pi.t_DropOut]
[x.50/51Pi.t_DropOut] [x.50/51Pi.t_DropOut]
Dropout time
Dropout time

Figure 3.12-9 Definite-time dropout characteristics of phase overcurrent protection

 Inverse-time characteristics

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When I>[x.50/51Pi.I_Set], phase overcurrent protection begins to accumulate, the accumulated


value after tP (Assuming tP is less than the theoretical operating time) is calculated according to
the following equation.

tP
1
Itp = ∫ dt
t(I)
0

If I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection begins to drop out, and the dropout
characteristics meets the following equations.

tR

Itp − ∫
1
t R (I)
dt = 0 3
0

tr
t R (I) = { } × TMS
I 2
1 − (I )
P

Where:

tR is the dropout time.

IP is the current setting [x.50/51Pi.I_Set].

TMS is the inverse-time time multiplier, i.e., the setting [x.50/51Pi.TMS].

tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
phase overcurrent protection operates.

I is the measured current.

If 0.95×[x.50/51Pi.I_Set]<I<[x.50/51Pi.I_Set], the counter will neither accumulate nor drop out.

The inverse-time dropout characteristics curve is shown in Figure 3.12-10.

tr

I
[x.50/51Pi.I_Set]

Figure 3.12-10 Inverse-time dropout curve of phase overcurrent protection

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The sequence diagram of inverse-time dropout characteristics among start signal, operating
signal and the counter is shown in Figure 3.12-11.

Start time

I>[x.50/51Pi.I_Set]

x.50/51Pi.St

3
x.50/51Pi.Op

Phase overcurrent protection operating


[x.50/51Pi.t_Op]

Operating counter

Dropout time Coefficient (tr)

Dropout time
Dropout time

Figure 3.12-11 Inverse-time dropout characteristics of phase overcurrent protection

3.12.2 Function Block Diagram

x.50/51P.HMB

x.50/51P.HMB.in_I3P x.50/51P.HMB.Op

x.50/51P.DIR

x.50/51P.DIR.in_I3P x.50/51P.DIR.Fwd

x.50/51P.DIR.in_U3P x.50/51P.DIR.Rev

x.50/51P.VCE

x.50/51P.VCE.in_U3P x.50/51P.VCE.Op

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x.50/51Pi

x.50/51Pi.in_I3P x.50/51Pi.St

x.50/51Pi.Enable x.50/51Pi.StA

x.50/51Pi.Block x.50/51Pi.StB

x.50/51Pi.VCE x.50/51Pi.StC

x.50/51Pi.FwdDir x.50/51Pi.Op

x.50/51Pi.RevDir x.50/51Pi.Op.PhA

x.50/51Pi.HMB x.50/51Pi.Op.PhB 3
x.50/51Pi.Op.PhC

x.50/51Pi.On

x.50/51Pi.Blocked

x.50/51Pi.Valid

x.50/51Pi.Alm

“x.50/51P.VCE” is the voltage control element in 50/51P.

“x.50/51P.DIR” is the direction control element in 50/51P.

“x.50/51P.HMB” is the harmonic control element in 50/51P.

“x.50/51Pi” is the stage i of phase overcurrent element.

3.12.3 I/O Signal


Table 3.12-1 Input signals of phase overcurrent protection

No. Input signal Description


Three-phase current data input for harmonic control element of phase
1 x.50/51P.HMB.in_I3P
overcurrent protection
Three-phase current data input for direction control element of phase
2 x.50/51P.DIR.in_I3P
overcurrent protection
Three-phase voltage data input for direction control element of phase
3 x.50/51P.DIR.in_U3P
overcurrent protection
Three-phase voltage data input for voltage control element of phase
4 x.50/51P.VCE.in_U3P
overcurrent protection
5 x.50/51Pi.in_I3P Three-phase current data input for phase overcurrent protection (i=1~6)
6 x.50/51Pi.Enable Input signal of enabling stage i of phase overcurrent protection (i=1~6)
7 x.50/51Pi.Block Input signal of blocking stage i of phase overcurrent protection (i=1~6)
8 x.50/51Pi.VCE Input signal of voltage control element of stage i of phase overcurrent

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No. Input signal Description


protection (i=1~6)
Input signal of forward direction element of stage i of phase overcurrent
9 x.50/51Pi.FwdDir
protection (i=1~6)
Input signal of reverse direction element of stage i of phase overcurrent
10 x.50/51Pi.RevDir
protection (i=1~6)
Input signal of harmonic control element of stage i of phase overcurrent
11 x.50/51Pi.HMB
protection (i=1~6)

Table 3.12-2 Output signals of phase overcurrent protection

3 No. Output signal Description


1 x.50/51P.HMB.Op The harmonic control element of phase overcurrent protection operates.
2 x.50/51P.DIR.Fwd The forward direction element of phase overcurrent protection operates.
3 x.50/51P.DIR.Rev The reverse direction element of phase overcurrent protection operates.
4 x.50/51P.VCE.Op The voltage control element of phase overcurrent protection operates.
5 x.50/51Pi.St Stage i of phase overcurrent protection starts. (i=1~6)
6 x.50/51Pi.StA Stage i of phase-A overcurrent protection starts. (i=1~6)
7 x.50/51Pi.StB Stage i of phase-B overcurrent protection starts. (i=1~6)
8 x.50/51Pi.StC Stage i of phase-C overcurrent protection starts. (i=1~6)
9 x.50/51Pi.Op Stage i of phase overcurrent protection operates. (i=1~6)
10 x.50/51Pi.Op.PhA Stage i of phase-A overcurrent protection operates. (i=1~6)
11 x.50/51Pi.Op.PhB Stage i of phase-B overcurrent protection operates. (i=1~6)
12 x.50/51Pi.Op.PhC Stage i of phase-C overcurrent protection operates. (i=1~6)
13 x.50/51Pi.On Stage i of phase overcurrent protection is enabled. (i=1~6)
14 x.50/51Pi.Blocked Stage i of phase overcurrent protection is blocked. (i=1~6)
15 x.50/51Pi.Valid Stage i of phase overcurrent protection is valid. (i=1~6)
16 x.50/51Pi.Alm Stage i of phase overcurrent protection alarms. (i=1~6)

3-104 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

3.12.4 Logic

SET Ia>[x.50/51Pi.I_Set]

SIG X.50/51P.VCE.Op_A >=1 &

EN [x.50/51Pi.En_Volt_Blk]

SIG x.50/51P.DIR.Fwd_A

selection
Direction
SIG x.50/51P.DIR.Rev_A

SIG [x.50/51Pi.Opt_Dir] x.50/51Pi.StA


&
SIG x.50/51P.HMB.Op_A & & Timer
t 3
t
EN [x.50/51Pi.En_Hm_Blk]

SIG x.50/51Pi.Pkp &


x.50/51Pi.Op.PhA
SET [x.50/51Pi.Opt_Trp/Alm]=Trp

&
x.50/51Pi.Alm_A
SET [x.50/51Pi.Opt_Trp/Alm]=Alm

SIG x.50/51Pi.StA
>=1
SIG x.50/51Pi.StB x.50/51Pi.St

SIG x.50/51Pi.StC

SIG x.50/51Pi.Op.PhA
>=1
SIG x.50/51Pi.Op.PhB x.50/51Pi.Op

SIG x.50/51Pi.Op.PhC

SIG x.50/51Pi.Alm_A
>=1
SIG x.50/51Pi.Alm_B x.50/51Pi.Alm

SIG x.50/51Pi.Alm_C

Figure 3.12-12 Logic of phase overcurrent protection

3.12.5 Settings
Table 3.12-3 Settings of phase overcurrent protection

No. Name Range Unit Default Description


10.000~100.0 Low voltage setting of
1 x.50/51P.VCE.Upp V 70.000
00 voltage control element
Negative-sequence voltage
2 x.50/51P.VCE.U2 2.000~57.000 V 8.000 setting of voltage control
element
Zero-sequence voltage
3 x.50/51P.VCE.3U0 2.000~57.000 V 8.000
setting of voltage control

PCS-978S Transformer Relay 3-105


Date: 2022-01-17
3 Protection Functions

No. Name Range Unit Default Description


element
Enabling/Disabling phase
overcurrent protection with
voltage control element is
Disabled
4 x.50/51P.VCE.En_VTS_Blk - Disabled blocked by VT circuit failure
Enabled
when VT circuit supervision
is enabled and VT circuit
fails
The characteristic angle of
5 x.50/51P.DIR.RCA -180~179 ° 45
3 direction control element
The minimum boundary in
6 x.50/51P.DIR.phi_Min_Fwd 10~90 ° 90 forward direction of phase
overcurrent protection
The maximum boundary in
7 x.50/51P.DIR.phi_Max_Fwd 10~90 ° 90 forward direction of phase
overcurrent protection
The minimum boundary in
8 x.50/51P.DIR.phi_Min_Rev 10~90 ° 90 reverse direction of phase
overcurrent protection
The maximum boundary in
9 x.50/51P.DIR.phi_Max_Rev 10~90 ° 90 reverse direction of phase
overcurrent protection
The voltage polarization
mode of direction control
element
Upp: phase-to-phase
Upp voltage is used as polarized
10 x.50/51P.DIR.Opt_PolarizedVolt Up - Upp voltage
U1 Up: phase-to-ground voltage
is used as polarized
voltage
U1: positive-sequence
voltage is used as polarized
The minimum operating
11 x.50/51P.DIR.I_Min 0.050~1.000 In 0.050 current setting of direction
control element
The minimum operating
12 x.50/51P.DIR.U_Min 1.000~10.000 V 4.000 voltage setting of direction
control element
Enabling/Disabling phase
Disabled overcurrent protection with
13 x.50/51P.DIR.En_VTS_Blk - Disabled
Enabled direction control element is
blocked by VT circuit failure

3-106 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

No. Name Range Unit Default Description


when VT circuit supervision
is enabled and VT circuit
fails
The coefficient of second
14 x.50/51P.HMB.K_Hm2 0.100~1.000 - 0.200 harmonics of harmonic
control element
The current setting of
2.000~150.00
15 x.50/51P.HMB.I_Rls A 20.000 releasing harmonic control
0
element
The option of harmonic 3
blocking mode
PhaseBlk,
PhaseBlk: phase blocking
16 x.50/51P.HMB.Opt_Blk CrossBlk, - PhaseBlk
CrossBlk: cross blocking
MaxPhaseBlk
MaxPhaseBlk: maximum
phase blocking
The current setting for stage
0.050~200.00
17 x.50/51Pi.I_Set A 15.000 i of phase overcurrent
0
protection (i=1~6)
The operating time delay for
0.000~100.00
18 x.50/51Pi.t_Op s 0.100 stage i of phase overcurrent
0
protection (i=1~6)
The dropout time delay for
0.000~100.00
19 x.50/51Pi.t_DropOut s 0.000 stage i of phase overcurrent
0
protection (i=1~6)
Enabling/Disabling stage i of
Disabled phase overcurrent protection
20 x.50/51Pi.En_Volt_Blk - Disabled
Enabled controlled by voltage control
element (i=1~6)
The option direction
NonDirectional
NonDirec characteristic for stage i of
21 x.50/51Pi.Opt_Dir Forward -
tional phase overcurrent protection
Reverse
(i=1~6)
Enabling/Disabling stage i of
Disabled phase overcurrent protection
22 x.50/51Pi.En_Hm_Blk - Disabled
Enabled controlled by harmonic
control element (i=1~6)
Enabling/disabling stage i of
Disabled
23 x.50/51Pi.En - Enabled phase overcurrent protection
Enabled
(i=1~6)
Enabling/disabling stage i of
Trp phase overcurrent protection
24 x.50/51Pi.Opt_Trp/Alm - Trp
Alm operate to trip or alarm
(i=1~6)

PCS-978S Transformer Relay 3-107


Date: 2022-01-17
3 Protection Functions

No. Name Range Unit Default Description


Trp: for tripping purpose
Alm: for alarm purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
ANSILTV The option of operating

3 25 x.50/51Pi.Opt_Curve
ANSILT
IECN
-
IECDefTi
me
characteristics curve
stage i of phase overcurrent
for

IECV protection (i=1~6)


IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of dropout
characteristics curve for
stage i of phase overcurrent
protection (i=1~6)
Inst
Inst: instantaneous dropout
26 x.50/51Pi.Opt_Curve_DropOut DefTime - Inst
characteristics
IDMT
DefTime: definite-time
dropout characteristics
IDMT: inverse-time dropout
characteristics
Time multiplier setting for
stage i of inverse-time phase
27 x.50/51Pi.TMS 0.040~20.000 - 1.000
overcurrent protection
(i=1~6)
The minimum operating time
for stage i of inverse-time
28 x.50/51Pi.tmin 0.000~10.000 s 0.020
phase overcurrent protection
(i=1~6)
The constant “K” for stage i
0.0010~120.0 of customized inverse-time
29 x.50/51Pi.K - 0.1400
000 phase overcurrent protection
(i=1~6)
The constant “α” for stage i
0.0100~3.000
30 x.50/51Pi.Alpha - 0.0200 of customized inverse-time
0
phase overcurrent protection

3-108 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

No. Name Range Unit Default Description


(i=1~6)
The constant “C” for stage i
0.0000~1.000 of customized inverse-time
31 x.50/51Pi.C - 0.0000
0 phase overcurrent protection
(i=1~6)

3.13 Earth Fault Overcurrent Protection (50/51G)

Under normal conditions, three phases of the power system is symmetrical, its zero-sequence
current and voltage are zero theoretically. Most of the faults are asymmetrical, so various 3
protections reflect sequence component principle can be fulfilled based on the fault's
asymmetrical characteristics. Earth fault protection has been widely used in power systems, it can
be applied for the fault as long as there is zero-sequence current, including single-phase earth
fault and phase-to-phase short-circuit earth fault etc.

3.13.1 Function Description


The device can provide 4 stages of earth fault protection with independent logic by default. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics. It
can be chosen whether it is blocked by harmonic control element. The direction control element
can be set as no direction, forward direction and reverse direction. The zero-sequence current
used by earth fault protection can derived from calculated zero-sequence current or measured
zero-sequence current.

Earth fault protection can operate to trip or alarm and can be enabled or disabled via the settings
or the signals, for some specific applications, this protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block earth fault
protection.

EN [x.50/51Gi.En] &
x.50/51Gi.On
SIG x.50/51Gi.Enable
&
SIG x.50/51Gi.Block >=1 x.50/51Gi.Blocked

SIG Fail_Device
&
x.50/51Gi.Valid

Figure 3.13-1 Logic of enabling earth fault protection

The pickup logic of earth fault protection is shown in Figure 3.13-2.

PCS-978S Transformer Relay 3-109


Date: 2022-01-17
3 Protection Functions

SET x.3I0>0.95×[x.50/51Gi.3I0_Set] & x.50/51Gi.Pkp


0 500ms &
SIG x.50/51Gi.On &
FD.Pkp
SIG x.50/51Gi.Valid

SET [x.50/51Gi.Opt_Trp/Alm]=Alm

Figure 3.13-2 Pickup logic of earth fault protection

3.13.1.1 Direction Control Element

3 In order to ensure the selectivity of earth fault protection, direction control element can be
available. The setting [x.50/51Gi.Opt_Dir] (i=1~4) is used to select the direction characteristics for
each stage of earth fault protection: no direction, forward direction and reverse direction are
selectable. The operation boundary of the forward direction element can be set by
[x.50/51G.DIR.phi_Min_Fwd] and [x.50/51G.DIR.phi_Max_Fwd]. The operation boundary of the
reverse direction element can be set by [x.50/51G.DIR.phi_Min_Rev] and
[x.50/51G.DIR.phi_Max_Rev].

-U0

[x.50/51G.DIR.phi_Min_Fwd]

Non-operating I0
area

Operating area in
[x.50/51G.DIR.phi_Max_Rev] forward direction

[x.50/51G.DIRRCA]

Operating area in
reverse direction

[x.50/51G.DIR.phi_Max_Fwd]

Non-operating
area
[x.50/51G.DIR.phi_Min_Rev]

Figure 3.13-3 Operating characteristics of direction control element

The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode.

3-110 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

Polarization Polarized
Operating current Angle difference
mode voltage
Calculated residual current:
- 3U0 Angle=Angle(-3U0)-Angle(3I0_Cal)-RCA
Zero-sequence 3I0_Cal
voltage polarized Measured residual current:
- 3U0 Angle=Angle(-3U0)-Angle(3I0_Ext)-RCA
3I0_Ext

The direction element calculation needs to judge the current threshold and voltage threshold. The
corresponding operating current must be greater than the minimum operating current setting
[x.50/51G.DIR.3I0_Min], otherwise the direction element can‘t operate. The polarized voltage
must be greater than the minimum operating voltage setting [x.50/51G.DIR.3U0_Min], otherwise
the direction element can’t operate. 3
The logic of forward direction element and reverse direction element are shown in Figure 3.13-4.

For transformers, the polarity of neutral-point CT is at grounding side by


default. So, in case of an out-of-zone fault, the directions of calculated
residual current and external residual current are reversed, and the
method of calculating angle difference is the same, which should be noted
when setting the characteristic angle.

PCS-978S Transformer Relay 3-111


Date: 2022-01-17
3 Protection Functions

EN [x.50/51G.DIR.En_VTS_Blk] &

SIG x.VTS.Alm & >=1


&
SIG x.3I0_Ext, x.3I0_Cal x.50/51G.DIR.Fwd

Forward direction
criterion
3 SIG x.3U0_Cal

BI x.BI_En_VT &

EN [x.En_VT]

SET x.Iop>[x.50/51G.DIR.3I0_Min]

SET x.Upo>[x.50/51G.DIR.3U0_Min]

EN [x.50/51G.DIR.En_VTS_Blk] &

SIG x.VTS.Alm & >=1


&
SIG x.3I0_Ext, x.3I0_Cal x.50/51G.DIR.Rev
Reverse direction
criterion

SIG x.3U0_Cal

BI x.BI_En_VT &

EN [x.En_VT]

SET x.Iop>[x.50/51G.DIR.3I0_Min]

SET x.Upo>[x.50/51G.DIR.3U0_Min]

Figure 3.13-4 Logic of forward and reverse direction element

Where:

x.3I0_Ext is the measured residual current.

x.3I0_Cal is the calculated residual current.

x.3U0_Cal is the calculated residual voltage.

3-112 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

x.Iop: the operating current.

x.Upo: the polarized voltage.

3.13.1.2 Harmonic Control Element

Harmonic control element based on zero-sequence current can be used to prevent earth fault
protection from maloperation due to inrush current. Zero-sequence current can be calculated or
measured. When the percentage of second harmonic component to fundamental component in
residual current is greater than the setting [x.50/51G.HMB.K_Hm2], harmonic control element
operates to block earth fault protection if the corresponding setting [x.50/51Gi.En_Hm_Blk] is set
as "Enabled" (i=1~4). When the fundamental component of zero-sequence current is greater than
the setting [x.50/51G.HMB.I_Rls], earth fault protection will be unblocked by harmonic control
3
element. The logic of harmonic control element is shown in Figure 3.13-5.

SET x.3I0>[x.50/51G.HMB.I_Rls]

SIG x.3I0_Ext or x.3I0_Cal


&
x.50/51G.HMB.Op
Harmonic
criterion

SET x.3I0_2nd/3I0>[x.50/51G.HMB.K_Hm2]

Figure 3.13-5 Logic of harmonic control element

Where:

x.3I0_2nd is secondary harmonic component of residual current.

3.13.1.3 Operating Characteristics

Earth fault protection can operate instantaneously or with a fixed time delay. It can also operate
with inverse-time characteristics, and its characteristics curve complies with the standards IEC
60255-3 and ANSI C37.112. Earth fault protection can support definite-time characteristics, IEC &
ANSI standard inverse-time characteristics and user-defined inverse-time characteristics, which
are determined by the setting [x.50/51Gi.Opt_Curve] (i=1~4). The relationship between the setting
and the characteristics curve is shown in the table below.

50/51Gi.Opt_Curve Time Characteristic k α c tr


ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite time - - - -
ANSILTE ANSI Long time extremely inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long time very inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long time inverse 0.086 0.02 0.185 4.6
IECN IEC Normal inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -

PCS-978S Transformer Relay 3-113


Date: 2022-01-17
3 Protection Functions

50/51Gi.Opt_Curve Time Characteristic k α c tr


IECI IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short time inverse 0.05 0.04 0 -
IECLT IEC Long time inverse 120.0 1.0 0 -
IECDefTime IEC Definite time - - - -
UserDefine Programmable

When the setting [x.50/51Gi.Opt_Curve] is set as "UserDefine", it means that user-defined


inverse-time characteristics is selected. These settings [x.50/51Gi.K], [x.50/51Gi.C] and
[x.50/51Gi.Alpha] are valid, and the inverse-time operating curve is determined by the three
3 settings.

 Instantaneous characteristics

When x.3I0>[x.50/51Gi.3I0_Set], earth fault protection operates immediately.

 Definite-time characteristics

When x.3I0>[x.50/51Gi.3I0_Set], earth fault protection operates with a time delay


[x.50/51Gi.t_Op], and the operating characteristics curve is as shown in Figure 3.13-6.

[x.50/51Gi.t_Op]

I0
[x.50/51Gi.3I0_Set]

Figure 3.13-6 Definite-time operating curve of earth fault protection

 Inverse-time characteristics

When x.3I0>[x.50/51Gi.3I0_Set], earth fault protection begins to accumulate, and the operating
time is affected by the applied current x.3I0. The operating time will decrease with the current
increasing, but the operating time shall not less than the setting [x.50/51Gi.tmin] (i=1~4). The
inverse-time operating characteristics equation is:

3-114 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

K
t={ + C} × TMS
x. 3I0 α
( ) −1
I0P

Where:

I0P is the current setting [x.50/51Gi.3I0_Set].

TMS is the inverse-time time multiplier, i.e. the setting [x.50/51Gi.TMS].

K is the inverse-time coefficient, i.e. the setting [x.50/51Gi.K].

C is the inverse-time coefficient, i.e. the setting [x.50/51Gi.C]. 3


α is the inverse-time coefficient, i.e. the setting [x.50/51Gi.Alpha].

x.3I0 is the measured residual current.

The inverse-time operating characteristics curve is shown Figure 3.13-7.

[x.50/51Gi.tmin]

I0
[x.50/51Gi.3I0_Set] ID

Figure 3.13-7 Inverse-time operating curve of earth fault protection

When the applied residual current is not a fixed value, but changes with the time, the operating
behavior of inverse-time earth fault protection is shown in the following equation.

T0
1
∫ dt = 1
t(x. 3I0 )
0

Where:

T0 is the operating time of the protection element.

t(x.3I0) is the theoretical operating time when the current is x.3I0.

PCS-978S Transformer Relay 3-115


Date: 2022-01-17
3 Protection Functions

3.13.1.4 Dropout Characteristics

The supported dropout characteristics of earth fault protection include instantaneous, definite-time
and ANSI inverse-time characteristics. When the operating characteristics curve is selected as
definite-time, IEC inverse-time or user-defined inverse-time characteristics, the dropout
characteristic curve can only be selected as instantaneous or definite-time characteristics, and the
alarm signal "Fail_Settings" will be issued and the device will be blocked if ANSI inverse-time
characteristics is selected. When the operating characteristics curve is selected as ANSI
inverse-time characteristics, the dropout characteristic curve can be selected as instantaneous,
definite-time and ANSI inverse-time characteristics.

3  Instantaneous characteristics

When x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection drops out immediately.

 Definite-time characteristics

When x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection drops out with a time delay
[x.50/51Gi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among
start signal, operating signal and the counter is as shown in Figure 3.13-8.

Start time

x.3I0>[x.50/51Gi.3I0_Set]

x.50/51Gi.St

x.50/51Gi.Op

[x.50/51Gi.t_Op] Earth fault protection


operating

Operating counter

[x.50/51Gi.t_DropOut]
[x.50/51Gi.t_DropOut] [x.50/51Gi.t_DropOut]
Dropout time
Dropout time

Figure 3.13-8 Definite-time dropout characteristics of earth fault protection

 Inverse-time characteristics

3-116 PCS-978S Transformer Relay

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When x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection begins to accumulate, the


accumulated value after tP (Assuming tP is less than the theoretical operating time) is calculated
according to the following equation.

tP
1
Itp = ∫ dt
t(x. 3I0 )
0

If x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection begins to drop out, and the dropout
characteristics meets the following equations.

tR

Itp − ∫
1
t R (x. 3I0 )
dt = 0 3
0

tr
t R (x. 3I0 ) = 2 × TMS
x. 3I0
{1 − ( I0P } )

Where:

tR is the dropout time.

I0P is zero-sequence current setting [x.50/51Gi.3I0_Set].

TMS is the inverse-time time multiplier, i.e., the setting [x.50/51Gi.TMS].

tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
earth fault protection operates.

x.3I0 is the measured residual current.

If 0.95×[x.50/51Gi.3I0_Set]< x.3I0<[x.50/51Gi.3I0_Set], the counter will neither accumulate nor


drop out.

The inverse-time dropout characteristics curve is shown in Figure 3.13-9.

PCS-978S Transformer Relay 3-117


Date: 2022-01-17
3 Protection Functions

3 tr

I0
[x.50/51Gi.3I0_Set]

Figure 3.13-9 Inverse-time dropout curve of earth fault protection

The sequence diagram of inverse-time dropout characteristics among start signal, operating
signal and the counter is shown in the following figure.

Start time

x.3I0>[x.50/51Gi.3I0_Set]

x.50/51Gi.St

x.50/51Gi.Op

Earth fault protection operating


[x.50/51Gi.t_Op]

Operating counter

Dropout time Coefficient (tr)

Dropout time
Dropout time

Figure 3.13-10 Inverse-time dropout characteristics of earth fault protection

3-118 PCS-978S Transformer Relay

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3 Protection Functions

3.13.2 Function Block Diagram

x.50/51G.HMB

x.50/51G.HMB.in_I3P x.50/51G.HMB.Op

x.50/51G.HMB.in_I1P

x.50/51G.DIR

x.50/51G.DIR.in_I3P x.50/51G.DIR.Fwd

x.50/51G.DIR.in_I1P x.50/51G.DIR.Rev
3
x.50/51G.DIR.in_U3P

x.50/51Gi

x.50/51Gi.in_I3p x.50/51Gi.St

x.50/51Gi.in_I1p x.50/51Gi.Op

x.50/51Gi.Enable x.50/51Gi.On

x.50/51Gi.Block x.50/51Gi.Blocked

x.50/51Gi.FwdDir x.50/51Gi.Valid

x.50/51Gi.RevDir x.50/51Gi.Alm

x.50/51Gi.HMB

“x.50/51G.HMB” is the harmonic control element in 50/51G.

“x.50/51G.DIR” is the direction control element in 50/51G.

“x.50/51Gi” is the stage i of earth fault overcurrent element.

3.13.3 I/O Signal


Table 3.13-1 Input signals of earth fault protection

No. Input signal Description


1 x.50/51G.HMB.in_I3P Three-phase current data input for harmonic control element
2 x.50/51G.HMB.in_I1P Single-phase current data input for harmonic control element
3 x.50/51G.DIR.in_I3P Three-phase current data input for direction control element
4 x.50/51G.DIR.in_I1P Single-phase current data input for direction control element
5 x.50/51G.DIR.in_U3P Three-phase voltage data input for direction control element
6 x.50/51Gi.in_I3P Three-phase current data input for earth fault protection (i=1~4)

PCS-978S Transformer Relay 3-119


Date: 2022-01-17
3 Protection Functions

No. Input signal Description


7 x.50/51Gi.in_I1P Single-phase current data input for earth fault protection (i=1~4)
8 x.50/51Gi.Enable Input signal of enabling stage i of earth fault protection (i=1~4)
9 x.50/51Gi.Block Input signal of blocking stage i of earth fault protection (i=1~4)
10 x.50/51Gi.FwdDir Input signal of forward direction element of stage i of earth fault protection (i=1~4)
11 x.50/51Gi.RevDir Input signal of reverse direction element of stage i of earth fault protection (i=1~4)
12 x.50/51Gi.HMB Input signal of harmonic control element of stage i of earth fault protection (i=1~4)

Table 3.13-2 Output signals of earth fault protection

No. Output signal Description


3 1 x.50/51G.HMB.Op The harmonic control element of earth fault protection operates.
2 x.50/51G.DIR.Fwd The forward direction element of earth fault protection operates.
3 x.50/51G.DIR.Rev The reverse direction element of earth fault protection operates.
4 x.50/51Gi.St Stage i of earth fault protection starts. (i=1~4)
5 x.50/51Gi.Op Stage i of earth fault protection operates. (i=1~4)
6 x.50/51Gi.On Stage i of earth fault protection is enabled. (i=1~4)
7 x.50/51Gi.Blocked Stage i of earth fault protection is blocked. (i=1~4)
8 x.50/51Gi.Valid Stage i of earth fault protection is valid. (i=1~4)
9 x.50/51Gi.Alm Stage i of earth fault protection alarms. (i=1~4)

3.13.4 Logic

SET x.3I0>[x.50/51Gi.3I0_Set]

SIG X.50/51G.DIR.Fwd x.50/51Gi.St


&
selection
Direction

SIG x.50/51G.DIR.Rev & Timer


t
SET [x.50/51Gi.Opt_Dir] t

SIG x.50/51G.HMB.Op &

EN [x.50/51Gi.En_Hm_Blk]

SIG x.50/51Gi.Pkp
&
x.50/51Gi.Op
SET [x.50/51Gi.Opt_Trp/Alm]=Trp

&
x.50/51Gi.Alm
SET [x.50/51Gi.Opt_Trp/Alm]=Alm

Figure 3.13-11 Logic diagram of earth fault overcurrent protection

3.13.5 Settings
Table 3.13-3 Settings of earth fault overcurrent protection

No. Name Range Unit Default Description

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No. Name Range Unit Default Description


The characteristic angle of
1 x.50/51G.DIR.RCA -180~179 ° 45
direction control element
The minimum boundary in
2 x.50/51G.DIR.phi_Min_Fwd 10~90 ° 90 forward direction of earth
fault protection
The maximum boundary in
3 x.50/51G.DIR.phi_Max_Fwd 10~90 ° 90 forward direction of earth
fault protection
The minimum boundary in
4 x.50/51G.DIR.phi_Min_Rev 10~90 ° 90 reverse direction of earth 3
fault protection
The maximum boundary in
5 x.50/51G.DIR.phi_Max_Rev 10~90 ° 90 reverse direction of earth
fault protection
The minimum operating
6 x.50/51G.DIR.3I0_Min 0.050~1.000 In 0.050 current setting of
direction control element
The minimum operating
7 x.50/51G.DIR.3U0_Min 1.000~10.000 V 4.000 voltage setting of
direction control element
Enabling/Disabling earth
fault protection with
direction control element is
Disabled
8 x.50/51G.DIR.En_VTS_Blk - Disabled blocked by VT circuit failure
Enabled
when VT circuit supervision
is enabled and VT circuit
fails
The option of the residual
current used by earth fault
protection with direction
Ext control element
9 x.50/51G.DIR.Opt_3I0 - Ext
Cal Ext: the measured residual
current
Cal: the calculated residual
current
The coefficient of second
10 x.50/51G.HMB.K_Hm2 0.100~1.000 - 0.200 harmonics of harmonic
control element
The current setting of
11 x.50/51G.HMB.I_Rls 2.000~150.000 A 20.000 releasing harmonic control
element
Ext The option of the residual
12 x.50/51G.HMB.Opt_3I0 - Ext
Cal current used by earth fault

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No. Name Range Unit Default Description


overcurrent protection with
harmonic control element
Ext: the measured residual
current
Cal: the calculated residual
current
The option of the residual
current used by earth fault
overcurrent protection
Ext
3 13 x.50/51Gi.Opt_3I0
Cal
- Ext Ext: the measured residual
current
Cal: the calculated residual
current
The zero-sequence current
14 x.50/51Gi.3I0_Set 0.050~200.000 A 15.000 setting for stage i of earth
fault protection (i=1~40)
The operating time delay
15 x.50/51Gi.t_Op 0.000~100.000 s 0.100 for stage i of earth fault
protection (i=1~4)
The dropout time delay for
16 x.50/51Gi.t_DropOut 0.000~100.000 s 0.000 stage i of earth fault
protection (i=1~4)
The option direction
NonDirectional
characteristic for stage i of
17 x.50/51Gi.Opt_Dir Forward - NonDirectional
earth fault protection
Reverse
(i=1~4)
Enabling/Disabling stage i
Disable of earth fault protection
18 x.50/51Gi.En_Hm_Blk - Disabled
Enabled controlled by harmonic
control element (i=1~4)
Enabling/disabling stage i
Disabled
19 x.50/51Gi.En - Enabled of earth fault protection
Enabled
(i=1~4)
Enabling/disabling stage i
of earth fault protection
Trp operate to trip or alarm
20 x.50/51Gi.Opt_Trp/Alm - Trp
Alm (i=1~4)
Trp: for tripping purpose
Alm: for alarm purpose
ANSIE The option of operating
ANSIV characteristics curve for
21 x.50/51Gi.Opt_Curve - IECDefTime
ANSIN stage i of earth fault
ANSIM protection (i=1~4)

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No. Name Range Unit Default Description


ANSIDefTime
ANSILTE
ANSILTV
ANSILT
IECN
IECV
IECI
IECE
IECST
IECLT
IECDefTime
3
UserDefine
The option of dropout
characteristics curve for
stage i of earth fault
protection (i=1~4)
Inst
Inst: instantaneous dropout
22 x.50/51Gi.Opt_Curve_DropOut DefTime - Inst
characteristics
IDMT
DefTime: definite-time
dropout characteristics
IDMT: inverse-time dropout
characteristics
Time multiplier setting for
stage i of inverse-time
23 x.50/51Gi.TMS 0.040~20.000 - 1.000
earth fault protection
(i=1~4)
The minimum operating
time for stage i of
24 x.50/51Gi.tmin 0.000~10.000 s 0.020
inverse-time earth fault
protection (i=1~4)
The constant “K” for stage i
of customized inverse-time
25 x.50/51Gi.K 0.0010~120.0000 - 0.1400
earth fault protection
(i=1~4)
The constant “α” for stage i
of customized inverse-time
26 x.50/51Gi.Alpha 0.0100~3.0000 - 0.0200
earth fault protection
(i=1~4)
The constant “C” for stage i
of customized inverse-time
27 x.50/51Gi.C 0.0000~1.0000 - 0.0000
earth fault protection
(i=1~4)

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3 Protection Functions

3.14 Negative-sequence Overcurrent Protection (50/51Q)

When a phase-to-phase fault occurs in the system, the fault current is small, and phase current
criterion may not detect the fault. At this time, negative-sequence overcurrent protection is
sensitive to the fault and can be used. Negative-sequence overcurrent protection can also be
used to detect pole disagreement operation or unbalanced load.

3.14.1 Function Description

The device can provide two stages of negative-sequence overcurrent protection with independent

3 logic. Each stage can be independently set as definite-time characteristics or inverse-time


characteristics. For parallel lines or a ring network line, the flow direction of negative-sequence
current may be different. Considering the selectivity of negative-sequence overcurrent protection,
the direction control element can be set as no direction, forward direction and reverse direction.

Negative-sequence overcurrent protection can operate to trip or alarm and can be enabled or
disabled via the settings or the signals, for some specific applications, negative-sequence
overcurrent protection needs to be blocked by the external signal, so the device provides a
function block input signal to be used to block negative-sequence overcurrent protection.

EN [x.50/51Qi.En] &
x.50/51Qi.On
SIG x.50/51Qi.Enable
&
SIG x.50/51Qi.Block >=1 x.50/51Qi.Blocked

SIG Fail_Device
&
x.50/51Qi.Valid

Figure 3.14-1 Logic of enabling negative-sequence overcurrent protection

The pickup logic of negative-sequence overcurrent protection is shown in Figure 3.13-2.

SET x.I2>0.95×[x.50/51Qi.I2_Set] & x.50/51Qi.Pkp


0 500ms &
SIG x.50/51Qi.On &
FD.Pkp
SIG x.50/51Qi.Valid

SET [x.50/51Qi.Opt_Trp/Alm]=Alm

Figure 3.14-2 Pickup logic of negative-sequence protection

3.14.1.1 Direction Control Element

In order to ensure the selectivity of negative-sequence overcurrent protection, direction control


element can be available. The setting [x.50/51Qi.Opt_Dir] (i=1 or 2) is used to select the direction

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characteristics for each stage of negative-sequence overcurrent protection: no direction, forward


direction and reverse direction are selectable. The direction control element selects
negative-sequence voltage as the polarized voltage, its operating characteristics is shown in
Figure 3.14-3.

The operation boundary of the forward direction element can be set by


[x.50/51Q.DIR.phi_Min_Fwd] and [x.50/51Q.DIR.phi_Max_Fwd]. The operation boundary of the
reverse direction element can be set by [x.50/51Q.DIR.phi_Min_Rev] and
[x.50/51Q.DIR.phi_Max_Rev].

-U2
3
[x.50/51Q.DIR.phi_Min_Fwd]

Non-operating I2
area
[x.50/51Q.DIR.phi_Max_Rev]
Operating area in
forward direction

[x.50/51Q.DIR.RCA]

Operating area in
reverse direction

[x.50/51Q.DIR.phi_Max_Fwd]
Non-operating
area

[x.50/51Q.DIR.phi_Min_Rev]

Figure 3.14-3 Operating characteristics of direction control element

The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode.

Polarized
Polarization mode Operating current Angle difference
voltage
Negative-sequence
Negative-sequence current: I2 -U2 Angle=Angle(-U2)-Angle(I2)-RCA
voltage polarized

The direction element calculation needs to judge the current threshold and voltage threshold. The
corresponding operating current must be greater than the minimum operating current setting
[x.50/51Q.DIR.I2_Min], otherwise the direction element can’t operate. The polarized voltage must
be greater than the minimum operating voltage setting [x.50/51Q.DIR.U2_Min], otherwise the
direction element can’t operate.

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The logic of forward direction element and reverse direction element are shown in Figure 3.14-4.

EN [x.50/51Q.DIR.En_VTS_Blk] &

SIG x.VTS.Alm & >=1


&
SIG x.I2 x.50/51Q.DIR.Fwd

Forward direction
3 criterion
SIG x.U2

SIG x.BI_En_VT &

EN [x.En_VT]

SET x.Iop>[x.50/51Q.DIR.I2_Min]

SET x.Upo>[x.50/51Q.DIR.U2_Min]

EN [x.50/51Q.DIR.En_VTS_Blk] &

SIG x.VTS.Alm & >=1


&
SIG x.I2 x.50/51Q.DIR.Rev
Reverse direction
criterion

SIG x.U2

SIG x.BI_En_VT &

EN [x.En_VT]

SET x.Iop>[x.50/51Q.DIR.I2_Min]

SET x.Upo>[x.50/51Q.DIR.U2_Min]

Figure 3.14-4 Logic of forward and reverse direction element

3.14.1.2 Operating Characteristics

Negative-sequence overcurrent protection can operate instantaneously or with a fixed time delay.
It can also operate with inverse-time characteristics, and its characteristics curve complies with
the standards IEC 60255-3 and ANSI C37.112. Negative-sequence overcurrent protection can
support definite-time characteristics, IEC & ANSI standard inverse-time characteristics and

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user-defined inverse-time characteristics, which are determined by the setting


[x.50/51Qi.Opt_Curve] (i=1 or 2). The relationship between the setting and the characteristics
curve is shown in the table below.

50/51Qx.Opt_Curve Time Characteristic k α c tr


ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite time - - - -
ANSILTE ANSI Long time extremely inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long time very inverse 28.55 2.0 0.712 13.46
3
ANSILT ANSI Long time inverse 0.086 0.02 0.185 4.6
IECN IEC Normal inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -
IECI IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short time inverse 0.05 0.04 0 -
IECLT IEC Long time inverse 120.0 1.0 0 -
IECDefTime IEC Definite time - - - -
UserDefine Programmable

When the setting [x.50/51Qi.Opt_Curve] is set as "UserDefine", it means that user-defined


inverse-time characteristics is selected. These settings [x.50/51Qi.K], [x.50/51Qi.C] and
[x.50/51Qi.Alpha] are valid, and the inverse-time operating curve is determined by the three
settings.

 Instantaneous characteristics

When x.I2>[x.50/51Qi.I2_Set], negative-sequence overcurrent protection operates immediately.

 Definite-time characteristics

When x.I2>[x.50/51Qi.I2_Set], negative-sequence overcurrent protection operates with a time


delay [x.50/51Qi.t_Op], the operating characteristics curve is as shown in Figure 3.14-5.

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[x.50/51Qi.t_Op]

3
I2
[x.50/51Qi.I2_Set]

Figure 3.14-5 Definite-time operating curve of negative-sequence overcurrent protection

 Inverse-time characteristics

When x.I2>[x.50/51Qi.I2_Set], negative-sequence overcurrent protection begins to accumulate,


and the operating time is affected by the applied current x.I2. The operating time will decrease
with the current increasing, but the operating time shall not less than the setting [x.50/51Qi.tmin]
(i=1 or 2). The inverse-time operating characteristics equation is:

K
t={ + C} × TMS
x. I2 α
(I ) −1
2P

Where:

I2P is the current setting [x.50/51Qi.I2_Set].

TMS is the inverse-time time multiplier, i.e. the setting [x.50/51Qi.TMS].

K is the inverse-time coefficient, i.e. the setting [x.50/51Qi.K].

C is the inverse-time coefficient, i.e. the setting [x.50/51Qi.C].

α is the inverse-time coefficient, i.e. the setting [x.50/51Qi.Alpha].

x.I2 is the measured negative-sequence current.

The inverse-time operating characteristics curve is shown Figure 3.14-6.

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[x.50/51Qi.tmin]
3

I2
[x.50/51Qi.I2_Set] ID

Figure 3.14-6 Inverse-time operating curve of negative-sequence overcurrent protection

When the applied negative-sequence current is not a fixed value, but changes with the time, the
operating behavior of inverse-time negative-sequence overcurrent protection is shown in the
following equation.

T0
1
∫ dt = 1
t(x. I2 )
0

Where:

T0 is the operating time of the protection element.

t(x.I2) is the theoretical operating time when the current is x.I2.

3.14.1.3 Dropout Characteristics

The supported dropout characteristics of negative-sequence overcurrent protection include


instantaneous, definite-time and ANSI inverse-time characteristics. When the operating
characteristics curve is selected as definite-time, IEC inverse-time or user-defined inverse-time
characteristics, the dropout characteristic curve can only be selected as instantaneous or
definite-time characteristics, and the alarm signal "Fail_Settings" will be issued and the device
will be blocked if ANSI inverse-time characteristics is selected. When the operating characteristics
curve is selected as ANSI inverse-time characteristics, the dropout characteristic curve can be
selected as instantaneous, definite-time and ANSI inverse-time characteristics.

 Instantaneous characteristics

When x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection drops out


immediately.

 Definite-time characteristics

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When x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection drops out with a


time delay [x.50/51Qi.t_DropOut], and the sequence diagram of definite-time dropout
characteristic among start signal, operating signal and the counter is as shown in Figure 3.14-7.

Start time

x.I2>[x.50/51Qi.I2_Set]

3 x.50/51Qi.St

x.50/51Qi.Op

[x.50/51Qi.t_Op] Negative-sequence overcurrent


protection operating

Operating counter

[x.50/51Qi.t_DropOut]
[x.50/51Qi.t_DropOut] [x.50/51Qi.t_DropOut]
Dropout time
Dropout time

Figure 3.14-7 Definite-time dropout characteristics of negative-sequence overcurrent protection

 Inverse-time characteristics

When x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection begins to


accumulate, the accumulated value after tP (Assuming tP is less than the theoretical operating
time) is calculated according to the following equation.

tP
1
Itp = ∫ dt
t(x. I2 )
0

If x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection begins to drop out, and


the dropout characteristics meets the following equations.

tR
1
Itp − ∫ dt = 0
t R (x. I2 )
0

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tr
t R (I2 ) = { } × TMS
x. I2 2
1−( )
I2P

Where:

tR is the dropout time.

I2P is negative-sequence current setting [x.50/51Qi.I2_Set].

TMS is the inverse-time time multiplier, i.e., the setting [x.50/51Qi.TMS].

tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after 3
negative-sequence overcurrent protection operates.

x.I2 is the measured negative-sequence current.

If 0.95×[x.50/51Qi.I2_Set]< x.I2<[x.50/51Qi.I2_Set], the counter will neither accumulate nor drop


out.

The inverse-time dropout characteristics curve is shown in Figure 3.14-8.

tr

I2
[x.50/51Qi.I2_Set]

Figure 3.14-8 Inverse-time dropout curve of negative-sequence overcurrent protection

The sequence diagram of inverse-time dropout characteristics among start signal, operating
signal and the counter is shown in Figure 3.14-9.

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Start time

x.I2>[x.50/51Qi.I2_Set]

x.50/51Qi.St

x.50/51Qi.Op

3 [x.50/51Qi.t_Op]
Negative-sequence overcurrent
protection operating

Operating counter

Dropout time Coefficient (tr)

Dropout time
Dropout time

Figure 3.14-9 Inverse-time dropout characteristics of negative-sequence overcurrent protection

3.14.2 Function Block Diagram

x.50/51Q.DIR

x.50/51Q.DIR.in_I3P x.50/51Q.DIR.Fwd

x.50/51Q.DIR.in_U3P x.50/51Q.DIR.Rev

x.50/51Qi

x.50/51Qi.in_I3P x.50/51Qi.St

x.50/51Qi.Enable x.50/51Qi.Op
x.50/51Qi.On
x.50/51Qi.Block
x.50/51Qi.Blocked
x.50/51Q.FwdDir
x.50/51Qi.Valid
x.50/51Q.RevDir
x.50/51Qi.Alm

“x.50/51Q.DIR” is the direction control element in 50/51Q.

“x.50/51Qi” is the stage i of negative-sequence overcurrent element.

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3.14.3 I/O Signal


Table 3.14-1 Input signals of negative-sequence overcurrent protection

No. Input signal Description


Three-phase current data input for negative-sequence overcurrent
1 x.50/51Qi.in_I3P
protection (i=1~2)
Input signal of enabling stage i of negative-sequence overcurrent protection
2 x.50/51Qi.Enable
(i=1~2)
Input signal of blocking stage i of negative-sequence overcurrent protection
3 x.50/51Qi.Block
(i=1~2)

4 x.50/51Qi.FwdDir
Input signal of forward direction element of stage i of negative-sequence 3
overcurrent protection (i=1~2)
Input signal of reverse direction element of stage i of negative-sequence
5 x.50/51Qi.RevDir
overcurrent protection (i=1~2)
Three-phase current data input for direction control element of
6 x.50/51Q.DIR.in_I3P
negative-sequence overcurrent protection
Three-phase voltage data input for direction control element of
7 x.50/51Q.DIR.in_U3P
negative-sequence overcurrent protection

Table 3.14-2 Output signals of negative-sequence overcurrent protection

No. Output signal Description


1 x.50/51Qi.St Stage i of negative-sequence overcurrent protection starts. (i=1~2)
2 x.50/51Qi.Op Stage i of negative-sequence overcurrent protection operates. (i=1~2)
3 x.50/51Qi.On Stage i of negative-sequence overcurrent protection is enabled. (i=1~2)
4 x.50/51Qi.Blocked Stage i of negative-sequence overcurrent protection is blocked. (i=1~2)
5 x.50/51Qi.Valid Stage i of negative-sequence overcurrent protection is valid. (i=1~2)
6 x.50/51Qi.Alm Stage i of negative-sequence overcurrent protection alarm. (i=1~2)
The forward direction element of negative-sequence overcurrent
7 x.50/51Q.DIR.Fwd
protection operates.
The reverse direction element of negative-sequence overcurrent
8 x.50/51Q.DIR.Rev
protection operates.

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3.14.4 Logic

SET x.I2>[x.50/51Qi.I2_Set]
x.50/51Qi.St
SIG x.50/51Q.DIR.Fwd
&
& Timer

selection
Direction
t
SIG x.50/51Q.DIR.Rev
t
SET [x.50/51Qi.Opt_Dir]

SIG x.50/51Qi.Pkp
&
x.50/51Qi.Op
SET [x.50/51Qi.Opt_Trp/Alm]=Trp

3 &
x.50/51Qi.Alm
SET [x.50/51Qi.Opt_Trp/Alm]=Alm

Figure 3.14-10 Logic of negative-sequence overcurrent protection

3.14.5 Settings
Table 3.14-3 Settings of negative-sequence overcurrent protection

No. Name Range Unit Default Description


The characteristic
1 x.50/51Q.DIR.RCA -180~179 ° 45 angle of direction
control element
The minimum
boundary in forward
direction of
2 x.50/51Q.DIR.phi_Min_Fwd 10~90 ° 90
negative-sequence
overcurrent
protection
The maximum
boundary in forward
direction of
3 x.50/51Q.DIR.phi_Max_Fwd 10~90 ° 90
negative-sequence
overcurrent
protection
The minimum
boundary in reverse
direction of
4 x.50/51Q.DIR.phi_Min_Rev 10~90 ° 90
negative-sequence
overcurrent
protection
The maximum
5 x.50/51Q.DIR.phi_Max_Rev 10~90 ° 90 boundary in reverse
direction of

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No. Name Range Unit Default Description


negative-sequence
overcurrent
protection
The minimum
operating current
6 x.50/51Q.DIR.I2_Min 0.050~1.000 In 0.050
setting of direction
control element
The minimum
operating voltage
7 x.50/51Q.DIR.U2_Min 1.000~10.000 V 4.000
setting of direction
control element
3
Enabling/Disabling
negative-sequence
overcurrent
protection with
direction control
Disabled
8 x.50/51Q.DIR.En_VTS_Blk - Disabled element is blocked
Enabled
by VT circuit failure
when VT circuit
supervision is
enabled and VT
circuit fails
The
negative-sequence
current setting for
9 x.50/51Qi.I2_Set 0.050~200.000 A 15.000 stage i of
negative-sequence
overcurrent
protection (i=1 or 2)
The operating time
delay for stage i of
10 x.50/51Qi.t_Op 0.030~100.000 s 0.100 negative-sequence
overcurrent
protection (i=1 or 2)
The dropout time
delay for stage i of
11 x.50/51Qi.t_DropOut 0.000~100.000 s 0.000 negative-sequence
overcurrent
protection (i=1 or 2)
The option direction
NonDirectional
characteristic for
12 x.50/51Qi.Opt_Dir Forward - NonDirectional
stage i of
Reverse
negative-sequence

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No. Name Range Unit Default Description


overcurrent
protection (i=1 or 2)
Enabling/disabling
stage i of
Disabled
13 x.50/51Qi.En - Enabled negative-sequence
Enabled
overcurrent
protection (i=1 or 2)
Enabling/disabling
stage i of

3 negative-sequence
overcurrent
protection operate to
Trp
14 x.50/51Qi.Opt_Trp/Alm - Trp trip or alarm (i=1 or
Alm
2)
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
The option of
ANSILTE
operating
ANSILTV
characteristics curve
ANSILT
15 x.50/51Qi.Opt_Curve - IECDefTime for stage i of
IECN
negative-sequence
IECV
overcurrent
IECI
protection (i=1 or 2)
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
Inst for stage i of
16 x.50/51Qi.Opt_Curve_DropOut DefTime - Inst negative-sequence
IDM overcurrent
protection (i=1 or 2)
Inst: instantaneous
dropout

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No. Name Range Unit Default Description


characteristics
DefTime:
definite-time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage i of

17 x.50/51Qi.TMS 0.040~20.000 - 1.000


inverse-time
negative-sequence
3
overcurrent
protection (i=1 or 2)
The minimum
operating time for
stage i of
18 x.50/51Qi.tmin 0.000~10.000 s 0.020 inverse-time
negative-sequence
overcurrent
protection (i=1 or 2)
The constant “K” for
stage i of customized
inverse-time
19 x.50/51Qi.K 0.0010~120.0000 - 0.1400
negative-sequence
overcurrent
protection (i=1 or 2)
The constant “α” for
stage i of customized
inverse-time
20 x.50/51Qi.Alpha 0.0100~3.0000 - 0.0200
negative-sequence
overcurrent
protection (i=1 or 2)
The constant “C” for
stage i of customized
inverse-time
21 x.50/51Qi.C 0.0000~1.0000 - 0.0000
negative-sequence
overcurrent
protection (i=1 or 2)

PCS-978S Transformer Relay 3-137


Date: 2022-01-17
3 Protection Functions

3.15 Thermal Overload Protection (49)

3.15.1 Application

During overload operation of a power equipment, great current results in greater heat to lead
equipment temperature increase and if the temperature reaches too high values, the equipment
might be damaged. The insulation within the equipment will have forced ageing. As a
consequence of this, the risk of internal phase-to-phase or phase-to-ground faults will increase.
For transformers and reactors, high temperature will degrade the quality of the oil.

3 Thermal overload protection estimates the internal heat content of the equipment (temperature)
continuously. This estimation is made by using a thermal model of the equipment with the time
constants, which is based on current measurement.

3.15.2 Function Description


The device provide two methods to fulfill thermal overload protection, one is to calculate thermal
accumulation according the actual measured current, and the other is applied to the scenario with
oil temperature measurement, it is to calculate temperature difference between winding
temperature and oil temperature according to the measured currents and can gain winding
temperature based on the oil temperature acquired by external transducer.

1. Method 1

Two stages overload protection are available, one stage for alarm purpose and the other stage for
trip purpose. When the temperature increases to the alarm value, thermal overload protection
issues alarm signal to remind the operator for attention, and if the temperature continues to
increase to the trip value, thermal overload protection issues trip command.

There are four thermal overload protection elements at most equipped at each side of transformer.
Thermal overload protection adopts IEC 60255-8 as thermal time characteristic, and fundamental
current or 1st to 11th harmonic current is used for protection calculation.

The device provides a thermal overload model which is based on the IEC60255-8 standard.

t Refer to IEC60255-8

Ip
P=—
IB

P = 0.0
P = 0.6
P = 0.8
P = 0.9

kIB I

Figure 3.15-1 Characteristic curve of thermal overload protection

3-138 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

There are two types of thermal time characteristic, cold start characteristic and hot start
characteristic. The thermal overload formulas are shown as below.

1. Cold start characteristic

I eq
t    ln Equation 3.15-1
I eq  (k  I B )

2. Hot start characteristic

t    ln
I eq  I p
Equation 3.15-2
3
I eq  (k  I B )

Where:

t is the theoretical operate time, following application of the overload current.

τ is the thermal time constant of the protected device, i.e. [x.49.Tau]. When the current I eq is lower
than 0.04In, the thermal time constant adopts the value of [x.49.Tau]*[x.49.C_Disspt].

Ieq is the equivalent heating current, i.e. actual measured current.

IP is the steady-state load current prior to the overload for a duration which would result in
constant thermal level (duration is greater than several time constant τ), which is memory current.
For cold start characteristic, it is zero.

ln is natural logarithm.

IB is the base current, i.e. [x.49.Ib_Set].

k is thermal overload coefficient, i.e. [x.49.K_Alm] or [x.49.K_Trp].

The hot start characteristic is adopted in the device. The calculation is carried out at zero of I P, so
users need not to set the value of IP.

Tripping outputs of the protection is controlled by current, even if the thermal accumulation value
is greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclose, will operate.

2. Method 2

The actual windings temperature can be gained by oil temperature, which is measured by external
transducer (Pt100), plus temperature difference between windings temperature and oil
temperature, i.e.,

T_windings (windings temperature) = T_oil (oil temperature) + T_Diff (temperature difference


between windings and oil)

PCS-978S Transformer Relay 3-139


Date: 2022-01-17
3 Protection Functions

The temperature difference can be calculated according to the current, and is changed with the
current. When the current is increased from 0 to I, the temperature accumulation complies with
the following equation.
t
I
T _ Diff  [ x.49.K _ T _ Diff ]  ( )  (1  e  )
[ x.49.Ib _ Set ]

Finally, stable temperature difference:

I
T _ Diff  [ x.49.K _ T _ Diff ]  ( )
[ x.49.Ib _ Set ]

3 Where:

I is the measured current.

α is cooling factor, taking 1.6 or 2.

t is time.

τ is time constant.

According to the calculated windings temperature, the user can compare it with user-defined
temperature value, and can set stage and time delay to trip or alarm by user-defined logic.

3.15.3 Function Block Diagram

x.49

x.49.in_I3P x.49.Accu_A

x.49.Clr x.49.Accu_B

x.49.Enable .
x.49.Block .
.
x.49.Valid

x.49.Alm

3.15.4 I/O Signals


Table 3.15-1 Input signals of thermal overload protection

No. Input signal Description


1 x.49.in_I3P Three-phase current data input for thermal overload protection at x side of transformer.
Clear command of thermal accumulation value for thermal overload protection at x side
2 x.49.Clr
of transformer.
Input signal of enabling thermal overload protection at x side of transformer. It is triggered
3 x.49.Enable
from binary input or programmable logic etc.
Input signal of blocking thermal overload protection at x side of transformer. It is triggered
4 x.49.Block
from binary input or programmable logic etc.

3-140 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

Table 3.15-2 Output signals of thermal overload protection

No. Output signal Description


1 x.49.Accu_A Phase-A thermal state of thermal overload protection at x side of transformer.
2 x.49.Accu_B Phase-B thermal state of thermal overload protection at x side of transformer.
3 x.49.Accu_C Phase-C thermal state of thermal overload protection at x side of transformer.
The calculated temperature difference of phase-A between winding temperature and oil
4 x.49.T_Diff_A
temperature.
The calculated temperature difference of phase-B between winding temperature and oil
5 x.49.T_Diff_B
temperature.
The calculated temperature difference of phase-C between winding temperature and oil
6 x.49.T_Diff_C
temperature. 3
7 x.49.St Thermal overload protection at x side of transformer starts.
8 x.49.StA Phase-A thermal overload protection at x side of transformer starts.
9 x.49.StB Phase-B thermal overload protection at x side of transformer starts.
10 x.49.StC Phase-C thermal overload protection at x side of transformer starts.
11 x.49.Op Thermal overload protection at x side of transformer operates to trip.
12 x.49.Op.PhA Phase-A thermal overload protection at x side of transformer operates to trip.
13 x.49.Op.PhB Phase-B thermal overload protection at x side of transformer operates to trip.
14 x.49.Op.PhC Phase-C thermal overload protection at x side of transformer operates to trip.
15 x.49.On Thermal overload protection at x side of transformer is enabled.
16 x.49.Blocked Thermal overload protection at x side of transformer is blocked.
17 x.49.Valid Thermal overload protection at x side of transformer is valid.
18 x.49.Alm Thermal overload protection at x side of transformer operates to alarm.

3.15.5 Logic

EN [x.49.En_Trp] >=1

EN [x.49.En_Alm] &
x.49.On
SIG x.49.Enable
&
SIG x.49.Block >=1 x.49.Blocked

SIG Fail_Device
&
x.49.Valid

Figure 3.15-2 Logic diagram of enabling thermal overload protection (method 1)

PCS-978S Transformer Relay 3-141


Date: 2022-01-17
3 Protection Functions

SIG Max(x.Ia, x.Ib, x.Ic)

SET [x.49.Ib_Set] &


0 500ms &
x.49.Pkp
SIG x.49.On
FD.Pkp
SIG x.49.Valid

Figure 3.15-3 Pickup logic of thermal overload protection (method 1)

SIG x.49.Pkp
&
3 SIG x.Ia x.49.StA

& Timer
SET [x.49.Ib_Set] t
x.49.Alm.PhA
t
EN [x.49.En_Alm]

& Timer
t
x.49.Op.PhA
t
EN [x.49.En_Trp]

SIG x.49.Clr

Figure 3.15-4 Logic diagram of thermal overload protection (method 1, phase A)

SIG x.49.StA
>=1
SIG x.49.StB x.49.St

SIG x.49.StC

SIG x.49.Op.PhA
>=1
SIG x.49.Op.PhB x.49.Op

SIG x.49.Op.PhC

SIG x.49.Alm.PhA
>=1
SIG x.49.Alm.PhB x.49.Alm

SIG x.49.Alm.PhC

Figure 3.15-5 Logic diagram of thermal overload protection (method 1)

3.15.6 Settings
Table 3.15-3 Settings of thermal overload protection

No. Item Range Unit Default Description


1 x.49.Ib_Set 0.050~200.000 A 15.000 Base current setting of thermal overload protection
Tripping setting of thermal capacity for thermal
2 x.49.K_Trp 1.000~3.000 - 1.200
overload protection

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Date: 2022-01-17
3 Protection Functions

No. Item Range Unit Default Description


Alarm setting of thermal capacity for thermal
3 x.49.K_Alm 1.000~3.000 - 1.100
overload protection
4 x.49.Tau 0.100~100.000 min 1.000 Thermal time constant setting
The convertor coefficient from the current to the
5 x.49.K_T_Diff 0.000~200.000 - 30.000
temperature
The cooling mode of transformer, usually,
6 x.49.Alpha_Cold 1.000~2.000 - 2.000 natural cooling: 1.6
forced cooling: 2
Heat dissipation time constant setting.

7 x.49.C_Disspt 0.100~10.000 - 1.000


When the equivalent heating current Ieq is lower 3
than 0.04In, the thermal time constant adopts the
value of [x.49.Tau]*[x.49.C_Disspt].
Disabled Logic setting of enabling/disabling thermal overload
8 x.49.En_Trp - Disabled
Enabled protection for trip purpose
Disabled Logic setting of enabling/disabling thermal overload
9 x.49.En_Alm - Disabled
Enabled protection for alarm purpose

3.16 Breaker Failure Protection (50BF)

When a fault happens to the power system, the device will operate to trip the circuit breaker, and
the fault will be isolated by opening the circuit breaker. If the circuit breaker fails to open within the
certain time due to some abnormalities (for example, low tripping pressure), the fault may cause
system stability being destroyed or electrical equipment being damaged. Breaker failure
protection is adopted to issue a backup tripping command to trip adjacent circuit breakers, and
isolate the fault as requested by the device.

According to the tripping information from the device and the auxiliary information (the current and
the circuit breaker position) of target circuit breaker, breaker failure protection constitutes the
criterion to discriminate whether the target circuit fails to open. If the criterion is confirmed, breaker
failure protection will operate to trip the target circuit breaker with the time delay [x.50BF.t_ReTrp],
trip it again with the time delay [x.50BF.t1_Op] and trip the adjacent circuit breakers with the time
delay [x.50BF.t2_Op]. As a special backup protection, breaker failure protection can quickly
isolate the fault, reduce the affected range by the fault, keep system stability and prevent
generators, transformers and other primary equipments from seriously damaged.

3.16.1 Function Description


Breaker failure protection can be current-based, contact-based or an adaptive combination of
these two conditions. Contact check criteria can be used where the fault current through the
breaker is small. The current check criterion and the contact check criterion can be independently
enabled or disabled by the settings [x.50BF.En_Curr] and [x.50BF.En_CBPos]. When both
criterions are enabled, the current check criterion is prior to the contact check criterion.

PCS-978S Transformer Relay 3-143


Date: 2022-01-17
3 Protection Functions

3.16.1.1 Current Check Criterion

The current check criterion includes three kinds of current elements: phase overcurrent element,
zero-sequence overcurrent element and negative-sequence overcurrent element.

1. Phase overcurrent element

𝑥. 𝐼𝜑 > [𝑥. 50𝐵𝐹. 𝐼_𝑆𝑒𝑡]

φ = A, B or C

The phase overcurrent element can be enabled or disabled by the setting [x.50BF.En_Ip]. For
single-phase initiating logic, if corresponding phase current is larger than the setting
3 [x.50BF.I_Set], the current check criterion based on phase overcurrent element meets the
condition. For three-phase initiating logic, if any phase current is larger than the setting
[x.50BF.I_Set], the current check criterion based on phase overcurrent element meets the
condition.

2. Zero-sequence overcurrent element

𝑥. 3𝐼0 > [𝑥. 50𝐵𝐹. 3𝐼0_𝑆𝑒𝑡]

3I0 is calculated residual current

The zero-sequence overcurrent element can be enabled or disabled by the setting


[x.50BF.En_3I0_1P] via single-phase initiating signal or [x.50BF.En_3I0_3P] via three-phase
initiating signal. The zero-sequence overcurrent element can improve the reliability and the
sensitivity. if residual current is larger than the setting [x.50BF.3I0_Set], the current check
criterion based on zero-sequence overcurrent element meets the condition.

3. Negative-sequence overcurrent element

𝑥. 𝐼2 > [𝑥. 50𝐵𝐹. 𝐼2_𝑆𝑒𝑡]

I2 is negative-sequence current

The negative-sequence overcurrent element can be enabled or disabled by the setting


[x.50BF.En_I2_3P]. The negative-sequence overcurrent element can improve the reliability
and the sensitivity. If negative-sequence current is larger than the setting [x.50BF.I2_Set], the
current check criterion based on negative-sequence overcurrent element meets the
condition.

3.16.1.2 Contact Check Criterion

For single-phase initiating logic, if corresponding phase circuit breaker is in closed position, the
contact check criterion meets the condition. For three-phase initiating logic, if any phase circuit
breaker is in closed position, the contact check criterion meets the condition.

3.16.1.3 Operating Characteristics

For breaker failure protection, phase-segregated re-trip, two phases inter-trip three phases,
three-phase re-trip and two time delays are available.

3-144 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

1. Phase-segregated re-trip

For phase-segregated tripping system, breaker failure protection provides phase-segregated


re-trip function. When breaker failure protection receives initiating signal of phase-segregated
tripping and the current check criterion or the contact check criterion meets the condition, the
device will issue phase-segregated tripping command to re-trip the target circuit breaker with
the time delay [x.50BF.t_ReTrp].

When the re-tripping is initiated by two-phase failure, two phase inter-trip three-phases
operates to trip three-phase circuit breaker. When the re-tripping is initiated by three-phase
failure, three-phase re-trip operates to trip three-phase circuit breaker.

2. Three-phase re-trip 3
For non phase-segregated tripping system, breaker failure protection provides three-phases
re-trip function. When breaker failure protection receives initiating signal of three-phases
tripping and the current check criterion or the contact check criterion meets the condition, the
device will issue three-phases tripping command to re-trip the target circuit breaker with the
time delay [x.50BF.t_ReTrp].

3. First time delay

As similar as three-phase re-trip, the device will operate to re-trip the target circuit breaker
again with the time delay [x.50BF.t1_Op] when the relevant operating criterion is satisfied. It
can be enabled by the setting [x.50BF.En_t1].

4. Second time delay

As similar as three-phase re-trip, the device will operate to trip the adjacent circuit breakers
with the time delay [x.50BF.t2_Op] when the relevant operating criterion is satisfied. It can be
enabled by the setting [x.50BF.En_t2].

In addition, breaker failure protection provides an independent initiating function via the circuit
breaker position. The input signal "x.50BF.ExTrp_WOI" is energized, normally closed
auxiliary contact of the circuit breaker is chosen to trigger the timer of breaker failure
protection. When the initiating signal of breaker failure protection is energized for longer than
10s, an alarm signal "x.50BF.Alm_Init" will be issued, and will drop out with a time delay of
10s.

PCS-978S Transformer Relay 3-145


Date: 2022-01-17
3 Protection Functions

3.16.2 Function Block Diagram

x.50BF

x.50BF.in_I3P x.50BF.Op_ReTrpA

x.50BF.Enable x.50BF.Op_ReTrpB

x.50BF.Block x.50BF.Op_ReTrpC

x.50BF.ExTrpA x.50BF.Op_ReTrp3P

x.50BF.ExTrpB x.50BF.Op_t1

3 x.50BF.ExTrpC x.50BF.Op_t2

x.50BF.ExTrp3P x.50BF.On

x.50BF.ExTrp_WOI x.50BF.Blocked

x.50BF.BI_52b_PhsA x.50BF.Valid

x.50BF.BI_52b_PhsB x.50BF.StA

x.50BF.BI_52b_PhsC x.50BF.StB

x.50BF.StC

x.50BF.St

x.50BF.Alm_Init

3.16.3 I/O Signals


Table 3.16-1 Input signals of breaker failure protection

No. Input Signal Description


1 x.50BF.in_I3P Three-phase current data input for breaker failure protection.
2 x.50BF.Enable Input signal of enabling breaker failure protection
3 x.50BF.Block Input signal of blocking breaker failure protection
4 x.50BF.ExtTrpA Input signal of initiating breaker failure protection (phase-A)
5 x.50BF.ExtTrpB Input signal of initiating breaker failure protection (phase-B)
6 x.50BF.ExtTrpC Input signal of initiating breaker failure protection (phase-C)
7 x.50BF.ExtTrp3P Input signal of initiating breaker failure protection (three-phases)
Input signal of initiating breaker failure protection with the position check of the
8 x.50BF.ExtTrp_WOI
circuit breaker
9 x.50BF.BI_52b_PhsA Input signal of open position of phase-A circuit breaker
10 x.50BF.BI_52b_PhsB Input signal of open position of phase-B circuit breaker
11 x.50BF.BI_52b_PhsC Input signal of open position of phase-C circuit breaker

Table 3.16-2 Output signals of breaker failure protection

No. Output Signal Description

3-146 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

No. Output Signal Description


1 x.50BF.Op_ReTrpA Breaker failure protection operates to re-trip phase-A circuit breaker.
2 x.50BF.Op_ReTrpB Breaker failure protection operates to re-trip phase-B circuit breaker.
3 x.50BF.Op_ReTrpC Breaker failure protection operates to re-trip phase-C circuit breaker.
4 x.50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phase circuit breaker.
5 x.50BF.Op_t1 Breaker failure protection operates with the time delay [x.50BF.t1_Op].
6 x.50BF.Op_t2 Breaker failure protection operates with the time delay [x.50BF.t2_Op].
7 x.50BF.On Breaker failure protection is enabled.
8 x.50BF.Blocked Breaker failure protection is blocked.
9 x.50BF.Valid Breaker failure protection is valid.
10 x.50BF.StA Breaker failure protection starts (phase-A). 3
11 x.50BF.StB Breaker failure protection starts (phase-B).
12 x.50BF.StC Breaker failure protection starts (phase-C).
13 x.50BF.St Breaker failure protection starts. (three-phases)
14 x.50BF.Alm_Init The initiating signal of breaker failure protection is energized consistently

3.16.4 Logic

EN [x.50BF.En] &
x.50BF.On
SIG x.50BF.Enable
&
SIG x.50BF.Block >=1 x.50BF.Blocked

SIG Fail_Device
&
x.50BF.Valid

Figure 3.16-1 Logic of enabling breaker failure protection

SIG x.50BF.ExtTrpA 10s 10s


>=1
SIG x.50BF.ExtTrpB 10s 10s

SIG x.50BF.ExtTrpC 10s 10s


>=1
SIG x.50BF.ExtTrp3P 10s 10s

SIG x.50BF.ExtTrp_WOI 10s 10s


&
EN [x.50BF.En_Alm_Init] x.50BF.Alm_Init

SIG x.50BF.Valid

Figure 3.16-2 Logic of breaker failure initiating signal abnormality

PCS-978S Transformer Relay 3-147


Date: 2022-01-17
3 Protection Functions

EN [x.50BF.En_3I0_1P] >=1
&
SET x.3I0>[x.50BF.3I0_Set]

SET x.IA (B, C)>[x.50BF.I_Set]


&
EN [x.50BF.En_Curr]

& >=1
Current/Contact check
EN [x.50BF.En_CBPos]
(A, B, C)

SIG x.50BF.BI_52b_PhsA (B, C)


3 &
&
EN [x.50BF.En_3I0_1P] >=1
& >=1
SET x.3I0>[x.50BF.3I0_Set] &
SET x.IA (B, C)>[x.50BF.I_Set]
&

SIG x.50BF.BI_52b_PhsA (B, C)

Figure 3.16-3 Logic of current/contact check (phase-segregated)

SIG x.IA>[x.50BF.I_Set]
>=1
SIG x.IB>[x.50BF.I_Set]

SIG x.IC>[x.50BF.I_Set]
&
EN [x.50BF.En_Curr]

&
EN [x.50BF.En_CBPos]

SIG x.50BF.BI_52b_PhsA
&
SIG x.50BF.BI_52b_PhsB

SIG x.50BF.BI_52b_PhsC &


SIG x.IA>[x.50BF.I_Set]
& >=1
>=1 >=1 Current/Contact check
SIG x.IB>[x.50BF.I_Set]

SIG x.IC>[x.50BF.I_Set] &


SIG x.50BF.BI_52b_PhsA
&
&
SIG x.50BF.BI_52b_PhsB

SIG x.50BF.BI_52b_PhsC

Figure 3.16-4 Logic of current/contact check (three-phase)

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SIG x.50BF.Valid &


&
SIG x.50BF.Alm_Init

EN [x.50BF.En_ReTrp]
&
SIG Current/Contact check (A) & [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpA

x.50BF.StA

&
SIG Current/Contact check (B) & [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpB

x.50BF.StB

&
SIG Current/Contact check (C) & [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpC

x.50BF.StC

SIG x.50BF.ExTrpA
>=2
>=1
&
[x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrp3P
3
& >=1
SIG x.50BF.ExTrpB
>=1 x.50BF.St
>=1

SIG x.50BF.ExTrpC

&
SIG Current/Contact check

EN [x.50BF.En_Ip]
&
[x.50BF.t1_Op] 0 x.50BF.Op_t1
EN [x.50BF.En_t1]

&
[x.50BF.t2_Op] 0 x.50BF.Op_t2
EN [x.50BF.En_t2]

Figure 3.16-5 Logic of breaker failure protection (phase-segregated)

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3 Protection Functions

SIG x.50BF.Valid &

SIG x.50BF.Alm_Init
&
EN [x.50BF.En_ReTrp] [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrp3P

SIG x.50BF.ExTrp3P
&
SIG Current/Contact check

EN [x.50BF.En_Ip]

SIG x.50BF.ExTrp3P
&
EN [x.50BF.En_3I0_3P] &

SET 3I0>[x.50BF.3I0_Set]
>=1
3 EN [x.50BF.En_I2_3P] &
& >=1 &
[x.50BF.t1_Op] 0 x.50BF.Op_t1

SET I2>[x.50BF.I2_Set]

SIG x.50BF.ExTrp_WOI
& >=1
EN [x.50BF.En_CB_Ctrl] x.50BF.St

SIG x.50BF.BI_52b_PhsA
&
SIG x.50BF.BI_52b_PhsB

SIG x.50BF.BI_52b_PhsC

EN [x.50BF.En_t1]
&
[x.50BF.t2_Op] 0 x.50BF.Op_t2
EN [x.50BF.En_t2]

Figure 3.16-6 Logic of breaker failure protection (three-phase)

3.16.5 Settings
Table 3.16-3 Settings of breaker failure protection

No. Name Range Unit Default Description


The phase current setting of breaker failure
1 x.50BF.I_Set 0.050~200.000 A 1.000
protection
The zero-sequence current setting of
2 x.50BF.3I0_Set 0.050~200.000 A 1.000
breaker failure protection
The negative-sequence current setting of
3 x.50BF.I2_Set 0.050~200.000 A 1.000
breaker failure protection
The re-trip time delay of breaker failure
4 x.50BF.t_ReTrp 0.000~20.000 s 0.050
protection
The first time delay of breaker failure
5 x.50BF.t1_Op 0.000~20.000 s 0.100
protection
The second time delay of breaker failure
6 x.50BF.t2_Op 0.000~20.000 s 0.200
protection
Disabled
7 x.50BF.En - Enabled Enabling/disabling breaker failure protection
Enabled
Disabled Enabling/disabling re-trip function of breaker
8 x.50BF.En_ReTrp - Enabled
Enabled failure protection
9 x.50BF.En_t1 Disabled - Disabled Enabling/disabling first time delay of breaker

3-150 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

No. Name Range Unit Default Description


Enabled failure protection
Disabled Enabling/disabling second time delay of
10 x.50BF.En_t2 - Disabled
Enabled breaker failure protection
Enabling/disabling phase overcurrent
Disabled
11 x.50BF.En_Ip - Disabled element of breaker failure protection via
Enabled
three-phases initiating signal
Enabling/disabling zero-sequence
Disabled
12 x.50BF.En_3I0_1P - Disabled overcurrent element of breaker failure
Enabled
protection via single-phase initiating signal

Disabled
Enabling/disabling zero-sequence 3
13 x.50BF.En_3I0_3P - Disabled overcurrent element of breaker failure
Enabled
protection via three-phases initiating signal
Enabling/disabling negative-sequence
Disabled
14 x.50BF.En_I2_3P - Disabled overcurrent element of breaker failure
Enabled
protection via three-phases initiating signal
Enabling/disabling breaker failure protection
Disabled
15 x.50BF.En_CB_Ctrl - Disabled be initiated by normally closed contact of
Enabled
circuit breaker
Disabled Enabling/disabling abnormality check of
16 x.50BF.En_Alm_Init - Disabled
Enabled breaker failure initiating signal
Disabled Enabling/disabling current check criterion of
17 x.50BF.En_Curr - Enabled
Enabled breaker failure protection
Disabled Enabling/disabling contact check criterion of
18 x.50BF.En_CBPos - Disabled
Enabled breaker failure protection

3.17 Phase Overvoltage Protection (59P)

In the power system, some abnormal conditions can generate high voltage, which may damage
the insulation performance of transformers, capacitors, motors and transmission lines, resulting in
equipment damage. Phase overvoltage protection can effectively detect the overvoltage that may
be generated in the system.

3.17.1 Function Description

The device can provide two stages of phase overvoltage protection with independent logic. When
a high voltage occurs in the system, phase overvoltage protection will operate to isolate the fault
from the system after a time delay if the voltage is greater than the setting. In addition, phase
overvoltage protection also provides the alarm function to notify that there is the overvoltage in the
system and find the cause timely to prevent from further deterioration of the fault.

Each stage of phase overvoltage protection can be independently set as definite-time


characteristics or inverse-time characteristics. The dropout characteristics can be set as
instantaneous dropout and definite-time dropout.

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Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [x.59Pi.Opt_Up/Upp]. “1-out-of-3” or “3-out-of-3” logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages)

Phase overvoltage protection can be enabled or disabled via the settings or the signals, for some
specific applications, phase overvoltage protection needs to be blocked by the external signal, so
the device provides a function block input signal to be used to block phase overvoltage protection.
In addition, if the local-side VT is out of service, phase overvoltage protection will be disabled.

EN [x.59Pi.En] &
3 x.59Pi.On
SIG x.59Pi.Enable

SIG x.59Pi.Block
&
>=1 x.59Pi.Blocked
SIG Fail_Device

EN [x.En_VT] & &


x.59Pi.Valid

SIG x.BI_En_VT

Figure 3.17-1 Logic of enabling phase overvoltage protection

The pickup logic of phase overvoltage protection is shown in Figure 3.17-2.

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SET [x.59Pi.Opt_Up/Upp]=Upp

SET x.Uab>U_DropOut
>=1
SET x.Ubc>U_DropOut &
SET x.Uca>U_DropOut

SET [x.59Pi.Opt_1P/3P]=1P
&
SET [x.59Pi.Opt_1P/3P]=3P >=1
SET x.Uab>U_DropOut
&
&
SET x.Ubc>U_DropOut

SET x.Uca>U_DropOut

SET x.Ua>U_DropOut
>=1
3
SET x.Ub>U_DropOut &
SET x.Uc>U_DropOut

SET [x.59Pi.Opt_1P/3P]=1P

SET [x.59Pi.Opt_1P/3P]=3P >=1


SET x.Ua>U_DropOut
&
&
SET x.Ub>U_DropOut >=1
SET x.Uc>U_DropOut
& &
0 500ms &
SET [x.59Pi.Opt_Up/Upp]=Up x.59Pi.Pkp

SIG x.59Pi.On

SIG x.59Pi.Valid
&
FD.Pkp
SET [x.59Pi.Opt_Trp/Alm]=Alm

Figure 3.17-2 Pickup logic of phase overvoltage protection

U_DropOut is the dropout voltage value, i.e. [x.59Pi.K_DropOut]×[x.59Pi.U_Set].

3.17.1.1 Operating Characteristics

Phase overvoltage protection can operate with a fixed time delay. It can also operate with
inverse-time characteristics. Phase overvoltage protection can support definite-time
characteristics, IEC & ANSI standard inverse-time characteristics and user-defined inverse-time
characteristics, which are determined by the setting [x.59Pi.Opt_Curve] (i=1 or 2). The
relationship between the setting and the characteristics curve is shown in the table below.

50/51Px.Opt_Curve Time Characteristic k α c


ANSIDefTime ANSI Definite time - - -
IECDefTime IEC Definite time - - -
UserDefine UserDefine
InvTime_U Voltage inverse 1 1 0

When the setting [x.59Pi.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, the operating


characteristics is definite-time phase overvoltage protection. When the setting [x.59Pi.Opt_Curve]

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is set as "UserDefine", it means that user-defined inverse-time characteristics is selected. These


settings [x.59Pi.K], [x.59Pi.C] and [x.59Pi.Alpha] are valid, and the inverse-time operating curve is
determined by the three settings. When the setting [x.59Pi.Opt_Curve] is set as “InvTime_U”, the
settings [x.59Pi.K], [x.59Pi.C] and [x.59Pi.Alpha] are useless.

 Definite-time characteristics

When x.U>[x.59Pi.U_Set], phase overvoltage protection operates with a time delay [x.59Pi.t_Op],
the operating characteristics curve is as shown in Figure 3.17-3.

[x.59Pi.t_Op]

U
[x.59Pi.U_Set]

Figure 3.17-3 Definite-time operating curve of phase overvoltage protection

 Inverse-time characteristics

When x.U>[x.59Pi.U_Set], phase overvoltage protection begins to accumulate, and the operating
time is affected by the applied voltage x.U. The operating time will decrease with the voltage
increasing, but the operating time shall not less than the setting [x.59Pi.tmin] (i=1 or 2). The
inverse-time operating characteristics equation is:

K
t={ α + C} × TMS
x. U
( ) −1
UP

Where:

UP is the voltage setting [x.59Pi.U_Set].

TMS is the inverse-time time multiplier, i.e. the setting [x.59Pi.TMS].

K is the inverse-time coefficient, i.e. the setting [x.59Pi.K].

C is the inverse-time coefficient, i.e. the setting [x.59Pi.C].

α is the inverse-time coefficient, i.e. the setting [x.59Pi.Alpha].

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x.U is the measured voltage.

The inverse-time operating characteristics curve is shown Figure 3.17-4.

[x.59Pi.tmin]

U
[x.59Pi.U_Set] UD

Figure 3.17-4 Inverse-time operating curve of phase overvoltage protection

When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overvoltage protection is shown in the following equation.

T0
1
∫ dt = 1
t(x. U)
0

Where:

T0 is the operating time of the protection element.

t(x.U) is the theoretical operating time when the voltage is x.U.

3.17.1.2 Dropout Characteristics

The supported dropout characteristics of phase overvoltage protection include instantaneous and
definite-time characteristics.

 Instantaneous characteristics

When x.U<[x.59Pi.K_DropOut]×[x.59Pi.U_Set], phase overvoltage protection drops out


immediately.

 Definite-time characteristics

When x.U<[x.59Pi.K_DropOut]×[x.59Pi.U_Set], phase overvoltage protection drops out with a


time delay [x.59Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic
among start signal, operating signal and the counter is as shown in Figure 3.17-5.

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Start time

x.U>[x.59Pi.U_Set]

x.59Pi.St

3 x.59Pi.Op

[x.59Pi.t_Op] Phase overvoltage


protection operating

Operating counter

[x.59Pi.t_DropOut]
[x.59Pi.t_DropOut] [x.59Pi.t_DropOut]
Dropout time
Dropout time

Figure 3.17-5 Definite-time dropout characteristics of phase overvoltage protection

3.17.2 Function Block Diagram

x.59Pi

x.59Pi.in_U3P x.59Pi.St

x.59Pi.Enable x.59Pi.StA

x.59Pi.Block x.59Pi.StB

x.59Pi.StC

x.59Pi.Op

X.59Pi.Op.PhA

x.59Pi.Op.PhB

x.59Pi.Op.PhC

x.59Pi.On

x.59Pi.Blocked

x.59Pi.Valid

x.59Pi.Alm

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3.17.3 I/O Signal


Table 3.17-1 Input signals of phase overvoltage protection

No. Input signal Description


1 x.59Pi.in_U3P Three-phase voltage data input for phase overvoltage protection (i=1~2)
2 x.59Pi.Enable Input signal of enabling stage i of phase overvoltage protection (i=1~2)
3 x.59Pi.Block Input signal of blocking stage i of phase overvoltage protection (i=1~2)

Table 3.17-2 Output signals of phase overvoltage protection

No. Output signal Description


1 x.59Pi.St Stage i of phase overvoltage protection starts. (i=1~2) 3
2 x.59Pi.StA Stage i of phase-A or -AB overvoltage protection starts. (i=1~2)
3 x.59Pi.StB Stage i of phase-B or -BC overvoltage protection starts. (i=1~2)
4 x.59Pi.StC Stage i of phase-C or -CA overvoltage protection starts. (i=1~2)
5 x.59Pi.Op Stage i of phase overvoltage protection operates. (i=1~2)
6 x.59Pi.Op.PhA Stage i of phase-A or -AB overvoltage protection operates. (i=1~2)
7 x.59Pi.Op.PhB Stage i of phase-B or -BC overvoltage protection operates. (i=1~2)
8 x.59Pi.Op.PhC Stage i of phase-C or -CA overvoltage protection operates. (i=1~2)
9 x.59Pi.On Stage i of phase overvoltage protection is enabled. (i=1~2)
10 x.59Pi.Blocked Stage i of phase overvoltage protection is blocked. (i=1~2)
11 x.59Pi.Valid Stage i of phase overvoltage protection is valid. (i=1~2)
12 x.59Pi.Alm Stage i of phase overvoltage protection alarm. (i=1~2)

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3.17.4 Logic

SET [x.59Pi.Opt_Up/Upp]=Upp

SET x.Uab>[x.59Pi.U_Set]
>=1
SET x.Ubc>[x.59Pi.U_Set] &
SET x.Uca>[x.59Pi.U_Set]

SET [x.59Pi.Opt_1P/3P]=1P
&
SET [x.59Pi.Opt_1P/3P]=3P >=1 >=1
SET x.Uab>[x.59Pi.U_Set]
&
&
3 SET x.Ubc>[x.59Pi.U_Set]

SET x.Uca>[x.59Pi.U_Set]

SET [x.59Pi.Opt_Up/Upp]=Up

SET x.Ua>[x.59Pi.U_Set]
>=1
SET x.Ub>[x.59Pi.U_Set] &
SET x.Uc>[x.59Pi.U_Set]

SET [x.59Pi.Opt_1P/3P]=1P
&
SET [x.59Pi.Opt_1P/3P]=3P >=1
SET x.Ua>[x.59Pi.U_Set]
&
& x.59Pi.St
SET x.Ub>[x.59Pi.U_Set]

& Timer
SET x.Uc>[x.59Pi.U_Set] t
&
t
SIG x.59Pi.Pkp x.59Pi.Op

SET [x.59Pi.Opt_Trp/Alm]=Trp

&
x.59Pi.Alm
SET [x.59Pi.Opt_Trp/Alm]=Alm

Figure 3.17-6 Logic of phase overvoltage protection

3.17.5 Settings
Table 3.17-3 Settings of phase overvoltage protection

No. Name Range Unit Default Description


The option of the voltage criterion
used by stage i of phase
3P
1 x.59Pi.Opt_1P/3P - 3P overvoltage protection (i=1 or 2)
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of the calculation
Up
2 x.59Pi.Opt_Up/Upp - Upp voltage used by stage i of phase
Upp
overvoltage protection (i=1 or 2)

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No. Name Range Unit Default Description


Up: phase voltage
Upp: phase-to-phase voltage
The voltage setting for stage i of
3 x.59Pi.U_Set 57.700~200.000 V 115.000 phase overvoltage protection (i=1
or 2)
The dropout coefficient for stage i
4 x.59Pi.K_DropOut 0.930~1.000 0.980 of phase overvoltage protection
(i=1 or 2)
The operating time delay for stage
5 x.59Pi.t_Op 0.100~100.000 s 1.000 i of phase overvoltage protection 3
(i=1 or 2)
The dropout time delay for stage i
6 x.59Pi.t_DropOut 0.000~100.000 s 0.000 of phase overvoltage protection
(i=1 or 2)
Enabling/disabling stage i of
Disabled
7 x.59Pi.En - Enabled phase overvoltage protection (i=1
Enabled
or 2)
Enabling/disabling stage i of
phase overvoltage protection
Trp
8 x.59Pi.Opt_Trp/Alm - Trp operate to trip or alarm (i=1 or 2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose
ANSIDefTime The option of operating
IECDefTime characteristics curve for stage i of
9 x.59Pi.Opt_Curve - IECDefTime
UserDefine phase overvoltage protection (i=1
InvTime_U or 2)
The option of dropout
characteristics curve for stage i of
phase overvoltage protection (i=1
Inst or 2)
10 x.59Pi.Opt_Curve_DropOut - Inst
DefTime Inst: instantaneous dropout
characteristics
DefTime: definite-time dropout
characteristics
Time multiplier setting for stage i
11 x.59Pi.TMS 0.040~20.000 - 1.000 of inverse-time phase overvoltage
protection (i=1 or 2)
The minimum operating time for
12 x.59Pi.tmin 0.000~10.000 s 0.020 stage i of inverse-time phase
overvoltage protection (i=1 or 2)
The constant “K” for stage i of
13 x.59Pi.K 0.0010~120.0000 - 1.0000 customized inverse-time phase
overvoltage protection (i=1 or 2)

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No. Name Range Unit Default Description


The constant “C” for stage i of
14 x.59Pi.Alpha 0.0100~3.0000 - 1.0000 customized inverse-time phase
overvoltage protection (i=1 or 2)
The constant “α” for stage i of
15 x.59Pi.C 0.0000~1.0000 - 0.0000 customized inverse-time phase
overvoltage protection (i=1 or 2)

3.18 Residual Overvoltage Protection (59G)

3 If an earth fault happens to the feeder in the grounding system via high resistance, the residual
current changes little and is difficult to detect. However, the amplitude of the residual voltage
changes significantly and can be used to detect the earth fault. In addition, the transformer is
grounded via the gap in the neutral point, the residual voltage increases once a fault occurs, so
residual overvoltage protection can also be used as backup protection of the transformer. The
residual voltage can be measured from broken-delta VT, and it can also be calculated internally by
the device using three-phase voltage.

3.18.1 Function Description


The device can provide two stages of residual overvoltage protection with independent logic.
When the residual voltage is greater than the setting, residual overvoltage protection will operate
to isolate the fault from the system after a time delay. In addition, residual overvoltage protection
also provides the alarm function to notify that there is an earth fault leading to residual voltage
generation, and find the cause timely to prevent from further deterioration of the fault.

Residual overvoltage protection supports definite-time characteristics. The dropout characteristics


can be set as instantaneous dropout and definite-time dropout. Residual overvoltage protection
can be enabled or disabled via the settings or the signals, for some specific applications, residual
overvoltage protection needs to be blocked by the external signal, so the device provides a
function block input signal to be used to block residual overvoltage protection. In addition, if the
residual voltage used by residual overvoltage protection is the calculated residual voltage, once
the local-side VT is out of service, the residual overvoltage protection will be disabled.

EN [x.59Gi.En] &
x.59Gi.On
SIG x.59Gi.Enable

SIG x.59Gi.Block
&
>=1 x.59Gi.Blocked
SIG Fail_Device

EN [x.En_VT] & &


x.59Gi.Valid

SIG x.BI_En_VT

Figure 3.18-1 Logic of enabling residual overvoltage protection

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The pickup logic of residual overvoltage protection is shown in Figure 3.18-2.

SET x.3U0_Cal>U_DropOut &


>=1
SET [x.59Gi.Opt_3U0]=Cal &
SET x.3U0_Ext>U_DropOut &

SET [x.59Gi.Opt_3U0]=Ext
0 500ms &
SIG x.59Gi.On
x.59Gi.Pkp
SIG x.59Gi.Valid &
FD.Pkp
3
SET [x.59Gi.Opt_Trp/Alm]=Alm

Figure 3.18-2 Pickup logic of residual overvoltage protection

U_DropOut is the dropout voltage value, i.e. [x.59Gi.K_DropOut]×[x.59Gi.3U0_Set]

3.18.1.1 Operating Characteristics

When x.3U0>[x.59Gi.3U0_Set], residual overvoltage protection operates with a time delay


[x.59Gi.t_Op], the operating characteristics curve is as shown in Figure 3.18-3.

[x.59Gi.t_Op]

U0
[x.59Gi.3U0_Set]

Figure 3.18-3 Definite-time operating curve of residual overvoltage protection

3.18.1.2 Dropout Characteristics

The supported dropout characteristics of residual overvoltage protection include instantaneous


and definite-time characteristics.

 Instantaneous characteristics

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When x.3U0<[x.59Gi.K_DropOut]×[x.59Gi.3U0_Set], residual overvoltage protection drops out


immediately.

 Definite-time characteristics

When x.3U0<[x.59Gi.K_DropOut]×[x.59Gi.3U0_Set], residual overvoltage protection drops out


with a time delay [x.59Gi.t_DropOut], and the sequence diagram of definite-time dropout
characteristic among start signal, operating signal and the counter is as shown in Figure 3.18-4.

Start time

3 x.3U0>[x.59Gi.3U0_Set]

x.59Gi.St

x.59Gi.Op

[x.59Gi.t_Op] Residual overvoltage


protection operating

Operating counter

[x.59Gi.t_DropOut]
[x.59Gi.t_DropOut] [x.59Gi.t_DropOut]
Dropout time
Dropout time

Figure 3.18-4 Definite-time dropout characteristics of residual overvoltage protection

3.18.2 Function Block Diagram

59G

x.59Gi.in_U3P x.59Gi.St

x.59Gi.in_U1P x.59Gi.Op

x.59Gi.Enable x.59Gi.On

x.59Gi.Block x.59Gi.Blocked

x.59Gi.Valid

x.59Gi.Alm

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3.18.3 I/O Signal


Table 3.18-1 Input signals of residual overvoltage protection

No. Input signal Description


1 x.59Gi.in_U3P Three-phase voltage data input for residual overvoltage protection (i=1~2)
2 x.59Gi.in_U1P Residual voltage input (i=1~2)
3 x.59Gi.Enable Input signal of enabling stage i of residual overvoltage protection (i=1~2)
4 x.59Gi.Block Input signal of blocking stage i of residual overvoltage protection (i=1~2)

Table 3.18-2 Output signals of residual overvoltage protection

No. Output signal Description 3


1 x.59Gi.St Stage i of residual overvoltage protection starts. (i=1~2)
2 x.59Gi.Op Stage i of residual overvoltage protection operates. (i=1~2)
3 x.59Gi.On Stage i of residual overvoltage protection is enabled. (i=1~2)
4 x.59Gi.Blocked Stage i of residual overvoltage protection is blocked. (i=1~2)
5 x.59Gi.Valid Stage i of residual overvoltage protection is valid. (i=1~2)
6 x.59Gi.Alm Stage i of residual overvoltage protection alarm. (i=1~2)

3.18.4 Logic

SET x.3U0_Cal>[x.59Gi.3U0_Set] &


>=1 x.59Gi.St
SET [x.59Gi.Opt_3U0]=Cal &
[x.59Gi.t_Op] 0
SET x.3U0_Ext>[x.59Gi.3U0_Set] &

SET [x.59Gi.Opt_3U0]=Ext

SIG x.59Gi.Pkp &


x.59Gi.Op
SET [x.59Gi.Opt_Trp/Alm]=Trp

&
x.59Gi.Alm
SET [x.59Gi.Opt_Trp/Alm]=Alm

Figure 3.18-5 Logic of residual overvoltage protection

3.18.5 Settings
Table 3.18-3 Settings of residual overvoltage protection

No. Name Range Unit Default Description


The option of the residual voltage used by
Ext
1 x.59Gi.Opt_3U0 - Ext residual overvoltage protection
Cal
Ext: the measured residual voltage

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No. Name Range Unit Default Description


Cal: the calculated residual voltage
The voltage setting for stage i of residual
2 x.59Gi.3U0_Set 1.000~200.000 V 50.000
overvoltage protection (i=1 or 2)
The dropout coefficient for stage i of
3 x.59Gi.K_DropOut 0.930~1.000 - 0.980
residual overvoltage protection (i=1 or 2)
The operating time delay for stage i of
4 x.59Gi.t_Op 0.100~100.000 s 1.000
residual overvoltage protection (i=1 or 2)
The dropout time delay for stage i of
5 x.59Gi.t_DropOut 0.000~100.000 s 0.000
residual overvoltage protection (i=1 or 2)

3 6 x.59Gi.En
Disabled
- Enabled
Enabling/disabling stage i of residual
Enabled overvoltage protection (i=1 or 2)
Enabling/disabling stage i of residual
overvoltage protection operate to trip or
Trp
7 x.59Gi.Opt_Trp/Alm - Trp alarm (i=1 or 2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose

3.19 Phase Undervoltage Protection (27P)

In the power system, some abnormal conditions will lead to low voltage. Electric equipment such
as motors cannot operate for a long time under the rated voltage and need to be isolated from the
system timely. In addition, the voltage decreasing may be related to the shortage of system
reactive power. Shedding some reactive loads through phase undervoltage protection can
improve the voltage level of the system.

3.19.1 Function Description

The device can provide two stages of phase undervoltage protection with independent logic.
When the voltage drops in the system and it is lower than the setting, phase undervoltage
protection will operate to isolate the fault from the system after a time delay. In addition, phase
undervoltage protection also provides the alarm function to notify that there is the undervoltage in
the system and find the cause timely to prevent from further deterioration of the fault.

Each stage of phase undervoltage protection can be independently set as definite-time


characteristics or inverse-time characteristics. The dropout characteristics can be set as
instantaneous dropout and definite-time dropout.

Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [x.27Pi.Opt_Up/Upp]. “1-out-of-3” or “3-out-of-3” logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages). The circuit breaker position with/without the current condition can be as an
auxiliary criterion for phase undervoltage protection, which can be configured via the setting
[x.27Pi.Opt_LogicMode].

Phase undervoltage protection can be enabled or disabled via the settings or the signals, for

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some specific applications, phase undervoltage protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block phase undervoltage
protection. In addition, if the local-side VT is out of service, phase undervoltage protection will be
disabled.

EN [x.27Pi.En] &
x.27Pi.On
SIG x.27Pi.Enable

SIG x.27Pi.Block &


>=1 x.27Pi.Blocked
SIG Fail_Device 3
EN [x.En_VT] & &
x.27Pi.Valid
SIG x.BI_En_VT

Figure 3.19-1 Logic of enabling phase undervoltage protection

The pickup logic of phase overvoltage protection is shown in Figure 3.19-2.

SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Upp

SET x.Uab<U_DropOut
&
SET x.Ubc<U_DropOut

SET x.Uca<U_DropOut
>=1
&
SET [x.27Pi.Opt_1P/3P]=1P

SET x.Uab<U_DropOut
>=1
SET x.Ubc<U_DropOut

SET x.Uca<U_DropOut

SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Up

SET x.Ua<U_DropOut
&
SET x.Ub<U_DropOut >=1
>=1 Voltage criterion
SET x.Uc<U_DropOut
&
SET [x.27Pi.Opt_1P/3P]=1P

SET x.Ua<U_DropOut
>=1
SET x.Ub<U_DropOut

SET x.Uc<U_DropOut

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SET [x.27Pi.Opt_LogicMode]=None

SET [x.27Pi.Opt_LogicMode]=Curr

SIG x.Ia>0.04In
&
SIG x.Ib>0.04In
& >=1

SIG x.Ic>0.04In

SET [x.27Pi.Opt_LogicMode]=CBPos &

SIG x.27Pi.52a

3 >=1
& >=1
>=1 Auxiliary criterion
SET [x.27Pi.Opt_LogicMode]=CurrOrCBPos

&
&

SET [x.27Pi.Opt_LogicMode]=CurrAndCBPos

SIG Voltage criterion


& x.27Pi.Pkp
SIG Auxiliary criterion 0 500ms &
&
SIG x.VTS.InstAlm & FD.Pkp
&
EN [x.27Pi.En_VTS_Blk]

SIG x.27Pi.On

SIG x.27Pi.Valid

SET [x.27Pi.Opt_Trp/Alm]=Alm

Figure 3.19-2 Pickup logic of phase undervoltage protection

U_DropOut is the dropout voltage value, i.e. [x.27Pi.K_DropOut]×[x.27Pi.U_Set].

3.19.1.1 Operating Characteristics

Phase undervoltage protection can operate with a fixed time delay. It can also operate with
inverse-time characteristics. Phase overvoltage protection can support definite-time
characteristics, IEC & ANSI standard inverse-time characteristics and user-defined inverse-time
characteristics, which are determined by the setting [x.27Pi.Opt_Curve] (i=1 or 2). The
relationship between the setting and the characteristics curve is shown in the table below.

x.27Pi.Opt_Curve Time Characteristic k α c


ANSIDefTime ANSI Definite time - - -
IECDefTime IEC Definite time - - -

3-166 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

x.27Pi.Opt_Curve Time Characteristic k α c


UserDefine UserDefine
InvTime_U Voltage inverse 1 1 0

When the setting [x.27Pi.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, the operating


characteristics is definite-time phase undervoltage protection. When the setting
[x.27Pi.Opt_Curve] is set as "UserDefine", it means that user-defined inverse-time characteristics
is selected. These settings [x.27Pi.K], [x.27Pi.C] and [x.27Pi.Alpha] are valid, and the inverse-time
operating curve is determined by the three settings. When the setting [x.27Pi.Opt_Curve] is set as
“InvTime_U”, the settings [x.27Pi.K], [x.27Pi.C] and [x.27Pi.Alpha] are useless.

 Definite-time characteristics 3
When U<[x.27Pi.U_Set], phase undervoltage protection operates with a time delay [x.27Pi.t_Op],
the operating characteristics curve is as shown in Figure 3.19-3.

[x.27Pi.t_Op]

U
[x.27Pi.U_Set]

Figure 3.19-3 Definite-time operating curve of phase undervoltage protection

 Inverse-time characteristic

When x.U<[x.27Pi.U_Set], phase undervoltage protection begins to accumulate, and the


operating time is affected by the applied voltage x.U. The operating time will decrease with the
voltage decreasing, but the operating time shall not less than the setting [x.27Pi.tmin] (i=1 or 2).
The inverse-time operating characteristics equation is:

K
t={ + C} × TMS
x. U α
1−(U )
P

Where:

UP is the voltage setting [x.27Pi.U_Set].

PCS-978S Transformer Relay 3-167


Date: 2022-01-17
3 Protection Functions

TMS is the inverse-time time multiplier, i.e. the setting [x.27Pi.TMS].

K is the inverse-time coefficient, i.e. the setting [x.27Pi.K].

C is the inverse-time coefficient, i.e. the setting [x.27Pi.C].

α is the inverse-time coefficient, i.e. the setting [x.27Pi.Alpha].

x.U is the measured voltage.

The inverse-time operating characteristics curve is shown Figure 3.19-4.

t
3

[x.27Pi.tmin]

U
UD [x.27Pi.U_Set]

Figure 3.19-4 Inverse-time operating curve of phase undervoltage protection

When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase undervoltage protection is shown in the following equation.

T0
1
∫ dt = 1
t(x. U)
0

Where:

T0 is the operating time of the protection element.

t(x.U) is the theoretical operating time when the voltage is x.U.

3.19.1.2 Dropout Characteristics

The supported dropout characteristics of phase undervoltage protection include instantaneous


and definite-time characteristics.

 Instantaneous characteristics

When x.U>[x.27Pi.K_DropOut]×[x.27Pi.U_Set], phase undervoltage protection drops out


immediately.

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Date: 2022-01-17
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 Definite-time characteristics

When x.U>[x.27Pi.K_DropOut]×[x.27Pi.U_Set], phase undervoltage protection drops out with a


time delay [x.27Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic
among start signal, operating signal and the counter is as shown in Figure 3.19-5.

Start time

x.U<[x.27Pi.U_Set]

3
x.27Pi.St

x.27Pi.Op

[x.27Pi.t_Op] Phase undervoltage


protection operating

Operating counter

[x.27Pi.t_DropOut]
[x.27Pi.t_DropOut] [x.27Pi.t_DropOut]
Dropout time
Dropout time

Figure 3.19-5 Definite-time dropout characteristics of phase undervoltage protection

PCS-978S Transformer Relay 3-169


Date: 2022-01-17
3 Protection Functions

3.19.2 Function Block Diagram

x.27Pi

x.27Pi.in_U3P x.27Pi.St

x.27Pi.Enable x.27Pi.StA

x.27Pi.Block x.27Pi.StB

x.27Pi.52a x.27Pi.StC

x.27Pi.LiveCur x.27Pi.Op

3 X.27Pi.Op.PhA

x.27Pi.Op.PhB

x.27Pi.Op.PhC

x.27Pi.On

x.27Pi.Blocked

x.27Pi.Valid

x.27Pi.Alm

3.19.3 I/O Signal


Table 3.19-1 Input signals of phase undervoltage protection

No. Input signal Description


1 x.27Pi.in_U3P Three-phase voltage data input for phase undervoltage protection (i=1~2)
2 x.27Pi.Enable Input signal of enabling stage i of phase undervoltage protection (i=1~2)
3 x.27Pi.Block Input signal of blocking stage i of phase undervoltage protection (i=1~2)
4 x.27Pi.52a Input signal of normally open contact of circuit breaker
5 x.27Pi.OnLoad A signal indicating there is load current detected at x side of transformer

Table 3.19-2 Output signals of phase undervoltage protection

No. Output signal Description


1 x.27Pi.St Stage i of phase undervoltage protection starts. (i=1~2)
2 x.27Pi.StA Stage i of phase-A or -AB undervoltage protection starts. (i=1~2)
3 x.27Pi.StB Stage i of phase-B or-BC undervoltage protection starts. (i=1~2)
4 x.27Pi.StC Stage i of phase-C or -CA undervoltage protection starts. (i=1~2)
5 x.27Pi.Op Stage i of phase undervoltage protection operates. (i=1~2)
6 x.27Pi.Op.PhA Stage i of phase-A or -AB undervoltage protection operates. (i=1~2)
7 x.27Pi.Op.PhB Stage i of phase-B or -BC undervoltage protection operates. (i=1~2)
8 x.27Pi.Op.PhC Stage i of phase-C or -CA undervoltage protection operates. (i=1~2)
9 x.27Pi.On Stage i of phase undervoltage protection is enabled. (i=1~2)
10 x.27Pi.Blocked Stage i of phase undervoltage protection is blocked. (i=1~2)

3-170 PCS-978S Transformer Relay

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No. Output signal Description


11 x.27Pi.Valid Stage i of phase undervoltage protection is valid. (i=1~2)
12 x.27Pi.Alm Stage i of phase undervoltage protection alarm. (i=1~2)

3.19.4 Logic

SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Upp

SET x.Uab<[x.27Pi.U_Set]
&
SET x.Ubc<[x.27Pi.U_Set]

SET x.Uca<[x.27Pi.U_Set]
&
>=1
3
SET [x.27Pi.Opt_1P/3P]=1P

SET x.Uab<[x.27Pi.U_Set]
>=1
SET x.Ubc<[x.27Pi.U_Set]

SET x.Uca<[x.27Pi.U_Set]

SET [x.27Pi.Opt_1P/3P]=3P
&
SET [x.27Pi.Opt_Up/Upp]=Up

SET x.Ua<[x.27Pi.U_Set]
&
SET x.Ub<[x.27Pi.U_Set] >=1
SET x.Uc<[x.27Pi.U_Set]
>=1
&
SET [x.27Pi.Opt_1P/3P]=1P

SET x.Ua<[x.27Pi.U_Set]
>=1
SET x.Ub<[x.27Pi.U_Set]

SET x.Uc<[x.27Pi.U_Set] x.27Pi.St


&
SIG Auxiliary criterion & Timer
t
t
SIG x.VTS.InstAlm &
&
EN [x.27Pi.En_VTS_Blk]

SIG x.27Pi.On

SIG x.27Pi.Pkp
&
x.27Pi.Op
SET [x.27Pi.Opt_Trp/Alm]=Trp

&
x.27Pi.Alm
SET [x.27Pi.Opt_Trp/Alm]=Alm

Figure 3.19-6 Logic of phase undervoltage protection

3.19.5 Settings
Table 3.19-3 Settings of phase undervoltage protection

No. Name Range Unit Default Description

PCS-978S Transformer Relay 3-171


Date: 2022-01-17
3 Protection Functions

No. Name Range Unit Default Description


The option of the
voltage criterion used
by phase undervoltage
3P
1 x.27Pi.Opt_1P/3P - 3P protection
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
(i=1 or 2)
The option of the
calculation voltage used

3 Up
by phase undervoltage
protection
2 x.27Pi.Opt_Up/Upp - Upp
Upp Up: phase voltage
Upp: phase-to-phase
voltage
(i=1 or 2)
The option of auxiliary
criterion mode for
phase undervoltage
protection
None: no check
Curr: check current
condition
None
CBPos: check normally
Curr
open auxiliary contact
3 x.27Pi.Opt_LogicMode CBPos - CurrAndCBPos
CurrOrCBPos: check
CurrOrCBPos
current condition or
CurrAndCBPos
normally open auxiliary
contact
CurrAndCBPos: check
current condition and
normally open auxiliary
contact
(i=1 or 2)
The voltage setting for
stage i of phase
4 x.27Pi.U_Set 5.000~120.000 V 80.000
undervoltage protection
(i=1 or 2)
The dropout coefficient
for stage i of phase
5 x.27Pi.K_DropOut 1.000 ~1.200 - 1.030
undervoltage protection
(i=1 or 2)
The operating time
6 x.27Pi.t_Op 0.100~100.000 s 1.000
delay for stage i of

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No. Name Range Unit Default Description


phase undervoltage
protection (i=1 or 2)
The dropout time delay
for stage i of phase
7 x.27Pi.t_DropOut 0.000~100.000 s 0.000
undervoltage protection
(i=1 or 2)
Enabling/Disabling
stage i of phase
undervoltage protection

8 x.27Pi.En_VTS_Blk
Disabled
Enabled
- Disabled
is blocked by VT circuit
failure when VT circuit
3
supervision is enabled
and VT circuit fails (i=1
or 2)
Enabling/disabling
Disabled stage i of phase
9 x.27Pi.En - Enabled
Enabled undervoltage protection
(i=1 or 2)
Enabling/disabling
stage i of phase
undervoltage protection
Trp
10 x.27Pi.Opt_Trp/Alm - Trp operate to trip or alarm
Alm
(i=1 or 2)
Trp: for tripping purpose
Alm: for alarm purpose
The option of operating
ANSIDefTime
characteristics curve for
IECDefTime
11 x.27Pi.Opt_Curve - IECDefTime stage i of phase
UserDefine
undervoltage protection
InvTime_U
(i=1 or 2)
The option of dropout
characteristics curve for
stage i of phase
undervoltage protection
Inst
12 x.27Pi.Opt_Curve_DropOut - Inst (i=1 or 2)
DefTime
Inst: instantaneous
dropout characteristics
DefTime: definite-time
dropout characteristics
Time multiplier setting
for stage i of
13 x.27Pi.TMS 0.040~20.000 - 1.000
inverse-time phase
undervoltage protection

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Date: 2022-01-17
3 Protection Functions

No. Name Range Unit Default Description


(i=1 or 2)
The minimum operating
time for stage i of
14 x.27Pi.tmin 0.030~10.000 s 0.030 inverse-time phase
undervoltage protection
(i=1 or 2)
The constant “K” for
stage i of customized
15 x.27Pi.K 0.0010~120.0000 - 0.1400 inverse-time phase

3 undervoltage protection
(i=1 or 2)
The constant “α” for
stage i of customized
16 x.27Pi.Alpha 0.0100~3.0000 - 0.0200 inverse-time phase
undervoltage protection
(i=1 or 2)
The constant “C” for
stage i of customized
17 x.27Pi.C 0.0000~1.0000 - 0.0000 inverse-time phase
undervoltage protection
(i=1 or 2)

3.20 Overfrequency Protection (81O)

Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The increase of frequency indicates that
the output power of the system is much larger than that of the load. When the system frequency is
greater than the predefined setting, the overfrequency protection will operate for removing some
part of active power supplies from the system.

3.20.1 Function Description

The device can provide four stages of overfrequency protection. If the system frequency is greater
than the setting, overfrequency protection will operate to remove some part of active power
supplies from the system. Overfrequency protection is with independent definite-time
characteristics and with instantaneous dropout characteristics.

Overfrequency protection can be enabled or disabled by the settings and the signals. For some
specific applications, overfrequency protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block overfrequency protection.

3-174 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

EN [81Oi.En] &
81Oi.On
SIG 81Oi.Enable
&
SIG 81Oi.Block >=1 81Oi.Blocked

SIG Fail_Device
&
81Oi.Valid

Figure 3.20-1 Logic of enabling overfrequency protection


3
The pickup logic of overfrequency protection is shown in Figure 3.20-2.

SET f>[81Oi.f_Set] &


&
SET Upp_min>[81.Upp_Blk] 0 500ms &
81Oi.Pkp
SIG 81Oi.On

SIG 81Oi.Valid
&
FD.Pkp
SET [81Oi.Opt_Trp/Alm]=Alm

Figure 3.20-2 Pickup logic of overfrequency protection

3.20.1.1 Operation Characteristics

Overfrequency protection supports definite-time characteristics. If the system frequency is greater


than the setting [81Oi.f_Set], overfrequency protection will operate with a time delay [81Oi.t_Op].

The operating characteristics curve of overfrequency protection is shown in Figure 3.20-3.

[81Oi.t_Op]

f
[81Oi.f_Set]

Figure 3.20-3 Definite-time operating curve of overfrequency protection

PCS-978S Transformer Relay 3-175


Date: 2022-01-17
3 Protection Functions

3.20.1.2 Dropout Characteristics

Overfrequency protection is with instantaneous dropout characteristics. If the system frequency is


less than the setting [81Oi.f_Set], overfrequency protection will drop out immediately.

3.20.2 Function Block Diagram

FreqCal

FreqCal.in_U3P FreqCal.FREQ

f
3 FreqCal.df/dt

81Oi

81Oi.In_FREQ 81Oi.St

81Oi.In_U3P 81Oi.Op

81Oi.Enable 81Oi.On

81Oi.Block 81Oi.Blocked

81Oi.Valid

81Oi.Alm

Figure 3.20-4 Function block diagram of overfrequency protection

“FreqCal” is the frequency calculation element.

“81Oi” is the stage i of overfrequency element.

3.20.3 I/O Signals


Table 3.20-1 Input signals of overfrequency protection

No. Input Signal Description


1 FreqCal.in_U3P Three-phase voltage data input for frequency protection calculation element
2 81Oi.in_FREQ Frequency data input for stage i of overfrequency protection(i=1~4)
Three-phase voltage data input for stage i of overfrequency protection
3 81Oi.in_U3p
(i=1~4)
4 81Oi.Enable Input signal of enabling stage i of overfrequency protection (i=1~4)
5 81Oi.Block Input signal of blocking stage i of overfrequency protection (i=1~4)

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Table 3.20-2 Output signals of overfrequency protection

No. Output Signal Description


1 FreqCal.FREQ A frequency data set, mainly used for the inputs of elements “81Oi”, “81Ui”.
2 f The calculated frequency value
3 FreqCal.df/dt The calculated rate-of-change of frequency value
4 81Oi.St Stage i of overfrequency protection starts. (i=1~4)
5 81Oi.Op Stage i of overfrequency protection operates. (i=1~4)
6 81Oi.On Stage i of overfrequency protection is enabled. (i=1~4)
7 81Oi.Blocked Stage i of overfrequency protection is blocked. (i=1~4)
8 81Oi.Valid Stage i of overfrequency protection is valid. (i=1~4)
9 81Oi.Alm Stage i of overfrequency protection alarms. (i=1~4)
3
3.20.4 Logic

SET f>[81Oi.f_Set] & 81Oi.St

&
SET Upp_min>[81.Upp_Blk] [81Oi.t_Op] 0

SIG 81Oi.Pkp
&
81Oi.Alm
SET [81Oi.Opt_Trp/Alm]=Alm

&
81Oi.Op
SET [81Oi.Opt_Trp/Alm]=Trp

Figure 3.20-5 Logic of overfrequency protection

3.20.5 Settings
Table 3.20-3 Settings of overfrequency protection

No. Name Range Unit Default Description


The phase-to-phase voltage setting used to
1 81Oi.Upp_Blk 10.000~150.000 V 70.000
block frequency protection (i=1~4)
The frequency setting for stage i of
2 81Oi.f_Set 50.000~65.000 Hz 52.000
overfrequency protection (i=1~4)
The time delay for stage i of overfrequency
3 81Oi.t_Op 0.100~100.000 s 0.300
protection (i=1~4)
Disabled Enabling/disabling stage i of overfrequency
4 81Oi.En - Enabled
Enabled protection (i=1~4)
Enabling/disabling stage i of overfrequency
81Oi.Opt_Trp/Al Trp protection operate to trip or alarm (i=1~4)
5 - Trp
m Alm Trp: for tripping purpose
Alm: for alarm purpose

PCS-978S Transformer Relay 3-177


Date: 2022-01-17
3 Protection Functions

3.21 Underfrequency Protection (81U)

Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The decrease of frequency indicates that
the output power of the system is much less than that of the load. When the system frequency is
less than the predefined setting, the underfrequency protection will operate for shedding some
part of loads from the system.

3.21.1 Function Description

3 The device can provide four stages of underfrequency protection. If the system frequency is less
than the setting, underfrequency protection will operate to shedding some part of loads from the
system. Underfrequency protection is with independent definite-time characteristics and with
instantaneous dropout characteristics.

Underfrequency protection can be enabled or disabled by the settings and the signals. For some
specific applications, underfrequency protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block underfrequency protection.

EN [81Ui.En] &
81Ui.On
SIG 81Ui.Enable
&
SIG 81Ui.Block >=1 81Ui.Blocked

SIG Fail_Device
&
81Ui.Valid

Figure 3.21-1 Logic of enabling underfrequency protection

The pickup logic of underfrequency protection is shown in Figure 3.21-2.

SET f<[81Ui.f_Set] &


&
SET Upp_min>[81.Upp_Blk] 0 500ms &
81Ui.Pkp
SIG 81Ui.On

SIG 81Ui.Valid
&
FD.Pkp
SET [81Ui.Opt_Trp/Alm]=Alm

Figure 3.21-2 Pickup logic of underfrequency protection

3.21.1.1 Operation Characteristics

Underfrequency protection supports definite-time characteristics. If the system frequency is


greater than the setting [81Ui.f_Set], underfrequency protection will operate with a time delay

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[81Ui.t_Op].

The operating characteristics curve of underfrequency protection is shown in Figure 3.21-3.

[81Ui.t_Op]
3

f
[81Ui.f_Set]

Figure 3.21-3 Definite-time operating curve of underfrequency protection

3.21.1.2 Dropout Characteristics

Underfrequency protection is with instantaneous dropout characteristics. If the system frequency


is less than the setting [81Oi.f_Set], underfrequency protection will drop out immediately.

3.21.2 Function Block Diagram

FreqCal

FreqCal.in_U3P FreqCal.FREQ

FreqCal.df/dt

81Ui

81Ui.in_FREQ 81Ui.St

81Ui.in_U3P 81Ui.Op

81Ui.Enable 81Ui.On

81Ui.Block 81Ui.Blocked

81Ui.Valid

81Ui.Alm

Figure 3.21-4 Function block diagram of underfrequency protection

PCS-978S Transformer Relay 3-179


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“FreqCal” is the frequency calculation element.

“81Ui” is the stage i of underfrequency element.

3.21.3 I/O Signals


Table 3.21-1 Input signals of underfrequency protection

No. Input Signal Description


1 FreqCal.in_U3P Three-phase voltage data input of frequency protection calculation element
3 2 81Ui.in_FREQ Frequency data input for stage i of underfrequency protection(i=1~4)
Three-phase voltage data input for stage i of underfrequency
3 81Ui.in_U3P
protection(i=1~4)
4 81Ui.Enable Input signal of enabling stage i of underfrequency protection (i=1~4)
5 81Ui.Block Input signal of blocking stage i of underfrequency protection (i=1~4)

Table 3.21-2 Output signals of underfrequency protection

No. Output Signal Description


1 FreqCal.FREQ A frequency data set, mainly used for the inputs of elements “81Oi”, “81Ui”.
2 f The calculated frequency value
3 FreqCal.df/dt The calculated rate-of-change of frequency value
4 81Ui.St Stage i of underfrequency protection starts. (i=1~4)
5 81Ui.Op Stage i of underfrequency protection operates. (i=1~4)
6 81Ui.On Stage i of underfrequency protection is enabled. (i=1~4)
7 81Ui.Blocked Stage i of underfrequency protection is blocked. (i=1~4)
8 81Ui.Valid Stage i of underfrequency protection is valid. (i=1~4)
9 81Ui.Alm Stage i of underfrequency protection alarms. (i=1~4)

3.21.4 Logic

SET f<[81Ui.f_Set] & 81Ui.St

&
SET Upp_min>[81.Upp_Blk] [81Ui.t_Op] 0

SIG 81Ui.Pkp
&
81Ui.Alm
SET [81Ui.Opt_Trp/Alm]=Alm

&
81Ui.Op
SET [81Ui.Opt_Trp/Alm]=Trp

Figure 3.21-5 Logic of underfrequency protection

3-180 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

3.21.5 Settings
Table 3.21-3 Settings of underfrequency protection

No. Name Range Unit Default Description


The phase-to-phase voltage setting used to block
1 81Ui.Upp_Blk 10.000~150.000 V 70.000
frequency protection
The frequency setting for stage i of underfrequency
2 81Ui.f_Set 45.000~60.000 Hz 48.000
protection (i=1~4)
The time delay for stage i of underfrequency
3 81Ui.t_Op 0.100~100.000 s 0.300
protection (i=1~4)

4 81Ui.En
Disabled
-
Enable Enabling/disabling stage i of underfrequency 3
Enabled d protection (i=1~4)
Enabling/disabling stage i of underfrequency
81Ui.Opt_Trp/ Trp protection operate to trip or alarm (i=1~4)
5 - Trp
Alm Alm Trp: for tripping purpose
Alm: for alarm purpose

3.22 Frequency Rate-of-change Protection (81R)

Frequency rate-of-change protection is used to detect the power system frequency changes
(increase and decrease). And the frequency rate-of-change can reflect the balance between the
generated active power and the consumed active power. When the frequency changes too fast, it
is generally considered that the system has a fault, and the frequency rate-of-change protection
can operate in such a situation.

3.22.1 Function Description

The device can provide two stages of frequency rate-of-change protection. If the system
frequency rate-of-change is greater than the setting, frequency rate-of-change protection will
operate. Frequency rate-of-change protection is with independent definite-time characteristics
and with instantaneous dropout characteristics.

Frequency rate-of-change protection can operate to trip or alarm. For some specific applications,
frequency rate-of-change protection needs to be blocked by the external signal, so the device
provides an input signal to be used to block frequency rate-of-change protection.

EN [81Ri.En] &
81Ri.On
SIG 81Ri.Enable
&
SIG 81Ri.Block >=1 81Ri.Blocked

SIG Fail_Device
&
81Ri.Valid

Figure 3.22-1 Logic of enabling frequency rate-of-change protection

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The pickup logic of frequency rate-of-change protection is shown in Figure 3.22-2.

SIG [81Ri.df/dt_Set]>0
&
SET df/dt>[81Ri.df/dt_Set] >=1
SET Upp_min>[81.Upp_Blk]

SIG [81Ri.df/dt_Set]<0
&
SET df/dt<[81Ri.df/dt_Set]

SET Upp_min>[81.Upp_Blk]
&
0 500ms &
SIG 81Ri.On 81Ri.Pkp
3 SIG 81Ri.Valid
&
FD.Pkp
SET [81Ri.Opt_Trp/Alm]=Alm

Figure 3.22-2 Pickup logic of frequency rate-of-change protection

3.22.1.1 Operation Characteristics

The operating characteristics curve of frequency rate-of-change protection is shown in Figure


3.22-3.

[81Ri.t_Op]

-df/dt df/dt
-[81Ri.df/dt_Set] 0 [81Ri.df/dt_Set]

Figure 3.22-3 Definite-time operating curve of frequency rate-of-change protection

Frequency rate-of-change protection supports definite-time characteristics complied with IEC


60255-3 and ANSI C37.112. If the absolute value of the system frequency rate-of-change is
greater than the absolute value of the setting [81Ri.df/dt_Set], frequency rate-of-change
protection will operate with a time delay [81Ri.t_Op].

3.22.1.2 Dropout Characteristics

Frequency rate-of-change protection is with instantaneous dropout characteristics. If the absolute


value of the system frequency rate-of-change is less than the absolute value of the setting
[81Ri.df/dt_Set], frequency rate-of-change protection will drop out immediately.

3-182 PCS-978S Transformer Relay

Date: 2022-01-17
3 Protection Functions

3.22.2 Function Block Diagram

FreqCal

FreqCal.in_U3P FreqCal.FREQ

FreqCal.df/dt

81Ri

81Ri.In_FREQ 81Ri.St 3
81Ri.In_U3P 81Ri.Op

81Ri.Enable 81Ri.On

81Ri.Block 81Ri.Blocked

81Ri.Valid

81Ri.Alm

“FreqCal” is the frequency calculation element.

“81Ri” is the stage i of frequency rate-of-change element.

3.22.3 I/O Signals


Table 3.22-1 Input signals of frequency rate-of-change protection

No. Input Signal Description


1 FreqCal.in_U3P Three-phase voltage data input for frequency protection calculation element
2 81Ri.in_FREQ Frequency data input for stage i of frequency rate-of-change protection (i=1~2)
Three-phase voltage data input for stage i of frequency rate-of-change protection
3 81Ri.in_U3P
(i=1~2)
4 81Ri.Enable Input signal of enabling stage i of frequency rate-of-change protection (i=1~2)
5 81Ri.Block Input signal of blocking stage i of frequency rate-of-change protection (i=1~2)

Table 3.22-2 Output signals of frequency rate-of-change protection

No. Output Signal Description


1 FreqCal.FREQ A frequency data set, mainly used for the inputs of elements “81Oi”, “81Ui”.
2 f The calculated frequency value
3 FreqCal.df/dt The calculated rate-of-change of frequency value
4 81Ri.St Stage i of frequency rate-of-change protection starts. (i=1~2)
5 81Ri.Op Stage i of frequency rate-of-change protection operates. (i=1~2)
6 81Ri.On Stage i of frequency rate-of-change protection is enabled. (i=1~2)

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7 81Ri.Blocked Stage i of frequency rate-of-change protection is blocked. (i=1~2)


8 81Ri.Valid Stage i of frequency rate-of-change protection is valid. (i=1~2)
9 81Ri.Alm Stage i of frequency rate-of-change protection alarms. (i=1~2)

3.22.4 Logic

SIG [81Ri.df/dt_Set]>0
&
SET df/dt>[81Ri.df/dt_Set] &
SET Upp_min>[81.Upp_Blk]

SIG f>[81Ri.f_Pkp]

3 SIG [81Ri.df/dt_Set]<0
& >=1
SET df/dt<[81Ri.df/dt_Set] &
SET Upp_min>[81.Upp_Blk]
81Ri.St
SIG f<[81Ri.f_Pkp]
&
[81Ri.t_Op] 0
SIG 81Ri.Pkp
&
81Ri.Alm
SET [81Ri.Opt_Trp/Alm]=Alm

&
81Ri.Op
SET [81Ri.Opt_Trp/Alm]=Trp

Figure 3.22-4 Logic of frequency rate-of-change protection

3.22.5 Settings
Table 3.22-3 Settings of frequency rate-of-change protection

No. Name Range Unit Default Description


The phase-to-phase voltage setting used to
1 81Ri.Upp_Blk 10.000~150.000 V 70.000
block frequency rate-of-change protection
The frequency rate-of-change setting for
2 81Ri.df/dt_Set -5.000~5.000 Hz/s 0.500 stage i of frequency rate-of-change
protection (i=1~2)
The pickup frequency setting for stage i of
3 81Ri.f_Pkp 45.000~65.000 Hz 50.000
frequency rate-of-change protection (i=1~2)
The time delay for stage i of frequency
4 81Ri.t_Op 0.100~100.000 s 0.100
rate-of-change protection (i=1~2)
Disabled Enabling/disabling stage i of frequency
5 81Ri.En - Enabled
Enabled rate-of-change protection (i=1~2)
Enabling/disabling stage i of frequency
rate-of-change protection operate to trip or
Trp
6 81Ri.Opt_Trp/Alm - Trp alarm (i=1~2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose

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3.23 Distance Protection (21T)

When phase overcurrent protection and earth fault protection can’t meet the sensitivity
requirement of transformer backup protection, distance protection may be configured. The
operation mode of power system has little effect on impedance protection, so distance protection
cooperates with protections of the adjacent equipment more easily.

Distance protection includes three independent phase-to-phase measuring loops and three
independent phase-to-ground measuring loops. Both mho and quadrilateral characteristics are
available for different application. In addition, load encroachment, power swing blocking and
releasing, and faulty phase selection functions are also provided. 3
3.23.1 Functions Description
Up to 4 distance protection zones are supplied for high- and middle-voltage side of transformer
respectively. Each zone includes three independent phase-to-phase measuring loops and three
independent phase-to-ground measuring loops. Phase-to-ground distance element can be
compensated by zero-sequence current of local line. The distance protection zones can operate,
independent of each other, in forward direction, reverse direction or non-direction.

Load encroachment can distinguish effectively between heavily loaded line and faulty line, and the
risk of encroachment of the load impedance into the tripping characteristics of the distance
protection can be excluded.

Power swing blocking and releasing can prevent distance protection from undesired operation
during power swing, even if measured impedance reaches into the operation area of distance
protection. Moreover, distance protection can operate reliably when a fault occurs during power
swing.

Based on distance protection characteristics, faulty phase can be identified correctly. It is


beneficial for the faulty phase selection which is important to the line which uses
phase-segregated circuit breaker and provides valid information for 1-pole auto-reclosing and
fault location.

3.23.1.1 Faulter Detector

The current amplitude is calculated based on the injected analogue quantities. The fault detector
continuously detects the change of phase-to-phase power frequency current and the calculated
zero-sequence and negative-sequence currents. The fault detector includes:

1. Fault detector based on DPFC current: DPFC current is greater than the setting value

2. Fault detector based on zero-sequence current: Zero-sequence current is greater than the
setting value

3. Fault detector based on negative-sequence current: Negative-sequence current is greater


than the setting value

If any of the above conditions is satisfied, the fault detector will operate to start distance protection

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calculation.

 Fault Detector Based on DPFC Current

DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from


that of a cycle before.

∆I = I(k) − I(k − 24)

I(k) is the current sampling point.

I(k-24) is the value of the sampling point before a cycle, 24 is the sampling points cycle.

3 200

100

-100

-200
0 20 40 60 80 100 120
Original Current
100

50

-50

-100
0 20 40 60 80 100 120
DPFC current

From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection. It is used to determine
whether this pickup condition is met according to Equation 3.23-1.

For multi-phase short-circuit fault, DPFC phase-to-phase current has high sensitivity to
ensure the pickup of protection device. For usual single phase to earth fault, it also has
sufficient sensitivity to pick up except the earth fault with very large fault resistance. Under
this condition, DPFC current may be very small and the sensitivity is reduced, however,
zero-sequence current is used to remedy the reduction of the sensitivity.

This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steady under normal or power swing
condition, the adaptive floating threshold with the ΔISet is higher than the change of current
under these conditions and hence maintains the element stability.

The criterion is:

ΔIΦΦMAX>1.25ΔITh+ΔISet Equation 3.23-1

Where:

ΔIΦΦMAX: The maximum half-wave integration value of phase-to-phase current (ΦΦ=AB, BC,
CA)

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ΔISet: The fixed threshold value (i.e. the setting [x.FD.DPFC.I_Set])

ΔITh: The floating threshold value

The coefficient, 1.25, is an empirical value which ensures that the threshold is always higher
than the unbalance current of the system.

If operation condition are satisfied, the fault detector based on DPFC current will operate. The
pickup signal will maintain 5s after the fault detector based on DPFC current drops off.

 Fault Detector Based on Zero-sequence Current

The operation condition will be satisfied when zero-sequence current (3I0) is greater than the
setting [x.FD.ROC.3I0_Set]. The fault detector based on zero-sequence current is always in 3
service. (3I0: zero-sequence current is calculated from the vector sum of Ia, Ib and Ic)

If operation condition are satisfied, the fault detector based on zero-sequence current will
operate. The pickup signal will maintain 5s after the fault detector based on zero-sequence
current drops off.

 Fault Detector Based on Negative-sequence Current

The operation condition will be satisfied when negative-sequence current (I2) is greater than
the setting [x.FD.NOC.I2_Set].

If operation condition are satisfied, the fault detector based on negative-sequence current will
operate. The pickup signal will maintain 5s after the fault detector based on
negative-sequence current drops off.

3.23.1.2 Quadrilateral Distance Protection

For forward direction or reverse direction close-in fault, the voltage of faulty phase is 0, the
measured impedance of faulty phase is located in the origin of R-X plane, so it can’t be
distinguished as forward direction or reverse direction fault if not handled.

For solving the problem, the positive-sequence voltage is used as polarized voltage to distinguish
between forward direction fault and reverse direction fault. As shown in Figure 3.23-1 and Figure
3.23-2, line OA and line OE are named direction line which has good direction characteristics with
positive-sequence voltage as the polarized voltage.

Phase comparison equation of forward direction distance element is:

U̇1
−β ≤ Arg ≤ 90° + α Equation 3.23-2

Phase comparison equation of reverse direction distance element is:

U̇1
180° − β ≤ Arg ≤ 270° + α Equation 3.23-3

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Where:

 For phase-to-ground distance element, taking phase-A as an example

U̇1 is positive-sequence voltage, U̇1 = U̇A1

İ is phase current compensated by zero-sequence current, İ = İA + K 0 × 3İ0

K0 is zero-sequence compensation coefficient.

 For phase-to-phase distance element, taking phase-AB as an example

U̇1 is positive-sequence voltage, U̇1 = U̇AB1

3 İ is phase current compensated by zero-sequence current, İ = İAB

jX

B Z_Set
θ D
C
Dꞌ

A
α
φ φ
R
R_Offset O β R_Set
E

Figure 3.23-1 Quadrilateral forward direction distance element

jX

E
R_Set β O R_Offset
R
φ φ
α
A

Dꞌ C
θ
B
D Z_Set

Figure 3.23-2 Quadrilateral reverse direction distance element

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jX

B Z_Set
D
C

φ φ φ
R
R_Offset R
φ O

3
A
Z_Offset E

Figure 3.23-3 Quadrilateral non direction distance element

Where:

Z_Set is the impedance setting.

R_Set is the resistance setting.

Z_Set is the offset impedance setting.

R_Set is the offset resistance setting.

α is the angle of directional line OA in the second quadrant.

β is the angle of directional line OE in the fourth quadrant.

θ is downward offset angle of the reactance line, which is used to prevent distance protection from
overreaching.

φ is line positive-sequence characteristic angle, which is shared by phase-to-ground distance


element and phase-to-phase distance element.

For forward direction or reverse direction close-in three-phase fault, positive-sequence voltage is
almost 0, so the dead zone of distance protection for a close-in three-phase fault must be
eliminated. Memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltages adopts 2 cycles pre-fault positive-sequence voltage.

When the memory fades out, the operating characteristics will be shifted toward forward direction
or reverse direction, as shown in Figure 3.23-4 and Figure 3.23-5.

The shift impedance setting is fixed as ZShift=Z_Set/8 by default, 4ohm<ZShift<10ohm.

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jX

B Z_Set
θ D
C
Dꞌ

A α
φ φ
O R
R_Offset β R_Set
ZShift
3 E

Figure 3.23-4 Shift impedance characteristics of forward direction

jX

B Z_Set
θ D
C
A
Dꞌ

α ZShift
E φ
R_Offset φ R
β R_Set
O

Figure 3.23-5 Shift impedance characteristics of reverse direction

For reverse direction distance element, the similar treatment as forward direction distance
element can be adopted, by rotating the operation characteristics of forward direction distance
element 180°, the operating characteristics of reverse direction distance element can be gained.

3.23.1.3 Mho Distance Protection

For forward direction or reverse direction close-in fault, the voltage of faulty phase is almost 0, and
the measured impedance of faulty phase is located in the origin of R-X plane. Positive-sequence
voltage is used as polarized voltage to distinguish between forward direction fault and reverse
direction fault.

Phase comparison equation of forward direction distance element and reverse direction distance
element is:

U̇OP∅
−90° ≤ Arg ≤ 90°
U̇P∅

Where:

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U̇P∅ is the polarized positive-sequence voltage, i.e., U̇P∅ = −U̇1∅

U̇OP∅ is the operating voltage.

 For forward direction characteristics: U̇OP∅ = U̇ − İ × Z

1) For phase-to-ground distance element:

U̇ is phase voltage.

İ is phase current compensated by zero-sequence current.

Taking phase-A as an example: U̇OPA = U̇A − (İA + K 0 × 3İ0 ) × Z

2) For phase-to-phase distance element: 3


U̇ is phase-to-phase voltage.

İ is phase-to-phase current.

Taking phase-AB as an example: U̇OPAB = U̇AB − İAB × Z

 For reverse direction characteristics: U̇OP∅ = U̇ + İ × Z

1) For phase-to-ground distance element:

U̇ is phase voltage.

İ is phase current compensated by zero-sequence current.

Taking phase-A as an example: U̇OPA = U̇A + (İA + K 0 × 3İ0 ) × Z

2) For phase-to-phase distance element:

U̇ is phase-to-phase voltage.

İ is phase-to-phase current.

Taking phase-AB as an example: U̇OPAB = U̇AB + İAB × Z

 For non-direction characteristics U̇P∅ = U̇ + İ × ZOFFSET

1) For phase-to-ground distance element:

U̇ is phase voltage.

İ is phase current compensated by zero-sequence current.

Taking phase-A as an example: U̇PA = U̇A + (İA + K 0 × 3İ0 ) × ZOFFSET

2) For phase-to-phase distance element:

U̇ is phase-to-phase voltage.

İ is phase-to-phase current.

Taking phase-AB as an example: U̇PAB = U̇AB + İAB × ZOFFSET

Non direction distance element adopts offset characteristics and does not use

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positive-sequence voltage as polarized voltage, and operation voltage is as same as that of


forward direction distance element.

jX

Z
θ
C
D

3 φ

R
O

Figure 3.23-6 Mho forward direction distance element

jX

φ R

θ
Z

Figure 3.23-7 Mho reverse direction distance element

jX

Z_Set

R
φ O

Z_Offset

Figure 3.23-8 Mho non direction distance element

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Where:

Z_Set is the impedance setting.

Z_Offset is the offset impedance setting.

θ is downward offset angle of the reactance line, which is used to prevent distance protection from
overreaching.

φ is line positive-sequence characteristic angle, which is shared by phase-to-ground distance


element and phase-to-phase distance element.

For the fault in forward direction, the operating characteristics of phase-to-ground distance
element is shown in Figure 3.23-9. Operating characteristics on R-X plane is a circle with line 3
connecting ends of Z_Set and -2ZS/3 as the diameter. The origin is enclosed in the circle.

jX

Z_Set

R
O

-2Zs/3

Figure 3.23-9 Phase-to-ground operating characteristics for forward fault

Where:

Z_Set is the impedance setting.

ZS is total impedance between local system and protective device location

φ is positive-sequence sensitive angle.

For the fault in forward direction, the operating characteristics of phase-to-phase distance element
is shown in Figure 3.23-10. Operating characteristics on R-X plane is a circle with line connecting
ends of Z_Set and -ZS/2 as the diameter. The origin is enclosed in the circle.

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jX

Z_Set

R
O

-Zs/2

3
Figure 3.23-10 Phase-to-phase operating characteristics for forward fault

For the fault in reverse direction, the operating characteristics is shown in Figure 3.23-11. This
characteristics is a circle with line connecting ends of Z_Set and Z' S as the diameter.

ZꞋs

jX
Z_Set

R
O

Figure 3.23-11 Operating characteristics for reverse fault

Where:

Z'S is total impedance between remote system and protective device location.

For reverse direction distance element, its operating characteristics can be gained by rotating the
operating characteristics of forward direction distance element 180°.

For forward direction or reverse direction close-in three-phase fault, positive-sequence voltage is
also 0, so the dead zone of distance protection for a close-in three-phase fault must be eliminated.
Memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltages adopts 2 cycles pre-fault positive-sequence voltage. When the memory fades out, the
operating characteristics will be shifted toward forward direction or reverse direction.

For the fault in forward direction, as shown in Figure 3.23-12, C1 is the operating characteristics

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before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is enclosed in the impedance circle.

jX

Z_Set

φ
O

C2
R
3
Zs C1

Figure 3.23-12 Operating characteristics of three-phase close-in fault

For the fault in reverse direction, as shown in Figure 3.23-13, C1 is the operating characteristics
before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is not enclosed in the impedance circle.

ZꞋs

jX

C1
Z_Set

C2
φ
O
R

Figure 3.23-13 Operating characteristics of three-phase close-in fault

The distance protection with such design thoroughly eliminates the dead zone when three-phase
close-in fault occurs. It also has favorable directivity and will not operate for a reverse three-phase
fault at busbar.

3.23.1.4 Zero-sequence Current Compensation

For three-phase transmission line, the faulty phase is affected by the current of non-faulty phase
due to the mutual inductance among phase-to-phase conductors.

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ZL

ZM
IA

IB ZM

IC
UC UB UA

3 Figure 3.23-14 Phase-to-phase mutual inductance

Where:

ZL is line impedance

ZM is line mutual impedance

For metallic fault:

U̇A = İA × ZL + İB × ZM + İC × ZM = İA × (ZL − ZM ) + (İA + İB + İC ) × ZM

For three-phase symmetric line:

ZL1 = ZL − ZM

ZL0 = ZL + 2ZM

ZL1 is line positive-sequence impedance

ZL0 is line zero-sequence impedance

ZL0 − ZL1
ZM =
3

Z −Z ZL0 −ZL1
Hence, U̇A = İA × ZL1 + (İA + İB + İC ) × L0 3 L1 = (İA + 3İ0 × 3×Z ) × ZL1
L1

Zero-sequence compensation coefficient K 0

ZL0 − ZL1
K0 =
3 × ZL1

U̇A = (İA + K 0 × 3İ0 ) × ZL1

The device provides zero-sequence compensation coefficient to fulfill zero-sequence current


compensation.

For parallel double-circuit lines, due to mutual inductance of zero-sequence current from the
adjacent line, phase-to-ground characteristics of distance protection will be affected.

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ZL1

Z
I
3I0I ZM0

II
3I0II

Figure 3.23-15 Zero-sequence mutual inductance for double-circuit lines

Where: 3
3I0I is residual current of line I.

3I0II is residual current of line II.

ZM0 is mutual zeros-sequence current between line I and line II.

When phase-A earth fault happens to line I , phase-A voltage is:

U̇A = (İA + K 0 × 3İ0 ) × ZL1 + 3İ0II × ZM0

Due to mutual inductance of zero-sequence current from the adjacent line, the error item 3İ0II ×
ZM0 is imported. According to the actual application, K 0 and the setting range of distance
protection shall be adjusted reasonably to avoid undesired operation.

3.23.1.5 Load Encroachment

When distance protection is used to protect long, heavily loaded lines, the risk of encroachment of
the load impedance into the tripping characteristics of the distance protection may exist. A load
encroachment characteristics for all zones is used to exclude the risk of unwanted fault detected
by distance protection during heavy load flow. As shown in Figure 3.23-16, if the measured
impedance locate in the load area, distance protection will be blocked.

jX

φLoad φLoad
Load Area Load Area
R
O
RLoad RLoad

Figure 3.23-16 Distance element with load encroachment

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Two settings are equipped to exclude the encroachment of the load impedance:

RLoad: the minimum load resistance

φLoad: the load area angle

These values are common for all zones.

3.23.1.6 Power Swing Blocking and Releasing

When power swing occurs on the power system, the impedance measured by the distance
measuring element may vary from the load impedance area into the operating zone of the

3 distance element. The distance measuring element may operate due to the power swing occurs at
many points of interconnected power systems. To keep the stability of whole power system,
tripping due to operation of the distance measuring element during a power swing is generally not
allowed. Distance protection adopts power swing blocking releasing to avoid maloperation
resulting from power swing. In another word, distance protection is blocked all along under the
normal condition and power swing when the respective logic settings are enabled. Only when fault
(internal fault or power swing with internal fault) is detected, power swing blocking for distance
protection is released by PSBR element.

Power swing blocking for distance element will be released if any of the following PSBR elements
operates. Each distance zone elements has respective setting for selection this function.

 Fault detector PSBR element (FD PSBR)

 Unsymmetrical fault PSBR element (UF PSBR)

 Symmetrical fault PSBR element (SF PSBR)

1. Fault detector PSBR element

If any of the following condition is matched, FD PSBR will operate for 160ms.

Positive sequence current is lower than the setting [x.21T.I_PSBR] before general fault
detector element operates.

As shown in figure below, assuming that normal load impedance locates at position 1 and the
impedance locates at position 2 when positive-sequence current is lower than the setting
[x.21T.I_PSBR], it means FD operates between point 1 and point 2 if operation condition for
FD PSBR mentioned above is fulfilled (point 3 as an example), and then FD PSBR will
operate for 160ms.

[x.21T.I_PSBR]
FD Normal load
impedance
Point 1
Point 2

Point 3

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2. Unsymmetrical fault PSBR element

The operation criterion:

I0+I2>m×I1

The “m”, an empirical value, is internal fixed coefficient which can ensure UF PSBR operation
during power swing with internal unsymmetrical fault, while no operation during power swing
or power swing with external fault.

This decision mainly utilizes the "discrepancy" that there is no negative-sequence or


zero-sequence current during power swing, and there are negative-sequence and
zero-sequence currents in case of asymmetric fault. In addition, value of m is used to
differentiate internal asymmetric fault and external asymmetric fault in case of power swing.
3
 In case of power swing or both power swing and external fault, asymmetric fault
discriminating element will not operate and distance protection will be blocked:

In case of power swing but no fault, I0 and I2 are near zero, but I1 is very large.
Asymmetric fault discriminating element will not operate.

In case of both power swing and external fault, if center of power swing is in scope of
protection, both phase-to-phase and grounding impedance relays may operate. At this
time, selection of value of m is used to ensure no operation of asymmetric fault
discriminating element, blocking of distance protection, and no incorrect operation
without selectivity. If power swing center is not on this line, distance protection will not
operate incorrectly without selectivity due to power swing.

 In case of internal asymmetric fault, asymmetric fault discriminating element operates


and distance protection will be release to clear internal fault:

In case of both power swing and internal fault, if at the instant of short circuit, system
electric potential angle is not laid out, asymmetric fault discriminating element will
operate at once. If at the instant of short circuit, system electric potential angle is laid out,
asymmetric fault discriminating element will operate when system angle gradually
decreases, or local side tripping may be activated after immediate operation of opposite
side asymmetric fault discriminating element and releasing of distance protection tripping.
In case of normal internal asymmetric phase-to-phase or grounding fault in the system,
relatively large zero-sequence or negative-sequence component will exist. At this time,
the above equation is true and distance protection will be released.

3. Symmetrical fault PSBR element

If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD
PSBR nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is
provided for this case specially. This detection is based on measuring the voltage at power
swing center, during power swing, U1cosΦ will constantly change periodically.

UOS=U1×COSΦ

Where:

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Φ: the angle between positive sequence voltage and current

U1: the positive sequence voltage

As shown in the figure below, assume system connection impedance angle of 90°, current
vector will be perpendicular to the line connecting E M and EN, and have the same phase as
power swing center voltage. During normal operation of system or power swing, U1cosΦ just
reflects positive-sequence voltage of power swing center. In case of 3-phase short circuit,
U1cosΦ is voltage drop on arc resistor, transition resistance is arc resistance, and voltage
drop on arc resistor is less than 5%UN. In actual system, line impedance angle is not 90°.
Through compensation of angle Φ, power swing center voltage can be measured accurately.

3 After compensation, power swing center voltage is U1cos(Φ+90o-ΦL), where ΦL is line


impedance angle.

I
EM U EN
UOS

During power swing, power swing center voltage U1cosΦ has the following characteristics:
When electric potential phase angle difference between power supplies at two sides is 180 o,
U1cosΦ=0 and change rate dU1cosΦ/dt is the maximum. When this phase angle difference
is near 0o, power swing center voltage change rate dU 1cosΦ/dt is the minimum. During short
circuit, U1cosΦ remains unchanged and dU1cosΦ/dt=0. However, in early stage of short
circuit when normal state enters short circuit state, dU1cosΦ/dt is very large. Therefore, use
of dU1cosΦ/dt solely to differentiate power swing and short circuit is not complete.

For these reasons, the method to release distance protection on condition that power swing
center voltage U1cosΦ is less than a setting and after a short delay can be used as symmetric
fault discriminating element. This element can accurately differentiate power swing and
3-phase short circuit fault, and constitute a complete power swing blocking scheme with other
elements. The element to open distance protection if U 1cosΦ is less than a certain setting
and after a delay is easy to realize and has short delay, and can trip fault more quickly and
accurately trip 3-phase short circuit fault during power swing.

The criterion of SF PSBR element comprises the following two parts:

 when -0.03UN<UOS<0.08UN, the SF PSBR element will operate after 150ms.

 when -0.1UN<UOS<0.25UN, the SF PSBR element will operate after 500ms.

The second criterion is a backup of the first criterion allowing longer monitoring period of
voltage variation.

To reduce the time delay for SF PSBR element during power swing, the change rate of
voltage at power swing center is also used which can release SF PSBR element quickly for

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the fault occurred during power swing. The typical release time is less than 60ms.

3.23.1.7 Faulty Phase Selection

The realization of phase-segregated tripping and fault location depends on the faulty phase
selection. Each zone of distance protection contains three phase-to-ground measuring elements
and three phase-to-phase measuring elements, so non-faulty phase maybe operates when there
is a fault. For example, for near-end phase A fault, phase A distance element operates, while
phase AB and phase CA distance element are also possible to operate. Therefore, the faulty
phase selection of distance protection cannot only depend on the operating phase of distance
protection.

For single-phase fault, three phase-to-ground distance elements, three phase-to-phase distance
3
elements and the angle relation between I0 and I2A can effectively distinguish faulty phase. As
shown in Figure 3.23-17,

I
 −60° < 𝐴𝑟𝑔 I 0 < 60° region A is selected
2A

I
 60° < 𝐴𝑟𝑔 I 0 < 180° , region B is selected
2A

I
 180° < 𝐴𝑟𝑔 I 0 < 300° , region C is selected
2A

Region A
60° -60°

Region B Region C

180°

Figure 3.23-17 Faulty phase selection based on I0 and I2A

Zero-sequence current is used to distinguish between earth fault and phase-to-phase fault. For
earth fault, associating the angle relation between I0 and I2A, the operating phase of distance
protection can determine faulty phase. For phase-to-phase fault, the faulty phase is detected by
comparing the relative relationship of distance protection operating.

3.23.1.8 Time Delay Characteristics

For each distance protection zone, the three phase-to-ground distance elements share the same
time relay, and the three phase-to-phase distance elements share the same time relay.

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When there is a transferring fault, operating time of distance protection with time delay is subject
to the beginning of the first fault. For example:

T=0ms: there is phase A earth fault in the range of zone 2.

T=100ms: phase A earth fault is transferred into phase B earth fault.

T=150ms: the circuit breaker of phase A is open.

If the time delay of zone 2 of phase-to-ground distance element is set as 400ms, zone 2 of
phase-to-ground distance element will operate at T=400ms not T=500ms. However, time delay of
each distance protection zone is independent.

3 3.23.2 Function Block Diagram

x.21T.FD

x.21T.FD.in_U3p x.21T.FD.Pkp

x.21T.FD.in_I3p x.21T.FD.DPFC.Pkp

x.21T.FD.ROC.Pkp

x.21T.FD.NOC.Pkp

x.21T.FD.Alm_Pkp

x.21T

x.21T.Enable x.21T.On

x.21T.Block x.21T.Blocked

x.21T.FwdDir_ZeroSeq x.21T.Valid

x.21T.RevDir_ZeroSeq

x.21T.FwdDir_NegSeq

x.21T.RevDir_NegSeq

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x.21Ti

x.21Ti.Enable x.21Ti.On

x.21Ti.Block x.21Ti.Op

x.21Ti.ZG.Enable x.21Ti.Op.PhA

x.21Ti.ZG.Block x.21Ti.Op.PhB

x.21Ti.ZP.Enable x.21Ti.Op.PhC

x.21Ti.ZP.Block x.21Ti.ZG.LoadEnch.St

x.21Ti.Enable_PSBR x.21Ti.ZG.LoadEnch.StA 3
x.21Ti.Block_PSBR x.21Ti.ZG.LoadEnch.StB

x.21Ti.ZG.LoadEnch.StC

x.21Ti.ZP.LoadEnch.St

x.21Ti.ZP.LoadEnch.StAB

x.21Ti.ZP.LoadEnch.StBC

x.21Ti.ZP.LoadEnch.StCA

“x.21T.FD” is the fault detector element of distance protection.

“x.21T” is the common control element of distance protection.

“x.21Ti” is the zone i of distance element.

3.23.3 I/O Signals


Table 3.23-1 Input signals of distance protection

No. Input Signal Description


Three-phase current data input for fault detector element of distance
1 x.21T.FD.in_I3p
protection
Three-phase voltage data input for fault detector element of distance
2 x.21T.FD.in_U3p
protection
3 x.21T.Enable Input signal of enabling side x of distance protection
4 x.21T.Block Input signal of blocking side x of distance protection
5 x.21T.FwdDir_ZeroSeq Input signal of forward direction element of 50/51G
6 x.21T.RevDir_ZeroSeq Input signal of reverse direction element of 50/51G
7 x.21T.FwdDir_NegSeq Input signal of forward direction element of 50/51Q
8 x.21T.RevDir_NegSeq Input signal of reverse direction element of 50/51Q
9 x.21Ti.Enable Input signal of enabling zone i of distance protection (i=1~4)
10 x.21Ti.Block Input signal of blocking zone i of distance protection (i=1~4)

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11 x.21Ti.ZG.Enable Input signal of enabling zone i of phase-to-ground distance element (i=1~4)


12 x.21Ti.ZG.Block Input signal of blocking zone i of phase-to-ground distance element (i=1~4)
13 x.21Ti.ZP.Enable Input signal of enabling zone i of phase-to-phase distance element (i=1~4)
14 x.21Ti.ZP.Block Input signal of blocking zone i of phase-to-phase distance element (i=1~4)
Input signal of enabling power swing blocking releasing for zone i of
15 x.21Ti.Enable_PSBR
distance protection (i=1~4)
Input signal of blocking power swing blocking releasing for zone i of distance
16 x.21Ti.Block_PSBR
protection (i=1~4)

Table 3.23-2 Output signals of distance protection

3 No. Output Signal Description


1 x.21T.FD.Pkp The fault detector of distance protection operates.
2 x.21T.FD.DPFC.Pkp DPFC current fault detector element operates.
3 x.21T.FD.ROC.Pkp Zero-sequence current fault detector element operates.
4 x.21T.FD.NOC.Pkp Negative-sequence fault detector element operates.
5 x.21T.FD.Alm_Pkp Fault detector element operates for more than 50s.
6 x.21T.On Side x of distance protection is enabled.
7 x.21T.Blocked Side x of distance protection is blocked.
8 x.21T.Valid Side x of distance protection is valid.
9 x.21Ti.On Zone i of distance protection is enabled. (i=1~4)
10 x.21Ti.Op Zone i of distance protection operates (i=1~4)
11 x.21Ti.Op.PhA Zone i of distance protection operates (Phase A, i=1~4)
12 x.21Ti.Op.PhB Zone i of distance protection operates (Phase B, i=1~4)
13 x.21Ti.Op.PhC Zone i of distance protection operates (Phase C, i=1~4)
14 x.21Ti.ZG.LoadEnch.St Zone i of phase-to-ground load encroachment starts. (i=1~4)
15 x.21Ti.ZG.LoadEnch.StA Zone i of phase-to-ground load encroachment starts. (Phase A, i=1~4)
16 x.21Ti.ZG.LoadEnch.StB Zone i of phase-to-ground load encroachment starts. (Phase B, i=1~4)
17 x.21Ti.ZG.LoadEnch.StC Zone i of phase-to-ground load encroachment starts. (Phase C, i=1~4)
18 x.21Ti.ZP.LoadEnch.St Zone i of phase-to-phase load encroachment starts. (i=1~4)
19 x.21Ti.ZP.LoadEnch.StAB Zone i of phase-to-phase load encroachment starts. (Phase AB, i=1~4)
20 x.21Ti.ZP.LoadEnch.StBC Zone i of phase-to-phase load encroachment starts. (Phase BC, i=1~4)
21 x.21Ti.ZP.LoadEnch.StAC Zone i of phase-to-phase load encroachment starts. (Phase AC, i=1~4)

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3.23.4 Logic

SIG x.Ia Calculate DPFC phase-to- Δx.Iab>[x.21T.FD.DPFC.I_Set]


phase current: >=1
Δx.Iab=Δ(x.Ia-x.Ib)
SIG x.Ib Δx.Ibc>[x.21T.FD.DPFC.I_Set] x.21T.FD.DPFC.Pkp
Δx.Ibc=Δ(x.Ib-x.Ic)
Δx.Ica=Δ(x.Ic-x.Ia)
SIG x.Ic Δx.Ica>[x.21T.FD.DPFC.I_Set] >=1
0s 5s x.21T.FD.Pkp
FD.Pkp

Calculate residual current:


x.3I0>[x.21T.FD.ROC.3I0_Set] x.21T.FD.ROC.Pkp
x.3I0=x.Ia+x.Ib+x.Ic

Calculate negative-
sequence current: x.I2
x.I2>[x.21T.FD.NOC.I2_Set] x.21T.FD.NOC.Pkp 3
SIG x.21T.FD.Pkp 50s 10s x.21T.FD.Alm_Pkp

Figure 3.23-18 Logic of fault detector

SIG x.21T.Enable x.21T.On


&
SIG x.21T.Block >=1 x.21T.Blocked

SIG Fail_Device
&
x.21T.Valid

SIG x.21T.Valid
&
SIG x.21Ti.Enable

SIG x.21Ti.Block

EN [x.21Ti.ZG.En]
& &
& x.21Ti.ZG.Enabled
SIG x.21Ti.ZG.Enable

SIG x.21Ti.ZG.Block >=1


& x.21Ti.On
EN [x.21Ti.ZP.En]
&
SIG x.21Ti.ZP.Enable

SIG x.21Ti.ZP.Block

SIG x.VTS.Alm
&
>=1 x.21Ti.ZP.Enabled
SIG x.BI_En_VT &

EN [x.En_VT]

Figure 3.23-19 Logic of enabling distance protection (i=1~4)

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SIG x.21Ti.ZG.Enabled
&
SIG x.21T.FD.Pkp x.21Ti.Flag.ZG

EN [x.21Ti.ZG.En_3I0] >=1

SET 3I0>[FD.ROC.3I0_Set]

EN [x.21Ti.ZG.En_NeuDir_Blk]

SET [x.21Ti.DirMode]=Forward
&
& & x.21Ti.Flg_PSBR_ZG
>=1
SIG x.50/51G.DIR.Rev
3 SET [x.21Ti.DirMode]=Reverse &

SIG x.50/51G.DIR.Fwd

EN [x.21Ti.ZG.En_NegDir_Blk]
&
SET [x.21Ti.DirMode]=Forward & &
>=1
SIG x.50/51Q.DIR.Rev

SET [x.21Ti.DirMode]=Reverse &

SIG x.50/51Q.DIR.Fwd

SIG x.21Ti.ZG.StA
&
SET x.Ia>0.04In

SIG x.21Ti.LoadEnchPG.StA

SIG x.21Ti.ZG.StB
& >=1
SET x.Ib>0.04In

SIG x.21Ti.LoadEnchPG.StB

SIG x.21Ti.ZG.StC
&
SET x.Ic>0.04In

SIG x.21Ti.LoadEnchPG.StC

Figure 3.23-20 Logic of distance protection (phase-to-ground, i=1~4)

"x.21Ti.ZG.StA" means that zone i of phase-to-ground distance element starts. (phase A)

"x.21Ti.ZG.StB" means that zone i of phase-to-ground distance element starts. (phase B)

"x.21Ti.ZG.StC" means that zone i of phase-to-ground distance element starts. (phase C)

"x.21Ti.Flag.ZG" means that measured impedance of zone i of phase-to-ground distance element


is inside the operation area.

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SIG x.21Ti.ZP.Enabled
&
SIG x.21T.FD.Pkp x.21Ti.Flag.ZP

EN [x.21Ti.ZP.En_NegDir_Blk]

SET [x.21Ti.DirMode]=Forward & &


>=1 &
SIG x.50/51Q.DIR.Rev x.21Ti.Flg_PSBR_ZP

SET [x.21Ti.DirMode]=Reverse &

SIG x.50/51Q.DIR.Fwd

SIG x.21Ti.ZP.StAB
3
&
SET x.Iab>0.04In

SIG x.21T.LoadEnchPP.StAB

SIG x.21Ti.ZP.StBC
& >=1
SET x.Ibc>0.04In

SIG x.21T.LoadEnchPP.StBC

SIG x.21Ti.ZP.StCA
&
SET x.Ica>0.04In

SIG x.21T.LoadEnchPP.StCA

Figure 3.23-21 Logic of distance protection (phase-to-phase, i=1~4)

"x.21Ti.ZP.StAB" means that zone i of phase-to-phase distance element starts. (phase AB)

"x.21Ti.ZP.StBC" means that zone i of phase-to-phase distance element starts. (phase BC)

"x.21Ti.ZP.StCA" means that zone i of phase-to-phase distance element starts. (phase CA)

"x.21Ti.Flag.ZP" means that measured impedance of zone i of phase-to-phase distance element


is inside the operation area.

SIG x.21Ti.Rls_PSBR &


[x.21Ti.ZG.t_Op] 0 x.21Ti.ZG.Op
SIG x.21Ti.Flag.ZG
>=1
x.21Ti.Op

&
[x.21Ti.ZP.t_Op] 0 x.21Ti.ZP.Op
SIG x.21Ti.Flag.ZP

Figure 3.23-22 Logic of distance protection operating (zone i, i=1~4)

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3 Protection Functions

SIG x.21Ti.Flg_PSBR_ZG >=1


x.21Ti.Flg_PSBR
SIG x.21Ti.Flg_PSBR_ZP

SIG x.21Ti.En_PSBR &


x.21Ti.Enable_PSBR
SIG x.21Ti.Blk_PSBR

SIG x.21T.FD.Pkp &

SIG x.21Ti.Flg_PSBR

SIG x.21Ti.Enable_PSBR &


3 EN [x.21Ti.En_PSBR]
>=1
SIG -0.03Un<U1cosΦ<0.08Un 150ms 0 &
>=1 x.21Ti.Rls_PSBR
SIG -0.1Un<U1cosΦ<0.25Un 500ms 0

>=1
&
SIG |I0|+|I2|>m×I1

SIG x.21Ti.Flg_PSBR

SET x.I1>[x.21T.I_PSBR] 0 3s & &


0 160ms >=1
SIG x.21T.FD.Pkp

Figure 3.23-23 Logic of PSBR (i=1~4)

"x.21Ti.Rls_PSBR" is the releasing signal of power swing blocking element for zone i of distance
protection.

"x.21Ti.Flg_PSBR_ZG" is the operating condition of power swing blocking element for zone i of
phase-to-ground distance element.

"x.21Ti.Flg_PSBR_ZP" is the operating condition of power swing blocking element for zone i of
phase-to-phase distance element.

3.23.5 Settings
Table 3.23-3 Settings of distance protection

No. Name Range Unit Default Description


Current setting of DPFC current
1 x.21T.FD.DPFC.I_Set (0.050~40.000)×In A 0.100
fault detector element
Current setting of residual current
2 x.21T.FD.ROC.3I0_Set (0.050~40.000)×In A 0.100
fault detector element
3 x.21T.FD.NOC.I2_Set (0.050~40.000)×In A 0.100 Current setting of

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No. Name Range Unit Default Description


negative-sequence current fault
detector element
The angle of directional line in the
4 x.21T.Ang_Alpha 5~30 ° 15 second quadrant for quadrilateral
phase-to-ground distance element
The angle of directional line in the
5 x.21T.Ang_Beta 5~30 ° 15 fourth quadrant for quadrilateral
phase-to-ground distance element
Angle setting of load trapezoid
characteristics, it should be set 3
6 x.21T.LoadEnch.phi 5~50 ° 12 according to the maximum load
area angle (φLoad_Max), φLoad_Max+5°
is recommended.
Resistance setting of load
trapezoid characteristics, it should
be set according to the minimum
7 x.21T.LoadEnch.R_Set (0.000~4Unn)/In Ω 40.000
load resistance, 70%~90%
minimum load resistance is
recommended.
Current setting for power swing
8 x.21T.I_PSBR (0.050~30.000)×In A 1.000
blocking releasing
Mho Characteristics option of
9 x.21T.ZG.Opt_Characteristic - Mho
Quad phase-to-ground distance element
Mho Characteristics option of
10 x.21T.ZP.Opt_Characteristic - Mho
Quad phase-to-phase distance element
Forward
Direction option for zone i of
11 x.21Ti.DirMode Reverse - Forward
distance protection (i=1~4)
Non_Directional
Real component of zero-sequence
12 x.21Ti.Real_K0 -4.000~4.000 - 0.660 compensation coefficient for zone i
of distance protection (i=1~4)
Imaginary component of
zero-sequence compensation
13 x.21Ti.Imag_K0 -4.000~4.000 - 0.000
coefficient for zone i of distance
protection (i=1~4)
Phase angle of positive-sequence
14 x.21Ti.phi1_Reach 30~89 ° 78 impedance for zone i of distance
protection (i=1~4)
Downward offset angle of the
reactance line for zone i of
15 x.21Ti.ZG.RCA 0~45 ° 12
phase-to-ground distance element
(i=1~4)
16 x.21Ti.ZG.Z_Set (0.000~4Unn)/In Ω 10.000 Impedance setting of zone i of

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3 Protection Functions

No. Name Range Unit Default Description


phase-to-ground distance element
(i=1~4)
Shift impedance setting of zone i of
17 x.21Ti.ZG.Z_Offset (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element
(i=1~4)
Resistance setting of zone i of
18 x.21Ti.ZG.R_Set (0.000~4Unn)/In Ω 10.000 quadrilateral phase-to-ground
distance element (i=1~4)
Shift resistance setting of zone i of

3 19 x.21Ti.ZG.R_Offset (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element


(i=1~4)
Time delay of zone i of
20 x.21Ti.ZG.t_Op 0.000~10.000 s 0.200 phase-to-ground distance element
(i=1~4)
Enabling/disabling zone i of
Disabled
21 x.21Ti.ZG.En - Enabled phase-to-ground distance element
Enabled
(i=1~4)
Enabling/disabling zone i of
Disabled phase-to-ground distance element
22 x.21Ti.ZG.En_3I0 - Disabled
Enabled controlled by residual current fault
detector element (i=1~4)
Enabling/disabling zone i of
phase-to-ground distance element
Disabled
23 x.21Ti.ZG.En_NeuDir_Blk - Enabled blocked by direction control
Enabled
element of earth fault protection
(i=1~4)
Enabling/disabling zone i of
phase-to-ground distance element
Disabled
24 x.21Ti.ZG.En_NegDir_Blk - Enabled blocked by direction control
Enabled
element of negative-sequence
overcurrent protection (i=1~4)
Downward offset angle of the
reactance line for zone i of
25 x.21Ti.ZP.RCA 0~45 ° 12
phase-to-phase distance element
(i=1~4)
Impedance setting of zone i of
26 x.21Ti.ZP.Z_Set (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(i=1~4)
Shift impedance setting of zone i of
27 x.21Ti.ZP.Z_Offset (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(i=1~4)
Resistance setting of zone i of
28 x.21Ti.ZP.R_Set (0.000~4Unn)/In Ω 10.000
quadrilateral phase-to-phase

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No. Name Range Unit Default Description


distance element (i=1~4)
Shift resistance setting of zone i of
29 x.21Ti.ZP.R_Offset (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(i=1~4)
Time delay of zone i of
30 x.21Ti.ZP.t_Op 0.000~10.000 s 0.200 phase-to-phase distance element
(i=1~4)
Enabling/disabling zone i of
Disabled
31 x.21Ti.ZP.En - Enabled phase-to-phase distance element
Enabled
(i=1~4) 3
Enabling/disabling zone i of
phase-to-phase distance element
Disabled
32 x.21Ti.ZP.En_NegDir_Blk - Enabled blocked by direction control
Enabled
element of negative-sequence
overcurrent protection (i=1~4)
Enabling/disabling load trapezoid
Disabled
33 x.21Ti.LoadEnch.En - Enabled characteristics for zone i of
Enabled
distance protection (i=1~4)
Enabling/disabling zone i of
Disabled
34 x.21Ti.En_PSBR - Enabled distance protection controlled by
Enabled
PSBR (i=1~4)
Enabling/disabling zone i of
Disabled
35 x.21Ti.En_ReacLine - Disabled distance protection controlled by
Enabled
the reactance line (i=1~4)

3.24 Output Map (OutMap)

Output map controls tripping outputs of protection elements and programmable logics. Each
protection element has its corresponding tripping logic setting used to configure tripping output
contacts, and 120 tripping outputs of programmable logics are equipped for visual logic
programming.

3.24.1 Function Description

All tripping output contacts are with a settable dwell time to ensure sufficient time of tripping
command to open the circuit breaker.

3.24.1.1 Protection Element Trip Output

Each protection element can control total 32 groups of tripping output contacts by tripping logic
settings. Therefore, the user can configure the tripping output contacts of each protection element
individually though the corresponding tripping logic setting. 32 groups of independent tripping
output contacts can be defined to trip HV side, MV side, and LVS side etc. Each group of tripping
contacts can correspond to certain amount of contacts on binary output plug-in modules.

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Tripping logic settings are used to specify which breakers will be tripped when some protection
element operates. This logic setting comprises 32 binary bits as follows and is expressed by a
hexadecimal number of 8 digits from 00000000H to FFFFFFFFH. The tripping logic setting is
specified as follows:

Bit Definition Bit Definition


0 Output001 16 Output017
1 Output002 17 Output018
2 Output003 18 Output019
3 Output004 19 Output020
4 Output005 20 Output021
3 5 Output006 21 Output022
6 Output007 22 Output023
7 Output008 23 Output024
8 Output009 24 Output025
9 Output010 25 Output026
10 Output011 26 Output027
11 Output012 27 Output028
12 Output013 28 Output029
13 Output014 29 Output030
14 Output015 30 Output031
15 Output016 31 Output032

“Output001” just means to drive the 1st group of tripping output contacts and please refer to
Chapter “Hardware”. The tripping outputs are recorded as “Output001_OutMap ~
Output032_OutMap” by the device when they operate, and “Outputxxx” (xxx=001, 002…032)
represents “trip output xxx” (xxx=001, 002…032). The circuit breaker corresponding with bit which
is set as “1” will be tripped. Tripping output logic settings should be set on basis of
application-specific drawings.

For example, if transformer differential protection operates to make “Output001”, “Output002”,


“Output003” contacts pickup, bit “0”, bit “1” and bit “2” shall be filled with “1” and other bits shall be
filled with “0”. Then a hexadecimal number 00000007H is formed as the tripping output logic
setting, i.e. [87T.OutMap] shall be set as “00000007H”.

3.24.1.2 Programmable Trip Output

The device provides 120 programmable trip output with I/O signals and settings for users used by
visualization programming.

For example, if it is required to set stage 1 of phase overcurrent protection at HV side of the
transformer operate to issue trip command after its operation criterion is satisfied “AND” receiving
a binary input which can be a blocking signal from other device, programmable trip output can
complete the function configuration as following steps.

1. Finish required programming logic by PCS-Studio.

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2. Connect final output of programming logic to input signal of programmable trip output.

3. Set corresponding tripping logic setting of programmable trip output to complete the function
configuration.

3.24.2 I/O Signals


Table 3.24-1 Output signals of programmable trip output

No. Output signal Description


Outputxxx_OutMap
1 Output signal of programmable tripping output element xxx.
(xxx=001, 002…032)

3.24.3 Settings
3
Table 3.24-2 Settings of programmable trip output

No. Name Range Unit Default Description


OutMapxxx 0X0~
1 - 0X1 0X0~ 0XFFFFFFFF
(xxx=001, 002…120) 0XFFFFFFFF
t_Dwell_xxx_OutMap The pulse width setting of programmable trip
2 0.000~0.500 s 0.060
(xxx=001, 002…032) output map xxx

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4 Control Functions

Table of Contents

4.1 Switchgear Control .......................................................................................... 4-1


4.1.1 Function Description............................................................................................................. 4-2

4.1.2 Function Block Diagram ....................................................................................................... 4-5

4.1.3 I/O Signals ............................................................................................................................ 4-5

4.1.4 Logics ................................................................................................................................... 4-7

4.1.5 Settings ............................................................................................................................... 4-10


4
4.2 Manual Closing Synchronism Check ............................................................4-11
4.2.1 Function Description........................................................................................................... 4-12

4.2.2 Function Block Diagram ..................................................................................................... 4-14

4.2.3 I/O Signals .......................................................................................................................... 4-14

4.2.4 Logics ................................................................................................................................. 4-15

4.2.5 Settings ............................................................................................................................... 4-18

4.3 Voltage Selection ........................................................................................... 4-20


4.3.1 Function Description........................................................................................................... 4-20

4.3.2 Function Block Diagram ..................................................................................................... 4-23

4.3.3 I/O Signals .......................................................................................................................... 4-23

4.3.4 Logics ................................................................................................................................. 4-24

4.3.5 Settings ............................................................................................................................... 4-26

4.4 Tap Position Indication and Control ............................................................ 4-26


4.4.1 Function Description........................................................................................................... 4-27

4.4.2 I/O Signals .......................................................................................................................... 4-28

4.4.3 Logic ................................................................................................................................... 4-30

4.4.4 Settings ............................................................................................................................... 4-31

4.5 Automatic Voltage Regulation (90V) ............................................................ 4-32


4.5.1 Function Description........................................................................................................... 4-32

4.5.2 Function Block Diagram ..................................................................................................... 4-41

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Date: 2022-01-17
4 Control Functions

4.5.3 I/O Signals .......................................................................................................................... 4-41

4.5.4 Logic ................................................................................................................................... 4-43

4.5.5 Settings ............................................................................................................................... 4-43

4.6 Parallel Voltage Regulation (PVR) ................................................................ 4-45


4.6.1 Function Description........................................................................................................... 4-45

4.6.2 Function Block Diagram ..................................................................................................... 4-47

4.6.3 I/O Signals .......................................................................................................................... 4-48

4.6.4 Logic ................................................................................................................................... 4-49

4.6.5 Settings ............................................................................................................................... 4-50

4 List of Figures

Figure 4.1-1 Logic diagram of switchgear closing operation ............................................... 4-8

Figure 4.1-2 Logic diagram of switchgear opening operation ............................................. 4-8

Figure 4.1-3 Logic diagram of DPS synthesis ........................................................................ 4-9

Figure 4.1-4 Logic diagram of DPS alarm ............................................................................... 4-9

Figure 4.1-5 Logic diagram of trip counter triggering ........................................................... 4-9

Figure 4.1-6 Logic diagram of Interlocking .......................................................................... 4-10

Figure 4.1-7 Logic diagram of manual control ..................................................................... 4-10

Figure 4.2-1 Relationship between reference and synchronous voltages ....................... 4-12

Figure 4.2-2 Synchronism check enabling logic.................................................................. 4-15

Figure 4.2-3 Synchro-check logic .......................................................................................... 4-16

Figure 4.2-4 Dead charge check logic ................................................................................... 4-18

Figure 4.3-1 Voltage wiring diagram of 1 CB with 2 busbars (1-phase bus voltage) ....... 4-21

Figure 4.3-2 Voltage wiring diagram of 1 CB with 2 busbars (3-phase bus voltage) ....... 4-21

Figure 4.3-3 Voltage wiring diagram of 2 CB in 3/2 CB arrangement ................................ 4-22

Figure 4.3-4 Voltage selection logic diagram of 1 CB with 2 busbars (1-phase bus voltage)
................................................................................................................................................... 4-24

Figure 4.3-5 Voltage selection logic diagram of 1 CB with 2 busbars (3-phase bus voltage)
................................................................................................................................................... 4-25

Figure 4.3-6 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing bus CB)
................................................................................................................................................... 4-25

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Date: 2022-01-17
4 Control Functions

Figure 4.3-7 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing tie CB)
................................................................................................................................................... 4-26

Figure 4.4-1 Diagram of conversion from DC analog input to TPI ..................................... 4-27

Figure 4.4-2 Logic diagram of manual control of tap position ........................................... 4-30

Figure 4.4-3 Logic diagram of control operation of tap position changer ........................ 4-30

Figure 4.5-1 Diagram of ATCC process ................................................................................. 4-32

Figure 4.5-2 Sequence diagram of ATCC operation ............................................................ 4-34

Figure 4.5-3 IDMT operating characteristic curve of the initial tap change command of
ATCC ......................................................................................................................................... 4-35

Figure 4.5-4 Logic diagram of selection of target voltage value........................................ 4-35

Figure 4.5-5 Logic diagram of automatic/manual mode switch of voltage regulation .... 4-36 4
Figure 4.5-6 Logic diagram of under voltage of ATCC ........................................................ 4-37

Figure 4.5-7 Logic diagram of over voltage of ATCC .......................................................... 4-37

Figure 4.5-8 Logic diagram of over current of ATCC........................................................... 4-38

Figure 4.5-9 Logic diagram of TPI over range of ATCC....................................................... 4-38

Figure 4.5-10 Logic diagram of invalid input of ATCC ........................................................ 4-38

Figure 4.5-11 Logic diagram of general blocking of ATCC ................................................. 4-39

Figure 4.5-12 Equivalent circuit diagram of line voltage drop ........................................... 4-40

Figure 4.5-13 Vector diagram for compensation of line voltage drop ............................... 4-40

Figure 4.5-14 Logic diagram of ATCC tap change command ............................................. 4-43

Figure 4.6-1 Logic diagram of over current of ATCC........................................................... 4-45

Figure 4.6-2 Logic diagram of PVR in master BCU ............................................................. 4-49

Figure 4.6-3 Logic diagram of PVR in follower BCU ........................................................... 4-49

Figure 4.6-4 Logic diagram of PVR general blocking signal .............................................. 4-50

List of Tables

Table 4.1-1 Remote/Local control mode switch logic............................................................ 4-2

Table 4.1-2 Input signals of control function .......................................................................... 4-6

Table 4.1-3 Output signals of control function....................................................................... 4-6

Table 4.1-4 Settings of DPS settings ..................................................................................... 4-10

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Date: 2022-01-17
4 Control Functions

Table 4.1-5 Settings of control settings ................................................................................ 4-11

Table 4.1-6 Settings of interlocking settings ........................................................................ 4-11

Table 4.2-1 Input signals of manual closing synchronism check ...................................... 4-14

Table 4.2-2 Output signals of manual closing synchronism check ................................... 4-14

Table 4.2-3 Settings of synchronism check ......................................................................... 4-18

Table 4.3-1 Input signals of voltage selection ...................................................................... 4-23

Table 4.3-2 Output signals of voltage selection ................................................................... 4-24

Table 4.3-3 Settings of voltage selection .............................................................................. 4-26

Table 4.4-1 Input signals of tap position indication and control ........................................ 4-28

Table 4.4-2 Output signals of tap position indication and control..................................... 4-28
4 Table 4.4-3 Settings of tap position indicator ...................................................................... 4-31

Table 4.5-1 Input signals of automatic voltage regulation .................................................. 4-41

Table 4.5-2 Output signals of automatic voltage regulation ............................................... 4-41

Table 4.5-3 Settings of automatic voltage regulation .......................................................... 4-43

Table 4.6-1 Input signals of parallel voltage regulation ...................................................... 4-48

Table 4.6-2 Output signals of parallel voltage regulation ................................................... 4-48

Table 4.6-3 Settings of parallel voltage regulation .............................................................. 4-50

4-d PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

4.1 Switchgear Control

The switchgear control function is mainly used to realize operation of primary equipment such as
circuit breaker (CB), disconnect switch (DS) and earthing switch (ES). This function can be
divided into remote control and local control according to the control source location. A remote
control mainly refers to remote control commands from substation automation system (SAS) or
network control centre (NCC). However, a control triggered manually from the device LCD, by a
terminal contact or by a panel handle is a local control. The switchgear control function is closely
related to interlocking, double point status (DPS), remote/local control mode switching and trip
counter.

A control command can realize various control signals such as the CB/DS/ES opening/closing. In
order to ensure the reliability of the control output, a locking circuit is added to each control object.
The operation is strictly in accordance with the selection, check and execution steps, to ensure
that the control operation can be safely and reliably implemented. In addition, the device has a 4
hardware self-checking and blocking function to prevent hardware damage from maloperation
output.

When the device is in the remote-control mode, the control command may be sent via
communication protocol; when it is in the local control mode, the local operation may be
performed on the device LCD or panel handle.

A complete control process is:

1. Protocol module sends a selection command;

2. Control module responds the success or failure result of selection;

3. If the selection is successful, the protocol module sends an execution command, otherwise it
sends a cancel command;

4. Control module responds the success or failure result of execution;

5. The control operation may be open/close or up/down/stop.

When the device is in the maintenance status, it can still respond to local control commands.

The switchgear control function can cooperate with functions such as synchronism check and
interlocking criteria calculation to complete the output of the corresponding operation command. It
can realize the normal control output in one bay and the interlocking and programmable logic
configuration between bays.

This device supports the following functional control module:

Module Description
CSWI Control of circuit breaker (CB), disconnector switch (DS) or earthing switch (ES)
RMTLOC Remote or local control mode
XCBR Synthesis of CB position, three-phase or phase separated
XSWI Synthesis of DS/ES position

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Date: 2022-01-17
4 Control Functions

Module Description
SXCBR/SCSWI Trip counter of CB/DS/ES
RSYN Synchronism check for CB closing
CILO Interlocking logic for CB/DS/ES control
MCSWI Manual control of CB/DS/ES
CHKPOS Position verification for switchgear control

The initiation of a control command may be sent to the device by the SCADA or the NCC through
communication protocol. It may also be the operation of the device LCD or the manual triggering
through configured signal. The command is sent by the CPU to the control module for processing,
and a control record is made on the CPU module according to the control result.

4.1.1 Function Description

4.1.1.1 Remote/Local Control Mode Switch


4
Since the source of a control command may be SAS or NCC, or may be triggered by the device
LCD or terminal contact, it is necessary to provide a remote/local control mode switch function.

The remote/local control mode switch function determines whether the device is in the remote or
the local control permission state through the configuration of terminal contact, function key, or
binary signal. Each control object provides a remote/local input, and the control module
determines the current control authority to be remote or local according to the input value. By
default, if the input is not configured, any control operation is blocked.

Table 4.1-1 Remote/Local control mode switch logic

in_Remote in_Local Remote Control Local Control


NULL NULL Disable Disable
0 NULL Disable Enable
1 NULL Enable Disable
NULL 0 Enable Disable
NULL 1 Disable Enable
0 0 Disable Disable
0 1 Disable Enable
1 0 Enable Disable
1 1 Enable Enable

4.1.1.2 Double Point Status

A double point status (DPS), which usually indicates switchgear status, can be derived from 2
ordinary binary inputs. The signification of a DPS is shown in the following table. For switchgear
status, only the 2 statuses "01" and "10" indicating respectively the positions opening and closing
are valid. The other 2 statuses "00" and "11", i.e. intermediate or bad status, will cause the alarm
"DPS.Alm".

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4 Control Functions

DPS Bit0 = 0 Bit0 = 1


Bit1 = 0 DPS_INT DPS_OFF
Bit1 = 1 DPS_ON DPS_BAD

For the convenient use in user-defined logic programming, this functional module derives four
single-bit outputs to indicate each DPS state.

Indication Signal
DPS_ON DPS_OFF DPS_INT DPS_BAD
DPS State
ON 1 0 0 0
OFF 0 1 0 0
INT 0 0 1 0
BAD 0 0 0 1

This unit also supports the DPS synthesis through switchgear opening and closing positions after
jittering processing. The synthetic DPS contains original SOE timestamp. The CB control function
supports phase-segregated position inputs and can synthesize these inputs into general position.
4
In accordance with the control object, the DPS synthesis function is divided into 2 modules: XCBR
and XSWI. The XCBR is mainly used for CB position synthesis, including phase-segregated
positions, while the XSWI is used DS or ES position synthesis.

4.1.1.3 Trip Counter

The trip counter function takes the DPS of switchgear position as input count the trip times. For
CB, this device supports phase-segregated and general trip counter. The trip counter function is
triggered by DPS change. The counting result is stored in non-volatile memory for power-off
holding.

Use the clear command from the menu in local LCD or customized binary signal to reset trip
counter.

4.1.1.4 Interlocking

The interlocking function will influence the control operation output. When the function is enabled,
the device determines whether the control operation is permitted based on the interlocking logic
result. Each control object is equipped with an independent interlocking logic which supports
unlocking operation through a binary signal.

The interlocking function is very important for the control operation of switchgears. During the
operation of primary equipment, the positions of the relevant equipment must be correct for
operation permission. For remote control, i.e. command from SAS or NCC, this device could
detect the interlocking logic depending on the message within the command; for local control
through device LCD or terminal contact, please use the corresponding logic setting to
enable/disable the interlocking function.

4.1.1.5 Manual Control

The switchgear control function supports manual control function that can be configured with a

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Date: 2022-01-17
4 Control Functions

terminal contact or binary signal to trigger the control operation.

The manual control function supports the control input configuration of selection and open/close
operations. When the control object selection input is configured, the signal "1" indicates that the
current control object has to be selected before a control operation; if the control object selection
input is not configured, the control command can be directly issued without judgment of selection.

4.1.1.6 Switchgear Position Verification

The position verification function is provided during switchgear control process. In a control
function block of circuit breaker, disconnector or earthing switch, if the input “in_CheckPos_En” is
set as 1, the CB/DS/ES position shall be verified when receiving a remote or local control
command.

The verification logic complies with IEC 61850 standard is:

4  A control object only permits to be opened when its DPS is CLOSE;

 A control object only permits to be closed when its DPS is OPEN;

 The device shall respond control command failed with the cause of failure when its DPS is
INT, BAD or opposite (i.e. OPEN while opening or CLOSE while closing).

4.1.1.7 Direct Control

For applications such as signal reset and function enable/disable, the control mode is generally
direct control, i.e. execution without selection before, direct control with normal security in IEC
61850.

The direct control function provides remote/local switch and interlocking configurations. The
control command is usually issued directly by the SAS. It also supports the command triggered by
binary signal.

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Date: 2022-01-17
4 Control Functions

4.1.2 Function Block Diagram

XCBR: circuit breaker

XSWI: disconnector switch or earthing switch

DONS: direct control object

4.1.3 I/O Signals

The prefix CB** for circuit breaker, DS** for disconnector switch and
DirCtrl** for direct control in the following lists are hidden since their
description (if valid) are similar.

PCS-978S Transformer Relay 4-5


Date: 2022-01-17
4 Control Functions

Table 4.1-2 Input signals of control function

No. Input Signal Description


1 in_en Enabling function
2 in_blk Disabling function
3 in_Remote Remote control mode
4 in_Local Local control mode
5 in_Pos_NO Normally opened contact input for DPS opening position
6 in_Pos_NC Normally closed contact input for DPS closing position
7 in_Pos_A_NO Phase A normally opened contact input for DPS opening position
8 in_Pos_A_NC Phase A normally closed contact input for DPS closing position
9 in_Pos_B_NO Phase B normally opened contact input for DPS opening position
10 in_Pos_B_NC Phase B normally closed contact input for DPS closing position
11 in_Pos_C_NO Phase C normally opened contact input for DPS opening position

4 12
13
in_Pos_C_NC
in_N_Trp
Phase C normally closed contact input for DPS closing position
Opening command for trip counter
14 in_N_Trp_A Phase A opening command for trip counter
15 in_N_Trp_B Phase B opening command for trip counter
16 in_N_Trp_C Phase C opening command for trip counter
17 in_Clr_Cnt Clear trip counters
18 in_Rsyn Structure pointer of synchronism check element
19 in_EnaOpn Opening permission for interlocking
20 in_EnaCls Closing permission for interlocking
21 in_CILO_Bypass Bypass for interlocking
22 in_Manual_Sel Selection for manual control
23 in_Manual_Opn Opening for manual control
24 in_Manual_Cls Closing for manual control
25 in_CheckPos_En Input signal of enabling of position verification function for switchgear control

Table 4.1-3 Output signals of control function

No. Output Signal Description


1 NO_DPS DPS opening position
2 NC_DPS DPS closing position
3 NO_DPS_A Phase A DPS opening position
4 NC_DPS_A Phase A DPS closing position
5 NO_DPS_B Phase B DPS opening position
6 NC_DPS_B Phase B DPS closing position
7 NO_DPS_C Phase C DPS opening position
8 NC_DPS_C Phase C DPS closing position
9 DPS Synthetic DPS for switchgear position
10 DPS_A Synthetic DPS for switchgear phase A position
11 DPS_B Synthetic DPS for switchgear phase B position
12 DPS_C Synthetic DPS for switchgear phase C position

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4 Control Functions

No. Output Signal Description


13 N_Trp Trip counter
14 N_Trp_A Phase A trip counter
15 N_Trp_B Phase B trip counter
16 N_Trp_C Phase C trip counter
17 Opn_Enabled Permission of opening operation
18 Cls_Enabled Permission of closing operation
19 Opn/Cls_Enabled Permission of operation (Opn_Enabled OR Cls_Enabled)
20 Opn_Exec Opening operation
21 Cls_Exec Closing operation
22 Opn_Sel Opening selection
23 Cls_Sel Closing selection
24 DPS.Alm Alarm signal when DPS status is BAD or INT
25 Cmd_ManSel Selection command for manual control
26 Cmd_ManOpn Opening command for manual control 4
27 Cmd_ManCls Closing command for manual control
28 RSYN_ChkInprog Synchronism check is in progress
29 DPS_ON Single-bit DPS state indication of ON
30 DPS_OFF Single-bit DPS state indication of OFF
31 DPS_INT Single-bit DPS state indication of INT
32 DPS_BAD Single-bit DPS state indication of BAD
33 DPS_A_ON Phase A single-bit DPS state indication of ON
34 DPS_A_OFF Phase A single-bit DPS state indication of OFF
35 DPS_A_INT Phase A single-bit DPS state indication of INT
36 DPS_A_BAD Phase A single-bit DPS state indication of BAD
37 DPS_B_ON Phase B single-bit DPS state indication of ON
38 DPS_B_OFF Phase B single-bit DPS state indication of OFF
39 DPS_B_INT Phase B single-bit DPS state indication of INT
40 DPS_B_BAD Phase B single-bit DPS state indication of BAD
41 DPS_C_ON Phase C single-bit DPS state indication of ON
42 DPS_C_OFF Phase C single-bit DPS state indication of OFF
43 DPS_C_INT Phase C single-bit DPS state indication of INT
44 DPS_C_BAD Phase C single-bit DPS state indication of BAD

4.1.4 Logics

The prefix CB** for circuit breaker and DS** for disconnector switch in the
following diagrams are hidden since their logics (if valid) are similar.

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Date: 2022-01-17
4 Control Functions

EN [CB**.En_CILO_Cls] >=1

SIG CB**.Cls_Enabled

SIG CB** Control Mode = Remote


&
SIG CB**.Cmd_ManCls >=1 >=1 &
0 [CB**.t_PW_Cls] CB**.Cls_Exec
CB** closing cmd. from device local HMI

&

CB** closing cmd. from SCADA/Gateway

SIG CB**.25.RSYN_OK
>=1
SIG CB**.25.SynChk_Enabled &

SIG CB**.25.DdChk_Enabled

4
EN [DS**.En_CILO_Cls] >=1

SIG DS**.Cls_Enabled

SIG DS** Control Mode = Remote & &


>=1 0 [DS**.t_PW_Cls] DS**.Cls_Exec
SIG DS**.Cmd_ManCls >=1

DS** closing cmd. from device local HMI &

DS** closing cmd. from SCADA/Gateway

Figure 4.1-1 Logic diagram of switchgear closing operation

EN [XXXX.En_CILO_Opn] >=1

SIG XXXX.Opn_Enabled

SIG XXXX Control Mode = Remote & &


>=1 0 [XXXX.t_PW_Opn] XXXX.Opn_Exec
SIG XXXX.Cmd_ManOpn >=1

XXXX opening cmd. from device local HMI &

XXXX opening cmd. from SCADA/Gateway

Figure 4.1-2 Logic diagram of switchgear opening operation

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Date: 2022-01-17
4 Control Functions

SIG XXXX.DPS_A = OFF


&
SIG XXXX.DPS_B = OFF XXXX.DPS = OFF

SIG XXXX.DPS_C = OFF

SIG XXXX.DPS_A = ON
&
SIG XXXX.DPS_B = ON XXXX.DPS = ON

SIG XXXX.DPS_C = ON

SIG XXXX.DPS_A = INT


&
SIG XXXX.DPS_B = INT XXXX.DPS = INT

SIG XXXX.DPS_C = INT

SIG XXXX.DPS_A = BAD


&
SIG XXXX.DPS_B = BAD XXXX.DPS = BAD 4
SIG XXXX.DPS_C = BAD

Figure 4.1-3 Logic diagram of DPS synthesis

SIG XXXX.DPS=BAD >=1


&
SIG XXXX.DPS= INT [XXXX.DPS.t_Alm] [XXXX.DPS.t_Alm] XXXX.Alm_DPS

EN [XXXX.DPS.En_Alm]

Figure 4.1-4 Logic diagram of DPS alarm

SIG Rasing edge of in_N_Trp_A & N_Trp_A + 1

SIG DPS_A change form ON to OFF

SIG Rasing edge of in_N_Trp_B & &


N_Trp_B + 1
>=1 N_Trp + 1
SIG DPS_B change form ON to OFF

SIG Rasing edge of in_N_Trp_C & N_Trp_C + 1

SIG DPS_C change form ON to OFF

SIG Rasing edge of in_N_Trp &

SIG DPS change form ON to OFF

Figure 4.1-5 Logic diagram of trip counter triggering

PCS-978S Transformer Relay 4-9


Date: 2022-01-17
4 Control Functions

From SCADA/Gateway with


"Interlocking"
Remote control
>=1
The interlocking logic of
Local control
XXXX is activated
From device HMI with "InterlockChk"
>=1
From energized contact via binary input &
SIG Manual control

EN [XXXX.En_CILO_Opn] >=1

EN [XXXX.En_CILO_Cls]

Figure 4.1-6 Logic diagram of Interlocking

SIG in_Manual_Sel = NUL &


>=1
4 SIG in_Manual_Opn

SIG in_Manual_Sel &

SIG in_Manual_Opn
&
SIG Opn_Enabled Cmd_ManOpn

SIG Control mode = Local

SIG in_Manual_Sel = NUL &

SIG in_Manual_Cls
>=1
SIG in_Manual_Sel &

SIG in_Manual_Cls
&
SIG Cls_Enabled Cmd_ManCls

SIG Control mode = Local

Figure 4.1-7 Logic diagram of manual control

4.1.5 Settings
Table 4.1-4 Settings of DPS settings

No. Setting Range Unit Default Description


Delay Pick Up (DPU) time, i.e. debounce time, for
1 CB**.DPS.t_DPU 0~60000 ms 500
CB DPS
Disabled
2 CB**.DPS.En_Alm - Disabled Logic setting for CB DPS alarm
Enabled
3 CB**.DPS.t_Alm 0~60000 ms 500 Operation time delay of CB DPS alarm
Delay Pick Up (DPU) time, i.e. debounce time, for
4 DS**.DPS.t_DPU 0~60000 ms 500
DS DPS

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Date: 2022-01-17
4 Control Functions

No. Setting Range Unit Default Description


Disabled
5 DS**.DPS.En_Alm - Disabled Logic setting for DS DPS alarm
Enabled
6 DS**.DPS.t_Alm 0~60000 ms 500 Operation time delay of DS DPS alarm

Table 4.1-5 Settings of control settings

No. Setting Range Unit Default Description


Pulse Width (PW), i.e. holding time, for CB
1 CB**.t_PW_Opn 0~60000 ms 500
opening output
Pulse Width (PW), i.e. holding time, for CB closing
2 CB**.t_PW_Cls 0~60000 ms 500
output
Pulse Width (PW), i.e. holding time, for DS
3 DS**.t_PW_Opn 0~60000 ms 500
opening output
Pulse Width (PW), i.e. holding time, for DS closing
4 DS**.t_PW_Cls 0~60000 ms 500
output 4
Pulse Width (PW), i.e. holding time, for direct
5 DirCtrl**.t_PW_Opn 0~60000 ms 500
opening output
Pulse Width (PW), i.e. holding time, for direct
6 DirCtrl**.t_PW_Cls 0~60000 ms 500
closing output

Table 4.1-6 Settings of interlocking settings

No. Setting Range Unit Default Description


Disabled Logic setting for interlocking logic control of CB
1 CB**.En_CILO_Opn - Disabled
Enabled opening output.
Disabled Logic setting for interlocking logic control of CB
2 CB**.En_CILO_Cls - Disabled
Enabled closing output.
Disabled Logic setting for interlocking logic control of DS
3 DS**.En_CILO_Opn - Disabled
Enabled opening output.
Disabled Logic setting for interlocking logic control of DS
4 DS**.En_CILO_Cls - Disabled
Enabled closing output.
Disabled Logic setting for interlocking logic control of
5 DirCtrl**.En_CILO_Opn - Disabled
Enabled direct opening output.
Disabled Logic setting for interlocking logic control of
6 DirCtrl**.En_CILO_Cls - Disabled
Enabled direct closing output.

4.2 Manual Closing Synchronism Check

The purpose of synchronism check is to ensure two systems are synchronous before they are
going to be connected.

When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus, closing operation is
applied with the synchronism check to avoid this situation and maintain the system stability. The
synchronism check includes synchro-check and dead charge check.

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Date: 2022-01-17
4 Control Functions

4.2.1 Function Description

4.2.1.1 Synchro-check

The comparative relationship between the reference voltage and the synchronization voltage for
synchro-check is as follow. Furthermore, the measured three-phase voltages for synchro-check
should not exceed the overvoltage threshold [25.U_OV] or lag the undervoltage threshold
[25.U_UV].

U_Ref
U_Syn

Figure 4.2-1 Relationship between reference and synchronous voltages

This figure shows the characteristics of synchro-check element used for CB closing if both
reference and synchronous sides are live. The element operates if the voltage difference,
frequency difference, frequency variation difference and phase angle difference are all within their
setting ranges.

 The voltage difference between the reference side and the synchronous side is checked by
the following equations

[25.U_UV] ≤ U_Ref ≤ [25.U_OV]

[25.U_UV] ≤ U_Syn ≤ [25.U_OV]

|U_Ref- U_Syn| ≤ [25.U_Diff_Set]

 The frequency difference between the reference side and the synchronous side is checked
by the following equations

[25.f_UF] ≤ f(U_Ref) ≤ [25.f_OF]

[25.f_UF] ≤ f(U_Syn) ≤ [25.f_OF]

|f(U_Ref)-f(U_Syn)| ≤ [25.f_Diff_Set]

 The frequency variation is checked by the following equation

df/dt ≤ [25.df/dt_Set]

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4 Control Functions

 The phase difference between the reference voltage and the synchronization voltage is
checked by the following equation

∆δ ≤ [25.phi_Diff_Set]

4.2.1.2 Dead Charge Check

The dead charge check mode checks either the reference side or the synchronization voltage.
Several dead charge check modes are supported in using the setting [25.Opt_Mode_DdChk]. The
device compares the reference side and the synchronization voltages at both ends of a circuit
breaker with the settings [25.U_LvChk] and [25.U_DdChk]. When the voltage is higher than
[25.U_LvChk], the corresponding side is regarded as live. When the voltage is lower than
[25.U_DdChk], the corresponding side is regarded as dead.

4.2.1.3 Enabling Logic

If one of the following conditions is met, the synchro-check for CB closing is enabled. 4
 [25.Opt_ValidMode] = Setting, [25.En_SynChk] = Enabled;

 [25.Opt_ValidMode] = Config, “25.in_syn_chk” = 1.

If one of the following conditions is met, the dead charge check for CB closing is enabled.

 [25.Opt_ValidMode] = Setting, [25.En_DdChk] = Enabled;

 [25.Opt_ValidMode] = Config, “25.in_vol_chk” = 1.

If none of synchro-check and dead charge check is enabled, the synchronism check for CB
closing is disabled.

4.2.1.4 Voltage Input Channel

The synchronism check function is suitable for several applications. According to different
application scenarios, user needs to configure different voltage input channel. For both the
reference side and the synchronous side, the voltage input channel may be single phase or
three-phase.

While configuring through the PCS-Studio software, user can configure three-phase or
single-phase voltage channel for reference and synchronous sides inputs.

In the meantime, the voltage selection logic can be adopted for the synchronism check input
channel, please refer to the corresponding section.

PCS-978S Transformer Relay 4-13


Date: 2022-01-17
4 Control Functions

4.2.2 Function Block Diagram

4
4.2.3 I/O Signals
Table 4.2-1 Input signals of manual closing synchronism check

No. Input Signal Description


1 in_en Enabling function
2 In_blk Disabling function
3 in_ref_A Reference voltage channel (phase A)
4 in_ref_B Reference voltage channel (phase B)
5 in_ref_C Reference voltage channel (phase C)
6 in_syn_A Synchronization voltage channel (phase A)
7 in_syn_B Synchronization voltage channel (phase B)
8 in_syn_C Synchronization voltage channel (phase C)
9 in_25_Blk Signal to block synchronism check logic
10 in_Dd_Blk Signal to block dead charge logic
11 in_Lv_Blk Signal to block live check logic
12 in_SYN_Blk Signal to block synchro-check logic
13 in_25_Bypass Signal to temporarily bypass synchronism check logic
14 in_syn_chk Activate synchro-check (valid only if the setting [CB**.25.Opt_ValidMode] = Config)
15 in_vol_chk Activate dead charge check (valid only if the setting [CB**.25.Opt_ValidMode] = Config)

Table 4.2-2 Output signals of manual closing synchronism check

No. Output Signal Description


1 25.RSYN Pointer to struct of synchronism check element
2 25.U_Ref_Sec Reference voltage secondary value
3 25.U_Ref_Pri Reference voltage primary value
4 25.f_Ref Reference side frequency
5 25.U_Syn_Sec Synchronization voltage secondary value

4-14 PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

No. Output Signal Description


6 25.U_Syn_Pri Synchronization voltage primary value
7 25.f_Syn Synchronous side frequency
8 25.U_Diff_Sec Voltage difference secondary value
9 25.U_Diff_Pri Voltage difference primary value
10 25.phi_DIff Phase angle difference
11 25.f_Diff Frequency difference
12 25.df/dt Frequency rate-of-change
13 25.RSYN_OK Satisfaction of synchronism check logic, i.e. SynChk_OK or DdChk_OK
14 25.SynChk_OK Satisfaction of synchro-check logic
15 25.DdChk_OK Satisfaction of dead charge check logic
16 25.SynChk_Enabled Synchro-check is enabled
17 25.DdChk_Enabled Dead charge check is enabled
18 25.Alm_Cfg_Ch Channel configuration for reference or synchronization is not correct.
19 25.U_Diff_OK Voltage difference within setting range 4
20 25.f_Diff_OK Frequency difference within setting range
21 25.df/dt_OK Frequency variation difference within setting range
22 25.phi_Diff_OK Phase difference within setting range
23 25.RefDd The reference side is dead.
24 25.RefLv The reference side is live.
25 25.SynDd The synchronous side is dead.
26 25.SynLv The synchronous side is live.

4.2.4 Logics

EN [25.Opt_ValidMode] = Setting &


≥1
EN [25.En_SynChk] 25.SynChk_Enabled

EN [25.Opt_ValidMode] = Config
&

SIG 25.in_syn_chk

EN [25.Opt_ValidMode] = Setting &


≥1
EN [25.En_DdChk] 25.DdChk_Enabled

EN [25.Opt_ValidMode] = Config &

SIG 25.in_vol_chk

SIG 25.SynChk_Enabled &


Synchronism check for CB closing is disabled

SIG 25.DdChk_Enabled

Figure 4.2-2 Synchronism check enabling logic

PCS-978S Transformer Relay 4-15


Date: 2022-01-17
4 Control Functions

SIG in_25_Bypass

SIG in_25_Blk
SIG in_SYN_Blk
SET df/dt [25.df/dt_Set]
1
SET [25.En_df/dt_Chk] = Disabled
SET ΔU [25.U_Diff_Set]
SET Δf [25.f_Diff_Set]
1
SET [25.En_f_Diff_Chk] = Disabled
1 25.SynChk_OK
SET Δδ [25.phi_Diff_Set] &
SET U_Ref [25.U_UV]
SET U_Ref [25.U_OV]
1
SET U_Syn [25.U_UV]
SET U_Syn [25.U_OV]

SET f_Ref [25.f_UF]


SET f_Ref [25.f_OF]
1
SET f_Syn [25.f_UF]
4 SET f_Syn [25.f_OF]

SIG Cmd without synchro-check

SIG 25.SynChk_OK 1 SynChk Success


SIG [25.SynChk_Enabled &
SIG Cmd with synchro-check

Figure 4.2-3 Synchro-check logic

4-16 PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

SIG Ua_Ref < [25.U_DdChk]

SIG Ub_Ref < [25.U_DdChk]


&
SIG Uc_Ref < [25.U_DdChk]
>=1
SIG U_Ref is three-phase voltage 25.RefDd

SIG U_Ref < [25.U_DdChk] &

SIG U_Ref is single-phase voltage

SIG Ua_Syn < [25.U_DdChk]

SIG Ub_Syn < [25.U_DdChk]


&
SIG Uc_Syn < [25.U_DdChk]
>=1
SIG U_Syn is three-phase voltage 25.SynDd
4
SIG U_Syn < [25.U_DdChk] &

SIG U_Syn is single-phase voltage

SIG Ua_Ref > [25.U_LvChk]

SIG Ub_Ref > [25.U_LvChk]


&
SIG Uc_Ref > [25.U_LvChk]
>=1
SIG U_Ref is three-phase voltage 25.RefLv

SIG U_Ref > [25.U_LvChk] &

SIG U_Ref is single-phase voltage

SIG Ua_Syn > [25.U_LvChk]

SIG Ub_Syn > [25.U_LvChk]


&
SIG Uc_Syn > [25.U_LvChk]
>=1
SIG U_Syn is three-phase voltage 25.SynLv

SIG U_Syn > [25.U_LvChk] &

SIG U_Syn is single-phase voltage

PCS-978S Transformer Relay 4-17


Date: 2022-01-17
4 Control Functions

SIG in_25_Bypass >=1


25.DdChk_OK
SIG in_25_Blk

SET [25.Opt_Mode_DdChk]

SIG 25.RefDd &


&
SIG in_Dd_Blk
&

criteria selection
Dead check
SIG 25.SynDd

SIG 25.RefLv &

4 SIG in_Lv_Blk
&

SIG 25.SynLv

SIG Cmd. without dead charge check


>=1
SIG 25.DdChk_Ok
& DdChk Success
SIG 25.DdChk_Enabled

SIG Cmd. with dead charge check

Figure 4.2-4 Dead charge check logic

4.2.5 Settings
Table 4.2-3 Settings of synchronism check

No. Setting Range Unit Default Description


Selection of decision
1 25.Opt_ValidMode Setting or Config - Setting mode for synchronism
check
Logic setting for
synchro-check (valid only
2 25.En_SynChk Disabled or Enabled - Enabled if the setting
[25.Opt_ValidMode] =
Setting)
Logic setting for dead
charge check (valid only if
3 25.En_DdChk Disabled or Enabled - Enabled the setting
[25.Opt_ValidMode] =
Setting)

4-18 PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

No. Setting Range Unit Default Description


Percentage threshold of
4 25.U_UV 0.00~100.00 % 80.00 under voltage for CB
closing blocking
Percentage threshold of
5 25.U_OV 100.00~170.00 % 170.00 over voltage for CB
closing blocking
Percentage threshold of
6 25.f_UF 0.000~65.000 Hz 45.000 under frequency for CB
closing blocking
Percentage threshold of
7 25.f_OF 0.000~65.000 Hz 65.000 over frequency for CB
closing blocking

Ua, Ub, Uc, Uab, Ubc, Selection of voltage for


8 25.Opt_U_SynChk
Uca
- Ua
synchronism check 4
Threshold of voltage
9 25.U_Diff_Set 0.00~100.00 V 10.00 difference for synchronism
check
Threshold of frequency
10 25.f_Diff_Set 0.00~2.00 Hz 0.50 difference for synchronism
check
Threshold of frequency
11 25.df/dt_Set 0.00~2.00 Hz/s 1.00 variation for synchronism
check.
Threshold of phase
12 25.phi_Diff_Set 0.00~180.00 ° 15.00 difference for synchronism
check
Compensation angle of
13 25.phi_Comp 0.00~360.00 ° 0.00 phase difference for
synchronism check
SynDdRefDd
SynLvRefDd
SynDdRefLv
Selection of dead charge
14 25.Opt_Mode_DdChk RefDd - AnySideDd
check mode
SynDd
SynLvRefDd/SynDdRefLv
AnySideDd
Threshold for voltage
15 25.U_DdChk 0.00~100.00 V 17.32
dead check
Threshold for voltage live
16 25.U_LvChk 0.00~100.00 V 34.64
check
Threshold of duration for
17 25.t_Reset 0~60 s 5
synchrocheck

PCS-978S Transformer Relay 4-19


Date: 2022-01-17
4 Control Functions

No. Setting Range Unit Default Description


Circuit breaker closing
time. It is the time from
18 25.t_Close_CB 0~2000 ms 20 receiving closing
command pulse till the CB
is completely closed.
Logic setting for frequency
19 25.En_f_Diff_Chk Disabled or Enabled - Enabled
difference check
Logic setting for frequency
20 25.En_df/dt_Chk Disabled or Enabled - Enabled
variation difference check

 25.Opt_Mode_DdChk

Setting Value Dead charge check mode

4 SynDdRefDd Dead check for both the reference and the synchronous sides

SynLvRefDd Live check for synchronous side and dead check for reference side

SynDdRefLv Dead check for synchronous side and live check for reference side

RefDd Dead check for reference side

SynDd Dead check for synchronous side

SynLvRefDd/SynDdRefLv Option 2 or 3

AnySideDd Option 1, 2 or 3

4.3 Voltage Selection

The voltage selection function can be used to switch the reference and synchronization voltages
of synchronism check in double busbars and one-and-half circuit breakers application scenarios,
or to switch three-phase voltages of both busbars for the use in protection calculation or
measurement.

4.3.1 Function Description

By default, this device adopts the principle of proximity in built-in voltage selection logic. Moreover,
it supports customized selection logic. The default voltage selection logic is automatically disabled
if the customized voltage selection logic is correctly configured.

The customized selection result may be derived from any source binary signals, such as binary
inputs, isolators status and programmable logic output signals.

If voltage selection logic fails, the alarm "x.VoltSel.Alm_Invalid_Sel" will be issued and the
selection output remains unchanged.

The voltage selection function maybe used in the following scenarios:

 For single circuit breaker with double busbars, the selection of appropriate voltage from both
busbars for synchronism check is required. Line VT input is taken as reference.

4-20 PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

Bus2

Bus1

DS1 DS2
UB1

UB2

DS1.DPS

CB

DS2.DPS

Ua

UL1 Ub
Line
Uc

Figure 4.3-1 Voltage wiring diagram of 1 CB with 2 busbars (1-phase bus voltage)
4
 For single circuit breaker with double busbars, the selection of three-phase voltage from both
busbars is used as reference voltage of synchronism check. Single-phase voltage from line
VT is the synchronization voltage.

Bus2

Bus1

DS1 DS2
Ua

UB1 Ub
Uc
Ua

UB2 Ub
Uc
CB
DS1.DPS

DS2.DPS

UL1
Line

Figure 4.3-2 Voltage wiring diagram of 1 CB with 2 busbars (3-phase bus voltage)

 For a bus side CB of one-and-half breakers arrangement in the application scenario of double
circuit breakers, the selection of voltage from Line1_VT, Line2_VT and the other bus side VT
is the synchronization voltage to be synchronized with the reference voltage of local bus side.

For the tie CB of one-and-half breakers arrangement in the application scenario of double
circuit breakers, the selection of voltage from Line1_VT & Bus1_VT and Line2_VT &
Bus2_VT is the reference voltage and synchronization voltage respectively to check
synchronism for the closing operation.

PCS-978S Transformer Relay 4-21


Date: 2022-01-17
4 Control Functions

Bus1

UB1

Bus1_CB.DPS Bus1_CB
Line 1

Ua
UL1 Ub
Uc DS1

DS1.DPS

Tie_CB.DPS Tie_CB
Line 2

UL2

4 DS2.DPS

DS2

Bus2_CB.DPS Bus2_CB

UB2

Bus2

Figure 4.3-3 Voltage wiring diagram of 2 CB in 3/2 CB arrangement

 For a customized voltage selection logic, the inputs "in_bus1_sel", "in_bus2_sel",


"in_line1_sel" and "in_line2_sel" are derived from binary signals, such as switchgear
positions, binary inputs, programmable logic outputs, etc. The inputted value "1" means
"Channel selected" while the inputted value "0" means "Channel not selected". Make sure
that all these customized voltage selection inputs and measurement channels are correctly
configured before put the logic into service.

4-22 PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

4.3.2 Function Block Diagram

4.3.3 I/O Signals


Table 4.3-1 Input signals of voltage selection

No. Input Signal Description


1 in_UB1_A_Chn Voltage input for Bus1 (phase A)
2 in_UB1_B_Chn Voltage input for Bus1 (phase B)
3 in_UB1_C_Chn Voltage input for Bus1 (phase C)
4 in_UB2_A_Chn Voltage input for Bus2 (phase A)
5 in_UB2_B_Chn Voltage input for Bus2 (phase B)
6 in_UB2_C_Chn Voltage input for Bus2 (phase C)
7 in_UL1_A_Chn Voltage input for Line1 (phase A)
8 in_UL1_B_Chn Voltage input for Line1 (phase B)
9 in_UL1_C_Chn Voltage input for Line1 (phase C)
10 in_UL2_A_Chn Voltage input for Line2 (phase A)
11 in_UL2_B_Chn Voltage input for Line2 (phase B)
12 in_UL2_C_Chn Voltage input for Line2 (phase C)
13 in_Bus1_CB DPS position for the Bus 1 side CB in one-and-half arrangement
14 in_Tie_CB DPS position for the tie CB in one-and-half arrangement
15 in_Bus2_CB DPS position for the Bus 2 side CB in one-and-half arrangement
16 in_DS1 DPS position for the Line 1 in one-and-half or Busbar1 in double busbars arrangement
17 in_DS2 DPS position for the Line 2 in one-and-half or Busbar2 in double busbars arrangement
18 in_bus1_sel Bus1-selected input for customized programmable voltage selection logic

PCS-978S Transformer Relay 4-23


Date: 2022-01-17
4 Control Functions

No. Input Signal Description


19 in_bus2_sel Bus2-selected input for customized programmable voltage selection logic
20 in_line1_sel Line1-selected input for customized programmable voltage selection logic
21 in_line2_sel Line2-selected input for customized programmable voltage selection logic

Table 4.3-2 Output signals of voltage selection

No. Output Signal Description


1 x.VoltSel.Ref_Chn_A Reference voltage channel (Phase A)
2 x.VoltSel.Ref_Chn_B Reference voltage channel (Phase B)
3 x.VoltSel.Ref_Chn_C Reference voltage channel (Phase C)
4 x.VoltSel.Syn_Chn_A Synchronization voltage channel (Phase A)
5 x.VoltSel.Syn_Chn_B Synchronization voltage channel (Phase B)
6 x.VoltSel.Syn_Chn_C Synchronization voltage channel (Phase C)
7 x.VoltSel.Bus1_Sel Bus1 voltage channel for customized programmable voltage selection logic
4 8 x.VoltSel.Line1_Sel Line1 voltage channel for customized programmable voltage selection logic
9 x.VoltSel.Line2_Sel Line2 voltage channel for customized programmable voltage selection logic
10 x.VoltSel.Bus2_Sel Bus2 voltage channel for customized programmable voltage selection logic
11 x.VoltSel.Alm_Invalid_Sel Voltage selection is invalid.

4.3.4 Logics

SIG DS1.DPS=ON &


UB1_Sel
SIG DS2.DPS=OFF

SIG DS1.DPS=OFF &


UB2_Sel
SIG DS2.DPS=ON

&
Alm_Invalid_Sel

UB1 U_Syn
Single-phase voltage of busbars for
synchronization side
UB2

Figure 4.3-4 Voltage selection logic diagram of 1 CB with 2 busbars (1-phase bus voltage)

4-24 PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

SIG DS1.DPS=ON &


UB1_Sel
SIG DS2.DPS=OFF

SIG DS1.DPS=OFF &


UB2_Sel
SIG DS2.DPS=ON

&
Alm_Invalid_Sel

UB1 U_Ref
Three-phase voltage of busbars for reference side
UB2

Figure 4.3-5 Voltage selection logic diagram of 1 CB with 2 busbars (3-phase bus voltage)

SIG DS1.DPS=ON UL1_Sel


4
SIG DS1.DPS=OFF
&
SIG Tie_CB.DPS=ON UL2_Sel

SIG DS2.DPS=ON

SIG DS1.DPS=OFF
&
SIG Tie_CB.DPS=ON UB2_Sel

SIG DS2.DPS=OFF &


&
Alm_Invalid_Sel
SIG Bus2_CB.DPS=ON

UL1

UL2 U_Syn

UB2

UB1 U_Ref

Figure 4.3-6 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing bus CB)

PCS-978S Transformer Relay 4-25


Date: 2022-01-17
4 Control Functions

SIG DS1.DPS=ON UL1_Sel

SIG DS1.DPS=OFF &


UB1_Sel
SIG Bus1_CB.DPS=ON

UL1 Uref

UB1

SIG DS2.DPS=ON UL2_Sel

SIG DS2.DPS=OFF &


UB2_Sel
SIG Bus2_CB.DPS=ON

4 UL2 Usyn

UB2

&

>=1
& Alm_Invalid_Sel

Figure 4.3-7 Voltage selection logic diagram of 2 CB in 3/2 CB arrangement (closing tie CB)

4.3.5 Settings
Table 4.3-3 Settings of voltage selection

No. Setting Range Unit Default Description


NoVolSel,
DblBusOneCB, Selection of circuit breaker arrangement for
1 x.VoltSel.Opt_CBConfig - NoVolSel
3/2BusCB, voltage selection.
3/2TieCB.

4.4 Tap Position Indication and Control

A tap changer is a connection point selection mechanism along a power transformer winding that
allows a variable number of turns to be selected in discrete steps. A transformer with a variable
turn's ratio is produced, enabling stepped voltage regulation of the output. The tap selection may
be made via an automatic or manual tap changer mechanism.

4-26 PCS-978S Transformer Relay

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4 Control Functions

4.4.1 Function Description

4.4.1.1 Tap Position Indicator

The Tap Position Indicator (TPI) input could be Binary-Coded Decimal (BCD), independent
contacts, carry inputs or DC analog input.

 Binary input

For the BCD and the independent contacts input modes, the indicator supports
phase-segregated inputs “84.in_tap**” and phase discordance alarm(s)
“84.Alm_Invalid_TP**”. Refer to the following I/O signals and settings description for more
detail.

 DC analog input

For the DC analog input mode, the indicator adopts a channel of DCAI module as the input.
By parameterization, the DC analog input range could be defined into several step segments
4
which correspond to different tap positions. Thus, the input is converted into three-phase tap
position indication.

TPI

DCAI
R-Δ R R+Δ

Figure 4.4-1 Diagram of conversion from DC analog input to TPI

In the above diagram of conversion, take the second segment as an example:

R is [84.Rated_AI_Segment02] that defines the rated value of DC analog input in segment


No.2.

Δ is [84.Devn_AI_Segment02] that defines the corresponding deviation.

The [84.Value_Segment02] = 9 is set to indicate that an input within this second segment,
which is defined in the range (R-Δ, R+Δ), represents the tap position 9.

Similarly, the first segment is defined to present TPI 3 and the third segment is defined to
present TPI 5.

Beside, [84.Num_AI_Segment] should be defined to involve the maximum number of


possible tap position indication.

PCS-978S Transformer Relay 4-27


Date: 2022-01-17
4 Control Functions

4.4.1.2 Tap Changer Control

The control of tap changer is treated as binary outputs, including "84CSWI1.Opn" (descend),
"84CSWI1.Cls" (raise) and "84CSWI2.Opn" (emergency stop), in this device.

4.4.1.3 Runaway Trip

During a tap position control process, if the situation "tap position runaway" occurs, the power
supply of tap changer's motor mechanism should be cut off. In this device, the runaway situation
means that the tap changer is out of control to step up/down continuously (more than one step) in
one control procedure.

When [84.En_RunawayTrip] is enabled and the device executes a tap command successfully, a
supervision window will be initiated to detect whether the change of TPI is greater than "1" during
20s. If a runaway situation is conformed, the binary output "84.BO_RunawayTrip" will be issued.
4
The countdown of supervision windows starts from the rising edge of a tap
changer control execution indicating signal, i.e. "84CSWI1.Opn_Exec" or
"84CSWI1.Cls_Exec".

4.4.2 I/O Signals


Table 4.4-1 Input signals of tap position indication and control

No. Input Signal Description


1 84CSWI*.Enable Enabling function
2 84CSWI*.Block Disabling function
3 84CSWI*.Remote Remote control mode
4 84CSWI*.Local Local control mode
5 84CSWI*.CILO.EnaOpn Opening permission for interlocking
6 84CSWI*.CILO.EnaCls Closing permission for interlocking
7 84CSWI*.in_CILO_Bypass Bypass for interlocking
8 84CSWI*.in_Manual_Sel Selection for manual control
9 84CSWI*.in_Manual_Opn Opening for manual control
10 84CSWI*.in_Manual_Cls Closing for manual control
11 84.in_tap** TPI inputs
12 84.in_RunawayTrip External input to trigger runaway trip directly

Table 4.4-2 Output signals of tap position indication and control

No. Output Signal Description


1 84CSWI1.Opn_Enabled Permission of tap descending operation
2 84CSWI1.Cls_Enabled Permission of tap raising operation
3 84CSWI1.Opn/Cls_Enabled Permission of operation (tap descending or raising)
4 84CSWI1.Opn_Exec Tap descending operation

4-28 PCS-978S Transformer Relay

Date: 2022-01-17
4 Control Functions

No. Output Signal Description


5 84CSWI1.Cls_Exec Tap raising operation
6 84CSWI1.Opn_Sel Tap descending selection
7 84CSWI1.Cls_Sel Tap raising selection
Selection command for manual tap position control of descending or
8 84CSWI1.Cmd_ManSel
raising
9 84CSWI1.Cmd_ManOpn Descending command for manual tap position control
10 84CSWI1.Cmd_ManCls Raising command for manual tap position control
11 84CSWI2.Opn_Enabled Permission of tap change emergency stop operation
12 84CSWI2.Cls_Enabled Reserved
13 84CSWI2.Opn/Cls_Enabled Permission of tap change emergency stop operation
14 84CSWI2.Opn_Exec Tap change emergency stop operation
15 84CSWI2.Cls_Exec Reserved
16 84CSWI2.Opn_Sel Tap change emergency stop selection
17 84CSWI2.Cls_Sel Reserved 4
18 84CSWI2.Cmd_ManSel Selection command for manual tap position control of emergency stop
19 84CSWI2.Cmd_ManOpn Emergency stop command for manual tap position control
20 84CSWI2.Cmd_ManCls Reserved
21 84.Alm_Unmatched Three-phase TPI discordance alarm
22 84.TP01 Converted general TPI or phase A TPI
23 84.TP02 Converted phase B TPI
24 84.TP03 Converted phase C TPI
25 84.BO_RunawayTrip Tripping output for the situation "Tap runaway"
26 84.Alm_Invalid_TP01 Invalid input of converted general TPI or phase A TPI
27 84.Alm_Invalid_TP02 Invalid input of converted phase B TPI
28 84.Alm_Invalid_TP03 Invalid input of converted phase C TPI

PCS-978S Transformer Relay 4-29


Date: 2022-01-17
4 Control Functions

4.4.3 Logic

SIG in_Manual_Sel = NUL &


>=1
SIG in_Manual_Opn

SIG in_Manual_Sel &

SIG in_Manual_Opn
&
SIG Opn_Enabled Cmd_ManOpn

SIG Control mode = Local

SIG in_Manual_Sel = NUL &

4 SIG in_Manual_Cls
>=1
SIG in_Manual_Sel &

SIG in_Manual_Cls
&
SIG Cls_Enabled Cmd_ManCls

SIG Control mode = Local

Figure 4.4-2 Logic diagram of manual control of tap position

EN [84CSWI*.En_CILO_Cls] >=1

SIG 84CSWI*.Cls_Enabled

SIG 84CSWI* Control Mode = Remote & &


>=1 0 [84CSWI*.t_PW_Cls] 84CSWI*.Cls_Exec
SIG 84CSWI*.Cmd_ManCls >=1

84CSWI* closing cmd. from device local HMI &

84CSWI* closing cmd. from SCADA/Gateway

EN [84CSWI*.En_CILO_Opn] >=1

SIG 84CSWI*.Opn_Enabled

SIG 84CSWI* Control Mode = Remote & &


>=1 0 [84CSWI*.t_PW_Opn] 84CSWI*.Opn_Exec
SIG 84CSWI*.Cmd_ManOpn >=1

84CSWI* opening cmd. from device local HMI &

84CSWI* opening cmd. from SCADA/Gateway

Figure 4.4-3 Logic diagram of control operation of tap position changer

4-30 PCS-978S Transformer Relay

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4 Control Functions

EN [84.En_RunawayTrip]

SIG 84CSWI1.Opn_Exec >=1 &


0 [84.t_RunawayTrip] >=1
SIG 84CSWI1.Cls_Exec 84.BO_RunawayTrip

SIG |84.TP01(N) - 84.TP01(N-1)| > 1


>=1
SIG |84.TP02(N) - 84.TP02(N-1)| > 1

SIG |84.TP03(N) - 84.TP03(N-1)| > 1

SIG 84.in_RunawayTrip

Figure 4.4-4 Logic diagram of runaway trip during tap position control process

4.4.4 Settings
Table 4.4-3 Settings of tap position indicator
4
No. Setting Range Unit Default Description
The option of the input code of tap
position indication (TPI)
Resv: direct input or DC analogue
channel
Resv BCD: 6-bit BCD for max. 39 positions
BCD Carry: 13-bit carry inputs for max. 29
Carry positions
1 84.Opt_Code - BCD
Independent Independent: 26-bit independent
BCD-PhSeg contacts for max. 26 positions
Independent-PhSeg BCD-PhSeq: 18-bit BCD for max. 39
phase-segregated positions
Independent-PhSeq: 24-bit
independent contacts for max. 8
phase-segregated positions
The Delay Pick Up (DPU) time, i.e.
2 84.t_DPU 0~6000 ms 500
debounce time, of TPI
Enabling/disabling the trip of tap
Disabled or
3 84.En_RunawayTrip - Disabled changer motor power supply during
Enabled
the situation "Tap runaway"
The holding time of output signal for
the trip of tap changer motor power
4 84.t_RunawayTrip 0~60000 ms 500
supply during the situation "Tap
runaway"
The number of the defined segment,
5 84.Num_AI_Segment 0~48 - 1 i.e. tap positions, in the DC analog
input range of TPI
The rated value corresponding to the
6 84.Rated_AI_Segment** -220.00~220.00 - 0.00
No.** segment in DC analog input

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No. Setting Range Unit Default Description


range of TPI
The rated value deviation
7 84.Devn_AI_Segment** 0.00~100.00 % 0.00 corresponding to the No.** segment in
DC analog input range of TPI
The TPI number of the No.** segment
8 84.Value_Segment** -50~50 - 0
in DC analog input range

4.5 Automatic Voltage Regulation (90V)

Voltage regulation function can regulate the object voltage to the pre-set target value by changing
the tap position of transformer. The device provides both automatic and manual modes of
transformer tap changer control.

4 4.5.1 Function Description

The Automatic Tap Changer Control (ATCC) function can provide up to four target voltage values.
It regulates voltage by sending a raising or descending command to the tap changer of
transformer after a latency. The initial regulation can be set as definite-time or inverse-time
characteristic. The blocking criteria by limits of voltage, current, tap position, etc. are available. In
addition, the device can regulate voltage at the end of transmission line by compensating the
voltage drop according to line resistance and reactance.

4.5.1.1 Regulation Process

An ATCC process example is illustrated in the following figure.

URegulated
Latency3

Latency1 Latency2 Latency2

t3 t4 t5 t6 t7
Bandwidth

UTarget

t1 t2
Latency1
TIME

Figure 4.5-1 Diagram of ATCC process

 t2 - t1 = Latency1

The ATCC function is triggered from t1 because the regulated voltage exceeds the bandwidth,

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and the Latency1 of initial tap change command starts. However, during t2-t1, the regulated
voltage returns back to the bandwidth. Thus, no command will be issued.

 t4 - t3 = Latency1

The ATCC function is triggered from t3 because the regulated voltage exceeds the bandwidth,
and the Latency1 of initial tap change command starts. During t4-t3, the regulated voltage
remains to be outside of the bandwidth. Then, a step down command is issued from t4.

 t5 - t4 = Latency2

The Latency2 of sequential tap change command starts from t4 because the regulated
voltage is still outside of the bandwidth after the initial command. During t5-t4, the regulated
voltage remains to be outside of the bandwidth. Then, a step down command is issued from
t5.

 t6 - t5 = Latency2

The Latency2 of sequential tap change command starts from t5 because the regulated
4
voltage is still outside of the bandwidth after the previous commands. However, during t6-t5,
the regulated voltage returns back to the bandwidth. Thus, no command will be issued.

 t7 - t3 = Latency3

During t7-t3, the regulated voltage returns back to the bandwidth, the ATCC function
successfully completes the task. Otherwise, the ATCC function will be blocked and the alarm
signal "90V.ReguFail_Blk" will be issued immediately.

Where:

UTarget is the target voltage value of regulation that defined by the setting [90V.U_Target_*], * can
be 1, 2, 3 or 4.

Bandwidth is the acceptable range of target voltage and is defined by the setting
[90V.U_Bandwidth].

Latency1 is the settable interval before the sending of initial command and is defined by the
setting [90V.t1_Intvl].

Latency2 is the settable interval between two times of tap change and is defined by the setting
[90V.t2_Intvl].

Latency3 is the result judgement interval of the whole process of ATCC function and is defined by
the setting [90V.t_ReguFail].

The bandwidth represents the permitted fluctuation range of measured voltage compared to the
target value. If the regulated voltage is inside of the bandwidth, no more control command will be
issued to change the tap. If the voltage exceeds the bandwidth, a tap change command shall be
issued after Latency1. Then the on-load tap-changer will carry out an operation according to the
command.

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4.5.1.2 Sequential Regulation

If the regulated voltage exceeds the target voltage bandwidth, and none of the blocking criteria is
met, the ATCC function initiates step up/down command automatically. The Latency1 before the
initial command is defined by the setting [90V.t1_Intvl]. A serial of commands will be sent
sequentially until the regulated voltage appears within the pre-set target voltage bandwidth. The
following Latency2 between two tap change commands is defined by the setting [90V.t2_Intvl].

TIME

Bandwidth

4
Cmd pulse

Latency2

Cmd pulse
Latency2

Cmd pulse

Latency2

Cmd pulse

Latency1

URegulated

Lower limit UTarget Upper limit

Figure 4.5-2 Sequence diagram of ATCC operation

4.5.1.3 Inverse Time Operating Characteristic

To reduce the delay of Latency1 for the initial tap change command, the inverse-time
characteristics can be put into service by the logic setting [90V.En_IDMT]. The greater the voltage
deviation appears to the bandwidth, the shorter the time delay will be. Thus, the inverse-time
characteristics can react faster to large voltage variation. The time calculation equation is:

Latency1BandwidthU_Target
𝑡=
|ΔU|

Where:

Latency1 is the initial operating time delay of ATCC, which is defined by the setting [90V.t1_Intvl].

Bandwidth is the acceptable range of target voltage and is defined by the setting
[90V.U_Bandwidth] in percentage value.

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|ΔU| is the absolute value of voltage deviation which is calculated by the target voltage
“90V.U_Target” and the regulated voltage “90V.U_Regu”.

180 [90V.t1_Intvl]
120
80
40

U/B
4
Figure 4.5-3 IDMT operating characteristic curve of the initial tap change command of ATCC

4.5.1.4 Selection of Target Voltage

This device supports four target voltage values. At a time, only one can be the valid value. The
selection function supports the priority from high (target voltage 1) to low (target voltage 4) of
these four values. It is user-programmable in using the configuration tool PCS-studio. If the four
input terminals are left blank, the selection logic hasn’t been configured. The default selected
target voltage value is then defined by [90V.U_Target_1].

SIG 90V.in_set_target1 90V.U_target_1 is seletced

&
90V.U_target_2 is seletced
SIG 90V.in_set_target2

&
90V.U_target_3 is seletced
SIG 90V.in_set_target3

&
90V.U_target_4 is seletced
SIG 90V.in_set_target4

Figure 4.5-4 Logic diagram of selection of target voltage value

4.5.1.5 Switch of Automatic/Manual Mode

The ATCC function can automatically send command to tap changer according to blocking criteria
in real time. Additionally, this device can switch on the manual mode of voltage regulation in using
of the tap position control function (84). The automatic mode and the manual mode of voltage

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regulation is this device are mutually exclusive to each other.

User may use the [90V.Link_Auto] setting value or the “90V.in_auto” signal state to switch the
automatic/manual mode. The device provides the input terminal “90V.in_opt_mode” for the
decision of device voltage regulation mode via logic link setting or binary input. The switching logic
is shown in the following figure.

SET 90V.Link_Auto &

>=1
SIG 90V.in_opt_mode 90V.Auto
&

SIG 90V.in_auto

SET 90V.Link_Auto &


4
>=1
SIG 90V.in_opt_mode 90V.Manual
&

SIG 90V.in_auto

Figure 4.5-5 Logic diagram of automatic/manual mode switch of voltage regulation

4.5.1.6 Alarm and Blocking Conditions

The ATCC function judges the alarm and blocking criteria listed in the following table. If any of
them is met, the ATCC function will issue the corresponding alarm signal or even be blocked with
the general alarm signal “90V.Total_Blk”.

ATCC Alarm/Blocking Signal Cause Reset Mode

90V.Manual_Blk The manual mode of voltage regulation is activated. Auto

90V.Maint_Blk The device is in maintenance state. Auto

90V.VTS_Blk Alarm signal of VT circuit supervision Auto

90V.Alm_UV /
The regulated voltage is under the ATCC function lower limit.
90V.UV_Blk Auto

90V.Alm_OV /
The regulated voltage is under the ATCC function upper limit.
90V.OV_Blk Auto

90V.Alm_OC Any phase current is greater than the ATCC function /

90V.OC_Blk overcurrent threshold. Auto

90V.ReguFail_Blk Failure of ATCC Manual


Detection of tap runaway situation (the tap changer is out of
90V.Runaway_Blk control and raises or descends continuously, i.e. more than Manual
one step for one control command)
90V.TP_OvRange_Blk The tap position indication is out of limit. Auto

90V.Quality_Blk Data abnormal quality of regulated voltage, current or tap Auto

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ATCC Alarm/Blocking Signal Cause Reset Mode


position indication

90V.N_Regu_OvLmt_Blk Too many commands in one ATCC process Manual

90V.ExtBlk1 The blocking input "in_extern1_block" is 1. Manual

90V.ExtBlk2 The blocking input "in_extern2_block" is 1. Auto

 90V.Alm_UV, 90V.UV_Blk, 90V.Alm_OV and 90V.OV_Blk

The regulated voltage range is defined by the settings [90V.U_UV] and [90V.U_OV]. An
out-of-limit of such range can trigger the alarm “90V.Alm_UV” or “90V.Alm_OV” or even block
the ATCC function depending on the corresponding logic settings [90V.En_Alm_UV],
[90V.En_Alm_OV], [90V.En_UV_Blk] and [90V.En_OV_Blk].

EN 90V.En_Alm_UV &

SET 90V.U_Regu<[90V.U_UV]
10s 1s 90V.Alm_UV
4
EN 90V.En_UV_Blk &
90V.UV_Blk
SET 90V.U_Regu<[90V.U_UV]

Figure 4.5-6 Logic diagram of under voltage of ATCC

EN 90V.En_Alm_OV &
10s 1s 90V.Alm_OV
SET 90V.U_Regu>[90V.U_OV]

EN 90V.En_OV_Blk &
90V.OV_Blk
SET 90V.U_Regu>[90V.U_OV]

Figure 4.5-7 Logic diagram of over voltage of ATCC

 90V.Alm_OC, 90V.OC_Blk

The overcurrent limit is defined by the setting [90V.I_OC]. An out-of-limit can trigger the alarm
“90V.Alm_OC” or even block the ATCC function depending on the corresponding logic
settings [90V.En_Alm_OC] and [90V.En_OC_Blk].

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EN 90V.En_Alm_OC &
10s 1s 90V.Alm_OC
SET IA>[90V.I_OC]
>=1
SET IB>[90V.I_OC]
&
SET IC>[90V.I_OC]
90V.OC_Blk
EN 90V.En_OC_Blk

Figure 4.5-8 Logic diagram of over current of ATCC

 90V.ReguFail_Blk

Since the initial ATCC command is issued, if the regulated voltage is still out of the bandwidth
of target voltage after the timeout of the ATCC failure period defined by the setting
[90V.t_ReguFail] (see Latency3=t7-t3 in the Figure 4.5-1), the actual round of ATCC ends. At
the same time, the blocking signal “90V.ReguFail_Blk” is issued and the ATCC function is
4 blocked. The blocking state is maintained until one of the following conditions appears:
manual reset, regulated voltage return within the bandwidth or change of target voltage value.

 90V.TP_OvRange_Blk

The tap position range is defined by the settings [90V.TP_Min] and [90V.TP_Max]. An
out-of-limit of such range can block the ATCC function.

SET 84.TP01 < [90V.TP_Min] >=1


90V.TP_OvRange_Blk
SET 84.TP01 > [90V.TP_Max]

Figure 4.5-9 Logic diagram of TPI over range of ATCC

 90V.Quality_Blk

If there is an abnormal quality alarm of the ATCC related quantities, the ATCC function shall
be blocked. The two kinds of ATCC related quantities are: regulated voltage and current
received from merging unit; and tap position indication that is defined in the Section 4.4.1.1.

SIG U or I: link disconnection or invalid "q" >=1


90V.Quality_Blk
SIG 84.Alm_Invalid_TP

Figure 4.5-10 Logic diagram of invalid input of ATCC

 90V.N_Regu_OvLmt_Blk

In an ATCC process, if the number of issued commands within the regulation period defined
by the setting [90V.t_Period_Regu] exceeds the limit defined by the setting [90V.Num_Regu],
the actual process ends. At the same time, the blocking signal “90V.N_Regu_OvLmt_Blk” is
issued and the ATCC function is blocked. The blocking is maintained until one of the following

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conditions appears: manual reset, expiration of the regulation period or change of target
voltage value.

 90V.ExtBlk1, 90V.ExtBlk2

The device supports the blocking of ATCC function by two external signals “90V.ExtBlk1” and
“90V.ExtBlk2”. For “90V.ExtBlk1”, the ATCC function cannot be automatically unlocked and
the manual reset is mandatory. However, the ATCC function can be automatically unlocked
after the rest of “90V.ExtBlk2”.

The logic of ATCC function general block signal and automatic/manual reset is shown in the
following figure.

Manual Reset
SIG 90V.Runaway_Blk

SIG 90V.ReguFail_Blk >=1 4


SIG 90V.N_Regu_Ovlmt_Blk

SIG 90V.ExtBlk1

Automatic Reset

SIG 90V.Manual_Blk
>=1
SIG 90V.Maint_Blk

SIG 90V.VTS_Blk >=1


90V.Total_Blk
SIG 90V.UV_Blk
>=1
SIG 90V.OV_Blk

SIG 90V.OC_Blk

SIG 90V.TP_OvRange_Blk
>=1
SIG 90V.Quality_Blk

SIG 90V.ExtBlk2

Figure 4.5-11 Logic diagram of general blocking of ATCC

4.5.1.7 Compensation of Line Voltage Drop

When transmitting electric power from transformer to load over a long distance, the load side
voltage at the end of the transmission line will drop due to line resistance and reactance. To
accurately regulate the voltage at the end of the transmission line, the ATCC function can
compensate the voltage drop according to line parameters and total active/reactive power of
transformer.

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HV Side LV Side Load Side

RL XL

Transformer Transmission Line

Figure 4.5-12 Equivalent circuit diagram of line voltage drop

The calculation equation is:


2
𝑈𝐿 = √(𝑈𝐵 − 𝑎)2 + 𝑏2

𝑃𝑅𝐿 +𝑄𝑋𝐿 𝑃𝑋𝐿 −𝑄𝑅𝐿


𝑎= , 𝑏=
𝑈𝐵 𝑈𝐵

Where:
4
UL: load side voltage

UB: transformer side voltage

P: transformer active power

Q: transformer reactive power

RL: line resistance

XL: line reactance

Im

UB

jXLIL Re
O UL
RLIL

Figure 4.5-13 Vector diagram for compensation of line voltage drop

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4.5.2 Function Block Diagram

ATCC

in_pqcalc
in_opt_mode
in_auto
in_test
in_sel_target1
in_sel_target2
in_sel_target3
in_sel_target4
in_vts_block
in_runaway_block
in_extern1_block
in_extern2_block 4
in_manual_reset
in_tap_pos

4.5.3 I/O Signals

Table 4.5-1 Input signals of automatic voltage regulation

No. Input Signal Description


1 90V.in_pqcalc A data set including three-phase current and voltage information
Input signal to decide the automatic/manual voltage regulation mode via logic
2 90V.in_opt_mode
link or binary input.
Input signal to decide the automatic/manual voltage regulation mode by
3 90V.in_auto
binary input
4 90V.in_test Input signal of device maintenance state, i.e. “BI_Maintenance” signal
5 90V.in_sel_target1 Input value of ATCC target voltage 1
6 90V.in_sel_target2 Input value of ATCC target voltage 2
7 90V.in_sel_target3 Input value of ATCC target voltage 3
8 90V.in_sel_target4 Input value of ATCC target voltage 4
9 90V.in_vts_block Input of ATCC blocking signal by VT circuit supervision alarm
10 90V.in_runaway_block Input of ATCC blocking signal by tap runaway situation
11 90V.in_extern1_block Input of ATCC external blocking signal 1
12 90V.in_extern2_block Input of ATCC external blocking signal 2
13 90V.in_manual_reset Input signal of manual reset of ATCC blocking
14 90V.in_tap_pos Input value of tap position indication

Table 4.5-2 Output signals of automatic voltage regulation

No. Output Signal Description


1 90V.U_Target The selected target voltage value
2 90V.U_Regu Regulated voltage value

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No. Output Signal Description


3 90V.U_Regu_Percent The ratio in percentage of the regulated voltage to the target voltage
4 90V.I_Load Load side current value
Countdown interval of Latency1 or Latency2 before the sending of tap
5 90V.Intvl_Countdown
change command
6 90V.Auto ATCC function is in automatic regulation mode
ATCC function is out of service, the device may regulate voltage in manual
7 90V.Manual
mode
8 90V.StepUpTP ATCC step up command
9 90V.StepDownTP ATCC step down command
10 90V.U_Normal The regulated voltage is inside the target voltage bandwidth
11 90V.Total_Blk ATCC general blocking signal
12 90V.Alm_UV ATCC undervoltage alarm of regulated voltage
13 90V.Alm_OV ATCC overvoltage alarm of regulated voltage
4 14 90V.Alm_OC ATCC overcurrent alarm of load side current
15 90V.Manual_Blk ATCC blocking signal by device manual voltage regulation mode
16 90V.Maint_Blk ATCC blocking signal by device maintenance state
17 90V.VTS_Blk ATCC blocking signal by VT circuit supervision alarm
18 90V.UV_Blk ATCC blocking signal by undervoltage of regulated voltage
19 90V.OV_Blk ATCC blocking signal by overvoltage of regulated voltage
20 90V.OC_Blk ATCC blocking signal by overcurrent of load side current
21 90V.ReguFail_Blk ATCC blocking signal by overtime of regulation
22 90V.Runaway_Blk ATCC blocking signal by tap position runaway situation
23 90V.TP_OvRange_Blk ATCC blocking signal by over range of tap position
ATCC blocking signal by bad quality of analog or tap position indication
24 90V.Quality_Blk
inputs
25 90V.N_Regu_OvLmt_Blk ATCC blocking signal by too many times of sending command
26 90V.ExtBlk1 ATCC blocking signal by external blocking signal 1
27 90V.ExtBlk2 ATCC blocking signal by external blocking signal 2
Alarm of ATCC analog channel configuration which should correspond to
28 90V.Alm_Cfg_Ch
the regulated voltage

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4.5.4 Logic

SIG 90V.Auto

SIG 90V.Total_Blk &

SIG UR is outside the bandwidth >=1


[84CSWI1.t_PW_Cls] 0ms 84CSWI1.Cls_Exec
SIG Raising command from 84 &

SIG 90V.Manual

SIG 90V.Auto

SIG 90V.Total_Blk &

SIG UR is outside the bandwidth >=1


4
[84CSWI1.t_PW_Opn] 0ms 84CSWI1.Opn_Exec
SIG Descending command from 84 &

SIG 90V.Manual

Figure 4.5-14 Logic diagram of ATCC tap change command

UR is outside the bandwidth means:

90V.U_Regu > [90V.U_Target_*]  (1 + [90V.U_Bandwidth]) or

90V.U_Regu < [90V.U_Target_*]  (1 - [90V.U_Bandwidth])

The logic diagram takes an auto-transformer, which raises tap to step up


and descends tap to step down voltage, as the example.

4.5.5 Settings

Table 4.5-3 Settings of automatic voltage regulation

No. Name Range Unit Default Description


1 90V.U_Target_1 0.00~160.00 V 100.00 The ATCC target voltage value 1
2 90V.U_Target_2 0.00~160.00 V 110.00 The ATCC target voltage value 2
3 90V.U_Target_3 0.00~160.00 V 120.00 The ATCC target voltage value 3
4 90V.U_Target_4 0.00~160.00 V 130.00 The ATCC target voltage value 4
The permissive bandwidth of the ATCC target
5 90V.U_Bandwidth 0.10~30.00 % 10.00
voltage
6 90V.Opt_U Ua - Uab The phase option of the target voltage

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No. Name Range Unit Default Description


Ub
Uc
Uab
Ubc
Uca
The upper limit of the regulatable tap position
7 90V.TP_Max 0~64 - 10
range of ATCC
The lower limit of the regulatable tap position
8 90V.TP_Min 0~64 - 0
range of ATCC
The threshold of the ATCC undervoltage
9 90V.U_UV 0.00~150.00 V 80.00
supervision function
Disabled Enabling /disabling the alarm function by ATCC
10 90V.En_Alm_UV - Enabled
Enabled undervoltage
4 11 90V.En_UV_Blk
Disabled
- Enabled
Enabling /disabling the blocking function by
Enabled ATCC undervoltage
12 90V.U_OV 0.00~150.00 V 120.00 The threshold of ATCC overvoltage
Disabled Enabling /disabling the alarm function by ATCC
13 90V.En_Alm_OV - Enabled
Enabled overvoltage
Disabled Enabling /disabling the blocking function by
14 90V.En_OV_Blk - Enabled
Enabled ATCC overvoltage
15 90V.I_OC 0.00~100.00 A 6.00 The threshold of ATCC overcurrent
Disabled Enabling /disabling the alarm function by ATCC
16 90V.En_Alm_OC - Enabled
Enabled overcurrent
Disabled Enabling /disabling the blocking function by
17 90V.En_OC_Blk - Enabled
Enabled ATCC overcurrent
Disabled Enabling /disabling the inverse-time
18 90V.En_IDMT - Disabled
Enabled characteristic of ATCC initial command
19 90V.t1_Intv1 0~600 s 30 The delay 1 of ATCC operation
20 90V.t2_Intv1 0~600 s 10 The delay 2 of ATCC operation
Disabled Enabling /disabling the line voltage drop
21 90V.En_LDCRX - Disabled
Enabled compensation function of ATCC
The line reactance of the line voltage drop
22 90V.X_LDC -100.00~100.00 ohm 0.00
compensation of ATCC
The line resistance of the line voltage drop
23 90V. R_LDC 0.00~100.00 ohm 0.00
compensation of ATCC
24 90V.t_ReguFail 0~3600 s 180 The judging period of ATCC failure
The limit of times of regulation in an ATCC
25 90V.Num_Regu 1~1000 - 48
process
26 90V.t_Period_Regu 1~24 h 24 The regulation period of and ATCC process

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4.6 Parallel Voltage Regulation (PVR)

When two transformers run parallel in Master-Follower mode, the follower transformer can
automatically step up/down according to the master transformer tap change command. Thus,
achieving a simultaneous voltage regulation of both transformers.

4.6.1 Function Description

Generally, when two transformers run in parallel, their characteristics such as capacity and tap
position are the same. The two transformers interact information, such as tap position indication,
tap change blocking signal, tap change command, etc., through the GOOSE network. When the
conditions are met, the follower changes its tap position according to the master tap change
command to regulate the voltage.

When changing tap position in parallel, both the master and the follower will judge whether the tap
position indications are consistent. The judgement can be made according to the actual TPI of 4
both transformers or to the state of the programmable input signal “PVR.in_tap_match”. However,
if “PVR.in_tap_match” has been configured through the configuration tool PCS-Studio, the TPI
consistency judgement will be disabled in PVR function.

Moreover, the tap change function in reverse sequence is available. When the master raises the
tap to step up, the follower can descend its tap to step up, and vice versa. The sequence of tap
change depends on the setting value of [PVR.Opt_Dir_TP]. For example, two transformers
(adjustable tap range 1~15) run in parallel and enable the reverse sequence tap change function.
When the master’s TPI is 3, the TPI of both transformers are consistent if the follower’s TPI is 13.

4.6.1.1 Regulation Process

For a parallel voltage regulation process, the timing coordination between master and follower is
shown in the following figure.

Master Master
[PVR.t_Wait] [PVR.t_Stable]

Tap change cmd. Send cmd. via


GOOSE

Master Idle state Wait for tap change Wait for stable state Idle state
operation

Receive cmd. via


GOOSE

Follower Idle state Idle state Wait for stable state Idle state
Follower
[PVR.t_Stable]

t1 t3 t2 t4 t5 t6 t

Figure 4.6-1 Logic diagram of over current of ATCC

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1. t1

a) The master has successfully sent the tap change command and begins to wait for tap
position change operation during the t2-t1 period defined by the setting [PVR.t_Wait]. Its
output signal “PVR.parallel_Reday” is set as 1.

b) The follower keeps idle state.

2. t2

If t3 > t2, the master will reset to idle state and this round of parallel voltage regulation is
aborted.

3. t3

a) The master’s tap change operation has completed. It begins to wait for stable state of
parallel voltage regulation and sends tap change command to the follower via GOOSE
4 communication network.

b) The follower keeps idle state.

4. t4

a) The master keeps waiting for stable state.

b) The follower receives the tap change command from the master via GOOSE
communication network and begins to wait for stable state.

5. t5

a) The master’s stable state waiting period t5-t3 defined by the setting [PVR.t_Stable] is
exhausted and returns to idle state.

b) The follower keeps waiting for stable state.

6. t6

a) The master keeps idle state.

b) The follower’s stable state waiting period t5-t4 defined by the setting [PVR.t_Stable] is
exhausted and return to idle state.

Stable state refers that the self BCU has completed the tap change and is
waiting for the peer BCU to complete the tap change. During such period,
the master sends GOOSE step up/down command; the follower proceeds
tap change operation.

The TPI consistency judgement of both transformers will not start until the

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4 Control Functions

stable state is over.


4.6.1.2 Switch of Parallel/Standalone Mode

The device supports two methods to switch the parallel/standalone mode:

 Value of the function link [PVR.Link_Standalone]

0: Parallel; 1: Standalone.

 Rising edge of the input signal “PVR.in_standalone”

Every time the rising edge of the input signal is received, the parallel/standalone mode is
switched once.

4.6.1.3 Switch of Master/Follower Mode

The device supports three methods to switch the master/follower mode:

 Setting value of the function link [PVR.Link_Master]


4
0: Follower; 1: Master.

 Rising edge of the input signal “PVR.in_master”

Every time the rising edge of the input signal is received, the master/follower mode will be
switched.

 Rising edge of the input signal “PVR.in_para_master” which is linked to the output signal
“PVR.Master” of the parallel BCU via GOOSE communication to indicate its master/follower
mode.

Every time the rising edge of the input signal is received, the master/follower mode will be
switched.

4.6.2 Function Block Diagram

PVR

in_master
in_standalone
in_para_master
in_self_tap
in_para_tap
in_self_block
in_para_block
in_goose_raise
in_goose_lower
in_inner_raise
in_inner_lower
in_tap_match

PCS-978S Transformer Relay 4-47


Date: 2022-01-17
4 Control Functions

4.6.3 I/O Signals

Table 4.6-1 Input signals of parallel voltage regulation

No. Input Signal Description


1 PVR.in_master Input signal to switch PVR master/follower mode

2 PVR.in_standalone Input signal to switch PVR parallel/standalone mode


Input signal to switch PVR master/follower mode by the mode switch
3 PVR.in_para_master
indication received from parallel BCU via GOOSE communication
4 PVR.in_self_tap Input value of tap position indication from self BCU

5 PVR.in_para_tap Input value of tap position indication from parallel BCU


6 PVR.in_self_block Input of PVR blocking signal from self BCU

7 PVR.in_para_block Input of PVR blocking signal from parallel BCU

8 PVR.in_goose_raise Received tap raising command via GOOSE network


4 9 PVR.in_goose_lower Received tap descending command via GOOSE network
10 PVR.in_inner_raise Input of tap raising command from self BCU

11 PVR.in_inner_lower Input of tap descending command from self BCU

12 PVR.in_tap_match Input signal of TPI consistency state of master and follower

Table 4.6-2 Output signals of parallel voltage regulation

No. Output Signal Description


Indication of PVR operating mode between master (value 1) and
1 PVR.Master
follower (value 0)
Indication of PVR operating mode of standalone (value 1) and
2 PVR.Standalone
parallel (value 0)
In parallel mode, the master tap change has been successfully
3 PVR.parallel_Ready
completed.
4 PVR.TP_Self Tap position indication from self BCU

5 PVR.TP_Peer Tap position indication from parallel BCU


6 PVR.StepUpTP_Self Tap raising command from self BCU

7 PVR.StepDownTP_Self Tap descending command from self BCU

8 PVR.Sent_StepUpTP_GOOSE Tap raising command is sent via GOOSE network

9 PVR.Sent_StepDownTP_GOOSE Tap descending command is sent via GOOSE network

10 PVR.Recvd_StepUpTP_GOOSE Tap raising command is received via GOOSE network

11 PVR.Recvd_StepDownTP_GOOSE Tap descending command is received via GOOSE network

12 PVR.Total_Blk PVR general blocking signal

13 PVR.Self_Blk PVR blocking signal from self BCU

14 PVR.Peer_Blk PVR blocking signal from parallel BCU

15 PVR.Sig_TP_Matched TPI consistency state of master and follower

16 PVR.ChCfg_Blk PVR blocking signal by configuration of any of the following

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4 Control Functions

No. Output Signal Description


signals:
"PVR.in_self_tap”, “PVR. in_para_tap”, “PVR.in_inner_raise”,
“PVR.in_inner_lower”, “PVR.in_goose_raise”,
“PVR.in_goose_lower”
PVR blocking signal by invalid data quality of any of the following
signals:
"PVR.TP_Self”, "PVR.TP_Peer”, "PVR.Self_Blk”,
17 PVR.Quality_Blk "PVR.Peer_Blk”, “PVR.Sent_StepUpTP_GOOSE”,
“PVR.Sent_StepDownTP_GOOSE”,
“PVR.Recvd_StepUpTP_GOOSE”,
“PVR.Recvd_StepDownTP_GOOSE”
PVR blocking signal by TPI inconsistency between master and
18 PVR.UnmatchedTP_Blk
follower

4.6.4 Logic
4
SIG PVR.Standalone &
>=1
PVR.StepUpTP_Self
SIG Manual tap change cmd. PVR.StepDownTP_Self
&
SIG PVR.Master

&
SIG PVR.Total_Blk

SIG PVR.Total_Blk (Follower) &


PVR.Sent_StepUpTP_GOOSE
PVR.Sent_StepDownTP_GOOSE
SIG Change of 84.TP01

Figure 4.6-2 Logic diagram of PVR in master BCU

SIG PVR.Standalone &

SIG Manual tap change cmd.


& >=1
PVR.StepUpTP_Self
PVR.StepDownTP_Self
SIG PVR.Master

&
SIG PVR.Total_Blk

SIG PVR.Total_Blk (Master)

&

SIG GOOSE cmd. (Master)

Figure 4.6-3 Logic diagram of PVR in follower BCU

PCS-978S Transformer Relay 4-49


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4 Control Functions

SIG PVR.ChCfg_Blk

SIG PVR.Quality_Blk >=1


PVR.Total_Blk
SIG PVR.UnmatchedTP_Blk

SIG PVR.Self_Blk

Figure 4.6-4 Logic diagram of PVR general blocking signal

4.6.5 Settings

Table 4.6-3 Settings of parallel voltage regulation

No. Name Range Unit Default Description


1 PVR.t_Wait 0~60 s 60 The waiting time of a tap changer operation of PVR
2 PVR.t_Stable 0~60 s 60 The waiting time of the stable state of PVR
The debounce time of the TPI consistency
4 3 PVR.t_UnmatchedTP 0~30 s 10
judgement of PVR
Forward
4 PVR.Opt_Dir_TP - Forward The option of the tap change sequence of PVR
Reverse

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5 Measurement

5 Measurement

Table of Contents

5.1 Overview ........................................................................................................... 5-1


5.2 Primary Values ................................................................................................. 5-1
5.2.1 General Values ..................................................................................................................... 5-1

5.2.2 Angle Values ......................................................................................................................... 5-1

5.2.3 Sequence Components Values ............................................................................................ 5-2

5.2.4 Power Values ........................................................................................................................ 5-2

5.2.5 DCAI Values ......................................................................................................................... 5-3

5.3 Secondary Values ............................................................................................ 5-3


5.3.1 General Values ..................................................................................................................... 5-3 5
5.3.2 Angle Values ......................................................................................................................... 5-3

5.3.3 Sequence Components Values ............................................................................................ 5-4

5.3.4 Power Values ........................................................................................................................ 5-4

5.3.5 DCAI Values ......................................................................................................................... 5-5

5.4 Function Values ............................................................................................... 5-5


5.4.1 Sum Values .......................................................................................................................... 5-5

5.4.2 Angle Values ......................................................................................................................... 5-5

5.4.3 OvExc Values ....................................................................................................................... 5-6

5.4.4 Diff Values............................................................................................................................. 5-6

5.4.5 REF Values ........................................................................................................................... 5-8

5.4.6 WdgDiff Values ..................................................................................................................... 5-9

5.4.7 ThOvLd Values ................................................................................................................... 5-10

5.4.8 Synchronism Check ........................................................................................................... 5-10

5.5 Energy Metering..............................................................................................5-11


5.6 DC Measuring Transducers ...........................................................................5-11
5.6.1 Function Description........................................................................................................... 5-11

5.6.2 I/O Signals .......................................................................................................................... 5-12

PCS-978S Transformer Relay 5-a


Date: 2022-01-17
5 Measurement

5.6.3 Settings ............................................................................................................................... 5-12

List of Figures

Figure 5.6-1 Characteristic curve of a DC measuring transducer input ........................... 5-12

List of Tables

Table 5.6-1 Input signals of DC measuring transducers ..................................................... 5-12

Table 5.6-2 Output signals of DC measuring transducers .................................................. 5-12

Table 5.6-3 Settings of DC measuring transducers ............................................................. 5-12

5-b PCS-978S Transformer Relay

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5 Measurement

In the chapter, the prefix ”x” in some measurements, represents some side
or bushing of transformer defined by user through PCS-Studio software,
which may be “HVS”, “MVS”, “LVS”, “HVS2”, “MVS2”, “LVS2”, “CWS”,
“HVB”, “MVB”, “LVB”, etc. If only one protection element is equipped, the
prefix “x.” may disappear.

5.1 Overview

This device performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.

5.2 Primary Values 5


Access path: MainMenu  “Measurements”  “Primary Values”

5.2.1 General Values

No. Item Definition Unit

1 x.Ia_Pri Phase-A secondary current A

2 x.Ib_Pri Phase B primary current A

3 x.Ic_Pri Phase C primary current A

4 x.Neu.3I0_Ext_Pri External residual primary current A

5 x.Ua_Pri Phase A primary voltage kV

6 x.Ub_Pri Phase B primary voltage kV

7 x.Uc_Pri Phase C primary voltage kV

8 x.Uab_Pri Phase AB primary voltage kV

9 x.Ubc_Pri Phase BC primary voltage kV

10 x.Uca_Pri Phase CA primary voltage kV

11 x.Neu.U_Pri Residual primary voltage kV

5.2.2 Angle Values

No. Item Definition Unit

1 x.Ang(Ia) Phase angle of phase A current deg

2 x.Ang(Ib) Phase angle of phase B current deg

PCS-978S Transformer Relay 5-1


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5 Measurement

No. Item Definition Unit

3 x.Ang(Ic) Phase angle of phase C current deg

4 x.Ang(3I0_Cal) Phase angle of calculated residual current deg

5 x.Neu.Ang(3I0_Ext) Phase angel of external neutral-point residual current deg

6 x.Ang(Ua) Phase angle of phase A voltage deg

7 x.Ang(Ub) Phase angle of phase B voltage deg

8 x.Ang(Uc) Phase angle of phase C voltage deg

9 x.Ang(3U0_Cal) Phase angle of calculated residual voltage deg

10 x.Neu.Ang(U) Phase angle of neutral-point residual voltage deg

11 x.Ang (Ia-Ib) Phase angle between phase A and phase B currents deg

12 x.Ang (Ib-Ic) Phase angle between phase B and phase C currents deg

13 x.Ang (Ic-Ia) Phase angle between phase C and phase A currents deg

14 x.Ang (Ua-Ub) Phase angle between phase A and phase B voltages deg

15 x.Ang (Ub-Uc) Phase angle between phase B and phase C voltages deg

16 x.Ang (Uc-Ua) Phase angle between phase C and phase A voltages deg
5
5.2.3 Sequence Components Values

No. Item Definition Unit

1 x.I1_Pri Positive sequence primary current A

2 x.I2_Pri Negative sequence primary current A

3 x.3I0_Cal_Pri Calculated residual primary current A

4 x.U1_Pri Positive sequence primary voltage kV

5 x.U2_Pri Negative sequence primary voltage kV

6 x.3U0_Cal_Pri Calculated residual primary voltage kV

5.2.4 Power Values

No. Item Definition Unit

1 x.Pa_Pri Phase A primary active power MW

2 x.Pb_Pri Phase B primary active power MW

3 x.Pc_Pri Phase C primary active power MW

4 x.Qa_Pri Phase A primary reactive power MVAr

5 x.Qb_Pri Phase B primary reactive power MVAr

6 x.Qc_Pri Phase C primary reactive power MVAr

7 x.Sa_Pri Phase A primary apparent power MVA

8 x.Sb_Pri Phase B primary apparent power MVA

9 x.Sc_Pri Phase C primary apparent power MVA

10 x.P_Pri Primary active power MW

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5 Measurement

No. Item Definition Unit

11 x.Q_Pri Primary reactive power MVAr

12 x.S_Pri Primary apparent power MVA

13 x.Cosa Phase A primary power factor -

14 x.Cosb Phase B primary power factor -

15 x.Cosc Phase C primary power factor -

16 x.Cos Primary power factor -

5.2.5 DCAI Values

Please find these values in Table 5.6-2 Output signals of DC measuring transducers.

5.3 Secondary Values

Access path: MainMenu  “Measurements”  “Secondary Values”

5.3.1 General Values


5
No. Item Definition Unit

1 x.Ia_Sec Phase A secondary current A

2 x.Ib_Sec Phase B secondary current A

3 x.Ic_Sec Phase C secondary current A

4 x.Neu.3I0_Ext_Sec External residual secondary current A

5 x.Ua_Sec Phase A secondary voltage V

6 x.Ub_Sec Phase B secondary voltage V

7 x.Uc_Sec Phase C secondary voltage V

8 x.Uab_Sec Phase AB secondary voltage V

9 x.Ubc_Sec Phase BC secondary voltage V

10 x.Uca_Sec Phase CA secondary voltage V

11 x.Neu.U_Sec Residual secondary voltage V

5.3.2 Angle Values

No. Item Definition Unit

1 x.Ang(Ia) Phase angle of phase A current deg

2 x.Ang(Ib) Phase angle of phase B current deg

3 x.Ang(Ic) Phase angle of phase C current deg

4 x.Ang(3I0_Cal) Phase angle of calculated residual current deg

5 x.Neu.Ang(3I0_Ext) Phase angel of external neutral-point residual current deg

6 x.Ang(Ua) Phase angle of phase A voltage deg

PCS-978S Transformer Relay 5-3


Date: 2022-01-17
5 Measurement

No. Item Definition Unit

7 x.Ang(Ub) Phase angle of phase B voltage deg

8 x.Ang(Uc) Phase angle of phase C voltage deg

9 x.Ang(3U0_Cal) Phase angle of calculated residual voltage deg

Phase angle of neutral-point residual voltage or phase-to-phase


10 x.Neu.Ang(U) deg
voltage

11 x.Ang (Ia-Ib) Phase angle between phase A and phase B currents deg

12 x.Ang (Ib-Ic) Phase angle between phase B and phase C currents deg

13 x.Ang (Ic-Ia) Phase angle between phase C and phase A currents deg

14 x.Ang (Ua-Ub) Phase angle between phase A and phase B voltages deg

15 x.Ang (Ub-Uc) Phase angle between phase B and phase C voltages deg

16 x.Ang (Uc-Ua) Phase angle between phase C and phase A voltages deg

5.3.3 Sequence Components Values

No. Item Definition Unit

5 1 x.I1_Sec Positive sequence secondary current A

2 x.I2_Sec Negative sequence secondary current A

3 x.3I0_Cal_Sec Calculated residual secondary current A

4 x.U1_Sec Positive sequence secondary voltage kV

5 x.U2_Sec Negative sequence secondary voltage kV

6 x.3U0_Cal_Sec Calculated residual secondary voltage kV

5.3.4 Power Values

No. Item Definition Unit

1 x.Pa_Sec Phase A secondary active power MW

2 x.Pb_Sec Phase B secondary active power MW

3 x.Pc_Sec Phase C secondary active power MW

4 x.Qa_Sec Phase A secondary reactive power MVAr

5 x.Qb_Sec Phase B secondary reactive power MVAr

6 x.Qc_Sec Phase C secondary reactive power MVAr

7 x.Sa_Sec Phase A secondary apparent power MVA

8 x.Sb_Sec Phase B secondary apparent power MVA

9 x.Sc_Sec Phase C secondary apparent power MVA

10 x.P_Sec Secondary active power MW

11 x.Q_Sec Secondary reactive power MVAr

12 x.S_Sec Secondary apparent power MVA

13 x.Cosa Phase A secondary power factor -

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5 Measurement

No. Item Definition Unit

14 x.Cosb Phase B secondary power factor -

15 x.Cosc Phase C secondary power factor -

16 x.Cos Secondary power factor -

5.3.5 DCAI Values

Please find these values in Table 5.6-2 Output signals of DC measuring transducers.

5.4 Function Values

Access path: MainMenu  “Measurements”  “Function Values”

5.4.1 Sum Values

No. Item Definition Unit

1 x.Sum.Ia_Sec Sum (secondary value) of phase A currents A

2 x.Sum.Ib_Sec Sum (secondary value) of phase B currents A


5
3 x.Sum.Ic_Sec Sum (secondary value) of phase C currents A

4 x.Sum.I1_Sec Sum (secondary value) of positive-sequence currents A

5 x.Sum.I2_Sec Sum (secondary value) of negative-sequence currents A

6 x.Sum.3I0_Cal_Sec Sum (secondary value) of calculated residual currents A

7 x.Sum.Ang(Ia) Phase angle of the sum of phase A currents deg

8 x.Sum.Ang(Ib) Phase angle of the sum of phase B currents deg

9 x.Sum.Ang(Ic) Phase angle of the sum of phase C currents deg

Phase angle between of phase-A sum current and phase-B sum


10 x.Sum.Ang(Ia-Ib) deg
current

Phase angle between of phase-B sum current and phase-C sum


11 x.Sum.Ang(Ib-Ic) deg
current

Phase angle between of phase-C sum current and phase-A sum


12 x.Sum.Ang(Ic-Ia) deg
current

5.4.2 Angle Values

No. Item Definition Unit

1 x.Ang(Ua-Ia) Phase angle between phase A voltage and current deg

2 x.Ang(Ub-Ib) Phase angle between phase B voltage and current deg

3 x.Ang(Uc-Ic) Phase angle between phase C voltage and current deg

PCS-978S Transformer Relay 5-5


Date: 2022-01-17
5 Measurement

5.4.3 OvExc Values

No. Item Definition Unit

1 f System frequency Hz

2 U/f Overexcitation multiple of definite-time overexcitation protection. /

Thermal state of inverse-time overexcitation protection. When the


3 24IDMT.ThermAccu %
value is “100%”, inverse-time overexcitation protection operates.

5.4.4 Diff Values

No. Item Definition Unit

1 87T.Ida Phase-A differential current of transformer differential protection. p.u.

2 87T.Idb Phase-B differential current of transformer differential protection. p.u.

3 87T.Idc Phase-C differential current of transformer differential protection. p.u.

4 87T.Ira Phase-A restraint current of transformer differential protection. p.u.

5 87T.Irb Phase-B restraint current of transformer differential protection. p.u.

6 87T.Irc Phase-C restraint current of transformer differential protection. p.u.

5 7 87T.Ia_Th
Threshold value of phase-A restraint current of transformer
p.u.
differential protection.

Threshold value of phase-B restraint current of transformer


8 87T.Ib_Th p.u.
differential protection.

Threshold value of phase-C restraint current of transformer


9 87T.Ic_Th p.u.
differential protection.

Phase-A corrected current of branch m (m= 1, 2, 3, 4, 5, 6) for


10 87T.Ia_Cr_Brm p.u.
differential protection of transformer differential protection.

Phase-B corrected current of branch m (m= 1, 2, 3, 4, 5, 6) for


11 87T.Ib_Cr_Brm p.u.
differential protection of transformer differential protection.

Phase-C corrected current of branch m (m= 1, 2, 3, 4, 5, 6) for


12 87T.Ic_Cr_Brm p.u.
differential protection of transformer differential protection.

Angle between phase-A currents of branch 1 and branch m (m= 2, 3,


13 87T.Ang(Ia)_Br1-Brm deg
4, 5, 6) of transformer differential protection.

Angle between phase-B currents of branch 1 and branch m (m= 2, 3,


14 87T.Ang(Ib)_Br1-Brm deg
4, 5, 6) of transformer differential protection.

Angle between phase-C currents of branch 1 and branch m (m= 2, 3,


15 87T.Ang(Ic)_Br1-Brm deg
4, 5, 6) of transformer differential protection.

Phase-A second harmonic percentage of total differential current of


16 87T.Ida_Hm2_Pcnt %
transformer differential protection.

Phase-B second harmonic percentage of total differential current of


17 87T.Idb_Hm2_Pcnt %
transformer differential protection.

Phase-C second harmonic percentage of total differential current of


18 87T.Idc_Hm2_Pcnt %
transformer differential protection.

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5 Measurement

No. Item Definition Unit

Phase-A third harmonic percentage of total differential current of


19 87T.Ida_Hm3_Pcnt %
transformer differential protection.

Phase-B third harmonic percentage of total differential current of


20 87T.Idb_Hm3_Pcnt %
transformer differential protection.

Phase-C third harmonic percentage of total differential current of


21 87T.Idc_Hm3_Pcnt %
transformer differential protection.

Phase-A fifth harmonic percentage of total differential current of


22 87T.Ida_Hm5_Pcnt %
transformer differential protection.

Phase-B fifth harmonic percentage of total differential current of


23 87T.Idb_Hm5_Pcnt %
transformer differential protection.

Phase-C fifth harmonic percentage of total differential current of


24 87T.Idc_Hm5_Pcnt %
transformer differential protection.

Reference current of branch m (m=1, 2, 3, 4, 5, 6) of transformer


25 87T.Ib_Brm A
differential protection.

26 87R.Ida Phase-A differential current of reactor differential protection. p.u.

27 87R.Idb Phase-B differential current of reactor differential protection. p.u. 5


28 87R.Idc Phase-C differential current of reactor differential protection. p.u.

29 87R.3I0d Zero-sequence differential current of reactor differential protection. p.u.

30 87R.Ira Phase-A restraint current of reactor differential protection. p.u.

31 87R.Irb Phase-B restraint current of reactor differential protection. p.u.

32 87R.Irc Phase-C restraint current of reactor differential protection. p.u.

33 87R.3I0r Zero-sequence restraint current of reactor differential protection. p.u.

Threshold value of phase-A restraint current of reactor differential


34 87R.Ia_Th p.u.
protection.

Threshold value of phase-B restraint current of reactor differential


35 87R.Ib_Th p.u.
protection.

Threshold value of phase-C restraint current of reactor differential


36 87R.Ic_Th p.u.
protection.

Threshold value of calculated residual restraint current of reactor


37 87R.3I0_Th p.u.
differential protection.

Corrected values of phase-A current of branch m (m= 1, 2, 3) of


38 87R.Ia_Cr_Brm p.u.
reactor differential protection.

Corrected values of phase-B current of branch m (m= 1, 2, 3) of


39 87R.Ib_Cr_Brm p.u.
reactor differential protection.

Corrected values of phase-C current of branch m (m= 1, 2, 3) of


40 87R.Ic_Cr_Brm p.u.
reactor differential protection.

Corrected values of calculated residual current of branch m (m= 1, 2,


41 87R.3I0_Cr_Brm p.u.
3) of reactor differential protection.

PCS-978S Transformer Relay 5-7


Date: 2022-01-17
5 Measurement

No. Item Definition Unit

Second harmonic percentage of phase-A differential current of


42 87R.Ida_Hm2_Pcnt %
reactor differential protection.

Second harmonic percentage of phase-B differential current of


43 87R.Idb_Hm2_Pcnt %
reactor differential protection.

Second harmonic percentage of phase-C differential current of


44 87R.Idc_Hm2_Pcnt %
reactor differential protection.

Third harmonic percentage of phase-A differential current of reactor


45 87R.Ida_Hm3_Pcnt %
differential protection.

Third harmonic percentage of phase-B differential current of reactor


46 87R.Idb_Hm3_Pcnt %
differential protection.

Third harmonic percentage of phase-C differential current of reactor


47 87R.Idc_Hm3_Pcnt %
differential protection.

Phase angles of phase-A current between branch 1 and branch m


48 87R.Ang(Ia)_Br1-Brm deg
(m= 2, 3) of reactor differential protection.

Phase angles of phase-B current between branch 1 and branch m


49 87R.Ang(Ib)_Br1-Brm deg
5 (m= 2, 3) of reactor differential protection.

Phase angles of phase-C current between branch 1 and branch m


50 87R.Ang(Ic)_Br1-Brm deg
(m= 2, 3) of reactor differential protection.

Phase angles of calculated residual current between branch 1 and


51 87R.Ang(3I0)_Br1-Brm deg
branch m (m= 2, 3) of reactor differential protection.

Reference current of branch m (m=1, 2, 3) of reactor differential


52 87R.Ib_Brm A
protection.

5.4.5 REF Values

No. Item Definition Unit

1 x.64REF.3I0d Residual differential current of x side REF protection. In

2 x.64REF.3I0r Residual restraint current of x side REF protection. In

3 x.64REF.3I0_Th Threshold of residual restraint current of x side REF protection. In

Corrected calculated residual current for branch m of x side REF


4 x.64REF.3I0_Cr_Brm In
protection (m=1, 2, 3, 4).

5 x.64REF.3I0_Cr_NP Corrected residual current from neutral CT of x side REF protection. In

Angle of calculated residual current between branch 1 and branch m


6 x.64REF.Ang(3I0)_Br1-Brm deg
of x side REF protection (m=2, 3, 4).

Angle between calculated residual current of branch 1 and current


7 x.64REF.Ang(3I0)_Br1-NP deg
from neutral CT of x side REF protection.

Corrected coefficient of current for branch m of x side REF protection


8 x.64REF.K_Brm /
(m=1, 2, 3, 4).

9 x. 64REF.K_NP Corrected coefficient of current from neutral CT of x side REF /

5-8 PCS-978S Transformer Relay

Date: 2022-01-17
5 Measurement

No. Item Definition Unit

protection

5.4.6 WdgDiff Values

No. Item Definition Unit

1 87W.Ida Phase-A differential current of winding differential protection. In

2 87W.Idb Phase-B differential current of winding differential protection. In

3 87W.Idc Phase-C differential current of winding differential protection. In

4 87W.3I0d Residual differential current of winding differential protection. In

5 87W.Ira Phase-A restraint current of winding differential protection. In

6 87W.Irb Phase-B restraint current of winding differential protection. In

7 87W.Irc Phase-C restraint current of winding differential protection. In

8 87W.3I0r Residual restraint current of winding differential protection. In

Threshold of phase-A restraint current of winding differential


9 87W.Ia_Th In
protection.

10 87W.Ib_Th
Threshold of phase-B restraint current of winding differential
protection.
In 5
Threshold of phase-C restraint current of winding differential
11 87W.Ic_Th In
protection.

Threshold of residual restraint current of winding differential


12 87W.3I0_Th In
protection.

Phase-A corrected current of branch m (m= 1,2, 3, 4, 5) for winding


13 87W.Ia_Cr_Brm In
differential protection.

Phase-B corrected current of branch m (m= 1,2, 3, 4, 5) for winding


14 87W.Ib_Cr_Brm In
differential protection.

Phase-C corrected current of branch m (m= 1,2, 3, 4, 5) for winding


15 87W.Ic_Cr_Brm In
differential protection.

Corrected calculated residual current for branch m (m=1, 2, 3, 4, 5)


16 87W.3I0_Cr_Brm In
of winding differential protection.

Angle between phase-A currents of branch 1 and branch m (m= 2, 3,


17 87W.Ang(Ia)_Br1-Brm deg
4, 5) of winding differential protection.

Angle between phase-B currents of branch 1 and branch m (m= 2, 3,


18 87W.Ang(Ib)_Br1-Brm deg
4, 5) of winding differential protection.

Angle between phase-C currents of branch 1 and branch m (m= 2, 3,


19 87W.Ang(Ic)_Br1-Brm deg
4, 5) of winding differential protection.

Angle between calculated residual current of branch 1 and branch m


20 87W.Ang(3I0)_Br1-Brm deg
(m= 2, 3, 4, 5) of winding differential protection.

Corrected coefficient of current for branch m of winding differential


21 87W.K_Brm /
protection. (m=1, 2, 3, 4, 5).

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5 Measurement

5.4.7 ThOvLd Values

No. Item Definition Unit

Phase A thermal state of thermal overload protection. When the


1 x.49.Accu_A %
value is “1”, thermal overload protection operates.

Phase B thermal state of thermal overload protection. When the


2 x.49.Accu_B %
value is “1”, thermal overload protection operates.

Phase C thermal state of thermal overload protection. When the


3 x.49.Accu_C %
value is “1”, thermal overload protection operates.

The calculated temperature difference of phase A between winding


4 x.49.T_Diff_A ℃
temperature and oil temperature.

The calculated temperature difference of phase B between winding


5 x.49.T_Diff_B ℃
temperature and oil temperature.

The calculated temperature difference of phase C between winding


6 x.49.T_Diff_C ℃
temperature and oil temperature.

5.4.8 Synchronism Check


5 No. Item Definition Unit

1 25.U_Ref_Sec Secondary voltage of reference side V

2 25.U_Ref_Pri Primary voltage of reference side kV

3 25.f_Ref Frequency of reference side Hz

4 25.U_Syn_Sec Secondary voltage of synchronization side V

5 25.U_Syn_Pri Primary voltage of synchronization side kV

6 25.f_Syn Synchronization side frequency Hz

7 25.U_Diff_Sec Secondary voltage difference for CB synchronism check V

8 25.U_Diff_Pri Primary voltage difference for CB synchronism check kV

9 25.phi_Diff Phase angle difference for CB synchronism check deg

10 25.f_Diff Frequency difference for CB synchronism check Hz

11 25.df/dt Frequency variation difference for CB synchronism check Hz/s

12 25.RSYN_OK Synchronism check is passed. -

13 25.SynChk_OK Synchro-check is passed. -

14 25.DdChk_OK Dead charge check is passed. -

15 25.U_Diff_OK Voltage difference criteria is satisfied. -

16 25.f_Diff_OK Frequency difference criteria is satisfied. -

17 25.df/dt_OK Voltage variation difference criteria is satisfied. -

18 25.phi_Diff_OK Phase difference criteria is satisfied. -

19 25.RefDd Dead check of reference side is passed. -

20 25.RefLv Live check of reference side is passed. -

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No. Item Definition Unit

21 25.SynDd Dead check of synchronization side is passed. -

22 25.SynLv Live check of synchronization side is passed. -

5.5 Energy Metering

Access path: MainMenu  “Measurements”  “Energy Metering”

No. Item Definition Unit

1 x.MMTR.EA_Accu_Fwd Positive active energy kWh

2 x.MMTR.EA_Accu_Rev Negative active energy kWh

3 x.MMTR.ER_Accu_Fwd Positive reactive energy kVArh

4 x.MMTR.ER_Accu_Rev Negative reactive energy kVArh

5 x.MMTR.EA_Accu_Fwd_Y Positive active energy for phase Y (Y=A, B, C) kWh

6 x.MMTR.EA_Accu_Rev_Y Negative active energy for phase Y (Y=A, B, C) kWh

7 x.MMTR.ER_Accu_Fwd_Y Positive reactive energy for phase Y (Y=A, B, C) kVArh

8 x.MMTR.ER_Accu_Rev_Y Negative reactive energy for phase Y (Y=A, B, C) kVArh 5


5.6 DC Measuring Transducers

The DC measuring transducer with an input rated at 0~±20mA or 0~±10V is optional in this device.
8 or 12 (depending on the subtype) inputs are available in one DC AI module, which can be
plugged into a plug-in module slot. Typically, slowly changing process variable such as
temperature or gas pressure are measured by such transducers.

5.6.1 Function Description

A DC measuring transducer input typically converts a value which represents a physical quantity
such as temperature or pressure. Therefore, a characteristic curve that assigns the physical
quantity to the DC analogue value is necessary. The following figure shows an example.

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5 Measurement

Temperature (⁰C)

Tmax

P
Tmin Tp
ITransd (mA)

O ip 20

Figure 5.6-1 Characteristic curve of a DC measuring transducer input

In this example, the setting of the range for the scaled value goes from a usable range of 0mA to
+20mA. The measured value 0mA means a temperature of Tmin which is defined by the setting
[B**.DCAI.Min_Transducer**] and the measured value 20mA signifies a temperature of Tmax
which is defined by the setting [B**.DCAI.Max_Transducer**]. Thus, for the actual point P, the
5 measured transducer current ip can be converted into a value of temperature.

5.6.2 I/O Signals

Table 5.6-1 Input signals of DC measuring transducers

No. Input Signal Description


1 B**.Enable Function enabling input
2 B**.Block Function blocking input
3 in_dc** Input value of DC measuring transducer channel **

Table 5.6-2 Output signals of DC measuring transducers

No. Output Signal Description


Access path: Main Menu  “Measurements”  “Primary Values” 
1 B**.DCAI.Input**_Pri “DCAI_Values”
Converted value (physical quantity) of DC measuring transducer channel **
Access path: Main Menu  “Measurements”  “Secondary Values” 
2 B**.DCAI.Input**_Sec “DCAI_Values”
Mearsured value (0~±20mA or 0~±10Vdc) of DC measuring transducer channel **

5.6.3 Settings
Table 5.6-3 Settings of DC measuring transducers

No. Setting Range Unit Default Description


Selection of DC analog
0~10V
1 B**.DCAI.Opt_Type_Transducer** - 0~20mA input type
0~20mA
Please refer to the

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No. Setting Range Unit Default Description


corresponding jumper
of DC AI module to
realize the selection.
The minimal converted
2 B**.DCAI.Min_Transducer** -60000.000~60000.000 - 0.000 value (physical
quantity)
The maximal converted
3 B**.DCAI.Max_Transducer** -60000.000~60000.000 - 250.00 value (physical
quantity)

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6 Supervision

6 Supervision

Table of Contents

6.1 Overview ........................................................................................................... 6-1


6.2 Device Hardware Supervision ........................................................................ 6-1
6.2.1 Hardware Resource Consumption Supervision ................................................................... 6-2

6.2.2 Hardware Status Supervision ............................................................................................... 6-2

6.2.3 Hardware Configuration Supervision ................................................................................... 6-3

6.2.4 Device Firmware Supervision .............................................................................................. 6-3

6.2.5 CPU Process and Module Supervision ................................................................................ 6-3

6.3 Analog Input Supervision ............................................................................... 6-3


6.4 Secondary Circuit Supervision....................................................................... 6-4
6.5 CT Circuit Supervision (CTS).......................................................................... 6-4
6.6 VT Circuit Supervision (VTS) .......................................................................... 6-4
6.6.1 Function Description............................................................................................................. 6-4
6
6.6.2 Function Block ...................................................................................................................... 6-5

6.6.3 I/O Signals ............................................................................................................................ 6-5

6.6.4 Logic ..................................................................................................................................... 6-6

6.6.5 Settings ................................................................................................................................. 6-7

6.7 Binary Input Supervision ................................................................................ 6-7


6.7.1 Debounce Time .................................................................................................................... 6-7

6.7.2 Jitter Processing ................................................................................................................... 6-9

6.7.3 High-Power Conducting Mode ........................................................................................... 6-11

6.8 Switchgear Trip Counter ............................................................................... 6-12


6.9 Supervision Alarms and Handling Suggestion ........................................... 6-12

List of Figures

Figure 6.6-1 VT circuit supervision logic diagram ................................................................. 6-6

Figure 6.7-1 Sequence chart of debounce technique ........................................................... 6-8

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Figure 6.7-2 Debounce time configuration page.................................................................... 6-8

Figure 6.7-3 Sequence chart of jitter processing................................................................. 6-10

Figure 6.7-4 High-power conducting mode .......................................................................... 6-12

List of Tables

Table 6.6-1 Input signals of VT circuit supervision ............................................................... 6-5

Table 6.6-2 Output signals of VT circuit supervision ............................................................ 6-6

Table 6.6-3 Settings of VT circuit supervision ....................................................................... 6-7

Table 6.9-1 Alarm description................................................................................................... 6-13

Table 6.9-2 Troubleshooting..................................................................................................... 6-21

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6.1 Overview

Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before
the LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore,
the automatic supervision function, which checks the health of the protection system when startup
and during normal operation, plays an important role.

The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.

In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.

When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.

6.2 Device Hardware Supervision

All hardware has real-time monitoring functions, such as CPU module monitoring, communication
interface status monitoring, power supply status monitoring. 6
The monitoring function of CPU module also includes processor self-check, memory self-check
and so on. The processor self-check is checked by designing execution instructions and data
operations. Check whether the processor can execute all instructions correctly, and whether it can
correctly calculate complex data operations to determine whether it works normally. For
peripherals, it can monitor the status of the interface module, check the input and output data,
send the communication interface and receive self-loop detection. Memory self-check is used to
detect unexpected memory errors in the running process. It can effectively prevent program logic
abnormality caused by memory errors.

The status monitoring of communication interface also includes Ethernet communication interface
monitoring and differential channel communication interface monitoring. By accessing the status
register of the communication interface, the state of the corresponding interface is obtained, such
as the state of connection, the number of sending frames, the number of frames received, and the
number of wrong frames. According to the statistics of the acquired interface state, it is judged
whether the interface work is abnormal.

The hardware supervision also includes the power supply status monitoring. The voltage
monitoring chip is used by all the power supplies. The reset voltage threshold is preset to the reset
monitoring circuit. When the power supply is abnormal, the voltage monitoring chip will output the
reset signal to control CPU to be in the reset state and avoid the wrong operation.

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6.2.1 Hardware Resource Consumption Supervision


1. Logic component total execution time monitoring

In the process of operation, the safety allowance should always be kept and no overload
phenomenon is allowed. When the user configures logic components with PCS-Studio, the
PCS-Studio automatically calculates the time required for the theoretical execution of the
configured components. When the security limit is exceeded, the PCS-Studio will indicate that the
configuration error is not allowed to download the current configuration to the device.

2. Module data exchange monitoring

During the operation of the device, there is a lot of data exchange between modules. The number
of data exchanges is related to the number of logical components configured by the user. When
the configuration is too large to cause the number of data exchange to exceed the upper limit
supported by the device, the PCS-Studio prompts the configuration error.

3. Configuration file size monitoring

The initialization of the device depends on the configuration files of each module. The user
configured logical components will eventually be embodied in the configuration file, limited to the
hardware memory space. When the configuration file size is more than the upper limit, the
PCS-Studio prompts the configuration error.

6.2.2 Hardware Status Supervision


6 1. Memory ECC and parity functions.

The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate
unexpected changes in memory caused by electromagnetic interference. The chip memory has
parity function. When an error occurs, the system can detect anomalies immediately, and
eliminate the logic abnormity caused by memory errors.

2. Memory error monitoring in code area and constant data area

In addition to the above hardware memory reliability measures, the device software is also
constantly checking the memory during operation, including code, constant data, and so on. Once
the error detection, the system will automatically restart the restore operation. If they detect the
error immediately after the restart, it may be the result of a permanent fault locking device
hardware, only at the moment and not restart.

3. Binary output relay drive monitoring

The reliability of the device is largely determined by the reliability of the export drive. By reading
the driving state of the binary output relay, the alarm signal will be generated and the device is
immediately blocked to prevent the relay from maloperation when the device is not given a
tripping order and the binary output relay driver is detected in the effective state.

4. CPU temperature monitoring

The CPU chip needs to be able to ensure long-term stability under the permissible working
temperature of the specification. Therefore, it is necessary to monitor the working temperature

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monitored by CPU.

6.2.3 Hardware Configuration Supervision

The device is blocked when the actual hardware configuration is not consistent with the hardware
configuration file. Compared with pre configured modules, this device will be blocked if more
module is inserted, fewer module is inserted, and wrong modules is inserted.

6.2.4 Device Firmware Supervision

1. Each hardware module configuration check code needs to be consistent with CPU module.

The device CPU module stores the configuration check codes of other modules. In initialization
procedure, it checks whether the configuration check code of each module is consistent with the
stored code in CPU module, and if it is not consistent, this device is blocked.

2. The hardware modules and process interface versions need to be consistent with the CPU
module.

If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this
moment, each hardware module and process will be upgraded synchronously, otherwise the
version of the interface will be inconsistent.

3. Configuration text is correct.

The configuration text formed by the device calibration visualization project includes checking
whether the check code is wrong or not. 6
4. Whether any setting is over the range, whether it needs to confirm the settings.

If the setting exceeds the configuration range, the device is blocked; if some settings are added, it
is necessary to confirm the new values through the LCD.

6.2.5 CPU Process and Module Supervision


1. Monitor the heartbeat of the module.

In the operation procedure, the CPU module sends a time synchronization command to other
module, each module repeats heartbeat message to the CPU module, if it does not respond or the
heartbeat is abnormal, then this device is blocked.

2. Check whether the settings of other modules are consistent with the CPU module.

The actual values of all the settings in the CPU module are initialized to send to the corresponding
slave modules. In the process of operation, the setting values stored in the CPU module and the
setting values of other modules will be checked one by one. If they are not consistent, this device
will issue the alarm signal "Fail_Settings".

6.3 Analog Input Supervision

The sampling circuit of this device is designed as dual-design scheme. Each analog sampling

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channel is sampled by two groups of ADC. The sampling data is self checking and inter checking
in real time. If any sampling circuit is abnormal, the device reports the alarm signal "Alm_Sample",
and the protection function related to the sampling channel is disabled at the same time. When
the sampling circuit returns to normal state, the related protection is not blocked after 10s.

6.4 Secondary Circuit Supervision

The secondary circuit supervision function includes current transformer supervision (CTS),
voltage transformer supervision (VTS), power supply supervision of binary inputs and
tripping/closing circuit supervision.

6.5 CT Circuit Supervision (CTS)

The purpose of the CTS is to detect whether the current transformer circuit is failed. In some
cases, if the CT is failed (broken-conductor, short-circuit), related protective element should be
blocked for preventing this device from mal-operation.

The CT circuit supervision function is integrated in the protection elements related to current
calculation, such as, 87T, 87W, 64REF, 87R, etc., there is no independent CT circuit supervision
element, so please refer to the corresponding protection in Chapter 3 for the details about the
CTS.

6
6.6 VT Circuit Supervision (VTS)

The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when measurement from VT circuit fails.

VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.

1. The VT is used as protection VT and the protected component is out of service.

2. Only current protection functions are enabled and VT is not connected to the device.

3. The specific current protection has picked up before the satisfaction of conditions of VT circuit
failure alarm.

6.6.1 Function Description


VT circuit supervision can detect failure of single-phase, two-phase and three-phase on VT. Under
normal condition, the device continuously supervises input voltage from VT. The VT circuit failure
alarm will be issued with configurable time delay if residual voltage exceeds or negative sequence
voltage exceeds the threshold value or positive-sequence voltage is less than the threshold value.
If a specific current protection (breaker failure protection for this device) operates to pick up, the

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time delay count-down will be paused until the protection returns to normal state.

Under normal conditions, the device detects residual voltage that is greater than the setting
[x.VTS.3U0_Set] or negative-sequence voltage that is greater than the setting [x.VTS.U2_Set] to
distinguish a single-phase or two-phase VT circuit failure, and detects positive-sequence voltage
that is less than the setting [x.VTS.U1_Set] to distinguish a three-phase VT circuit failure. Upon
detecting abnormality on VT circuit, an alarm will come up after a time delay of [x.VTS.t_DPU] and
drop-off with a time delay of [x.VTS.t_DDO] after that VT is restored to normal. Upon abnormality
detection on VT circuit, an instant alarm will be issued after a time delay of 25ms and drop-off
without time delay.

VT (secondary circuit) MCB auxiliary contact can be connected to the binary input circuit of the
device as a binary signal. If the MCB has been opened (i.e. [x.VTS.MCB_VT] is energized), the
device will consider that the VT circuit is in a bad condition and issue an alarm without a time
delay. If the auxiliary contact is not connected to the device, VT circuit supervision will be issued
with time delay as mentioned in previous paragraph.

When VT is not connected into the device, the alarm shall be not issued if the logic setting
[x.En_VT] is set as "Disabled". However, the alarm is still issued if the binary input
[x.VTS.MCB_VT] is energized, no matter that the logic setting [x.En_VT] is set as "Disabled" or
"Enabled".

6.6.2 Function Block

VTS 6
x.VTS.in_U3P x.VTS.InstAlm

x.VTS.in_I3P

x.VTS.Enable

x.VTS.Block

x.VTS.MCB_VT

x.VTS.in_52b_a

x.VTS.in_52b_b

x.VTS.in_52b_b

6.6.3 I/O Signals


Table 6.6-1 Input signals of VT circuit supervision

No. Input Signal Description


1 x.VTS.in_U3P Three-phase voltage data input
2 x.VTS.in_I3P Three-phase current data input
3 x.VTS.Enable VT circuit supervision enabling input
4 x.VTS.Block VT circuit supervision blocking input

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5 x.VTS.MCB_VT Binary input for VT MCB auxiliary contact


6 x.VTS.in_52b_a Binary input of auxiliary normally open contact of phase-A circuit breaker
7 x.VTS.in_52b_b Binary input of auxiliary normally open contact of phase-B circuit breaker
8 x.VTS.in_52b_c Binary input of auxiliary normally open contact of phase-C circuit breaker

Table 6.6-2 Output signals of VT circuit supervision

No. Output Signal Description


1 x.VTS.InstAlm Instantaneous alarm signal to indicate VT circuit fails

6.6.4 Logic

SIG Pickup of specific current prot.

SET x.3U0>[x.VTS.3U0_Set]
>=1
SET x.U2>[x.VTS.U2_Set]

SET x.U1<[x.VTS.U1_Set] &


>=1 If specific current prot. picks up, the
time delay count-down will be paused.
SET [x.VTS.Opt_VT]=Bay &
[x.VTS.t_DPU] [x.VTS.t_DDO] &
SIG 52b (three phase) >=1

SIG x.Ip > 0.04In >=1

[x.En_VT]
&
EN x.VTS.Alm

BI x.VTS.MCB_VT

EN [x.VTS.En]
&
x.VTS.Enable

6
SIG

SIG x.VTS.Block

Figure 6.6-1 VT circuit supervision logic diagram

SIG Pickup of specific current prot.

SET x.3U0>[x.VTS.3U0_Set]
>=1
SET x.U2>[x.VTS.U2_Set]

SET x.U1<[x.VTS.U1_Set] &


>=1 If specific current prot. picks up, the
time delay count-down will be paused.
SET [x.VTS.Opt_VT]=Bay &
[25ms] [0ms] &
SIG 52b (three phase) >=1

SIG x.Ip > 0.04In >=1

[x.En_VT]
&
EN x.VTS.InstAlm

BI x.VTS.MCB_VT

EN [x.VTS.En]
&
SIG x.VTS.Enable
SIG x.VTS.Block

Figure 6.6-2 Instantaneous VT circuit supervision logic diagram

Where:

x.VTS.Alm is the output signal of three-phase voltage element (TVOL3P), as shown in Section

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3.2.3.

x.Ip is any measured single-phase current.

In is the rated phase current value.

In this device, the specific current protection includes phase overcurrent protection, earth fault
protection, current differential protection and breaker failure protection.

 If the specific protection picks up firstly and then an abnormality on VT circuit is detected. The
VT circuit failure alarm should not be issued before the specific protection returns to normal
state.

 If an abnormality on VT circuit is detected firstly and then the specific protection operates to
pick up. The time delay count-down of VT circuit failure alarm shall be paused until the
protection return to normal state.

 If the specific protection operates and VT circuit failure alarm has been issued, the alarm will
be maintained.

6.6.5 Settings
Table 6.6-3 Settings of VT circuit supervision

No. Name Range Unit Default Description


Disabled
1 x.VTS.En - Enabled Enabling/disabling VY circuit supervision
Enabled
Voltage selection for protection calculation from
6
Bus busbar VT or bay VT
2 x.VTS.Opt_VT - Bus
Bay Bus: busbar VT
Bay: bay VT
3 x.VTS.t_DPU 0.000~30.000 s 1.500 Pickup time delay of VT circuit supervision
4 x.VTS.t_DDO 0.000~30.000 s 10.000 Dropoff time delay of VT circuit supervision
Positive-sequence voltage setting of VT circuit
5 x.VTS.U1_Set 0.00~100.00 V 30.00
supervision
Zero-sequence voltage setting of VT circuit
6 x.VTS.3U0_Set 0.00~100.00 V 8.00
supervision
Negative-sequence voltage setting of VT circuit
7 x.VTS.U2_Set 0.00~100.00 V 8.00
supervision function

6.7 Binary Input Supervision

6.7.1 Debounce Time

The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.7-1.

All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When

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the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the
binary input will be validated and wrote into SOE.

Binary input
state

SOE report SOE report


timestamps timestamps
Validated binary input Validated binary input
state changes state changes
1

Debounce time of Debounce time of


delayed pickup delayed dropout
Time

Figure 6.7-1 Sequence chart of debounce technique

In order to meet flexible configurable requirement for different project field, all binary inputs
provided by the device are configurable. Through the configuration tool, this device provides two
parameters to setup debounce time of delayed pickup and dropout based on specific binary
signal.

Figure 6.7-2 Debounce time configuration page

The configurable binary signals can be classified as follows:

1. Type 1

This type of binary inputs includes enable/disable of protection functions, “BI_RstTarg”,


“BI_Maintenance”, disconnector position, settings group switch, open and close command of
circuit breaker and disconnector, enable/disable of auxiliary functions (for example, manually
trigger recording). It is on the premise of reliability, and the debounce time of delayed pickup
and delayed dropout is recommended to set as 100ms at least.

2. Type 2

This type of binary inputs includes “CSWI**.Cmd_LocCtrl”, “CSWI**.Cmd_RmtCtrl”, etc.

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Debounce time

BI Input Signal.X1 t1 t2 &


Time delay Output
SIG Operation condition

 Time delay is equal to 0

The debounce time of delayed pickup and delayed dropout is recommended to set as
15ms, in order to prevent binary signals from maloperation due to mixed connection of
AC system and DC system.

 Time delay is not equal to 0

The debounce time of delayed pickup and delayed dropout is recommended to set as
(-t1+ t2+Time delay)≥15ms, in order to prevent binary signals from maloperation due to
mixed connection of AC system and DC system. Where, “t1” is the debounce time of
delayed pickup, and “t2” is the debounce time of delayed dropout.

3. Type 3

This type of binary inputs is usually used as auxiliary input condition, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 5ms.

6
When users have their own reasonable setting principles, they can set the
debounce time related settings according to their own setting principles.

6.7.2 Jitter Processing


This device can handle repetitive signal or so-called jitter via binary input module with the following
settings:

[Mon_Window_Jitter] T, monitoring window of binary input jitter processing

[Num_Blk_Jitter] N, times threshold to block binary input status change due to jitter

[Blk_Window_Jitter] T’, blocking window of binary input status change due to jitter

[Num_Reblk_Jitter] N’, times threshold to initiate immediately another blocking


window of binary input status change due to continuous jitter

For a binary input voltage variation, if the jitter processing function is enabled, its handling
principle is:

1. During the T,

a) If the actual jitter times < N, the block will not be initiated and the status change of this
binary input will be considered.

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b) If the actual jitter times ≥ N, the T’ is initiated, and the status change of binary input will
be ignored during the T’.

2. During the T’,

a) If the actual jitter times < N’, the block window will expire. The final status of this binary
input will be compared to the original one before T’, so as to determine whether there is a
change or not.

b) If the actual jitter times ≥ N’, the T’ will be initiated again immediately (i.e. restart the
timer), and the status change of binary input will be ignored during the next T’.

An example of jitter processing is shown in the following sequence chart:

Debounce time Input voltage level


(falling edge)

Debounce time
(rising edge)

Jitter blocking flag


n=N
initiate jitter block
Signal after
debounce & jitter
n=6<N=7
n=N processing
Prolong blocking
window

T
T t7 t8

6 t5 t6

T T T

t1 t2 t3 t4 t9 t10 t

Figure 6.7-3 Sequence chart of jitter processing

①Red line Voltage variation of binary input

②Green line Blocking signal of binary input status change due to jitter

③Blue line Binary input status after debounce and jitter processing

n Actual jitter times

We take N = 7 and N’ = 5 in this example.

3. T = t2 - t1

a) n = 6 < N;

b) No blocking, ② stays at 0 and ③ is tracing the voltage variation to create SOE.

4. T = t4 - t3, at t5

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a) n = 7 = N;

b) The processing initiates the blocking immediately due to jitter;

c) Jitter blocking, no more SOE, ② changes its status to 1 and ③ stops the tracing.

5. T’ = t6 - t5

a) At t7, n = 5 =N’, the processing prolongs the blocking immediately due to jitter;

b) Jitter blocking continues, no SOE, ② stays at 1 and ③ keeps its status.

6. T’ = t8 - t7

a) At t9, n = 5 =N’, the processing prolongs the blocking immediately due to jitter.

b) Jitter blocking continues, no SOE, ② stays at 1 and ③ keeps its status.

7. T’ = t10 - t9

a) n = 2 < N’;

b) At t10, jitter unblocking, ② changes its status to 0, the blocking window expires and ③
restart to trace the voltage variation imeediately. At this point, no debounce time takes
effect and SOE can be created since then.

6.7.3 High-Power Conducting Mode


In order to realize protection functions of primary equipment body or thermal overload protection,
signals may be transmitted to the binary input terminal of the device through a long cable, which
6
directly triggers the protection operating without any auxiliary criterion.

Because of the long cable and the large coupling capacitance, it is easy to be interfered by
external signals, to cause undesired operation. The device provides two kinds of BI modules,
NR6604 and NR6611, which support the high-power conducting mode of binary inputs through
the setting [En_BICheckInstP] to fulfill mechanical binary input.

 When voltage is greater than 95% of the settable ON value of binary input, the high-power
conducting mode is triggered. Under the compensation of a relatively large current, the
instantaneous active power immediately rises to the threshold.

 This pulsed current will remain constant for the next 20ms. During which time, as the voltage
rises, the power will also rise.

 If the voltage drops below 95% of the settable ON value of binary input, the device turns off
the high-power conducting mode.

 However, if the voltage rises and exceeds the 95% threshold again, the high-power
conducting mode will restart.

Therefore, it is possible to avoid interference signal in small voltage fluctuations so as to ensure


correct state change of binary input. The logical process is shown in Figure 6.7-4.

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20ms 20ms

UPickup
0.95UPickup
Interference Signal Valid Signal UDropout
U (In)

Pulsed constant current Pulsed constant current


I (Load)

BI (Out)
BI debounce time BI debounce time
(rising edge, >20ms) (falling edge, >20ms)

Time

Figure 6.7-4 High-power conducting mode

Only the binary inputs whose rated voltage is 110Vdc, 125Vdc, 220Vdc or
6 250Vdc (@50Hz), is capable to apply the high-power conducting mode.

6.8 Switchgear Trip Counter

The switchgear trip counter function supports counting of opening operations for circuit breaker
and disconnector. For a phase-segregated circuit breaker, if the position of any phase changes
from close to open, the opening counter increase.

6.9 Supervision Alarms and Handling Suggestion

Hardware circuit and operation status of this device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.

A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts “BO_Fail” will be given. The
protective device then cannot work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.

If the device is blocked or alarm signal is sent during operation, please do find out its reason with

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the help of self-diagnostic record. If the reason cannot be found at site, please notify the factory
NR. Please do not simply press button “TARGET RESET” on the protection panel or re-energize
on the device.

In the following table, “ON” means the LED is lit, “OFF” means the LED is
extinguished, “×” means having no influence, “YES” means the LED status
is modifiable, “NO” means the LED status is unmodifiable.

Table 6.9-1 Alarm description

Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
Fail signals (Device will be blocked)
This signal will be issued if any
1 Fail_Device OFF × NO fail signal picks up and it will drop
off when all fail signals drop off.
This signal will be issued if any
hardware or software failure is
2 Fail_DeviceInit OFF × NO
detected in the device
initialization process.
This signal will be issued due to
mismatch between the 6
3 Fail_BoardConfig OFF × NO configuration of plug-in modules
and the designing drawing of an
applied-specific project.
This signal will be issued if the
CCD process level configure file
4 Fail_ProcLevelConfig OFF × NO is parsed wrongly or the type in
the file is inconsistent with the
actual device.
After configuration file is updated,
settings of the file and settings
saved on the device are not
matched. This signal will be
5 Fail_SettingItem_Chgd OFF × NO
issued instantaneously and will
be latched unless the
recommended handling
suggestion is adopted.
The value of any setting is out of
scope. This signal will be issued
6 Fail_Setting_OvRange OFF × NO instantaneously and will be
latched unless the recommended
handling suggestion is adopted.

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Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
The alarm signal will be issued
instantaneously when an error is
7 Fail_Memory OFF × NO found during checking memory
data, and usually, it will
automatically drop out.
The configuration process does
8 Fail_ProcessConfig OFF × NO
not run properly.
The board fails to register the
variable, because of abnormal
9 Fail_BoardRegister OFF × NO
board, insufficient memory space,
or incorrect configuration.
The board fails to be initialized,
because of abnormal board,
10 Fail_BoardInit OFF × NO
insufficient memory space, or
incorrect configuration.
Error is found during checking
settings. The inappropriate or
11 Fail_Settings OFF × NO
incorrect value is set in a certain
application scenario.
A/D sampling data push error, the
6 12 Fail_Sample OFF × NO
possible cause is that the data
verification fails or no data is
sampled by A/D converter.
An abnormality is detected during
13 Bxx.Fail_Board OFF × NO self-check of No. xx board of this
device. (xx=04, 05...)
14 P1.Fail_Board OFF × NO The PWR module is abnormal.
Alarm signals (Device will not be blocked)
The device is abnormal. This
signal will be issued if any alarm
15 Alm_Device × ON NO
signal picks up and it will drop off
when all alarm signals drop out.
This signal will be issued if any
hardware or software
16 Alm_DeviceInit × × NO
configuration wrong is detected in
the device initialization process.
The error is found during
checking the version of software
downloaded to the device. This
17 Alm_Version × ON NO
signal will be issued
instantaneously and will drop off
instantaneously.

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Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
The device is in the
communication test mode. This
18 Alm_CommTest × ON NO signal will be issued
instantaneously and will drop off
instantaneously.
The device is in the GOOSE test
mode. This signal will be issued
19 Alm_GOOSETest × × NO
instantaneously and will drop off
instantaneously.
The active group set by settings
in device and that set by binary
20 Alm_BI_SettingGrp × × NO input are not matched. This signal
will issued instantaneously and
will drop off instantaneously.
The time synchronization
21 Alm_TimeSyn × ON YES
abnormality alarm.
The memory of CPU plug-in
22 Alm_Insuf_Memory × ON NO
module is insufficient.
The configuration file of IEC103 is
detected to not be correct when
23 Alm_CfgFile_IEC103 × ON NO
this file is parsed in the device 6
initialization process.
CPU module detects that some
module is reset due to the
24 Alm_Board × × NO
abnormality during the device
operating.
No sufficient NOR flash space
25 Alm_Insuf_NORflash × × NO used to store the program in CPU
module
The network mode is
inconsistent, such as the setting
Alm_NetMode_Unmatch
26 × × NO is set as HSR mode, but the
ed
actual operation mode is PRP
mode.
The set value of the setting
[RecDur_PostFault] is greater
27 Alm_Settings_DFR × × NO
than the set value of the setting
[MaxRecDur_PostTrigDFR].
The settings which are stored in
CPU module are different with the
28 Alm_Settings × ON NO
settings which are used by other
modules.

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Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
The device's master process is
29 Alm_master × ON NO abnormal and it is blocked for
more than 1 minute.
Error is detected in the FPGA
30 B**.Alm_CfgFile_FPGA × × NO
configuration file.
B**.Alm_DSP_HTM_Co Error is detected in internal
31 × ON NO
mm communication.
Error is detected in the
B**.Alm_CRC_ProcLeve
32 × × NO configuration file of process level
l
by CRC.
Alm_CfgFile_TCP1_DN The configuration file of DNP
33 × × NO
P client 1 is incorrect.
Alm_CfgFile_TCP2_DN The configuration file of DNP
34 × × NO
P client 2 is incorrect.
Alm_CfgFile_TCP3_DN The configuration file of DNP
35 × × NO
P client 3 is incorrect.
Alm_CfgFile_TCP4_DN The configuration file of DNP
36 × × NO
P client 4 is incorrect.
Function alarm signals (Device will not be blocked)
The device is in maintenance
6 37 Alm_Maintenance × ON YES
state.
38 Alm_BOTest × × NO The device is in output test mode.
This signal will be issued if the
sampled values from the dual A/D
converters are inconsistent or the
39 Alm_Sample × ON NO sampled value contains a large
DC component during the self or
mutual supervision of sampling
channels.
The quality of sampled data is
40 Alm_Quality × ON NO
abnormal.
CT secondary circuit at x side
41 x.CTS.Alm × ON YES
fails.
VT secondary circuit at x side
42 x.VTS.Alm × ON YES
fails.
CT secondary circuit for
43 87T.Alm_CTS × ON YES transformer differential protection
fails.
CT secondary circuit for restricted
44 x.64REF.Alm_CTS × ON YES earth fault protection at x side
fails.

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Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
CT secondary circuit of winding
45 87W.Alm_CTS × ON YES
differential protection fails.
CT secondary circuit of reactor
46 87R.Alm_CTS × ON YES current differential protection
fails.
Differential current of transformer
47 87T.Alm_Diff × ON YES differential protection is
abnormal.
Differential current of restricted
48 x.64REF.Alm_Diff × ON YES earth-fault protection at x side is
abnormal.
Differential current of winding
49 87W.Alm_Diff × ON YES differential protection is
abnormal.
Differential current of reactor
50 87R.Alm_Diff × ON YES current differential protection is
abnormal.
Definite-time overexcitation alarm
51 24DT2.Alm × × YES
element operates.
Inverse-time overexcitation alarm
52 24IDMT.Alm × × YES
element operates. 6
Stage i of phase overcurrent
53 x.50/51Pi.Alm × × YES protection operates to issue
alarm signal.
Stage i of earth fault overcurrent
54 x.50/51Gi.Alm × × YES protection operates to issue
alarm signal.
Stage i of negative-sequence
55 x.50/51Qi.Alm × × YES overcurrent protection operates
to issue alarm signal.
Thermal overload protection
56 x.49.Alm × × YES
operates to issue alarm signal.
The initiating signal of breaker
57 x.50BF.Alm_Init × ON YES failure protection is energized
consistently.
Stage i of phase overvoltage
58 x.59Pi.Alm × × YES protection operates to issue
alarm signal.
Stage i of residual overvoltage
59 x.59Gi.Alm × × YES protection operates to issue
alarm signal.

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Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
Stage i of phase undervoltage
60 x.27Pi.Alm × × YES protection operates to issue
alarm signal.
Stage i of overfrequency
61 81Oi.Alm × × YES protection operates to issue
alarm signal.
Stage i of underfrequency
62 81Ui.Alm × × YES protection operates to issue
alarm signal.
Stage i of frequency
63 81Ri.Alm × × YES rate-of-change protection
operates to issue alarm signal.
Fault detector element of
distance protection operates for
more than 50s.
64 x.21T.FD.Alm_Pkp × × YES
This signal will pick up with a time
delay of 50s and will drop off with
a time delay of 10s.
x.VoltSel.Alm_Invalid_Se
65 × × YES Voltage selection is invalid.
l
6 For synchronism check voltage
input channel configuration, the
voltage source to connect to the
inputs "in_ref" and "in_syn"
66 25.Alm_Cfg_Ch × × YES should be the same with that
used in measurement function,
such as BayMMXU and UMMXN.
Otherwise, this alarm will be
issued.
If a DPS signal indicating CB
position is intermediate or bad,
this alarm will be issued.
67 CB**.DPS.Alm × × YES
This signal will pick up and drop
off with a time delay defined by
[CB**.DPS.t_Alm].
If a DPS signal indicating DS
position is intermediate or bad,
this alarm will be issued.
68 DS**DPS.Alm × × YES
This signal will pick up and drop
off with a time delay defined by
[DS**.DPS.t_Alm].

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Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
The three-phase tap positions are
69 84.Alm_Unmatched × × YES
unmatched.
GOOSE alarm signals (Device will not be blocked)
The GOOSE communication is
abnormal.
It is an overall alarm signal and
70 GAlm_Overall × ON NO will be issued if any GOOSE
alarm signal picks up and it will
drop-off when all these alarm
signals drop-off.
Error is detected in the GOOSE
71 GAlm_CfgFile × ON NO
configuration file.
For GOOSE link, the incoming
data with test=true &
B01.GAlm_Maint_Unmat validity=good &
72 × ON NO
ched operatorBlocked=false, but the
quality status (q) of the device
equals to "on".
For link XX, the connection of
GOOSE network A is
disconnected. (No GOOSE 6
message is received within two
73 XX.GAlm_ADisc × ON NO
times TAL from link XX)
XX is determined by description
setting
[B**.Name_**_GCommLink]
For link XX, the connection of
GOOSE network A is
disconnected. (No GOOSE
message is received within two
74 XX.GAlm_BDisc × ON NO
times TAL from link XX)
XX is determined by description
setting
[B**.Name_**_GCommLink]
Mismatch is detected between
the GOOSE control blocks
received via network and the
XX.GAlm_CfgUnmatche
75 × ON NO ones defined in GOOSE
d
configuration file. (Including
config version, number of data
sets and data type)
SV alarm signals (Device will not be blocked)

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Running Status LED


No. Item Description
"HEALTHY" "ALARM" Modifiable
The SV communication is
abnormal.
It is an overall alarm signal and
76 SVAlm_Overall × ON NO will be issued if any SV alarm
signal picks up and it will drop-off
when all these alarm signals
drop-off.
Error is detected in the SV
77 SVAlm_CfgFile × ON NO
configuration file.
For SV link, the incoming data
with test=true & validity=good &
SVAlm_Maint_Unmatche
78 × ON NO operatorBlocked=false, but the
d
quality status (q) of the device
equals to "on".
For link XX, the connection of SV
network A is disconnected.
(Including data timeout, decoding
79 XX.SVAlm_ADisc × ON NO error, or sampling counter error)
XX is determined by description
setting
6 [B**.Name_**_SVCommLink].
For link XX, the connection of SV
network B is disconnected.
(Including data timeout, decoding
80 XX.SVAlm_BDisc × ON NO error, or sampling counter error)
XX is determined by description
setting
[B**.Name_**_SVCommLink].
Interpolation error of sampling
81 XX.SVAlm_Data × ON NO
data in link XX
XX.SVAlm_SmplSynLos
82 × ON NO Loss of synchronization in link XX
s
XX.SVAlm_InvalidSampl
83 × ON NO Invalid sampling data in link XX
e
Jittering error of sampling data in
84 XX.SVAlm_Jitter_Ch × ON NO
link XX
85 XX.SVAlm_tdrChgd_Ch × ON NO The delay of link XX changes.
XX.SVAlm_tdrOvRange_ The delay of link XX exceeds the
86 × ON NO
Ch limit.
87 XX.SVAlm_Maintenance × ON NO Link XX is in maintenance state

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Table 6.9-2 Troubleshooting

No. Item Handling suggestion


Fail signals
The signal is issued with other specific fail signals, and please refer to the
1 Fail_Device
handling suggestion other specific alarm signals.
2 Fail_DeviceInit Please inform the manufacturer or the agent for repair.
1. Go to the menu “Information→Borad Info”, check the abnormality
information.
3 Fail_BoardConfig 2. For the abnormality board, if the board is not used, then remove, and if
the board is used, then check whether the board is installed properly and
work normally.
Check whether the CCD process level configuration file of this device is
4 Fail_ProcLevelConfig exist and whether the file content is correct. May need to download and
update the correct CCD process level configuration file.
Please check the settings mentioned in the prompt message on the LCD,
5 Fail_SettingItem_Chgd and go to the menu “Settings” and select “Confirm Settings” item to
confirm settings. Then, the device will restore to normal operation stage.
Please reset setting values according to the range described in the
6 Fail_Setting_OvRange technical manual, then re-power or reboot the device and the device will
restore to normal operation state.
7 Fail_Memory Please inform the manufacturer or the agent for repair.

8 Fail_ProcessConfig
View the menu "Initialization Error" to check the detailed reason, and
send the reason to the manufacturer or the agent.
6
9 Fail_BoardRegister Please inform the manufacturer or the agent for repair.
View the menu "Initialization Error" to check the detailed reason, and
10 Fail_BoardInit
send the reason to the manufacturer or the agent.
11 Fail_Settings Please check the settings and set them correctly
12 Fail_Sample Please check the connection of CPU plug-in module.
13 Bxx.Fail_Board Please inform the manufacturer or the agent to deal with it.
14 P1.Fail_Board Please check the connection of PWR plug-in module.
Alarm signals
The signal is issued with other specific alarm signals, and please refer to
15 Alm_Device
the handling suggestion other specific alarm signals.
16 Alm_DeviceInit Please inform the manufacturer or the agent to deal with it.
Users may pay no attention to the alarm signal in the project
commissioning stage, but it is needed to download the latest package file
(including correct version checksum file) provided by R&D engineer to
17 Alm_Version make the alarm signal disappear. Then users get the correct software
version. It is not allowed that the alarm signal is issued on the device
already has been put into service. The devices have been put into service
so that the alarm signal disappears.
18 Alm_CommTest No special treatment is needed, and disable this test function after the
19 Alm_GOOSETest completion of the test.

PCS-978S Transformer Relay 6-21


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No. Item Handling suggestion


Please check the value of the setting [Active_Grp] and binary inputs of
indicating active group, and make them matched. Then the “ALARM” LED
20 Alm_BI_SettingGrp
will be extinguished and the corresponding alarm message will disappear
and the device will restore to normal operation state.
1. Check whether the selected clock synchronization mode matches the
clock synchronization source;
2. Check whether the wiring connection between the device and the clock
synchronization source is correct
3. Check whether the setting for selecting clock synchronization (i.e.
21 Alm_TimeSyn
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization,
please set the setting [Opt_TimeSyn] as ”NoTimeSyn”.
After the abnormality is removed, the “ALARM” LED will be extinguished
and the corresponding alarm message will disappear and the device will
restore to normal operation state.
22 Alm_Insuf_Memory Please inform the manufacturer or the agent to deal with it.
Please inform the configuration engineer to check and confirm the
23 Alm_CfgFile_IEC103
contents of IEC 60870-5-103 configuration file.
24 Alm_Board Please inform the manufacturer or the agent to deal with it.
25 Alm_Insuf_NORflash Please inform the manufacturer or the agent to deal with it.
Check the setting of network mode, or upload the device log and confirm
26 Alm_NetMode_Unmatched
with the manufacturer or agent whether the network mode is supported.
6 27 Alm_Settings_DFR
Please check the settings [RecDur_PostFault] and
[MaxRecDur_PostTrigDFR], and set them reasonably.
28 Alm_Settings Please inform the manufacturer or the agent for repair.
29 Alm_master Please check the load of the device.
30 B**.Alm_CfgFile_FPGA
31 B**.Alm_DSP_HTM_Comm Please inform the manufacturer or the agent for repair.
32 B**.Alm_CRC_ProcLevel
33 Alm_CfgFile_TCP1_DNP
34 Alm_CfgFile_TCP2_DNP Please contact the configuration engineer to check and confirm the
35 Alm_CfgFile_TCP3_DNP contents of DNP configuration file.
36 Alm_CfgFile_TCP4_DNP
Function alarm signals
It is normal prompt information of the device and does not need to be
37 Alm_Maintenance
handled.
It is normal prompt information of the device and does not need to be
38 Alm_BOTest
handled.
39 Alm_Sample Please check the connection of AC AI module and CPU module.
40 Alm_Quality Please check SV quality if adopting IEC 61850-9-2.
41 x.CTS.Alm Please check the corresponding CT/VT secondary circuit. After the
abnormality is eliminated, “ALARM” LED will go off automatically and
42 x.VTS.Alm
equipment returns to normal operation state.

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No. Item Handling suggestion


43 87T.Alm_CTS
Please check the corresponding CT secondary circuit. After the
44 x.64REF.Alm_CTS
abnormality is eliminated, equipment can return to normal operation state
45 87W.Alm_CTS
by energizing the binary input [BI_RstTarg]
46 87R.Alm_CTS
47 87T.Alm_Diff Please check the corresponding sampling values and CT secondary
48 x.64REF.Alm_Diff circuit to find out the reason resulting in the abnormality. If sample values
49 87W.Alm_Diff of the equipment are not correct, please inform the manufacturer or agent
for maintenance, and if it is caused by the failure of the CT secondary
50 87R.Alm_Diff circuit or primary system, please finish troubleshooting according to the
operating instructions of protection relay.
51 24DT2.Alm
52 24IDMT.Alm
53 x.50/51Pi.Alm
Please treat according to the specific application requirements.
54 x.50/51Gi.Alm
55 x.50/51Qi.Alm
56 x.49.Alm
Please check the contacts of binary inputs "x.50BF.ExtTrpA",
57 x.50BF.Alm_Init "x.50BF.ExtTrpB", "x.50BF.ExtTrpC", "x.50BF.ExtTrp3P",
"x.50BF.ExtTrp_WOI".
58 x.59Pi.Alm
59 x.59Gi.Alm
60 x.27Pi.Alm Please treat according to the specific application requirements.
6
61 81Oi.Alm
62 81Ui.Alm
63 81Ri.Alm
Please check secondary values and protection settings. If the settings are
not set reasonable to make fault detectors pick up, please reset settings,
64 x.21T.FD.Alm_Pkp
and then the alarm message will disappear and the device will restore to
normal operation state.
65 x.VoltSel.Alm_Invalid_Sel Check the voltage selection logic.
66 25.Alm_Cfg_Ch Check the channel configuration for synchronism check.
67 CB**.DPS.Alm
Check the corresponding DPS signal.
68 DS**DPS.Alm
69 84.Alm_Unmatched Check the tap positions inputs.
GOOSE alarm signals
The signal is issued with other specific GOOSE alarm signals, and please
70 GAlm_Overall
refer to the handling suggestion of them.
71 GAlm_CfgFile Please check GOOSE configuration file.
72 B01.GAlm_Maint_Unmatched Please check the quality status (q) of incoming data and the device.
73 XX.GAlm_ADisc
74 XX.GAlm_BDisc Please check GOOSE network and GOOSE configuration file.
75 XX.GAlm_CfgUnmatched

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No. Item Handling suggestion


SV alarm signals
The signal is issued with other specific SV alarm signals, and please refer
76 SVAlm_Overall
to the handling suggestion of them.
77 SVAlm_CfgFile Please check SV configuration file.
78 SVAlm_Maint_Unmatched Please check the quality status (q) of incoming data and the device.
79 XX.SVAlm_ADisc Please check SV network and SV configuration file.
80 XX.SVAlm_BDisc Please check SV network and SV configuration file.
81 XX.SVAlm_Data Please check SV network and SV configuration file.
82 XX.SVAlm_SmplSynLoss Please check synchronization clock of link XX.
83 XX.SVAlm_InvalidSample Please check the validity of quality type definition in link XX.
84 XX.SVAlm_Jitter_Ch Please check send interval of link XX.
85 XX.SVAlm_tdrChgd_Ch Please check channel delay of link XX
86 XX.SVAlm_tdrOvRange_Ch Please check channel delay of link XX
87 XX.SVAlm_Maintenance Please check the quality status (q) of link XX via MU

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7 System Functions

7 System Functions

Table of Contents

7.1 Clock Synchronization .................................................................................... 7-1


7.1.1 Clock Synchronization Mode ................................................................................................ 7-1

7.1.2 Clock Synchronization Abnormality ...................................................................................... 7-1

7.1.3 Clock Synchronization Priority ............................................................................................. 7-1

7.1.4 SNTP Setup .......................................................................................................................... 7-2

7.2 State Information ............................................................................................. 7-2


7.2.1 Overview............................................................................................................................... 7-2

7.2.2 Access Method ..................................................................................................................... 7-3

7.3 Event Recording .............................................................................................. 7-4


7.3.1 Overview ............................................................................................................................... 7-4

7.3.2 Disturbance Records ............................................................................................................ 7-4

7.3.3 Supervision Events ............................................................................................................... 7-4

7.3.4 Binary Events ....................................................................................................................... 7-4

7.3.5 Device Logs .......................................................................................................................... 7-4 7


7.3.6 Control Logs ......................................................................................................................... 7-4

7.3.7 Access Method ..................................................................................................................... 7-4

7.4 Fault Recording ............................................................................................... 7-5


7.4.1 Overview ............................................................................................................................... 7-5

7.4.2 Fault Report .......................................................................................................................... 7-5

7.4.3 Fault Waveform .................................................................................................................... 7-6

7.4.4 Access Method ..................................................................................................................... 7-7

7.5 Maintenance State ........................................................................................... 7-7


7.6 Communication Test ....................................................................................... 7-7
7.7 Output Test ....................................................................................................... 7-8
7.8 Target Reset ..................................................................................................... 7-9
7.9 Switch Setting Groups .................................................................................... 7-9

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7.1 Clock Synchronization

7.1.1 Clock Synchronization Mode

The device supports both hardware-based and software-based clock synchronization modes.

1. Hardware clock synchronization ([Opt_TimeSyn]=Conventional)

 IRIG-B: IRIG-B via serial port (RS-485 or TTL level), female BNC (TTL level) or
ST-connector port

 PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), female BNC (TTL
level), ST-connector port or binary input

 IEEE 1588: Clock message based on IEEE 1588 via Ethernet network

2. Software clock synchronization ([Opt_TimeSyn]=SAS)

 SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network

 Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol

7.1.2 Clock Synchronization Abnormality


The device provide an alarm signal "Alm_TimeSyn", which indicates the signal of clock
synchronization is abnormal or is lost. The setting [Opt_TimeSyn] should be set reasonably
according to actual clock synchronization source.

If the setting [Opt_TimeSyn] is set as "Conventional" and no hardware clock synchronization


signal is connected, the device will automatically switch into software clock synchronization and
issue the alarm signal. If the setting [Opt_TimeSyn] is set as "SAS" and neither hardware clock 7
synchronization signal nor software clock synchronization signal is connected, the device will
issue the alarm signal. If the setting [Opt_TimeSyn] is set as "NoTimeSyn" and no clock
synchronization signal is connected, the device will not issue the alarm signal. The clock
synchronization is still fulfilled when valid clock synchronization signal is received.

7.1.3 Clock Synchronization Priority

The device provides a priority-based adaptive clock synchronization scheme, which means that
the device can automatically identify multiple clock synchronization sources in the same clock
synchronization mode and choose the highest priority of lock synchronization sources.

The setting [Opt_TimeSyn] is set as "SAS".

Clock synchronization mode Clock synchronization signal Priority selection

Software-based SNTP + Clock message SNTP

The setting [Opt_TimeSyn] is set as "Conventional" and the setting [En_ConvModeSNTP] is set
as "Disabled"

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Clock synchronization mode Clock synchronization signal Priority selection

IRIG-B + PPS + IEEE 1588 IRIG-B


Hardware-based
PPS + IEEE 1588 PPS

The setting [Opt_TimeSyn] is set as "Conventional" and the setting [En_ConvModeSNTP] is set
as "Enabled"

Clock synchronization mode Clock synchronization signal Priority selection

IRIG-B + PPS + IEEE 1588 + SNTP IRIG-B

Hardware-based + SNTP PPS + IEEE 1588 + SNTP PPS

IEEE 1588 + SNTP IEEE 1588

7.1.4 SNTP Setup


When the device adopts SNTP to realize clock synchronization, [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] shall be set correctly.

[IP_Server_SNTP] is the address of SNTP clock synchronization server which sends SNTP timing
messages to the relay or BCU. [IP_StandbyServer_SNTP] is the address of standby SNTP clock
synchronization server.

Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock


synchronization is valid.

When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "0.0.0.0", the device
receives broadcast SNTP synchronization message.
7
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "0.0.0.0", the device
adopts the setting whose value is not equal to "0.0.0.0" as SNTP server address and receives
unicast SNTP synchronization message.

If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "0.0.0.0", the device adopts


the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP synchronization
message. If the device does not receive any server response after 30s, it adopts the setting
[IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP synchronization
message.

The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it


does not receive any server response in 30s.

7.2 State Information

7.2.1 Overview
The device can provide real-time state information, including analog quantities (such primary

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measurement value, secondary measurement value, metering value and so on) and status
quantities (supervision status, input status, output status and so on). By check these state
information, operators can know operation state of the protected equipment and whether the
device is healthy.

7.2.2 Access Method

7.2.2.1 Access by Local HMI (Human Machine Interface)

These state information can be gained via local HMI. The menu path is:

1. Analog quantities

 MainMenu  "Measurements"  "Primary Values"

 MainMenu  "Measurements"  "Secondary Values"

 MainMenu  "Measurements"  "Function Values" "Synchronism Check"

 MainMenu  "Measurements"  "Energy Metering"

 MainMenu  "Measurements"  "UserDef Values"

2. Status quantities

 MainMenu  "Status"  "Inputs"

 MainMenu  "Status"  "Outputs"

 MainMenu  "Status"  "Superv Status"

 MainMenu  "Status"  "Running Status"

 MainMenu  "Status"  "UserDef Status" 7


7.2.2.2 Access by Virtual HMI

Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.

7.2.2.3 Access by Communication Client

Device's state information can be uploaded into clients through message communication. For
differential protocols, the state information can be gained through corresponding communication
service.

7.2.2.4 Access by Printer

The device can print the current state information, so that the operator can observe and save the
current operation condition. The access path is:

MainMenu  "Print"  "Device Status"

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7.3 Event Recording

7.3.1 Overview
The device can store the latest 1024 time-stamped disturbance records, 1024 time-stamped
binary events, 1024 time-stamped supervision events, 256 time-stamped control logs and 1024
time-stamped device logs. All the records are stored in non-volatile memory, and when the
available space is exhausted, the oldest record is automatically overwritten by the latest one.

7.3.2 Disturbance Records


When any protection element operates or drops out, such as fault detector, distance protection
etc., they will be logged in event records. Disturbance records include signal name, its value
before and after changing, and the time precision is up to 1ms.

7.3.3 Supervision Events


The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records. Supervision events include signal name, its value before and after changing, and the
time precision is up to 1ms.

7.3.4 Binary Events


When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records. Binary events include signal name, its value
before and after changing, and the time precision is up to 1ms.

7.3.5 Device Logs


7
If an operator executes some operations on the device, such as reboot protective device, modify
setting, etc., they will be logged in event records. Device logs include signal name, its value
before and after changing, and the time precision is up to 1ms.

7.3.6 Control Logs


When an operator executes a control command via local LCD, PCS-Studio or communication
client, it will be logged in control logs. Control logs include time stamp, controlled object, control
origination, control position, operation condition, interlocking condition, control command and
operation result.

7.3.7 Access Method

7.3.7.1 Access by Local HMI

The device provides corresponding menus to view event recorders. The menu path is:

MainMenu  "Test"  "Disturb Events"

MainMenu  "Records"  "Superv Events"

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MainMenu  "Records"  "IO Events"

MainMenu  "Records"  "Device Logs"

MainMenu  "Records"  "Control Logs"

7.3.7.2 Access by Virtual HMI

Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.

7.3.7.3 Access by Communication Client

Event recorders can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).

7.3.7.4 Access by Printer

The device can print event recorders, so that the operator can observe and save the current
operation condition. The access path is:

MainMenu  "Print"  "Superv Events"

MainMenu  "Print"  "IO Events"

7.4 Fault Recording

7.4.1 Overview

Fault recorder can be used to have a better understanding of the behavior of the power network
and related primary and secondary equipment during and after a disturbance. Analysis of the
7
recorded data provides valuable information that can be used to improve existing equipment. This
information can also be used when planning for and designing new installations.

The fault recorder is comprised of the report and the waveform, which can be triggered by pickup
signals, trip signals and configurable binary signal [BI_TrigDFR].

The fault memory of the device is automatically updated with every recording. When the fault
memory is filled completely, the oldest records are overwritten automatically. Thus, the most
recent recordings are always stored safely. The maximum number of recordings is 64.

7.4.2 Fault Report

For each fault report, the following items are included:

1. Sequence number

Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.

2. Date and time of fault occurrence

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The date and time is recorded when a system fault is detected. The time resolution is 1ms.

3. Relative operating time

An operating time (not including the operating time of output relays) is recorded in the record. The
time resolution is 1ms.

4. Fault information

Including faulty phase, fault location and protection elements

7.4.3 Fault Waveform

A fault waveform contains all analog and digital quantities related to protection such as currents,
voltages, differential current, alarm elements, and binary inputs and etc.

The overall duration of a single fault recording comprises the total duration of the configurable
recording criterion, the pre-trigger time and the post-trigger time. With the fault recording
parameter, these components can be individually set. The pre-trigger waveform recorded duration
is configured via the setting [RecDur_PreTrigDFR]. The waveform recorded duration after the fault
disappears is configured via the setting [RecDur_PostFault]. The maximum post-trigger waveform
recorded duration is configured via the setting [MaxRecDur_PostTrigDFR].

4. [MaxRecDur_PostTrigDFR]

1. [RecDur_PreTrigDFR] 2.Pickup 3. [RecDur_PostFault]

Trigger point

Total recording time

7
1. Pre-trigger recording time

Use the setting [RecDur_PreTrigDFR] to set this time.

2. Pickup recording time

The pickup recording time cannot be set. It continues as long as any valid trigger condition, binary
or analog, persists (unless limited by the limit time, which is determined by the setting
[MaxRecDur_PostTrigDFR]).

3. Post-fault recording time

The recording time begins after all activated triggers are reset. Use the setting [RecDur_PostFault]
to set this time.

4. Maximal post-trigger recording time

Use the setting [MaxRecDur_PostTrigDFR] to set this time. If the summation of pickup recording
time and post-fault recording time is larger than maximal post-trigger recording time, the
post-trigger recording time shall be equal to the setting [MaxRecDur_PostTrigDFR].

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7.4.4 Access Method

7.4.4.1 Access by Local HMI

The device provides corresponding menus to check fault recording. The menu path is:

MainMenu  "Records"  "Disturb Records"

7.4.4.2 Access by Virtual HMI

Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.

7.4.4.3 Access by Communication Client

Fault recording can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).

7.4.4.4 Access by Printer

The device can print fault recording, so that the operator can observe and save the current
operation condition. The access path is:

MainMenu  "Print"  "Disturb Records"

7.5 Maintenance State

The device provides maintenance state, i.e., the binary input [BI_Maintenance] is energized,
which is convenient for maintenance work. For adopting conventional CT/VT, binary inputs and
binary outputs, maintenance state has no influence on protection logics. For binary inputs and
7
binary outputs by GOOSE connections. During device maintenance, the object will send GOOSE
message with Test quality attribute. The Test quality attribute indicates to the receiver device that
the object received via a GOOSE message was created under test conditions and not operating
conditions. If the Test quality attribute received is different with the object's Test quality attribute,
binary inputs and binary outputs by GOOSE connections will be affected based on different types
of binary inputs and binary outputs. For SV (Sampling Value) message, if the Test quality attribute
received is different with the object's Test quality attribute, the relevant protection functions will be
blocked.

For IEC60870-5-103 protocol, only the messages in link layer maintained, service messages in
the application layer which is uploaded automatically are blocked, and service messages in the
application layer which is issued by the client are rejected. For IEC61850 protocol, all Test quality
attribute set as "1". For DNP3.0 and ModBus protocol, they are not affected.

7.6 Communication Test

The device provides Test Mode to allow all protection elements, supervision events and binary

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7 System Functions

events to fulfill communication test, but to avoid the output contacts to close. During
communication test, protection functions are not affected, the signals generated by
communication test are recorded in relevant reports, and event recording and fault recording will
not stop recording disturbance information. The alarm signal "Alm_CommTest" will be issued to
indicate the operator when activating Test Mode and exiting Test Mode.

Communication test can be gained via local HMI and the virtual HMI, the corresponding content
can be viewed through the following menu paths:

 Events Simulation

Main Menu  "Test"  "Device Test"  "Disturb Events"

Main Menu  "Test"  "Device Test"  "Superv Events"

Main Menu  "Test"  "Device Test"  "IO Events"

 Forced Measurements

Main Menu  "Test"  "Device Test"  "Measurements"

Forced measurement ONLY affects the values modified and transmitted to


station control or control center. Primary circuit, secondary circuit and
device local logic will not be influenced. Forced value will remain during the
test until the exit of this menu.

If no input operation is carried out within 60s, this test will exit and return to
the previous menu automatically.
7
7.7 Output Test

The device provides Output Test Mode to test all outputs. Through this mode, there will be real
operations, such as contact closing and GOOSE output value change, triggered by the device to
test output circuits and links. So, protection functions outputs and the connecting primary
equipments are affected. The output signals generated by output test are not recorded, while the
entering and exiting of output test mode will be recorded in Superv Events. During the output test,
the protection functions will not stop, nor will the all recording functions.

Output test can be gained via the local LCD or virtual HMI of a debugging PC, the corresponding
content can be viewed through the following menu paths:

 Contacts Outputs

Main Menu  "Test"  "Device Test"  "Contact Outputs"

 GOOSE Outputs

Main Menu  "Test"  "Device Test"  "GOOSE Outputs"

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Dismantle the wiring connection if any influence on relevant primary


equipments is undesired. The output test will cause operation of relay
contacts through secondary circuit and GOOSE link.

7.8 Target Reset

The device provides target reset which can be used to reset local signals (including magnetic
latching output relays), latched LEDs, and confirm pop-up windows of reports. The function does
not affect the protection logic and communication function. There are several ways to reset.

1. Reset via local HMI

 Access menu path: MainMenu  "Local Cmd"  "Reset Target"

 Press the command pushbutton “ESC”+“ENT” on operation panel of the device under
main interface

 Press the command pushbutton " TARGET RESET" on operation panel of the device

2. Reset via virtual HMI

Access menu path: MainMenu  "Local Cmd"  "Reset Target"

3. Reset via binary input

Energize the binary input "BI_RstTarg"

4. Reset via IEC61870-5-103


7
Use ASDU20, INF19 of IEC61870-5-103 protocol

5. Reset via remote control

Use standard remote service of corresponding protocol

7.9 Switch Setting Groups

For different applications users can save the respective function settings in so-called settings
groups, and if necessary enable them quickly. Up to 20 different settings groups can be saved in
the device. In the process, only one settings group is active at any given time. During operation,
the operator can switch between setting groups.

The device will be temporarily blocked during switching setting groups. During temporary device
blocking, the device will loss protection functions and communication functions. Alarm signals
"Fail_Device" and "Alm_Device" will be issued. There are several ways to switch setting groups.

1. Switch via local HMI

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 Access menu path: MainMenuSettingGlobal SettingsSystem Settings, change


the value of the setting [Active_Grp]

 Press the command push-button "MENU" under main interface (password is required)

2. Switch via virtual HMI

Access menu path: MainMenuSettingGlobal SettingsSystem Settings, modify the


setting [Active_Grp]

3. Switch via communication client

The communication protocols IEC 60870-5-103 or IEC 61850 can be used for switching the
setting groups via a communication connection.

 Use "General Service" of IEC61870-5-103 protocol to modify the setting [Active_Grp]

 Use "SelectActiveSG" of IEC61850 protocol to switch setting groups.

4. Switch via binary signals

The device also provides an available function by configuring associated binary signals via
PCS-Studio to switch setting group, which can be external binary inputs or internal logic
signals. By default, no binary signals are configured, so the function is invalid.

Each input signal is coded with a sequence number that corresponds to a setting group.
When the associated input signal changes, the device scans all input signals and selects the
input with the smallest sequence number as the valid input. The device switches to the
setting range corresponding to the input signal. The device can switch up to 20 setting
groups.

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8 Hardware

Table of Contents

8.1 Overview ........................................................................................................... 8-1


8.2 Typical Wiring .................................................................................................. 8-4
8.3 CT Requirements ............................................................................................. 8-6
8.3.1 CT Types .............................................................................................................................. 8-6

8.3.2 CT Requirements ................................................................................................................. 8-6

8.3.3 K Value Requirements .......................................................................................................... 8-7

8.3.4 Example................................................................................................................................ 8-8

8.4 Plug-in Module Description ............................................................................ 8-8


8.4.1 Human-machine Interface Module (NR6855/NR6856) ........................................................ 8-8

8.4.2 Power Supply Module (NR6305/NR6310/NR6311) ............................................................. 8-8

8.4.3 CPU Module (NR6106) ...................................................................................................... 8-12

8.4.4 NET-DSP Module (NR6113) ............................................................................................... 8-17

8.4.5 AC Analog Input Module (NR6641) .................................................................................... 8-18

8.4.6 Binary Input Module (NR6601/NR6604/NR6610/NR6611) ................................................ 8-21

8.4.7 Binary Output Module (NR6651/NR6652/NR6660/NR6663) ............................................. 8-29

8.4.8 Binary Input and Binary Output Module (NR6661) ............................................................ 8-34

8.4.9 Mechanical Relay Input and Output Module (NR6662) ..................................................... 8-36 8
8.4.10 DC Analog Input Module (NR6630/NR6631) ................................................................... 8-38

List of Figures

Figure 8.1-1 Hardware diagram ................................................................................................ 8-1

Figure 8.1-2 Front view of PCS-978S ......................................................................................... 8-3

Figure 8.1-3 Typical rear view of PCS-978S with ring ferrule .................................................. 8-3

Figure 8.1-4 Typical rear view of PCS-978S with pin ferrule .................................................... 8-4

Figure 8.2-1 Typical hardware configuration............................................................................. 8-4

Figure 8.2-2 Typical wiring ......................................................................................................... 8-5

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Figure 8.4-1 View of power supply module ............................................................................... 8-9

Figure 8.4-2 View of CPU module ............................................................................................ 8-14

Figure 8.4-3 Connection of communication terminal .......................................................... 8-16

Figure 8.4-4 Jumpers of printer/RS-485 port ........................................................................ 8-16

Figure 8.4-5 View of NET-DSP module .................................................................................. 8-17

Figure 8.4-6 Schematic diagram of CT circuit automatically closed ................................. 8-18

Figure 8.4-7 Terminal definition of analog input module .................................................... 8-19

Figure 8.4-8 Current connection examples .......................................................................... 8-20

Figure 8.4-9 Voltage connection examples........................................................................... 8-21

Figure 8.4-10 Voltage dependence for binary inputs........................................................... 8-22

Figure 8.4-11 View of binary input module (NR6601A) ........................................................ 8-23

Figure 8.4-12 View of binary input module (NR6604A) ....................................................... 8-24

Figure 8.4-13 View of binary input module (NR6610A and NR6610B) ............................... 8-26

Figure 8.4-14 View of binary input module (NR6611A) ........................................................ 8-28

Figure 8.4-15 View of binary output module (NR6651A) ..................................................... 8-30

Figure 8.4-16 View of binary output module (NR6651B) ..................................................... 8-31

Figure 8.4-17 View of binary output module (NR6652A) ..................................................... 8-32

Figure 8.4-18 View of binary output module (NR6660A) ..................................................... 8-33

Figure 8.4-19 View of binary output module (NR6663A) ..................................................... 8-34

Figure 8.4-20 View of binary input and binary output module (NR6661A) ........................ 8-35

8 Figure 8.4-21 View of MR IO plug-in module (NR6662A, NR6662B and NR6662N) .......... 8-37

Figure 8.4-22 View of DC analog input module NR6630A ................................................... 8-39

Figure 8.4-23 View of DC analog input module NR6631A ................................................... 8-41

List of Tables

Table 8.4-1 Terminal definition and description of power supply module NR6305A ............ 8-10

Table 8.4-2 Terminal definition and description of power supply module NR6310A ............ 8-11

Table 8.4-3 Terminal definition and description of power supply module NR6311A............. 8-11

Table 8.4-4 Configuration and terminal definition of CPU module......................................... 8-14

Table 8.4-5 Terminal definition and description of binary input module ............................... 8-23

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Table 8.4-6 Terminal definition and description of binary input module (NR6604A) ............. 8-25

Table 8.4-7 Terminal definition and description of binary input module ............................... 8-26

Table 8.4-8 Terminal definition and description of binary input module (NR6611A) ............ 8-28

Table 8.4-9 Terminal definition and description of BIBO module NR6661A .......................... 8-35

Table 8.4-10 Terminal definition and description of MR IO module ....................................... 8-37

Table 8.4-11 Terminal definition and description of DC analog input module NR6630A ...... 8-39

Table 8.4-12 Terminal definition and description of DC analog input module NR6631A ...... 8-41

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8.1 Overview

The modular design of this device allows this device to be easily upgraded or repaired by a
qualified service person. The faceplate is hinged to allow easy access to the configurable
modules, and back-plugging structure design makes it easy to repair or replace any module.

This device adopts one 32-bit ARM core in the CPU chip as control core for management and
monitoring function, and adopts another 32-bit ARM core in the CPU chip for all the protection
calculation. The parallel processing of sampled data can be realized in each sampling interval to
ensure ultrahigh reliability and safety of the device.

This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 8.1-1 for the hardware diagram.

External
Binary Input

Conventional CT/VT A/D


Output
ARM1
Relay
A/D

Pickup
Electronic/Optic CT/VT Relay

ETHERNET

+E
LCD
Clock SYN
Power
Uaux LED ARM2
Supply
RJ45

Keypad
PRINT

Figure 8.1-1 Hardware diagram


8
The working process of the device is as shown in above figure: the currents and voltages from
conventional CT/VT are converted into small voltage signal and sent to ARM1 core after filtered
and A/D conversion for protection calculation and fault detector respectively (electronic/optic
CT/VT signals are sent to the device without A/D conversion). The ARM1 core carries out fault
detector, protection logic calculation, tripping output, and the ARM2 core performs SOE
(sequence of event) record, waveform recording, printing, communication between the device and
SAS and communication between HMI and CPU. When the fault detector detects a fault and picks
up, the positive power supply for output relay is provided.

The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS S series based on microcomputer
are classified into standard and optional modules.

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8 Hardware

Table 8.1-1 Module configuration of this device

Module ID Module description Remark


NR6855/NR6856 Human machine interface module (HMI module) Mandatory
NR6305/NR6310/NR6311 Power supply module (PWR module) Mandatory
NR6106 Main CPU module (CPU module) Mandatory
NR6113 Network digital signal processing module (NET-DSP module) Optional
NR6641 AC analog input module (AC AI module) Optional
NR6601/NR6610/NR6604/
Binary input module (BI module) Optional
NR6611
NR6651/NR6652//NR6660/
Binary output module (BO module) Optional
NR6663
NR6661 Binary input and binary output module (BIBO module) Optional
NR6662 Mechanical relay input and output module (MR IO module) Optional
NR6630/NR6631 DC analog input module (DC AI module) Optional

 HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.

 PWR module converts AC100V/110V/115V/120V/127V/220V/230V/240V/250V or


DC110V/125V/220V/250V into various DC voltage levels for modules of the device.

 CPU module provides functions like communication with SAS, event record, setting
management etc., and performs filtering, sampling, protection calculation and fault detector
calculation.

 NET-DSP module receives and transmits GOOSE messages, sampled values (SV) from
merging unit by IEC 61850-9-2 protocol.

 AC AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.

8  BI module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V~250V (configurable).

 BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.

 BIBO module provides both binary inputs (with rating voltage among AC110V/220V or
DC24V~250V) and output contacts for tripping and signal.

 MR IO module receives mechanical signals from transformer body and provides several
output contacts.

 DC AI module provides DC analog input channels 0~±20mA or 0~±10Vdc.

Following figures show the front and rear views of this device respectively.

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8 Hardware

8 8

1 1
3 3

9 4 9
4

2 2
5 5

6 7 6 7

Figure 8.1-2 Front view of PCS-978S

1. LCD for device status and information display

2. Easy-to-use keypad aids simple navigation and set-point adjustment

3. Push buttons for opening/closing operation and switch of local/remote control mode

4. Push button for user login/logout authority management

5. Push buttons with configurable labels for user-programmable functions

6. Front RJ45 multiplex debugging port

7. Push button for target reset

8. Two LED indictors for device running status

9. Up to 18 programmable LED indicators with configurable labels

1 1
8
4 5 6 4 5 6

2 2

3 3

Figure 8.1-3 Typical rear view of PCS-978S with ring ferrule

PCS-978S Transformer Relay 8-3


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8 Hardware

1 1

4 5 6 4 5 6

2 2

3 3

Figure 8.1-4 Typical rear view of PCS-978S with pin ferrule

1. Copper and optic Ethernet ports

2. RS-232 and RS-485 serial ports

3. Rear debugging port

4. AC current and voltage analog inputs

5. Binary inputs and outputs, DC current and voltage analog inputs

6. Power supply and standard I/O

8.2 Typical Wiring

B01 B02 & B03 B04 & B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 P1

NR6106BA NR6641-6I6U NR6641-12I Option Option Option Option Option Option Option NR6601A NR6651A NR6305A

01 Ia1 Ia1n 02 01 Ia1 Ia1n 02 01 BI_01 BI_02 02 01 BO_01 02 01 BI_01+ BI_01- 02

8 NET
03

05
Ib1

Ic1
Ib2n

Ic1n
04

06
03

05
Ib1

Ic1
Ib2n

Ic1n
04

06
03

05
BI_03

BI_05
BI_04

BI_06
04

06
03

05
BO_02

BO_03
04

06
03

05
BI_02+

BI_COM
BI_02-

BI_03
04

06

07 Ia2 Ia2n 08 07 Ia2 Ia2n 08 07 BI_07 BI_08 08 07 BO_04 08 07 BI_04 BI_05 08


LC
09 Ib2 Ib2n 10 09 Ib2 Ib2n 10 09 BI_09 BI_10 10 09 BO_05 10 09 BI_06 BI_07 10
LC
11 Ic2 Ic1n 12 11 Ic2 Ic1n 12 11 BI_11 BI_02 12 11 BO_06 12 11 BI_08 BI_09 12

13 Ua1 Ua1n 14 13 Ia3 Ia31n 14 13 BI_13 BI_02 14 13 BO_07 14 13 BO_01 14

15 Ub1 Ub1n 16 15 Ib3 Ib3n 16 15 BI_15 BI_02 16 15 BO_08 16 15 BO_02 16

17 Uc1 Uc1n 18 17 Ic3 Ic3n 18 17 BI_17 BI_02 18 17 BO_09 18 17 BO_03 18

01 1A 19 Ua2 Ua2n 20 19 Ia4 Ia14n 20 19 BI_19 BI_02 20 19 BO_10 20 19 BO_04 20


02 1B
03 SGND 21 Ub2 Ub2n 22 21 Ib4 Ib4n 22 21 BI_21 BI_02 22 21 BO_11 22 21 BO_05 22
04 2A
23 Uc2 Uc2n 24 23 Ic4 Ic4n 24 23 BI_23 BI_24 24 23 BO_12 24 23 BO_Fail 24
05 2B
06 SGND
25 BI_25 BI_COM 26 25 BO_13 26 25 PWR+ PWR- 26
07 SYN+
08 SYN-
09 SGND
10 SYN-TTL

CONSOLE
Ground

Figure 8.2-1 Typical hardware configuration

The wiring is given based on above hardware configuration

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0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212

0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0213
0214
Ia1 Ib1 Ic1 Ia2 Ib2 Ic2 Ua1 Ub1 Uc1 Ua2 Ub2 Uc2

BI_01 + 1301

Ethernet (RJ 45 and LC-


Connector)
BI_02 + 1302

To SCADA


BI_25 + 1325

1326 -

BI_01 + P101

- P102

BI_02 + P103

- P104

BI_03 + P106

1A 0101
COM

1B 0102 BI_04 + P107


SGND 0103
cable with single point earthing


To the screen of other coaxial

2A 0104
COM

2B 0105 BI_09 + P112


SGND 0106
P105 -
SYN+ 0107 P113
Clock SYN

SYN- 0108 BO_01 P114


SGND 0109 P115
TTL 0110 BO_02 P116

Console P121
BO_05 P122
1401 P123
1402 BO_01 BO_Fail P124
1403
1404 BO_02 P125
Power
PWR+
External DC power
8

1425 Supply P126 supply


PWR-
1426 BO_13

Grounding Bus
Ic4 Ib4 Ia4 Ic3 Ib3 Ia3 Ic2 Ib2 Ia2 Ic1 Ib1 Ia1
0414
0413
0424
0423
0422
0421
0420
0419
0418
0417
0416
0415

0412
0411
0410
0409
0408
0407
0406
0405
0404
0403
0402
0401

Figure 8.2-2 Typical wiring

PCS-978S Transformer Relay 8-5


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8 Hardware

8.3 CT Requirements

8.3.1 CT Types
Generally there are three types of CT: high remanence, low remanence and no remanence.

 High remanence: TPX, TPS, P, PX.

 Low remanence: TPY, PR, and the residual magnetism does not exceed 10% of the
saturation flux.

 No remanence: TPZ level, residual magnetism can actually be ignored.

The high residual magnetism CT may have large residual magnetism. When the fault
non-periodic component and residual magnetism are in the same direction, the CT saturation
degree will be more serious. The following CT type checking calculation takes into account
the maximum residual magnetism of CT and the maximum non periodic component on the
site.

8.3.2 CT Requirements
Rated secondary limit e.m.f (volts) formula:

Esl = Kalf × Isn × (Rct + Rbn)

Kalf Accuracy limit factor: Kalf = Ipal / Ipn

Isn Rated secondary current (amps)

Rct Current transformer secondary winding resistance (ohms)

Sbn Rated burden (VAs)

Rbn Rated resistance burden (ohms): Rbn = Sbn / Isn2

Actual secondary limit e.m.f (volts) under different fault conditions:

Esl1′ = k1×Ipcf1 ×Isn×(Rct+Rb)/Ipn


8
Esl2′ = k2×Ipcf2 ×Isn×(Rct+Rb)/Ipn

Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn

Esl4′ = k4×Ipcf4×Isn×(Rct+Rb)/Ipn

k1, k2, k3, k4 are transient factors.

Ipcf1 Maximum through fault current when out-zone fault (amps)

Maximum fault current through two bridge CB but not transformer when
Ipcf2
out-zone fault (amps)

Ipcf4 Maximum fault current when in-zone fault (amps)

Ipnt Transformer rated primary current (amps)


Ipn CT rated primary current (amps)

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Isn CT rated secondary current (amps)

Rct Current transformer secondary winding resistance (ohms)

Rb Real resistance burden (ohms): Rb = Rr + 2RL

RL Resistance of a single lead from relay to the CT (ohms)


Rr Impedance of relay phase current input (ohms)

8.3.3 K Value Requirements

8.3.3.1 For Transformer

1) Single CB connection, the following condition should be fulfilled

Esl > Esl1′

Esl > min (Esl3′, Esl4′)

While: k1=2,k3=30,k4=1.

2) Double CB connection, the following condition should be fulfilled:

Esl > Esl1′

Esl > Esl2′

Esl > min (Esl3′, Esl4′)

If both CTs of double CB are low remanence type, and with the same model, then k1=2,
k2=1.5, k3=30, k4=1.

Otherwise: k1=2,k2=2,k3=30,k4=1.

8.3.3.2 For Reactor

1) Single CB connection, the following condition should be fulfilled

Esl > min (Esl3′, Esl4′) 8


While: k3=30,k4=1.

When selecting CTs for 87R, the ratio between maximum rated primary value and
minimum rated primary value should not be greater than 10, and it is recommended to be
6.

2) Double CB connection, the following condition should be fulfilled:

Esl > Esl2′

Esl > min (Esl3′, Esl4′)

If both CTs of double CB are low remanence type, and with the same model, then k2=1.5,
k3=30, k4=1.

Otherwise: k2=2,k3=30,k4=1.

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8 Hardware

When selecting CTs for 87R, the ratio between maximum rated primary value and
minimum rated primary value should not be greater than 10, and it is recommended to be
6.

8.3.4 Example

For transformer applications, in single CB connection

Kalf=30, Isn=5A, Rct=1Ω, Sbn=60VA

Ipcf1=40000A, RL=0.5Ω, Rr=0.1Ω, Rc=0.1Ω, Ipn=2000A, Ipnt=1500A

Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/Isn2)

= 30×5×(1+60/25)=510V

Esl1′ = k1×Ipcf1×Isn×(Rct+Rb)/Ipn

= 2×Ipcf1 ×Isn×(Rct+(Rr+2×RL))/Ipn

= 2×40000×5×(1+(0.1+2×0.5))/2000=420V

Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn

=30×1500*5*(1+(0.1+2×0.5)) /2000=236.25V

Thus, Esl > Esl1′ and Esl > Esl3′, meeting the requirements.

8.4 Plug-in Module Description

The device consists of power supply module (PWR), main CPU module (CPU), AI module, BI
module, BO plug-in module and DC analog input plug-in module. Terminal definitions and
application of each plug-in module are introduced as follows.

8.4.1 Human-machine Interface Module (NR6855/NR6856)

8 The human machine interface (HMI) module is installed on the front panel of this device. It is used
to observe the running status and event information on the LCD, and configure the protection
settings and device operation mode. It can help the user to know the status of this device and
detailed event information easily, and provide convenient and friendly access interface for the
user.

8.4.2 Power Supply Module (NR6305/NR6310/NR6311)

The power supply module is a DC/DC converter with electrical insulation between input and
output. It has an input voltage range as described in Chapter 2 Technical Data. The standardized
output voltages are +5Vdc and +12Vdc. The tolerances of the output voltages are continuously
monitored.

The +5Vdc output provides power supply for all the electrical elements that need +5Vdc power
supply in this device.

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8 Hardware

The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device
is in cold reserve.

Figure 8.4-1 View of power supply module

Three types of power supply modules are provided: NR6305A, NR6310A and NR6311A.

The standard rated voltage of the PWR module is self-adaptive to the 8


range listed in the technical data. For a non-standard rated voltage power
supply module please specify when place order, and check if the rated
voltage of power supply module is the same as the voltage of power
source before the device being put into service.

The PWR module a grounding screw for device grounding. The grounding
screw shall be connected to grounding screw and then connected to the
earth copper bar of panel via dedicated grounding wire.

Effective grounding is the most important measure for a device to prevent


EMI, so effective grounding must be ensured before the device is put into
service.

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8 Hardware

8.4.2.1 NR6305A (input range: 88~300Vdc or 80~275Vac)

The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 26-pin connector is fixed on the power supply module. The terminal definition of
the connector is described as below.

Table 8.4-1 Terminal definition and description of power supply module NR6305A

Pin No. Symbol Description


01 BI_01+
The No.1 programmable binary input
02 BI_01-
03 BI_02+
The No.2 programmable binary input
04 BI_02-
05 BI_COM The common negative connection of the BI_01 to BI_09
06 BI_03 The No.3 programmable binary input
07 BI_04 The No.4 programmable binary input
08 BI_05 The No.5 programmable binary input
09 BI_06 The No.6 programmable binary input
10 BI_07 The No.7 programmable binary input
11 BI_08 The No.8 programmable binary input
12 BI_09 The No.9 programmable binary input
13
BO_01 The No.1 programmable binary output
14
15
BO_02 The No.2 programmable binary output
16
17
BO_03 The No.3 programmable binary output
18
19
BO_04 The No.4 programmable binary output
20
21
BO_05 The No.5 programmable binary output
8 22
23
BO_Fail The device failure signal output
24
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input

Grounded connection of the power supply

8.4.2.2 NR6310A (input range: 88~300Vdc or 80~275Vac)

The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 22-pin connector and a 4-pin connector are fixed on the power supply module.
The terminal definition of the connector is described as below.

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Table 8.4-2 Terminal definition and description of power supply module NR6310A

Pin No. Symbol Description


01 BI_01+
The No.1 programmable binary input
02 BI_01-
03 BI_02+
The No.2 programmable binary input
04 BI_02-
05 BI_COM The common negative connection of the BI_01 to BI_09
06 BI_03 The No.3 programmable binary input
07 BI_04 The No.4 programmable binary input
08 BI_05 The No.5 programmable binary input
09 BI_06 The No.6 programmable binary input
10 BI_07 The No.7 programmable binary input
11 BI_08 The No.8 programmable binary input
22-pin
12 BI_09 The No.9 programmable binary input
13
BO_01 The No.1 programmable binary output
14
15
BO_02 The No.2 programmable binary output
16
17
BO_03 The No.3 programmable binary output
18
19
BO_04 The No.4 programmable binary output
20
21
BO_05 The No.5 programmable binary output
22
23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input

Grounded connection of the power supply 8


8.4.2.3 NR6311A (input range: 18~72Vdc)

This power supply module provides 9 binary inputs, 5 binary outputs and a device failure binary
output. A 22-pin connector and a 4-pin connector are fixed on the power supply module. The
terminal definition of the connector is described as below.

Table 8.4-3 Terminal definition and description of power supply module NR6311A

Pin No. Symbol Description


01 BI_01+
The No.1 programmable binary input
02 BI_01-
22-pin
03 BI_02+
The No.2 programmable binary input
04 BI_02-

PCS-978S Transformer Relay 8-11


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8 Hardware

05 BI_COM The common negative connection of the BI_01 to BI_09


06 BI_03 The No.3 programmable binary input
07 BI_04 The No.4 programmable binary input
08 BI_05 The No.5 programmable binary input
09 BI_06 The No.6 programmable binary input
10 BI_07 The No.7 programmable binary input
11 BI_08 The No.8 programmable binary input
12 BI_09 The No.9 programmable binary input
13
BO_01 The No.1 programmable binary output
14
15
BO_02 The No.2 programmable binary output
16
17
BO_03 The No.3 programmable binary output
18
19
BO_04 The No.4 programmable binary output
20
21
BO_05 The No.5 programmable binary output
22
23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input

Grounded connection of the power supply

8.4.3 CPU Module (NR6106)

The CPU module is the central part of this device, and contains a multi-core 32-bit powerful
processor and some necessary electronic elements. This powerful processor performs all of the
functions for this device: protection function, communication function, human-machine interface
8 function and so on. There are several A/D conversion circuits on this module, which are used to
convert the AC analog signals to corresponding DC signals for fulfilling the demand of the
electrical level standard. A high-accuracy clock chip is contained in this module, it provide
accurate current time for this device.

The CPU module uses the internal bus to receive the data from other modules of the device. It
comprises 100BaseT Ethernet interfaces, RS-485 communication interfaces, PPS/IRIG-B
differential time synchronization interface and RS-232 printing interface, and supports
independent networking mode and mixed networking mode based on MMS/GOOSE/SV. By the
setting [B01.Opt_NetMode], the network mode of four Ethernet interfaces in CPU module can be
set as "Normal", "PRP" or "HSR" in station level.

The main functional details of the CPU module are listed as below:

 Protection calculation and logical judgment function

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The CPU module can calculate protective elements (such as overcurrent element) on the
basis of the analog sampled values (voltages and currents) and binary inputs, then it does
logical judgment function and decides whether the device needs to trip or close.

 Communication function

The CPU module can effectively manage all communication procedures, and reliably send
out some useful information through its various communication interfaces. These interfaces
are used to communicate with a SAS or a RTU. It also can communicate with the human
machine interface module. If an event occurs (such as SOE, protective tripping event etc.),
this module will send out the relevant event information through these interfaces, and make it
be easily observed by the user.

 Auxiliary calculation

Based on the voltage and current inputs, the CPU module also can calculate out the metering
values, such as active power, reactive power and power factor etc. All these values can be
sent to a SAS or a RTU through the communication interfaces.

 Human-machine interface function

This module can respond the commands from the keypad of this device and show the results
on the LCD and LED indicators of this device. It also can show the operation situation and
event information for the users through the LCD and LED indicators.

 Time synchronization

This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B
signal. Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on
the IRIG-B signal, this module can synchronize local clock with the standard clock.

The view of CPU module is shown in the following figure.

PCS-978S Transformer Relay 8-13


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8 Hardware

Figure 8.4-2 View of CPU module

Do NOT look into the end of an optical fiber connected to an optical port.

Do NOT look into an optical port/connector.

A direct sight to laser light may cause temporary or permanent blindness.

8 The configuration and terminal definition of the CPU modules are listed in following table

Table 8.4-4 Configuration and terminal definition of CPU module

Sampling
Module ID Interface Terminal No. Usage Physical Layer
Channel
Twisted-pair
2×RJ45 Ethernet
wire or optic
2×SFP (LC) communication
fibre
01 A
NR6106BA 36 RS-485 02 B To SCADA
03 SGND Twisted-pair
04 A wire
RS-485 05 B To SCADA
06 SGND

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Sampling
Module ID Interface Terminal No. Usage Physical Layer
Channel
07 SYN+
RS-485 08 SYN- To clock
09 SGND synchronization
TTL 10 SYN-TTL
RJ45 Debugging
Ethernet
4×SFP (LC)
communication Optic fibre
NR6106BH 36 ST-connector Time synchronization
Twisted-pair
RJ45 Ethernet Debugging
wire
Ethernet
4×SFP (LC) Optic fibre
communication
01 A
RS-485 02 B To SCADA
03 SGND
04 A
NR6106BJ 36 RS-485 05 B To SCADA
Twisted-pair
06 SGND
wire
07 SYN+
RS-485 08 SYN- To clock
09 SGND synchronization
TTL 10 SYN-TTL
RJ45 Ethernet Debugging
Twisted-pair
2×RJ45 Ethernet
wire or optic
2×SFP (LC) communication
fibre
01 A
RS-485 02 B To SCADA 8
03 SGND Twisted-pair
NR6106BP 36 04 A wire
RS-485 05 B To SCADA
06 SGND
To clock
BNC Coaxial cable
synchronization
Twisted-pair
RJ45 Ethernet Debugging
wire

The correct connection is shown in Figure 8.4-3. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface.

PCS-978S Transformer Relay 8-15


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8 Hardware

Twisted pair wire


A

COM
B

SGND

cable with single point earthing


To the screen of other coaxial
Twisted pair wire
SYN+

Clock SYN
SYN-

SGND

Cable
RTS

PRINT
TXD

SGND

Figure 8.4-3 Connection of communication terminal

Figure 8.4-4 Jumpers of printer/RS-485 port

8
The 2nd RS-485 port also can be configured as a printer port through the
jumpers “J10” and “J11”.

Jumper RS-485 Printer


J10 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
J11 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected

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8.4.4 NET-DSP Module (NR6113)

Figure 8.4-5 View of NET-DSP module

Do NOT look into the end of an optical fiber connected to an optical port.
8
Do NOT look into an optical port/connector.

A direct sight to laser light may cause temporary or permanent blindness.

The NR6113A/6113B module consists of high-performance DSP (digital signal processor),


NR6113A can provide twelve 100Mbit/s optical-fiber interfaces (LC type), and the first 4
optical-fiber interfaces can support PRP/HSR. NR6113B can provide four 1000Mbit/s optical-fiber
interfaces (LC type, the first 4 optical-fiber interfaces) and eight 100Mbit/s optical-fiber interfaces
(LC type), and the first 4 optical-fiber interfaces can support PRP/HSR.

It supports GOOSE and SV by IEC 61850-9-2 protocols and can be used for GOOSE & SV
message transmission by point-to-point connection or via LAN. It can receive and send GOOSE
messages to intelligent control device, and receive SV from MU (merging unit). Each interface can
be dedicated for GOOSE or SV message, it can also be shared by GOOSE & SV message.

PCS-978S Transformer Relay 8-17


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8 Hardware

8.4.5 AC Analog Input Module (NR6641)


The analog input module is applicable for power plant or substation with conventional VT and CT,
and it can transform high AC input values to relevant low AC output value, which are suited to the
analog inputs of the CPU module. The transformers are used both to step-down the currents and
voltages to levels appropriate to the device’s electronic circuitry and to provide effective isolation
between this device and the power system. A low pass filter circuit is connected to each
transformer (CT or VT) secondary circuit for reducing the noise of each analog AC input signal.

For the analog input module, if the plug is not put in the socket, external CT circuit is closed itself.
Just shown as below.

Plug
Socket

In

Out

plug is not put in the socket

In

Out

8
Put the plug in the socket

Figure 8.4-6 Schematic diagram of CT circuit automatically closed

There are two types of analog input modules. The rated current is adaptive (1A/5A). Please
declare which kind of AI module is needed before ordering. Maximum linear range of the current
converter is 40In.

 6CT+6VT

 8CT+4VT

 12CT

The terminal definition of the analog input module is shown as below.

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NR6641-6I6U NR6641-8I4U NR6641-12I


01 I1 I1n 02 01 I1 I1n 02 01 I1 I1n 02
03 I2 I2n 04 03 I2 I2n 04 03 I2 I2n 04
05 I3 I3n 06 05 I3 I3n 06 05 I3 I3n 06
07 I4 I4n 08 07 I4 I4n 08 07 I4 I4n 08
09 I5 I5n 10 09 I5 I5n 10 09 I5 I5n 10
11 I6 I6n 12 11 I6 I6n 12 11 I6 I6n 12
13 U1 U1n 14 13 I7 I7n 14 13 I7 I7n 14
15 U2 U2n 16 15 I8 I8n 16 15 I8 I8n 16
17 U3 U3n 18 17 U1 U1n 18 17 I9 I9n 18
19 U4 U4n 20 19 U2 U2n 20 19 I10 I10n 20
21 U5 U5n 22 21 U3 U3n 22 21 I11 I11n 22
23 U6 U6n 24 23 U4 U4n 24 23 I12 I12n 24

Figure 8.4-7 Terminal definition of analog input module

NEVER allow the current transformer (CT) secondary circuit connected to


this device to be opened while the primary system is energized. The
opened CT secondary circuit will produce a dangerously high voltage. If
this safety precaution is disregarded, personal death, severe personal
injury or considerable equipment damage will occur.

8
Each analog input channel can be configured according to practical
application through PCS-Studio.

8.4.5.1 Connection Examples

Some connection examples of the current transformers and voltage transformers which are
supported by this relay are shown in this section. If one of the analog inputs has no input in a
practical engineering, the relevant input terminals should be disconnected.

1. Current connections examples

PCS-978S Transformer Relay 8-19


Date: 2022-01-17
8 Hardware

A B C A B C
Ia Ia
Ian Ian
Ib Ib
Ibn Ibn
Ic Ic
Icn Icn
I01
I01n I01

(1) I01n

A B C (3)
Ia
Ian
Ib I0s

Ibn I0sn

Ic
(4)
Icn

I01 I02
I01n I02n

(2) (5)

Figure 8.4-8 Current connection examples

Where:

(1) Current connections to three current transformers with a star-point connection for ground
current (zero sequence current or residual current).

(2) Current connections to three current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer).

8 (3) Current connections to two current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer), only
for ungrounded or compensated networks.

(4) Current connection to a core balance neutral current transformer for sensitive ground
fault detection, only for ungrounded or compensated networks.

(5) Current connection to a separate ground current transformer (summation current


transformer or core balance current transformer) for the No.2 zero sequence current
input of this relay.

2. Voltage connections examples

8-20 PCS-978S Transformer Relay

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8 Hardware

A B C A B C

Ux
52 52 52 Ux 52 52 52
Uxn
Uxn

Ua Ua
Ub Ub
Uc Uc
Un Un

U0 U0
U0n U0n
(1) (2)

Figure 8.4-9 Voltage connection examples

Where:

(1) Voltage connections to three star-connected voltage transformers with open-delta


windings and additionally to any phase voltage (for synchronism check).

(2) Voltage connections to three star-connected voltage transformers with open-delta


windings and additionally to any phase-to-phase voltage (for synchronism check).

8.4.6 Binary Input Module (NR6601/NR6604/NR6610/NR6611)


The binary input module contains some binary inputs which are used to monitor the contact
positions of the corresponding bay, and all the binary inputs are configurable through PCS Studio
according to practical application.

There are five kinds of BI modules available, NR6601A, NR6604A, NR6610A, NR6610B and
NR6611A. The module NR6601A can provide 25 normal binary inputs (common negative supply,
ring ferrule), NR6610A and NR6610B can provide 32 normal binary inputs (common negative 8
supply, pin ferrule), NR6604A can provide 13 normal or high-power binary inputs (independent
negative supply, ring ferrule), and NR6611A can provide 14 normal or high-power binary inputs
(independent negative supply, pin ferrule).

The rated voltage of binary input is optional: 24Vdc, 30Vdc, 48Vdc, 110Vdc,
125Vdc, 220Vdc, 110Vac or 220Vac (@50Hz), which must be specified
when placed order. It is necessary to check whether the rated voltage of
binary input module complies with site DC power supply rating before put
this device in service.

PCS-978S Transformer Relay 8-21


Date: 2022-01-17
8 Hardware

Voltage

300

157.5

138.6

125

110

78.75

69.3

62.5
55 Operation

30.24
24 Operation uncertain
15.12
12
No operation
0 24V 48V 110V 125V 220V 250V

Figure 8.4-10 Voltage dependence for binary inputs

8.4.6.1 NR6601A

Each BI module is with a 26-pin connector for 25 binary inputs which share one common negative
power input and can be configurable. The pickup voltages and dropout voltages of the binary
8 inputs are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from
50%Un to 80%Un.

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01 BI_01 BI_02 02

03 BI_03 BI_04 04

05 BI_05 BI_06 06

07 BI_07 BI_08 08

09 BI_09 BI_10 10

11 BI_11 BI_12 12

13 BI_13 BI_14 14

15 BI_15 BI_16 16

17 BI_17 BI_18 18

19 BI_19 BI_20 20

21 BI_21 BI_22 22

23 BI_23 BI_24 24

25 BI_25 COM- 26

Figure 8.4-11 View of binary input module (NR6601A)

The terminal definition of the connector is described as below.

Table 8.4-5 Terminal definition and description of binary input module NR6601A

Pin No. Symbol Description


01 BI_01 The No.1 programmable binary input
02 BI_02 The No.2 programmable binary input
03
04
BI_03
BI_04
The No.3 programmable binary input
The No.4 programmable binary input
8
05 BI_05 The No.5 programmable binary input
06 BI_06 The No.6 programmable binary input
07 BI_07 The No.7 programmable binary input
08 BI_08 The No.8 programmable binary input
09 BI_09 The No.9 programmable binary input
10 BI_10 The No.10 programmable binary input
11 BI_11 The No.11 programmable binary input
12 BI_12 The No.12 programmable binary input
13 BI_13 The No.13 programmable binary input
14 BI_14 The No.14 programmable binary input
15 BI_15 The No.15 programmable binary input
16 BI_16 The No.16 programmable binary input

PCS-978S Transformer Relay 8-23


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8 Hardware

Pin No. Symbol Description


17 BI_17 The No.17 programmable binary input
18 BI_18 The No.18 programmable binary input
19 BI_19 The No.19 programmable binary input
20 BI_20 The No.20 programmable binary input
21 BI_21 The No.21 programmable binary input
22 BI_22 The No.22 programmable binary input
23 BI_23 The No.23 programmable binary input
24 BI_24 The No.24 programmable binary input
25 BI_25 The No.25 programmable binary input
26 BI_COM The common negative connection of the BI_01 to BI_25.

8.4.6.2 NR6604A

Each BI module is with a 26-pin connector for 13 binary inputs, each binary input has independent
negative power input and is configurable. The pickup voltages and drop-out voltages of the binary
inputs are settable by the setting [U_Pickup_BI] and [U_Dropout_BI], and the range is from
50%Un to 80%Un.

01 BI_01 Opto01- 02

03 BI_02 Opto02- 04

05 BI_03 Opto03- 06

07 BI_04 Opto04- 08

09 BI_05 Opto05- 10

11 BI_06 Opto06- 12

13 BI_07 Opto07- 14

8 15 BI_08 Opto08- 16

17 BI_09 Opto09- 18

19 BI_10 Opto10- 20

21 BI_11 Opto11- 22

23 BI_12 Opto12- 24

25 BI_13 Opto13- 26

Figure 8.4-12 View of binary input module (NR6604A)

The terminal definition of the connector is described as below.

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Table 8.4-6 Terminal definition and description of binary input module NR6604A

Pin No. Symbol Description


01 BI_01 Configurable binary input 1
02 Opto01- Negative pole of power supply of configurable binary input 1
03 BI_02 Configurable binary input 2
04 Opto02- Negative pole of power supply of configurable binary input 2
05 BI_03 Configurable binary input 3
06 Opto03- Negative pole of power supply of configurable binary input 3
07 BI_04 Configurable binary input 4
08 Opto04- Negative pole of power supply of configurable binary input 4
09 BI_05 Configurable binary input 5
10 Opto05- Negative pole of power supply of configurable binary input 5
11 BI_06 Configurable binary input 6
12 Opto06- Negative pole of power supply of configurable binary input 6
13 BI_07 Configurable binary input 7
14 Opto07- Negative pole of power supply of configurable binary input 7
15 BI_08 Configurable binary input 8
16 Opto08- Negative pole of power supply of configurable binary input 8
17 BI_09 Configurable binary input 9
18 Opto09- Negative pole of power supply of configurable binary input 9
19 BI_10 Configurable binary input 10
20 Opto10- Negative pole of power supply of configurable binary input 10
21 BI_11 Configurable binary input 11
22 Opto11- Negative pole of power supply of configurable binary input 11
23 BI_12 Configurable binary input 12
24 Opto12- Negative pole of power supply of configurable binary input 12
25 BI_13 Configurable binary input 13
26 Opto13- Negative pole of power supply of configurable binary input 13

8.4.6.3 NR6610A & NR6610B 8


Each BI module is with two 18-pin connectors for 32 binary inputs. The first 16 binary inputs share
one common negative power input and the last 16 binary inputs share another common negative
power input. All binary inputs are configurable. The pickup voltages and dropout voltages of the
binary inputs are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from
50%Un to 80%Un. The difference between NR6610A and NR6610B is that NR6610A equips
single AD sampling and NR6610B equips dual AD sampling.

PCS-978S Transformer Relay 8-25


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01 BI_01 19 BI_01

02 BI_02 20 BI_02

03 BI_03 21 BI_03

04 BI_04 22 BI_04

05 BI_05 23 BI_05

06 BI_06 24 BI_06

07 BI_07 25 BI_07

08 BI_08 26 BI_08

09 BI_09 27 BI_09

10 BI_10 28 BI_10

11 BI_11 29 BI_11

12 BI_12 30 BI_12

13 BI_13 31 BI_13

14 BI_14 32 BI_14

15 BI_15 33 BI_15

16 BI_16 34 BI_16

17 BI_COM 35 BI_COM

18 BI_COM 36 BI_COM

Figure 8.4-13 View of binary input module (NR6610A and NR6610B)

The terminal definition of the connector is described as below.

Table 8.4-7 Terminal definition and description of binary input module NR6610

Pin No. Symbol Description


01 BI_01 The No.1 programmable binary input
02 BI_02 The No.2 programmable binary input
03 BI_03 The No.3 programmable binary input
8 04 BI_04 The No.4 programmable binary input
05 BI_05 The No.5 programmable binary input
06 BI_06 The No.6 programmable binary input
07 BI_07 The No.7 programmable binary input
08 BI_08 The No.8 programmable binary input
18-pin
09 BI_09 The No.9 programmable binary input
10 BI_10 The No.10 programmable binary input
11 BI_11 The No.11 programmable binary input
12 BI_12 The No.12 programmable binary input
13 BI_13 The No.13 programmable binary input
14 BI_14 The No.14 programmable binary input
15 BI_15 The No.15 programmable binary input
16 BI_16 The No.16 programmable binary input

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8 Hardware

17 COM-
The common negative connection of the BI_01 to BI_16.
18 (01-16)
19 BI_17 The No.17 programmable binary input
20 BI_18 The No.18 programmable binary input
21 BI_19 The No.19 programmable binary input
22 BI_20 The No.20 programmable binary input
23 BI_21 The No.21 programmable binary input
24 BI_22 The No.22 programmable binary input
25 BI_23 The No.23 programmable binary input
26 BI_24 The No.24 programmable binary input
27 BI_25 The No.25 programmable binary input
18-pin
28 BI_26 The No.26 programmable binary input
29 BI_27 The No.27 programmable binary input
30 BI_28 The No.28 programmable binary input
31 BI_29 The No.29 programmable binary input
32 BI_30 The No.30 programmable binary input
33 BI_31 The No.31 programmable binary input
34 BI_32 The No.32 programmable binary input
35 COM-
The common negative connection of the BI_17 to BI_32.
36 (17-32)

8.4.6.4 NR6611A

Each BI module is with two 18-pin connectors for 14 binary inputs, each binary input has
independent negative power input and is configurable. The pickup voltages and drop-out voltages
of the binary inputs are settable by the setting [U_Pickup_BI] and [U_Dropout_BI], and the range
is from 50%Un to 80%Un.

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01 19

02 20

03 BI_01 21 BI_08

04 Opto01- 22 Opto08-

05 BI_02 23 BI_09

06 Opto02- 24 Opto09-

07 BI_03 25 BI_10

08 Opto03- 26 Opto10-

09 BI_04 27 BI_11

10 Opto04- 28 Opto11-

11 BI_05 29 BI_12

12 Opto05- 30 Opto12-

13 BI_06 31 BI_13

14 Opto06- 32 Opto13-

15 BI_07 33 BI_14

16 Opto07- 34 Opto14-

17 35

18 36

Figure 8.4-14 View of binary input module (NR6611A)

The terminal definition of the connector is described as below.

Table 8.4-8 Terminal definition and description of binary input module NR6611A

Pin No. Pin No. Symbol Description


01 Blank -
02 Blank -
03 BI_01 Configurable binary input 1
8 04 Opto01- Negative pole of power supply of configurable binary input 1
05 BI_02 Configurable binary input 2
06 Opto02- Negative pole of power supply of configurable binary input 2
07 BI_03 Configurable binary input 3
08 Opto03- Negative pole of power supply of configurable binary input 3
18-pin
09 BI_04 Configurable binary input 4
10 Opto04- Negative pole of power supply of configurable binary input 4
11 BI_05 Configurable binary input 5
12 Opto05- Negative pole of power supply of configurable binary input 5
13 BI_06 Configurable binary input 6
14 Opto06- Negative pole of power supply of configurable binary input 6
15 BI_07 Configurable binary input 7
16 Opto07- Negative pole of power supply of configurable binary input 7

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17 Blank -
18 Blank -
19 Blank -
20 Blank -
21 BI_08 Configurable binary input 8
22 Opto08- Negative pole of power supply of configurable binary input 8
23 BI_09 Configurable binary input 9
24 Opto09- Negative pole of power supply of configurable binary input 9
25 BI_10 Configurable binary input 10
26 Opto10- Negative pole of power supply of configurable binary input 10
27 BI_11 Configurable binary input 11
18-pin
28 Opto11- Negative pole of power supply of configurable binary input 11
29 BI_12 Configurable binary input 12
30 Opto12- Negative pole of power supply of configurable binary input 12
31 BI_13 Configurable binary input 13
32 Opto13- Negative pole of power supply of configurable binary input 13
33 BI_14 Configurable binary input 14
34 Opto14- Negative pole of power supply of configurable binary input 14
35 Blank -
36 Blank -

8.4.7 Binary Output Module (NR6651/NR6652/NR6660/NR6663)

The binary output module consists of some necessary contact outputs, and the binary outputs are
used as tripping and closing (protection, auto-reclosing or remote control) outputs or signal
outputs. It can receive tripping commands or closing commands from the CPU module, and then
executes these commands. It also can output some alarm signals from the CPU module.

The device can provide five types of binary output modules: NR6651A, NR6651B, NR6652A,
NR6660A and NR6663A.

8.4.7.1 NR6651A 8
The NR6651A provides 13 normally open contacts (NOC).

A 26-pin connector is fixed on the binary output module.

The terminal definition of the connector is shown in Figure 8.4-15.

PCS-978S Transformer Relay 8-29


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8 Hardware

BO_01 01 02

BO_02 03 04

BO_03 05 06

BO_04 07 08

BO_05 09 10

BO_06 11 12

BO_07 13 14

BO_08 15 16

BO_09 17 18

BO_10 19 20

BO_11 21 22

BO_12 23 24

BO_13 25 26

Figure 8.4-15 View of binary output module (NR6651A)

8.4.7.2 NR6651B

The NR6651B provides 11 normally open contacts (NOC, the first 11 contacts) and 2 normally
close contacts (NCC, the last 2 contacts).

A 26-pin connector is fixed on the binary output module.

The terminal definition of the connector is shown in Figure 8.4-16.


8

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BO_01 01 02

BO_02 03 04

BO_03 05 06

BO_04 07 08

BO_05 09 10

BO_06 11 12

BO_07 13 14

BO_08 15 16

BO_09 17 18

BO_10 19 20

BO_11 21 22

BO_12 23 24

BO_13 25 26

Figure 8.4-16 View of binary output module (NR6651B)

8.4.7.3 NR6652A

The NR6652A provides 4 normally open contacts (NOC, the first 4 contacts) with heavy capacity
for controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the
last 4 contacts).

A 26-pin connector is fixed on the binary output module.

The terminal definition of the connector is shown in Figure 8.4-17. 8

PCS-978S Transformer Relay 8-31


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8 Hardware

BO_01 01 02

03 04

BO_02 05 06

07 08

BO_03 09 10

11 12

BO_04 13 14

15 16

17 18

BO_05 19 20

BO_06 21 22

BO_07 23 24

BO_08 25 26

Figure 8.4-17 View of binary output module (NR6652A)

8.4.7.4 NR6660A

The NR6660A provides 15 normally open contacts (NOC) and 2 normally open contacts &
normally close contacts (NOC/NCC).

Two 18-pin connectors are fixed on the binary input module.

The terminal definition of the connector is shown in Figure 8.4-18.


8

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BO_01 01 02

BO_02 03 04

BO_03 05 06

BO_04 07 08

18-pin
BO_05 09 10

BO_06 11 12

BO_07 13 14

BO_08 15 16

BO_09 17 18

BO_10 19 20

BO_11 21 22

BO_12 23 24

BO_13 25 26

BO_14 27 28
18-pin

BO_15 29 30

BO_16 32
31
BO_16 33

BO_17 35
34
BO_17 36

Figure 8.4-18 View of binary output module (NR6660A)

8.4.7.5 NR6663A

The NR6663A provides 4 normal open contacts (NOC, the first 4 contacts) with heavy capacity for
controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the last
4 contacts).

Two 18-pin connectors are fixed on the binary input module.

The terminal definition of the connector is shown as below. 8

PCS-978S Transformer Relay 8-33


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8 Hardware

01 02

03 04
BO_01

Heavy-capacity tripping contact


05 06

07 08
BO_02
09 10

11 12
BO_03
13 14

15 16
BO_04
17 18

19 20

21 22

General tripping/signaling contact


BO_05
23 24

25 26
BO_06
27 28

29 30
BO_07
31 32

33 34
BO_08
35 36

Figure 8.4-19 View of binary output module (NR6663A)

Each binary output can be set as a specified tripping output contact or a


signal output contact through PCS-Studio according to practical
application.

8.4.8 Binary Input and Binary Output Module (NR6661)


8
The binary input and output module contains both binary inputs and contact outputs.

The rated voltage of binary input is optional: 24Vdc, 48Vdc, 110Vdc,


125Vdc, 220Vdc, 250Vdc, 110Vac or 220Vac (@50Hz). It is necessary to
check whether the rated voltage of binary input module complies with site
DC power supply rating before put this device in service.

Each IO module is with two 18-pin connectors for 16 binary inputs, 6 normally open contacts
(NOC) and 2 normally open contacts & normally close contacts (NOC/NCC). The 16 binary inputs
share one common negative power input. All binary inputs are configurable. The pickup voltages
and dropout voltages of the binary inputs are settable by the setting [U_Pickup_BI] and
[U_Dropoff_BI], and the range is from 50%Un to 80%Un.

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Two 18-pin connectors are fixed on the binary input module.

01 BI_01

02 BI_02

03 BI_03

04 BI_04

05 BI_05

06 BI_06

07 BI_07

08 BI_08

09 BI_09 BO_01 19 20

10 BI_10 BO _02 21 22

11 BI_11 BO_03 23 24

12 BI_12 BO _04 25 26

13 BI_13 BO_05 27 28

14 BI_14 BO _06 29 30

15 BI_15 BO_07_NO 32
31
16 BI_16 BO_07_NC 33
COM-
17 (01-16) BO_08_NO 35
COM-
34
18 BO_08_NC 36
(01-16)

Figure 8.4-20 View of binary input and binary output module (NR6661A)

The terminal definition of NR6661A is described as below.

Table 8.4-9 Terminal definition and description of BIBO module NR6661A

Pin No. Symbol Description


01 BI_01 The No.1 programmable binary input
02 BI_02 The No.2 programmable binary input 8
03 BI_03 The No.3 programmable binary input
04 BI_04 The No.4 programmable binary input
05 BI_05 The No.5 programmable binary input
06 BI_06 The No.6 programmable binary input
07 BI_07 The No.7 programmable binary input
18-pin 08 BI_08 The No.8 programmable binary input
09 BI_09 The No.9 programmable binary input
10 BI_10 The No.10 programmable binary input
11 BI_11 The No.11 programmable binary input
12 BI_12 The No.12 programmable binary input
13 BI_13 The No.13 programmable binary input
14 BI_14 The No.14 programmable binary input
15 BI_15 The No.15 programmable binary input

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8 Hardware

16 BI_16 The No.16 programmable binary input


17 COM-
The common negative connection of the BI_01 to BI_16.
18 (01-16)
19 The No.01 binary output contact. It is a normally open contact
BO_01
20 (NOC).
21
BO_02 The No.02 binary output contact. It is a normally open contact.
22
23
BO_03 The No.03 binary output contact. It is a normally open contact.
24
25
BO_04 The No.04 binary output contact. It is a normally open contact.
26
27
18-pin BO_05 The No.05 binary output contact. It is a normally open contact.
28
29
BO_06 The No.06 binary output contact. It is a normally open contact.
30
31
The No.07 binary output contact. It can be selected as a normally
32 BO_07
open contact or a normally closed contact (NCC).
33
34
The No.08 binary output contact. It can be selected as a normally
35 BO_08
open contact or a normally closed contact.
36

Each binary output can be set as a specified tripping output contact or a


signal output contact through PCS-Studio according to practical
application.

8.4.9 Mechanical Relay Input and Output Module (NR6662)

8 The mechanical relay input and output module NR6662 can provide five binary inputs and three
groups of normally open contacts for mechanical protection. This module is used to output various
signals, such as, trip signal, alarm signal and disturbance & fault recording signal, etc.

There are three kinds of optional MR IO modules, NR6662A (220Vdc), NR6662B (110Vdc) and
NR6662N (125Vdc).

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01 BI_COM 19 BO_COM_ 2
02 BI_COM 20 BO_COM_ 2
03 21 BO_MR1_2
Binary input
04 signals of BI_MR1 22 BO_MR2_2
05 mechanical BI_MR2 23 BO_MR3_2
protection
06 BI_MR3 24 BO_MR4_2
07 BI_MR4 25 BO_MR5_2
08 BI_MR5 26
09 27 BO_COM_ 3
10 BO_COM_ 1 28 BO_COM_ 3
11 BO_COM_ 1 29 BO_MR1_3
12 BO_MR1_1 30 BO_MR2_3
13 BO_MR2_1 31 BO_MR3_3
14 BO_MR3_1 32 BO_MR4_3
15
16
BO_MR4_1
BO_MR5_1
33
34
BO_MR5_3
8
17 35
18 36

Figure 8.4-21 View of MR IO plug-in module (NR6662A, NR6662B and NR6662N)

Table 8.4-10 Terminal definition and description of MR IO module

Pin No. Symbol Description


Mechanical signal inputs
01
BI_COM The common negative connection of BI_MR1 to BI_MR5.
02
03 Blank Not used
04 BI_MR1 Mechanical relay (MR) signal input 1
05 BI_MR2 Mechanical relay (MR) signal input 2

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Pin No. Symbol Description


06 BI_MR3 Mechanical relay (MR) signal input 3
07 BI_MR4 Mechanical relay (MR) signal input 4
08 BI_MR5 Mechanical relay (MR) signal input 5
09 Blank Not used
st
1 group of output contacts
10
BO_COM_1 The common terminal of the BO_MR1_1 to BO_MR5_1.
11
12 BO_MR1_1 NO contact, is closed when binary input [BI_MR1] is energized.
13 BO_MR2_1 NO contact, is closed when binary input [BI_MR2] is energized.
14 BO_MR3_1 NO contact, is closed when binary input [BI_MR3] is energized.
15 BO_MR4_1 NO contact, is closed when binary input [BI_MR4] is energized.
16 BO_MR5_1 NO contact, is closed when binary input [BI_MR5] is energized.
17 Blank Not used
18 Blank Not used
nd
2 group of output contacts
19
BO_COM_2 The common terminal of the BO_MR1_2 to BO_MR5_2.
20
21 BO_MR1_2 NO contact, is closed when binary input [BI_MR1] is energized.
22 BO_MR2_2 NO contact, is closed when binary input [BI_MR2] is energized.
23 BO_MR3_2 NO contact, is closed when binary input [BI_MR3] is energized.
24 BO_MR4_2 NO contact, is closed when binary input [BI_MR4] is energized.
25 BO_MR5_2 NO contact, is closed when binary input [BI_MR5] is energized.
26 Blank Not used
3rd group of output contacts
27
BO_COM_3 The common terminal of the BO_MR1_3 to BO_MR5_3.
28
29 BO_MR1_3 NO contact, is closed when binary input [BI_MR1] is energized.

8 30
31
BO_MR2_3
BO_MR3_3
NO contact, is closed when binary input [BI_MR2] is energized.
NO contact, is closed when binary input [BI_MR3] is energized.
32 BO_MR4_3 NO contact, is closed when binary input [BI_MR4] is energized.
33 BO_MR5_3 NO contact, is closed when binary input [BI_MR5] is energized.
34 Blank Not used
35 Blank Not used
36 Blank Not used

8.4.10 DC Analog Input Module (NR6630/NR6631)

The DC analog input module can provide 0~±20mA or 0~±10V input channels.

This device provides two types of DC analog input modules: NR6630A and NR6631A.

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8.4.10.1 NR6630A

The NR6630A provides 12 channels of 0~±20mA or 0~±10V inputs, and all channels can be set
as 0~±20mA or 0~±10V DC signal inputs respectively through the jumpers on the module and the
related channel type setting.

Module ID Jumper 0~±20mA 0~±10V


NR6630A J1~J12 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected

Figure 8.4-22 View of DC analog input module NR6630A

Two 18-pin connectors are fixed on this DC analog input module. The terminal definition of the 8
connector on the module NR6630A is listed as below.

Table 8.4-11 Terminal definition and description of DC analog input module NR6630A

Pin No. Symbol Description


01 DCAI_01+
The No.1 DC analog input channel
02 DCAI_01-
03 GND The grounding terminal
04 DCAI_02+
The No.2 DC analog input channel
05 DCAI_02-
06 GND The grounding terminal
07 DCAI_03+
The No.3 DC analog input channel
08 DCAI_03-
09 GND The grounding terminal

PCS-978S Transformer Relay 8-39


Date: 2022-01-17
8 Hardware

10 DCAI_04+
The No.4 DC analog input channel
11 DCAI_04-
12 GND The grounding terminal
13 DCAI_05+
The No.5 DC analog input channel
14 DCAI_05-
15 GND The grounding terminal
16 DCAI_06+
The No.6 DC analog input channel
17 DCAI_06-
18 GND The grounding terminal

19 DCAI_07+
The No.7 DC analog input channel
20 DCAI_07-
21 GND The grounding terminal
22 DCAI_08+
The No.8 DC analog input channel
23 DCAI_08-
24 GND The grounding terminal
25 DCAI_09+
The No.9 DC analog input channel
26 DCAI_09-
27 GND The grounding terminal
28 DCAI_10+
The No.10 DC analog input channel
29 DCAI_10-
30 GND The grounding terminal
31 DCAI_11+
The No.11 DC analog input channel
32 DCAI_11-
33 GND The grounding terminal
34 DCAI_12+
The No.12 DC analog input channel
35 DCAI_12-
36 GND The grounding terminal

8 8.4.10.2 NR6631A

The NR6631A provides 8 channels of 0~±20mA or 0~±10V inputs, and all channels can be set as
0~±20mA or 0~±10V DC signal inputs respectively through the jumpers on the module and the
related channel type setting.

Module ID Jumper 0~±20mA 0~±10V


NR6631A J1~J8 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected

8-40 PCS-978S Transformer Relay

Date: 2022-01-17
8 Hardware

Figure 8.4-23 View of DC analog input module NR6631A

A 26-pin connector is fixed on this DC analog input module.

The terminal definition of the connector of the module NR6631A is listed as below.

Table 8.4-12 Terminal definition and description of DC analog input module NR6631A

Pin No. Symbol Description


01 DCAI_01+
The No.1 DC analog input channel
02 DCAI_01- 8
03 GND The grounding terminal
04 DCAI_02+
The No.2 DC analog input channel
05 DCAI_02-
06 DCAI_03+
The No.3 DC analog input channel
07 DCAI_03-
08 GND The grounding terminal
09 DCAI_04+
The No.4 DC analog input channel
10 DCAI_04-
11 DCAI_05+
The No.5 DC analog input channel
12 DCAI_05-
13 GND The grounding terminal
14 DCAI_06+
The No.6 DC analog input channel
15 DCAI_06-

PCS-978S Transformer Relay 8-41


Date: 2022-01-17
8 Hardware

Pin No. Symbol Description


16 DCAI_07+
The No.7 DC analog input channel
17 DCAI_07-
18 GND The grounding terminal
19 DCAI_08+
The No.8 DC analog input channel
20 DCAI_08-
21 Empty
22 Empty
23 Empty
24 Empty
25 Empty
26 Empty

8-42 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

9 Settings

Table of Contents

9.1 Global Settings ................................................................................................ 9-1


9.1.1 System Settings.................................................................................................................... 9-1

9.1.2 Device Settings..................................................................................................................... 9-5

9.1.3 Communication Settings ...................................................................................................... 9-7

9.1.4 Disturbance Fault Recording Settings ............................................................................... 9-24

9.1.5 Label Settings ..................................................................................................................... 9-24

9.1.6 Clock Synchronization Settings .......................................................................................... 9-24

9.1.7 Supervision Settings ........................................................................................................... 9-28

9.1.8 OutMap Settings ................................................................................................................. 9-28

9.2 Protection Settings ........................................................................................ 9-28


9.2.1 Transformer Current Differential Protection (87T).............................................................. 9-28

9.2.2 Restricted Earth Fault Protection (64REF) ........................................................................ 9-30

9.2.3 Winding Differential Protection (87W) ................................................................................ 9-30

9.2.4 Reactor Current Differential Protection (87R) .................................................................... 9-31

9.2.5 Inter-turn Fault Protection (21IT) ........................................................................................ 9-31

9.2.6 Overexcitation Protection (24) ............................................................................................ 9-32

9.2.7 Phase Overcurrent Protection (50/51P) ............................................................................. 9-34

9.2.8 Earth Fault Overcurrent Protection (50/51G) ..................................................................... 9-38

9.2.9 Negative-sequence Overcurrent Protection (50/51Q) ....................................................... 9-41


9
9.2.10 Thermal Overload Protection (49) .................................................................................... 9-44

9.2.11 Breaker Failure Protection (50BF) .................................................................................... 9-45

9.2.12 Phase Overvoltage Protection (59P) ............................................................................... 9-46

9.2.13 Residual Overvoltage Protection (59G) ........................................................................... 9-48

9.2.14 Phase Undervoltage Protection (27P) ............................................................................. 9-48

9.2.15 Overfrequency Protection (81O) ...................................................................................... 9-51

9.2.16 Underfrequency Protection (81U) .................................................................................... 9-51

PCS-978S Transformer Relay 9-a


Date: 2022-01-17
9 Settings

9.2.17 Frequency Rate-of-change Protection (81R) ................................................................... 9-52

9.2.18 Distance Protection (21T) ................................................................................................ 9-52

9.3 Measurement and Control Settings ............................................................. 9-55


9.3.1 Function Settings ................................................................................................................ 9-55

9.3.2 Synchronism Check Settings ............................................................................................. 9-56

9.3.3 Double Point Status Settings ............................................................................................. 9-58

9.3.4 Control Settings .................................................................................................................. 9-58

9.3.5 Tap Position Indicator Settings ........................................................................................... 9-59

9.3.6 Interlocking Logic Settings ................................................................................................. 9-61

9.3.7 DC Measuring Transducers Settings ................................................................................. 9-62

9.3.8 Energy Metering Settings ................................................................................................... 9-62

9.3.9 Automatic Voltage Regulation Settings .............................................................................. 9-62

9.3.10 Parallel Voltage Regulation Settings ................................................................................ 9-64

9.4 Logic Links ..................................................................................................... 9-64


9.4.1 Function Links .................................................................................................................... 9-64

9.4.2 GOOSE Sending Links....................................................................................................... 9-64

9.4.3 GOOSE Receiving Links .................................................................................................... 9-64

9.4.4 SV Receiving Links ............................................................................................................ 9-65

List of Tables

Table 9.1-1 Matrix of phase compensation ............................................................................. 9-4

9-b PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

In the chapter, the prefix ”x.” in some settings, represents some side or
bushing of transformer defined by user through PCS-Studio software,
which may be “HVS”, “MVS”, “LVS”, “HVS2”, “MVS2”, “LVS2”, “CWS”,
“HVB”, “MVB”, “LVB”, etc. If only one protection element is equipped, the
prefix “x.” may disappear.

9.1 Global Settings

9.1.1 System Settings


Access path: MainMenu  Settings  Global Settings  System Settings

No. Settings Range Unit Default Remark


The number of active setting group,
several setting groups can be
1 Active_Grp 1~20 - 1
configured for protection settings, and
only one is active at a time.
2 Opt_SysFreq 50.0, 60.0 Hz 50.0 The system frequency.
Name of the protected primary
Max 20
3 PrimaryEquip_Name - - equipment, such as busbar,
characters
transformer, etc.
4 Sn 0.100~5000.000 MVA 500.000 Transformer or reactor capacity
Transformer HV-side primary rated
5 HVS.U1n_Plate 0.000~9999.000 kV 220.000
voltage stated on the nameplate
Transformer MV-side primary rated
6 MVS.U1n_Plate 0.000~9999.000 kV 110.000
voltage stated on the nameplate
Transformer LV-side primary rated
7 LVS.U1n_Plate 0.000~9999.000 kV 10.000
voltage stated on the nameplate
8 U1n 0.000~2000.000 kV 220.000 Reactor rated voltage
9 Zn_Reac_NP 0.000~10000.000 ohm 500.000 Impedance of neutral earthing reactor
Wiring o′clock of MV side with respect
10 Clk_MVS_WRT_HVS 0~11 Clk 0
to HV side 9
Wiring o′clock of LV side with respect
11 Clk_LVS_WRT_HVS 0~11 Clk 11
to HV side
The target o′clock that each side
12 Clk_PhComp 0~11 Clk 0 current will be shift to for phase
compensation
Logic setting of enabling/disabling
Enabled, zero-sequence current elimination for
13 HVS.En_I0Elim - Enabled
Disabled phase compensation of HV side of
transformer.

PCS-978S Transformer Relay 9-1


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


Logic setting of enabling/disabling
Enabled, zero-sequence current elimination for
14 MVS.En_I0Elim - Enabled
Disabled phase compensation of MV side of
transformer.
Logic setting of enabling/disabling
Enabled, zero-sequence current elimination for
15 LVS.En_I0Elim - Enabled
Disabled phase compensation of LV side of
transformer.
Rated primary voltage value of VT at x
16 x.U1n 0.000~1100.000 kV -
side of transformer
Rated secondary voltage value of VT
17 x.U2n 1.000~200.000 V -
at x side of transformer
Primary rated voltage of broken-delta
18 x.Neu.U1n 0.000~1100.000 kV -
VT at x side of transformer
Secondary rated voltage of
19 x.Neu.U2n 1.000~200.000 V - broken-delta VT at x side of
transformer
Primary voltage values of VT of
20 25.Ref.U1n 0.00~1100.00 kV 110.00
reference side of synchronism check
Secondary voltage values of VT of
21 25.Ref.U2n 1.00~200.00 V 100.00
reference side of synchronism check
Primary voltage values of VT of
22 25.Syn.U1n 0.00~1100.00 kV 110.00 synchronism side of synchronism
check
Secondary voltage values of VT of
23 25.Syn.U2n 1.00~200.00 V 100.00 synchronism side of synchronism
check
Primary rated current of CT at x side
24 x.I1n 0~9999 A 1000
of transformer
Secondary rated current of CT at x
25 x.I2n 1 or 5 A 1
side of transformer
Primary rated current of neutral CT at
26 x.Neu.I1n 0~9999 A 1000
9 x side of transformer
Secondary rated current of neutral CT
27 x.Neu.I2n 1 or 5 A 1
at x side of transformer
Enabled,
28 x.En_VT - Enabled Logic setting to put VT into service
Disabled
NoVolSel,
DblBusOneCB, Selection of circuit breaker
29 x.VoltSel.Opt_CBConfig - NoVolSel
3/2BusCB, arrangement for voltage selection.
3/2TieCB.
Enabled, Logic setting of enabling/disabling the
30 x.En_RevCT - Disabled
Disabled current polarity of CT reversed

9-2 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


Logic setting of enabling/disabling the
Enabled,
31 x.Neu.En_RevCT - Disabled current polarity of neutral CT
Disabled
reversed.
32 Opt_PhSeq ABC, ACB - ABC Option of phase sequence.

 [HVS.U1n_Plate], [MVS.U1n_Plate], [LVS.U1n_Plate], [U1n]

They are the primary rated voltages at x side of transformer or reactor marked on the
nameplate.

The setting principle of rated phase-to-phase voltages of each side is to take the primary
rated voltage marked on the nameplate of transformer as the primary rated voltage of
corresponding side. For an on-load tap changing transformer, the voltage of transformer with
tap in middle position is taken as the value of this setting.

For one side not used in the device, please set the primary rated voltage
value of the corresponding side as “0”.

 [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]

They are the wiring o′clock of MV/LV side with respect to HV side, is the parameter shown on
transformer nameplate with the range of 0~11, and need not further calculation.

 [Clk_PhComp]

It is the target o′clock each side current will be shift to for phase compensation.

For examples:

The vector group of a transformer is Y0/Δ11 and the target o′clock ([Clk_PhComp]) is set to
“11”. Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.

 For HV side, the clock of HV side with reference to target o′clock is 1 (i.e. wiring o′clock
12-target o′clock 11) clock, so the matrix of relative o′clock 1 is adopted to compensate
HV side current. Zero-sequence current elimination has no effect on phase
compensation in the condition.
9
 For LV side, the clock of LV side with reference to target o′clock is 0 (i.e. wiring o′clock 11-
target o′clock 11), so the matrix of relative o′clock 0 is adopted to compensate LV side
current. Then it is needed to decide whether zero-sequence current is eliminated and
select the corresponding matrix.

If an earthing transformer is connected at LV side out the protection zone of differential


protection, then matrix of relative o′clock 0 without zero-sequence current elimination can be
selected.

If an earthing transformer is connected at LV side in the protection zone of differential


protection, then zero-sequence current must be eliminated and otherwise differential

PCS-978S Transformer Relay 9-3


Date: 2022-01-17
9 Settings

protection may operate unexpectedly during an external fault. Therefore the matrix of relative
o′clock 0 with zero-sequence current elimination should be selected.

Table 9.1-1 Matrix of phase compensation

Relative Matrix (without zero-sequence current Matrix (with zero-sequence current


o'clock elimination) elimination)

 1 0 0  2  1  1
0
0 1 0 1 
  1 2  1
  3
0 0 1  1  1 2

 1  1 0
1 
1   0 1  1
3
 1 0 1

 0  1 0  1  2 1
2
 0 0 1  1 
  1 1  2
  3
 1 0 0  2 1 1

 0  1 1
1 
3   1 0  1
3
 1 1 0

0 0 1   1  1 2
1 
4
 1 0 0
    2  1  1
3
0 1 0  1 2  1

 1 0 1
1 
5   1  1 0
3
 0 1  1

 1 0 0  2 1 1
6
 0  1 0 1 
 1  2 1
  3 
 0 0  1  1 1  2
9
  1 1 0
1 
7   0  1 1
3
 1 0  1

 0 1 0  1 2  1 
8
0 0 1
1 
  1  1 2 
 3
 1 0 0  2  1  1

9-4 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

Relative Matrix (without zero-sequence current Matrix (with zero-sequence current


o'clock elimination) elimination)

 0 1  1
1 
9   1 0 1
3
 1  1 0
 0 0  1  1 1  2
10
 1 0 0
1 
  2 1 1
 3
 0  1 0  1  2 1

 1 0  1
1 
11   1 1 0
3
 0  1 1

 [x.En_RevCT]

It is used to adjust the current polarity of CT at x side of transformer, and default value is
Disabled.

Disabled: keep connected current polarity unchanged

Enabled: make connected current polarity reversed

When the current polarity of primary CT is different with defined forward direction by
PCS-978S, the setting can be set as “Enabled”. However, it is recommended to change
external wiring of primary CT.

9.1.2 Device Settings


Access path: MainMenu  Settings  Global Settings  Device Settings

No. Settings Range Unit Default Remark


Enabling/disabling the debugging port. Used
Disabled
1 En_DebugPort - Enabled for debugging tool connection, program
Enabled
download, variable debugging, etc.
Disabled
2 En_TelnetPort - Enabled Enabling/disabling the Telnet port.
Enabled
9
Disabled Enabling/disabling connect to the device via
3 En_VirtualLCDPort - Enabled
Enabled the software Teldevice
4 Ctrl_Password 000~999 - 111 The control password via local LCD
Disabled
5 En_NoCtrlPwd - Disabled Override control password via local LCD
Enabled
Enabled: all the events (including
Disabled disturbance records, supervision events, IO
6 En_PopupRecord_Blkd - Disabled
Enabled events, control events) will not pop up
automatically in the main graph of local LCD,

PCS-978S Transformer Relay 9-5


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


they can only be viewed by entering
corresponding menus.
Disabled: these events can pop up in the
main graph of local LCD automatically.
DC
7 Opt_Pwr_BI AC50Hz - DC Power supply mode of binary input module
AC60Hz
This setting is used to set voltage level of
8 B**.Un_BinaryInput 24~250 V 220
binary input module slot B**
This setting is used to set voltage level of
9 P1.Un_BinaryInput 24~250 V 220
binary input of PWR module
This setting is used to set pickup voltage of
10 U_Pickup_BI 50.0~80.0 % 63.0
binary input module.
This setting is used to set dropoff voltage of
11 U_Dropoff_BI 50.0~80.0 % 55.0
binary input module.
The logic setting to enable/disable the jitter
Disabled
12 En_Jitter_Blk - Disabled processing function in case of binary input
Enabled
voltage variation
Monitoring window of binary input jitter
13 Mon_Window_Jitter 0.000~500.000 s 1.000
processing
Times threshold to block binary input status
14 Num_Blk_Jitter 2~500000 - 10
change due to jitter
Blocking window of binary input status
15 Blk_Window_Jitter 0.000~500.000 s 1.000
change due to jitter
Times threshold to initiate immediately
16 Num_Reblk_Jitter 1~500000 - 10 another blocking window of binary input
status change due to continuous jitter
Enabled: Conducting mode by high power
with constant current drain of binary inputs is
enabled. Now the binary input will be
considered to be energized only when the
instantaneous active power rises to a certain

9 value together with constant current drain


during this mode, so as to avoid mistaken
Disabled signal.
17 B**.En_BICheckInstP - Disabled
Enabled Disabled: Conducting mode by high power
with constant current drain of binary inputs is
disabled. Now the binary input will be
considered to be energized with constant
current drain without checking the
instantaneous active power.
The conducting mode by high power with
constant current drain of binary inputs is only

9-6 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


available in the device equipped with some
certain modules (e.g.: NR6604A, NR6611A).
If these modules are not equipped, this
conducting mode will be unavailable, so this
setting will be hidden.
This setting cooperates with the BI
debouncing time configuration of this device.

9.1.3 Communication Settings

9.1.3.1 General Communication Settings

Access path: MainMenu  Settings  Global Settings  Comm Settings  General Comm
Settings

No. Settings Range Unit Default Remark


0.0.0.0~ IP address of Ethernet port
1 IP_LAN1 - 172.16.0.100
255.255.255.255 A
0.0.0.0~ Subnet mask of Ethernet
2 Mask_LAN1 - 255.255.0.0
255.255.255.255 port A
0.0.0.0~ IP address of Ethernet port
3 IP_LAN2 - 172.17.0.100
255.255.255.255 B
0.0.0.0~ Subnet mask of Ethernet
4 Mask_LAN2 - 255.255.0.0
255.255.255.255 port B
0.0.0.0~ IP address of Ethernet port
5 IP_LAN3 - 172.18.0.100
255.255.255.255 C
0.0.0.0~ Subnet mask of Ethernet
6 Mask_LAN3 - 255.255.0.0
255.255.255.255 port C
0.0.0.0~ IP address of Ethernet port
7 IP_LAN4 - 172.19.0.100
255.255.255.255 D
0.0.0.0~ Subnet mask of Ethernet
8 Mask_LAN4 - 255.255.0.0
255.255.255.255 port D
Disabled Put Ethernet port A into
9 En_LAN1 - Enabled
Enabled
Disabled
service
Put Ethernet port B into
9
10 En_LAN2 - Enabled
Enabled service
Disabled Put Ethernet port C into
11 En_LAN3 - Disabled
Enabled service
Disabled Put Ethernet port D into
12 En_LAN4 - Disabled
Enabled service
Normal;
The network method of the
1-2:Normal, 3-4:HSR;
13 B01.Opt_NetMode - Normal CPU module located in
1-2:Normal, 3-4:PRP;
slot No.1
1-2:Normal, 3-4:RSTP;

PCS-978S Transformer Relay 9-7


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


1-2:PRP, 3-4:PRP.
The network method of the
Normal
1st group interface of the
14 B02.Grp01.Opt_NetMode HSR - Normal
NET-DSP module NR6113
PRP
located in slot No.2.
The network method of the
Normal
2nd group interface of the
15 B02.Grp02.Opt_NetMode HSR - Normal
NET-DSP module NR6113
PRP
located in slot No.2.
4800
9600
19200
16 Baud_Printer bps 19200 Baud rate of printer port
38400
57600
115200
Disabled Enable/disable automatic
17 En_AutoPrint - Disabled
Enabled printing function
Communication protocol of
rear RS-485 serial port 1.
IEC103
18 Protocol_RS485-1 - IEC103 IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
Communication protocol of
rear RS-485 serial port 2.
IEC103
19 Protocol_RS485-2 - IEC103 IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
4800
9600
19200 Baud rate of rear RS-485
20 Baud_RS485-1 bps 19200
38400 serial port 1.
57600

9 115200
4800
9600
19200 Baud rate of rear RS-485
21 Baud_RS485-2 bps 19200
38400 serial port 2.
57600
115200
Communication address
between the device and
22 Addr_RS485-1 1~254 - 100
the SCADA or RTU via
RS-485 serial port 1.

9-8 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


Communication address
between the device and
23 Addr_RS485-2 1~254 - 100
the SCADA or RTU via
RS-485 serial port 2.
0.0.0.0~ IP address of the gateway
24 Gateway - 0.0.0.0
255.255.255.255 (router)
To set the channel bonding
25 Cfg_NetPorts_Bond 0, 3, 5, 6, 9, 10, 12 - 0 arrangement of two
Ethernet ports
The setting is used to set
IP address of syslog server
01, and the device can
upload audit log to syslog
server. The setting is
invalid unless cyber
0.0.0.0~
26 IP_SyslogServer01 - 0.0.0.0 security is configured in
255.255.255.255
the device.
Syslog is a communication
protocol for message
logging, it is used for
security auditing in this
device.
The setting is used to set
IP address of syslog server
02, and the device can
upload audit log to syslog
server. The setting is
invalid unless cyber
0.0.0.0~
27 IP_SyslogServer02 - 0.0.0.0 security is configured in
255.255.255.255
the device.
Syslog is a communication
protocol for message
logging, it is used for
security auditing in this
9
device.
The setting is used to set
IP address of syslog server
03, and the device can
0.0.0.0~ upload audit log to syslog
28 IP_SyslogServer03 - 0.0.0.0
255.255.255.255 server. The setting is
invalid unless cyber
security is configured in
the device.

PCS-978S Transformer Relay 9-9


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


Syslog is a communication
protocol for message
logging, it is used for
security auditing in this
device.
The setting is used to set
IP address of syslog server
04, and the device can
upload audit log to syslog
server. The setting is
invalid unless cyber
0.0.0.0~
29 IP_SyslogServer04 - 0.0.0.0 security is configured in
255.255.255.255
the device.
Syslog is a communication
protocol for message
logging, it is used for
security auditing in this
device.
A whitelist is a list of IP
addresses that are granted
access to a certain system
or protocol. When a
whitelist is used, all IP
Disabled
30 En_IP_Whitelist - Disabled addresses are denied
Enabled
access, except those
included in the whitelist.
This setting is used to
enable/disable the whitelist
function of this device.
No. ** IP address of the
whitelist. (**=01...16) This
setting is effective only
31 IP**_Whitelist 0.0.0.0~255.255.255.255 - 0.0.0.0
when the setting
9 “En_IP_Whitelist” is
enabled.

 [Cfg_NetPorts_Bond]

The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device support a bond between any
two Ethernet ports, and the bond among three or above Ethernet ports is impermissible.

The devices communicate with SAS by station level network. In order to ensure reliable
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of

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9 Settings

the device own the same IP address and MAC address, and network 1 and network 2 are
used as hot standby each other. When both network 1 and network 2 are normal, any of them
is used to communicate between the device and SAS. The device will automatically switch to
the other healthy network when one network is abnormal, which will not affect normal
communication.

Taking a CPU module with four Ethernet ports as an example, each bit is corresponding with
an Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet
port 2, Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and
Ethernet 2 is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is
shown as below.

Ethernet port 1

Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value
0 0 1 1 0011 3 1 0 0 1 1001 9
Ethernet port 2

Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value
0 1 0 1 0101 5 0 1 1 0 0110 6
Ethernet port 3

Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value

1 0 1 0 1010 10 1 1 0 0 1100 12
Ethernet port 4

CPU Module

The switching logic of Active-Standby mode is:

Take the device's Ethernet ports 1 & 2 for example and assume that Port 1 and Port 2 are
bonded, and Port 1 is connected to NET 1 while Port 2 is connected to NET 2.

 After the device is powered on, only Port 1 is activated when both NET 1 and NET 2 are
normal.

 If NET 1 is abnormal, Port 2 will be activated if NET 2 is normal.

 If NET1 is abnormal, Port 2 cannot be activated if NET 2 is also abnormal. The device will
keep trying on Port 1. 9
 If Port 2 is working, the device will maintain this state even if NET 1 has been restored to
normal. It will be switched to Port 1 only if NET 2 is abnormal.

9.1.3.2 IEC61850 Communication Settings

Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC61850


Settings

No. Settings Range Unit Default Remark


1 IEDNAME Max 20 - - The identification of the IED in IEC

PCS-978S Transformer Relay 9-11


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


characters 61850 protocol.
It cannot be an empty string and shall
be uique within an SCL file. IEDNAME
should be less than 20 characters
comprising letters or digits or underline
(_) and it is case sensitive.
If this setting is modified, the IED name
in “.cid” file will be changed
simultaneously and vice versa.
It is used to set the change detection
threshold for suddenly sending
2 Pcnt_Deadband 0.00~100.00 % 1.00 measurement value to the SCADA via
the device's Ethernet port using IEC
60870-5-103
Measurement values zero drift
3 Threshold_ZeroDrift 0.001~0.500 - 0.020
suppression threshold
If users need to support the quality
Disabled
4 En_Send_MMS_Qual_Chg - Disabled change upload function, this parameter
Enabled
should be set as “Enabled”
It is used to select the network mode of
MMS network for the communication
with SCADA
IEC61850
5 Opt_DualNetMode_MMS - IEC61850 IEC61850: Network mode with IEC
GB32890
61850 protocol.
GB32890: Network mode with
GB32890 standard.
Disabled The logic setting to enable/disable TCP
6 En_IEC62351_TCP_Port - Disabled
Enabled port in IEC62351 protocol
Disabled The logic setting to enable/disable TCP
7 En_IEC61850_TCP_Port - Enabled
Enabled port in IEC61850 protocol

9.1.3.3 DNP Communication Settings

9 Access path: MainMenu  Settings  Global Settings  Comm Settings  DNP Settings

No. Settings Range Unit Default Remark


The logic setting to
Disabled enable/disable the
1 En_TCP1_DNP - Disabled
Enabled No.1 network DNP
client
The local address of
2 Addr_Slave_TCP1_DNP 0~65519 - 2 the No.1 network DNP
client
3 Addr_Master_TCP1_DNP 0~65519 - 1 The master address of

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9 Settings

No. Settings Range Unit Default Remark


the No.1 network DNP
client
The IP address of the
0.0.0.0~
4 IP_Master_TCP1_DNP - 0.0.0.0 master of the No.1
255.255.255.255
network DNP client
The communication
5 Opt_Map_TCP1_DNP 0~4 - 0 map of the No.1
network DNP client
The timeout of the
application layer of the
6 t_AppLayer_TCP1_DNP 1~5 s 3
No.1 network DNP
client
The heartbeat time
7 t_KeepAlive_TCP1_DNP 0~7200 s 120 interval of the No.1
network DNP client
The logic setting to
enable/disable the UR
Disabled (Unsolicited Response)
8 En_UR_TCP1_DNP - Disabled
Enabled message function of
the No.1 network DNP
client.
When this setting is
enabled, the master
station must activate
UR reporting by
enabling unsolicited
application function
(Function code: 20).
After activation, the
No.1 network DNP
Disabled
9 En_MsgCtrlUR_TCP1_DNP - Enabled client of this device
Enabled
begins to send Class 1,
2, 3 events to the
master station
9
spontaneously.
When this setting is
disabled, this device
sends event data
spontaneously to the
master station.
The online
10 Num_URRetry_TCP1_DNP 2~10 - 3 retransmission number
for sending the

PCS-978S Transformer Relay 9-13


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


unsolicited message of
the No.1 network DNP
client
The offline
retransmission interval
for sending the
11 t_UROfflRetry_TCP1_DNP 1~5000 s 60
unsolicited message of
the No.1 network DNP
client
The default class level
of the “Binary Input” of
12 Class_BI_TCP1_DNP 0~3 - 1
the No.1 network DNP
client
The default class level
of the “Analog Input” of
13 Class_AI_TCP1_DNP 0~3 - 2
the No.1 network DNP
client
The selection timeout
of the remote control
14 t_Select_TCP1_DNP 0~240 s 30 and remote adjustment
of No.1 network DNP
client
The time interval of the
time synchronization
15 t_TimeSynIntvl_TCP1_DNP 0~3600 s 180
function of the No.1
network DNP client
The “OBJ1” default
1-BISingleBit
16 Obj01DefltVar_TCP1_DNP - 1-BISingleBit variation of the No.1
2-BIWithStatus
network DNP client
1-BIChWoutT The “OBJ2” default
17 Obj02DefltVar_TCP1_DNP 2-BIChWithAbsTime - 2-BIChWithAbsTime variation of the No.1
3-BIChWithRelTime network DNP client

9 1-AI32Int
2-AI16Int The “OBJ30” default
18 Obj30DefltVar_TCP1_DNP 3-AI32IntWoutF - 3-AI32IntWoutF variation of the No.1
4-AI16IntWoutF network DNP client
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
19 Obj32DefltVar_TCP1_DNP 2-AI16IntEvWoutT - 1-AI32IntEvWoutT variation of the No.1
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
20 Obj40DefltVar_TCP1_DNP 2-AO16Int - 1-AO32Int variation of the No.1
3-AO32Flt network DNP client

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9 Settings

No. Settings Range Unit Default Remark


The logic setting to
Disabled enable/disable the
21 En_TCP2_DNP - Disabled
Enabled No.2 network DNP
client
The local address of
22 Addr_Slave_TCP2_DNP 0~65519 - 2 the No.2 network DNP
client
The master address of
23 Addr_Master_TCP2_DNP 0~65519 - 1 the No.2 network DNP
client
The IP address of the
0.0.0.0~
24 IP_Master_TCP2_DNP - 0.0.0.0 master of the No.2
255.255.255.255
network DNP client
The communication
25 Opt_Map_TCP2_DNP 0~4 - 0 map of the No.2
network DNP client
The timeout of the
application layer of the
26 t_AppLayer_TCP2_DNP 1~5 s 3
No.2 network DNP
client
The heartbeat time
27 t_KeepAlive_TCP2_DNP 0~7200 s 120 interval of the No.2
network DNP client
The logic setting to
enable/disable the UR
Disabled (Unsolicited Response)
28 En_UR_TCP2_DNP - Disabled
Enabled message function of
the No.2 network DNP
client.
When this setting is
enabled, the master
station must activate
UR
enabling
reporting
unsolicited
by
9
application function
Disabled (Function code: 20).
29 En_MsgCtrlUR_TCP2_DNP - Enabled
Enabled After activation, the
No.1 network DNP
client of this device
begins to send Class 1,
2, 3 events to the
master station
spontaneously.

PCS-978S Transformer Relay 9-15


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


When this setting is
disabled, this device
sends event data
spontaneously to the
master station.
The online
retransmission number
for sending the
30 Num_URRetry_TCP2_DNP 2~10 - 3
unsolicited message of
the No.2 network DNP
client
The offline
retransmission interval
for sending the
31 t_UROfflRetry_TCP2_DNP 1~5000 s 60
unsolicited message of
the No.2 network DNP
client
The default class level
of the “Binary Input” of
32 Class_BI_TCP2_DNP 0~3 - 1
the No.2 network DNP
client
The default class level
of the “Analog Input” of
33 Class_AI_TCP2_DNP 0~3 - 2
the No.2 network DNP
client
The selection timeout
of the remote control
34 t_Select_TCP2_DNP 0~240 s 30 and remote adjustment
of No.2 network DNP
client
The time interval of the
time synchronization
35 t_TimeSynIntvl_TCP2_DNP 0~3600 s 180
9 function of the No.2
network DNP client
The “OBJ1” default
1-BISingleBit
36 Obj01DefltVar_TCP2_DNP - 1-BISingleBit variation of the No.2
2-BIWithStatus
network DNP client
1-BIChWoutT The “OBJ2” default
37 Obj02DefltVar_TCP2_DNP 2-BIChWithAbsTime - 2-BIChWithAbsTime variation of the No.2
3-BIChWithRelTime network DNP client
1-AI32Int The “OBJ30” default
38 Obj30DefltVar_TCP2_DNP 2-AI16Int - 3-AI32IntWoutF variation of the No.2
3-AI32IntWoutF network DNP client

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9 Settings

No. Settings Range Unit Default Remark


4-AI16IntWoutF
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
39 Obj32DefltVar_TCP2_DNP 2-AI16IntEvWoutT - 1-AI32IntEvWoutT variation of the No.2
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
40 Obj40DefltVar_TCP2_DNP 2-AO16Int - 1-AO32Int variation of the No.2
3-AO32Flt network DNP client
The logic setting to
Disabled enable/disable the
41 En_TCP3_DNP - Disabled
Enabled No.3 network DNP
client
The local address of
42 Addr_Slave_TCP3_DNP 0~65519 - 2 the No.3 network DNP
client
The master address of
43 Addr_Master_TCP3_DNP 0~65519 - 1 the No.3 network DNP
client
The IP address of the
0.0.0.0~
44 IP_Master_TCP3_DNP - 0.0.0.0 master of the No.3
255.255.255.255
network DNP client
The communication
45 Opt_Map_TCP3_DNP 0~4 - 0 map of the No.3
network DNP client
The timeout of the
application layer of the
46 t_AppLayer_TCP3_DNP 1~5 s 3
No.3 network DNP
client
The heartbeat time
47 t_KeepAlive_TCP3_DNP 0~7200 s 120 interval of the No.3
network DNP client
The logic setting to

Disabled
enable/disable the UR
(Unsolicited Response)
9
48 En_UR_TCP3_DNP - Disabled
Enabled message function of
the No.3 network DNP
client.
When this setting is
enabled, the master
Disabled station must activate
49 En_MsgCtrlUR_TCP3_DNP - Enabled
Enabled UR reporting by
enabling unsolicited
application function

PCS-978S Transformer Relay 9-17


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


(Function code: 20).
After activation, the
No.1 network DNP
client of this device
begins to send Class 1,
2, 3 events to the
master station
spontaneously.
When this setting is
disabled, this device
sends event data
spontaneously to the
master station.
The online
retransmission number
for sending the
50 Num_URRetry_TCP3_DNP 2~10 - 3
unsolicited message of
the No.3 network DNP
client
The offline
retransmission interval
for sending the
51 t_UROfflRetry_TCP3_DNP 1~5000 s 60
unsolicited message of
the No.3 network DNP
client
The default class level
of the “Binary Input” of
52 Class_BI_TCP3_DNP 0~3 - 1
the No.3 network DNP
client
The default class level
of the “Analog Input” of
53 Class_AI_TCP3_DNP 0~3 - 2
the No.3 network DNP
client
9 The selection timeout
of the remote control
54 t_Select_TCP3_DNP 0~240 s 30 and remote adjustment
of No.3 network DNP
client
The time interval of the
time synchronization
55 t_TimeSynIntvl_TCP3_DNP 0~3600 s 180
function of the No.3
network DNP client
56 Obj01DefltVar_TCP3_DNP 1-BISingleBit - 1-BISingleBit The “OBJ1” default

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Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


2-BIWithStatus variation of the No.3
network DNP client
1-BIChWoutT The “OBJ2” default
57 Obj02DefltVar_TCP3_DNP 2-BIChWithAbsTime - 2-BIChWithAbsTime variation of the No.3
3-BIChWithRelTime network DNP client
1-AI32Int
2-AI16Int The “OBJ30” default
58 Obj30DefltVar_TCP3_DNP 3-AI32IntWoutF - 3-AI32IntWoutF variation of the No.3
4-AI16IntWoutF network DNP client
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
59 Obj32DefltVar_TCP3_DNP 2-AI16IntEvWoutT - 1-AI32IntEvWoutT variation of the No.3
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
60 Obj40DefltVar_TCP3_DNP 2-AO16Int - 1-AO32Int variation of the No.3
3-AO32Flt network DNP client
The logic setting to
Disabled enable/disable the
61 En_TCP4_DNP - Disabled
Enabled No.4 network DNP
client
The local address of
62 Addr_Slave_TCP4_DNP 0~65519 - 2 the No.4 network DNP
client
The master address of
63 Addr_Master_TCP4_DNP 0~65519 - 1 the No.4 network DNP
client
The IP address of the
0.0.0.0~
64 IP_Master_TCP4_DNP - 0.0.0.0 master of the No.4
255.255.255.255
network DNP client
The communication
65 Opt_Map_TCP4_DNP 0~4 - 0 map of the No.4
network DNP client
The timeout of
application layer of the
the
9
66 t_AppLayer_TCP4_DNP 1~5 s 3
No.4 network DNP
client
The heartbeat time
67 t_KeepAlive_TCP4_DNP 0~7200 s 120 interval of the No.4
network DNP client
The logic setting to
Disabled enable/disable the UR
68 En_UR_TCP4_DNP - Disabled
Enabled (Unsolicited Response)
message function of

PCS-978S Transformer Relay 9-19


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


the No.4 network DNP
client.
When this setting is
enabled, the master
station must activate
UR reporting by
enabling unsolicited
application function
(Function code: 20).
After activation, the
No.1 network DNP
Disabled
69 En_MsgCtrlUR_TCP4_DNP - Enabled client of this device
Enabled
begins to send Class 1,
2, 3 events to the
master station
spontaneously.
When this setting is
disabled, this device
sends event data
spontaneously to the
master station.
The online
retransmission number
for sending the
70 Num_URRetry_TCP4_DNP 2~10 - 3
unsolicited message of
the No.4 network DNP
client
The offline
retransmission interval
for sending the
71 t_UROfflRetry_TCP4_DNP 1~5000 s 60
unsolicited message of
the No.4 network DNP
client
9 The default class level
of the “Binary Input” of
72 Class_BI_TCP4_DNP 0~3 - 1
the No.4 network DNP
client
The default class level
of the “Analog Input” of
73 Class_AI_TCP4_DNP 0~3 - 2
the No.4 network DNP
client
The selection timeout
74 t_Select_TCP4_DNP 0~240 s 30
of the remote control

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9 Settings

No. Settings Range Unit Default Remark


and remote adjustment
of No.4 network DNP
client
The time interval of the
time synchronization
75 t_TimeSynIntvl_TCP4_DNP 0~3600 s 180
function of the No.4
network DNP client
The “OBJ1” default
1-BISingleBit
76 Obj01DefltVar_TCP4_DNP - 1-BISingleBit variation of the No.4
2-BIWithStatus
network DNP client
1-BIChWoutT The “OBJ2” default
77 Obj02DefltVar_TCP4_DNP 2-BIChWithAbsTime - 2-BIChWithAbsTime variation of the No.4
3-BIChWithRelTime network DNP client
1-AI32Int
2-AI16Int The “OBJ30” default
78 Obj30DefltVar_TCP4_DNP 3-AI32IntWoutF - 3-AI32IntWoutF variation of the No.4
4-AI16IntWoutF network DNP client
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
79 Obj32DefltVar_TCP4_DNP 2-AI16IntEvWoutT - 1-AI32IntEvWoutT variation of the No.4
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
80 Obj40DefltVar_TCP4_DNP 2-AO16Int - 1-AO32Int variation of the No.4
3-AO32Flt network DNP client

9.1.3.4 IEC103 Communication Settings

Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC103 Settings

No. Settings Range Unit Default Remark


The language of group
caption of IEC103
protocol
Current_Language
1 Opt_Caption_103 Fixed_Chinese - Current_Language
It is recommended to be 9
set as “Fixed_Chinese”
Fixed_English
if the device
communicate with
SCADA in Chinese.
This setting is only used
for IEC 103 protocol. If
Disabled NR network IEC103
2 En_Broadcast_LAN1 - Disabled
Enabled protocol is used, the
setting must be set as
“Enabled”.

PCS-978S Transformer Relay 9-21


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


Disabled: the device
does not send UDP
messages through
Ethernet port A
Enabled: the device
sends UDP messages
through Ethernet port A
This setting is only used
for IEC 103 protocol. If
NR network IEC103
protocol is used, the
setting must be set as
Disabled “Enabled”.
3 En_Broadcast_LAN2 - Disabled
Enabled 0: the device does not
send UDP messages
through Ethernet port B
1: the device sends UDP
messages through
Ethernet port B
This setting is only used
for IEC 103 protocol. If
NR network IEC103
protocol is used, the
setting must be set as
“Enabled”.
Disabled
4 En_Broadcast_LAN3 - Disabled Disabled: the device
Enabled
does not send UDP
messages through
Ethernet port C
Enabled: the device
sends UDP messages
through Ethernet port C
This setting is only used
9 for IEC 103 protocol. If
NR network IEC103
protocol is used, the
setting must be set as
Disabled
5 En_Broadcast_LAN4 - Disabled “Enabled”.
Enabled
Disabled: the device
does not send UDP
messages through
Ethernet port D
Enabled: the device

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9 Settings

No. Settings Range Unit Default Remark


sends UDP messages
through Ethernet port D
This setting is used to
set the data format for
sending waveform list
using IEC 60870-5-103.
DisturbData
6 Format_Wave_Sent - File DisturbData: Send the
File
waveform list in
ASDU23 mode
File: Send the waveform
list in ASDU222 mode
It is used to set the
change detection
threshold for suddenly
sending measurement
7 Pcnt_Deadband_Net 0.00~100.00 % 1.00
value to the SCADA via
the device's Ethernet
port using IEC
60870-5-103
It is used to set the time
period for sending the
measurement value to
8 Period_Measmt_Net 0~65535 s 30 SCADA via the device's
Ethernet port using IEC
60870-5-103 or IEC
61850.
Enabling/disabling both
the TCP port and the
Disabled
9 En_103_TCP&UDP_Port - Disabled UDP port in using the
Enabled
NR network103
protocol.

9.1.3.5 Modbus Communication Settings


9
Access path: MainMenu  Settings  Global Settings  Comm Settings  Modbus Settings

No. Settings Range Unit Default Remark


Disabled The logic setting to enable/disable the TCP port
1 En_Modbus_TCP_Port - Disabled
Enabled in Modbus protocol

9.1.3.6 SV Communication Settings

Access path: MainMenuSettingsGlobal SettingsComm SettingsSV Settings

PCS-978S Transformer Relay 9-23


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


1 SampleRate_SV 0~65535 - 4000 It is used to set sampling rate of SV.
It is backward time delay of SV
2 t_Dly_Interp_Net_SV 1500~15000 μs 2000
interpolation for networking mode.
It is backward time delay of SV
3 t_Dly_Interp_P2P_SV 600~1500 μs 850 interpolation for peer-to-peer (P2P)
mode.
The option of SV receiving mode.
NetMode
NetMode: networking mode
4 Opt_RecvMode_SV P2P - P2P
P2P: peer-to-peer (P2P) mode
Resv
Resv: reserved

9.1.4 Disturbance Fault Recording Settings


Access path: MainMenu  Settings  Global Settings  DFR Settings

No. Settings Range Unit Default Remark


Waveform recorded duration before
1 RecDur_PreTrigDFR 0.000~1.000 s 0.100
the trigger element operating
Waveform recorded duration after the
2 RecDur_PostFault 0.000~10.000 s 1.000
fault happens
The maximum waveform recorded
3 MaxRecDur_PostTrigDFR 0.000~10.000 s 10.000 duration after the trigger element
operating

9.1.5 Label Settings


Access path: MainMenu  Settings  Global Settings  Label Settings

No. Setting Range Unit Default Remark


The description name of GOOSE
Max. 30 link. It will affect the displayed
1 B**.Name_**_GCommLink - GOOSE_Link**
characters GOOSE link name in "GOOSE
Superv" and other signals.
The description name of SV link. It
Max. 30 will affect the displayed SV link
9 2 B**.Name_**_SVCommLink
characters
- SV_Link**
name in "SV Superv" and other
signals.

9.1.6 Clock Synchronization Settings


Access path: MainMenu  Settings  Global Settings  ClockSyn Settings

No. Settings Range Unit Default Remark


Conventional Select the time
1 Opt_TimeSyn SAS - NoTimeSyn synchronization mode of the
NoTimeSyn device.

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Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


The local time zone also
2 OffsetHour_UTC -12~12 - 8 refered to as the hour offset
hour from UTC
The offset minute of local
3 OffsetMinute_UTC 0~60 - 0
time from UTC
The IP address of the server
0.0.0.0~ when SNTP time
4 IP_Server_SNTP - 0.0.0.0
255.255.255.255 synchronization mode is
selected
The IP address of the
0.0.0.0~ standby server when SNTP
5 IP_StandbyServer_SNTP - 0.0.0.0
255.255.255.255 time synchronization mode is
selected
When the setting
[OptTimeSyn] is configured
as “Conventional”, if it is
required to receive the SNTP
message as the backup clock
synchronization source while
hardware-based clock is lost
(i.e.: IRIG-B, IEEE 1588 or
PPS), please configure the
setting
[En_ConvModeSNTP] as
Enabled “Enabled”. In this condition,
6 En_ConvModeSNTP - Disabled
Disabled the alarm signal
“Alm_TimeSyn” will still be
issued, so as to indicate the
failure of the “Conventional”
clock synchronization.
If the SNTP backup clock
synchronization source is not
required
“Conventional”
for
mode,
the
9
please configure the setting
[En_ConvModeSNTP] as
“Disabled”.
The logic setting is used to
Enabled
7 DST.En - Disabled enable or disable Daylight
Disabled
Saving Time (DST)
It is used to set the minute
8 DST.OffsetMinute 0~255 - 60 offset of DST, i.e. the
difference between DST time

PCS-978S Transformer Relay 9-25


Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


and local time
Jan
Feb
Mar
Apr
May
Jun It is used to set the start
9 DST.MonthInYear_Start - Mar
Jul month of DST.
Aug
Sep
Oct
Nov
Dec
1st
2nd
It is used to set the start
10 DST.WeekInMonth_Start 3nd - 1st
week of DST.
4th
Last
Sunday
Monday
Tuesday,
It is used to set the start day
11 DST.DayInWeek_Start Wednesday - Sunday
of DST.
Thursday
Friday
Saturday
It is used to set the start hour
12 DST.HourInDay_Start 0~23 - 3
of DST.
Jan
Feb
Mar
Apr
May

9 13 DST.MonthInYear_End
Jun
Jul
- Oct
It is used to set the end
month of DST.
Aug
Sep
Oct
Nov
Dec
1st
2nd It is used to set the end week
14 DST.WeekInMonth_End - 1st
3nd of DST.
4th

9-26 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Settings Range Unit Default Remark


Last
Sunday
Monday
Tuesday
It is used to set the end day
15 DST.DayInWeek_End Wednesday - Sunday
of DST.
Thursday
Friday
Saturday
It is used to set the end hour
16 DST.HourInDay_End 0~23 - 9
of DST.

 [Opt_TimeSyn]

There are three selections for clock synchronization of the device, each selection includes
different time clock synchronization signals shown in the following table.

Option Description

IRIG-B: IRIG-B via serial port (RS-485 or TTL level), female BNC (TTL level) or
ST-connector port

Conventional PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), female BNC (TTL
level), ST-connector port or binary input

IEEE 1588: Clock message based on IEEE 1588 via Ethernet network

SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network
SAS
Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol

If the time synchronization function is not required, please select "NoTimeSyn". No


NoTimeSyn
clock synchronization alarm will be issued in this mode.

When the setting [Opt_TimeSyn] is set as "SAS", if there is no conventional clock


synchronization signal, the device will not send the alarm signal "Alm_TimeSyn".

When the setting [Opt_TimeSyn] is set as "Conventional", if there is no conventional clock 9


synchronization signal, "SAS" mode will be enabled automatically with the alarm signal
"Alm_TimeSyn" being issued simultaneously.

When the setting [Opt_TimeSyn] is set as "NoTimeSyn", the device will not send time
synchronization alarm signal.

The clock message via IEC103 protocol is INVALID when the device
receives the IRIG-B signal through RC-485 port.

PCS-978S Transformer Relay 9-27


Date: 2022-01-17
9 Settings

9.1.7 Supervision Settings


Access path: MainMenu  Settings  Global Settings  Superv Settings

No. Name Range Unit Default Description


Disabled
1 x.VTS.En - Enabled Enabling/disabling VY circuit supervision
Enabled
Voltage selection for protection
Bus calculation from busbar VT or bay VT
2 x.VTS.Opt_VT - Bus
Bay Bus: busbar VT
Bay: bay VT
Pickup time delay of VT circuit
3 x.VTS.t_DPU 0.200~30.000 s 1.250
supervision
Dropoff time delay of VT circuit
4 x.VTS.t_DDO 0.200~30.000 s 10.000
supervision
Positive-sequence voltage setting of VT
5 x.VTS.U1_Set 0.00~100.00 V 30.00
circuit supervision
Zero-sequence voltage setting of VT
6 x.VTS.3U0_Set 0.00~100.00 V 8.00
circuit supervision
Negative-sequence voltage setting of VT
7 x.VTS.U2_Set 0.00~100.00 V 8.00
circuit supervision function
Enabling/disabling resetting the CT circuit
Disabled
8 En_AutoRecov_Alm_CTS - Disabled failure alarm signal automatically after the
Enabled
CT circuit returns to normal condition.

9.1.8 OutMap Settings


Access path: MainMenu  Settings  Global Settings  OutMap Settings

No. Name Range Unit Default Description


OutMapxxx 0X0~ Tripping logic setting of programmable trip
1 - 0X1
(xxx=001, 002…120) 0XFFFFFFFF output map xxx
t_Dwell_xxx_OutMap The pulse width setting of programmable
2 0.000~0.500 s 0.060
(xxx=001, 002…032) trip output map xxx

9 9.2 Protection Settings

9.2.1 Transformer Current Differential Protection (87T)


Access path: MainMenu  Settings  Protection Settings  Diff Settings

No. Name Range Unit Default Description


Pickup setting of biased differential
1 87T.I_Biased 0.050~5.000 p.u. 0.500
element
Current setting of instantaneous
2 87T.I_Inst 0.050~20.000 p.u. 4.000
differential element

9-28 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Current setting of differential circuit
3 87T.I_Alm 0.050~1.500 p.u. 0.200
abnormality alarm
Current setting of knee point 1 for
4 87T.I_Knee1 0.100~3.500 p.u. 0.500
transformer differential protection
Current setting of knee point 2 for
5 87T.I_Knee2 4.000~8.000 p.u. 6.000
transformer differential protection
6 87T.Slope1 0.000~0.900 - 0.200 Slope 1 of biased differential element
7 87T.Slope2 0.100~1.900 - 0.500 Slope 2 of biased differential element
8 87T.Slope3 0.100~1.900 - 0.750 Slope 3 of biased differential element
Coefficient of second harmonics
9 87T.K_Hm2_Inrush 0.050~0.800 - 0.150
for inrush current detection
Coefficient of third harmonics for
10 87T.K_Hm3_Inrush 0.050~0.800 - 0.200
inrush current detection
Coefficient of third or fifth harmonic
11 87T.K_Hm3/Hm5_OvExc 0.050~0.800 - 0.250 for overexcitation detection
The recommended value is 0.25.
Enabled, Logic setting for enabling/disabling
12 87T.En_Inst - Disabled
Disabled instantaneous differential element
Logic setting for enabling/disabling
Enabled,
13 87T.En_Biased - Disabled conventional biased differential
Disabled
element
Enabled, Logic setting for enabling/disabling
14 87T.En_DPFC - Disabled
Disabled DPFC biased differential element
Option of inrush current
WaveSym discrimination principle:
15 87T.Opt_Inrush_Ident - Hm2
Hm2 WaveSym: waveform symmetry
Hm2: second harmonic principle
Option of inrush blocking mode
Adaptive: self-adaptive one-phase
inrush blocking one-phase
differential element
Adaptive,
2PBlk3P: two-phase inrush
16 87T.Opt_BlkMode_Inrush 2PBlk3P, - Adaptive
1PBlk3P
blocking three-phase differential
element
9
1PBlk3P: one-phase inrush
blocking three-phase differential
element
Logic setting for enabling/disabling
Enabled,
17 87T.En_Hm3_Blk - Enabled the third harmonic blocking for
Disabled
inrush current
Option of third or fifth harmonic for
18 87T.Opt_Hm3/Hm5_OvExc Hm3, Hm5 - Hm5 overexcitation criterion
Hm3: third harmonic

PCS-978S Transformer Relay 9-29


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Hm5: fifth harmonic
Logic setting for enabling/disabling
Enabled,
19 87T.En_CTS_Blk - Enabled blocking biased differential element
Disabled
during CT circuit failure

9.2.2 Restricted Earth Fault Protection (64REF)


Access path: MainMenu  Settings  Protection Settings  REF Settings

No. Name Range Unit Default Description


1 x.64REF.I_Biased 0.050~5.000 In 0.500 Pickup setting of REF
2 x.64REF.I_Alm 0.050~1.500 In 0.200 Current setting of REF abnormality alarm
Knee point setting of REF
3 x.64REF.I_Knee 0.100~4.000 In 0.500
0.5In is recommended.
Percentage restraint coefficient of REF
4 x.64REF.Slope 0.200~0.750 - 0.500
0.5 is recommended.
5 x.64REF.ROA 45.000~90.000 deg 60.000 Operation angle setting
Current setting of neutral-point on-load
6 x.64REF.I_NP_OnLoad 0.040~40.000 A 0.200
criterion
Time delay for REF
7 x.64REF.t_Op 0.000~20.000 s 0.000
Recommended value is zero.
Enabled,
8 x.64REF.En - Disabled Logic setting for enabling/disabling REF
Disabled
Enabled, Logic setting for enabling/disabling
9 x.64REF.En_NPCurr - Disabled
Disabled neutral current criterion
Enabled, Logic setting for enabling/disabling
10 x.64REF.En_CTS_Blk - Enabled
Disabled blocking REF during CT circuit failure
Logic setting for enabling/disabling the
Enabled,
11 x.64REF.En_Dir_Blk - Disabled function of direction criterion blocking
Disabled
REF

9.2.3 Winding Differential Protection (87W)


Access path: MainMenu  Settings  Protection Settings  WdgDiff Settings

9 No. Name Range Unit Default Description


Pickup setting of biased winding differential
1 87W.I_Biased 0.100~5.000 In 0.500
protection
Current setting of winding differential protection
2 87W.I_Alm 0.050~1.500 In 0.200
abnormality alarm
Knee point setting of biased winding differential
3 87W.I_Knee 0.100~4.000 In 0.500
protection.
Percentage restraint coefficient of biased
4 87W.Slope 0.100~0.900 - 0.500
winding differential protection
5 87W.t_Op 0.000~20.000 s 0.000 Time delay for winding differential protection

9-30 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Enabled, Logic setting for enabling/disabling
6 87W.En_PhSeg - Disabled
Disabled phase-segregated winding differential protection
Enabled, Logic setting for enabling/disabling residual
7 87W.En_REF - Disabled
Disabled winding differential protection
Logic setting for enabling/disabling blocking
Enabled,
8 87W.En_CTS_Blk - Enabled winding differential protection during CT circuit
Disabled
failure

9.2.4 Reactor Current Differential Protection (87R)

Transformer current differential protection and reactor current differential


protection are alternative for users, so setting lists of two protections must
not appear on device LCD and the access path of them is the same.

Access path: MainMenu  Settings  Protection Settings  Diff Settings

No. Item Range Unit Default Description


1 87R.I_Biased 0.050~5.000 p.u. 0.500 Pickup setting of biased differential element
Current setting of instantaneous differential
2 87R.I_Inst 0.050~20.000 p.u. 4.000
element
Current setting of differential current abnormality
3 87R.I_Alm 0.050~1.500 p.u. 0.200
alarm
4 87R.Slope 0.100~0.900 - 0.400 Slope of biased differential element
Coefficient of second harmonics for inrush
5 87R.K_Hm2_Inrush 0.050~0.800 - 0.150
current detection
Coefficient of third harmonics for inrush current
6 87R.K_Hm3_Inrush 0.050~0.800 - 0.200
detection
Enabled, Logic setting of enabling/disabling
7 87R.En_Inst - Disabled
Disabled instantaneous differential element
Enabled, Logic setting of enabling/disabling conventional
8 87R.En_Biased - Disabled
Disabled biased differential element
Enabled, Logic setting of enabling/disabling DPFC
9 87R.En_DPFC
Disabled
- Disabled
biased differential element
9
Enabled, Logic setting of enabling/disabling
10 87R.En_REF - Disabled
Disabled zero-sequence differential element
Enabled, Logic setting of enabling/disabling block biased
11 87R.En_CTS_Blk - Enabled
Disabled differential element during CT circuit failure

9.2.5 Inter-turn Fault Protection (21IT)


Access path: MainMenu  Settings  Protection Settings  IntTurn Settings

No. Name Range Unit Default Description

PCS-978S Transformer Relay 9-31


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Enabling/disabling inter-turn fault
1 21IT.En Enabled, Disabled - Disabled
protection.
Enabling/disabling the LV-side current as
the input current of 21IT.
This setting should be set according to the
input current actually configured in 21IT.
When the HV–side (head-end) current is
2 21IT.En_Curr_LVS Enabled, Disabled - Disabled
configured as the input current of 21IT,
this setting should be set as “0”; when the
LV–side (tail-end) current is configured as
the input current of 21IT, this setting
should be set as “1”.

9.2.6 Overexcitation Protection (24)


Access path: MainMenu  Settings  Protection Settings  OvExc Settings

No. Name Range Unit Default Description


It is used to set reference voltage of
overexcitation calculation, and it is usually
1 24Cal.U1n 0.000~2000.000 kV 220.000
set as primary rated voltage at calculated
side of transformer
Voltage option between phase voltage
and phase-to-phase voltage for
2 24Cal.Opt_Up/Upp Up, Upp - Up calculation of overexcitation protection
Up: phase voltage
Upp: phase-to-phase voltage
Multiple setting of stage 1 of definite-time
3 24DT1.K_Set 1.000~1.600 - 1.300
overexcitation protection for trip purpose
Time delay setting of stage 1 of
4 24DT1.t_Op 0.100~9999.000 s 1.000 definite-time overexcitation protection for
trip purpose
Logic setting for enabling/disabling stage
Enabled,
5 24DT1.En - Disabled 1 of definite-time overexcitation protection
9 Disabled
for trip purpose
Multiple setting of stage 2 of definite-time
6 24DT2.K_Set 1.000~1.600 - 1.300 overexcitation protection for alarm
purpose
Time delay setting of stage 2 of
7 24DT2.t_Alm 0.100~9999.000 s 1.00 definite-time overexcitation protection for
alarm purpose
Logic setting of enabling/disabling stage 2
Enabled,
8 24DT2.En - Disabled of definite-time overexcitation protection
Disabled
for alarm purpose

9-32 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Highest-limit multiple setting of
9 24IDMT.K0_Set 1.000~1.700 - 1.700
inverse-time overexcitation protection: n0
Time delay setting corresponding to
10 24IDMT.t0_Op 0.100~9999.000 s 1.000
highest-limit setting: t0
Multiple setting 1 of inverse-time
11 24IDMT.K1_Set 1.000~1.700 - 1.650
overexcitation protection: n1
Time delay setting corresponding to
12 24IDMT.t1_Op 0.100~9999.000 s 2.000
multiple setting 1: t1
Multiple setting 2 of inverse-time
13 24IDMT.K2_Set 1.000~1.700 - 1.600
overexcitation protection: n2
Time delay setting corresponding to
14 24IDMT.t2_Op 0.100~9999.000 s 5.000
multiple setting 2: t2
Multiple setting 3 of inverse-time
15 24IDMT.K3_Set 1.000~1.700 - 1.500
overexcitation protection: n3
Time delay setting corresponding to
16 24IDMT.t3_Op 0.100~9999.000 s 10.000
multiple setting 3: t3
Multiple setting 4 of inverse-time
17 24IDMT.K4_Set 1.000~1.700 - 1.400
overexcitation protection: n4
Time delay setting corresponding to
18 24IDMT.t4_Op 0.100~9999.000 s 20.000
multiple setting 4: t4
Multiple setting 5 of inverse-time
19 24IDMT.K5_Set 1.000~1.700 - 1.300
overexcitation protection: n5
Time delay setting corresponding to
20 24IDMT.t5_Op 0.100~9999.000 s 50.000
multiple setting 5: t5
Multiple setting 6 of inverse-time
21 24IDMT.K6_Set 1.000~1.700 - 1.250
overexcitation protection: n6
Time delay setting corresponding to
22 24IDMT.t6_Op 0.100~9999.000 s 100.000
multiple setting 6: t6
Multiple setting 7 of inverse-time
23 24IDMT.K7_Set 1.000~1.700 - 1.200
overexcitation protection: n7
Time delay setting corresponding to
24 24IDMT.t7_Op 0.100~9999.000 s 300.000
multiple setting 7: t7

25 24IDMT.K8_Set 1.000~1.700 - 1.150


Multiple setting 8 of inverse-time 9
overexcitation protection: n8
Time delay setting corresponding to
26 24IDMT.t8_Op 0.100~9999.000 s 600.000
multiple setting 8: t8
Lowest-limit multiple setting of
27 24IDMT.K9_Set 1.000~1.700 - 1.130
inverse-time overexcitation: n9
Time delay setting corresponding to
28 24IDMT.t9_Op 0.100~9999.000 s 1000.000
lowest-limit multiple setting: t9
Coefficient of time delay of inverse-time
29 24IDMT.K_Alm 0.500~1.000 - 0.700 overexcitation protection for alarm
purpose

PCS-978S Transformer Relay 9-33


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Cooling time of inverse-time
30 24IDMT.t_Cooling 0.100~9999.000 s 10.000
overexcitation protection
Logic setting for enabling/disabling
Enabled,
31 24IDMT.En_Trp - Disabled inverse-time overexcitation protection for
Disabled
trip purpose
Logic setting for enabling/disabling
Enabled,
32 24IDMT.En_Alm - Disabled inverse-time overexcitation protection for
Disabled
alarm purpose

9.2.7 Phase Overcurrent Protection (50/51P)


Access path: MainMenu  Settings  Protection Settings  OC Settings

No. Name Range Unit Default Description


Low voltage setting of
1 x.50/51P.VCE.Upp 10.000~100.000 V 70.000
voltage control element
Negative-sequence
2 x.50/51P.VCE.U2 2.000~57.000 V 8.000 voltage setting of
voltage control element
Zero-sequence voltage
3 x.50/51P.VCE.3U0 2.000~57.000 V 8.000 setting of voltage
control element
Enabling/Disabling
phase overcurrent
protection with voltage
Disabled control element is
4 x.50/51P.VCE.En_VTS_Blk - Disabled
Enabled blocked by VT circuit
failure when VT circuit
supervision is enabled
and VT circuit fails
The characteristic
5 x.50/51P.DIR.RCA -180~179 ° 45 angle of direction
control element
The minimum
9 6 x.50/51P.DIR.phi_Min_Fwd 10~90 ° 90
boundary in forward
direction of phase
overcurrent protection
The maximum
boundary in forward
7 x.50/51P.DIR.phi_Max_Fwd 10~90 ° 90
direction of phase
overcurrent protection
The minimum
8 x.50/51P.DIR.phi_Min_Rev 10~90 ° 90 boundary in reverse
direction of phase

9-34 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


overcurrent protection
The maximum
boundary in reverse
9 x.50/51P.DIR.phi_Max_Rev 10~90 ° 90
direction of phase
overcurrent protection
The voltage
polarization mode of
direction control
element
Upp: phase-to-phase
Upp voltage is used as
10 x.50/51P.DIR.Opt_PolarizedVolt Up - Upp polarized voltage
U1 Up: phase-to-ground
voltage is used as
polarized voltage
U1: positive-sequence
voltage is used as
polarized
The minimum
operating current
11 x.50/51P.DIR.I_Min 0.050~1.000 In 0.050
setting of direction
control element
The minimum
operating voltage
12 x.50/51P.DIR.U_Min 1.000~10.000 V 4.000
setting of direction
control element
Enabling/Disabling
phase overcurrent
protection with
direction control
Disabled
13 x.50/51P.DIR.En_VTS_Blk - Disabled element is blocked by
Enabled
VT circuit failure when
VT circuit supervision
is enabled and VT
9
circuit fails
The coefficient of
second harmonics of
14 x.50/51P.HMB.K_Hm2 0.100~1.000 - 0.200
harmonic control
element
The current setting of
15 x.50/51P.HMB.I_Rls 2.000~150.000 A 20.000 releasing harmonic
control element
16 x.50/51P.HMB.Opt_Blk PhaseBlk, - PhaseBlk The option of harmonic

PCS-978S Transformer Relay 9-35


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


CrossBlk, blocking mode
MaxPhaseBlk PhaseBlk: phase
blocking
CrossBlk: cross
blocking
MaxPhaseBlk:
maximum phase
blocking
The current setting for
stage i of phase
17 x.50/51Pi.I_Set 0.050~200.000 A 15.000
overcurrent protection
(i=1~6)
The operating time
delay for stage i of
18 x.50/51Pi.t_Op 0.000~100.000 s 0.100
phase overcurrent
protection (i=1~6)
The dropout time delay
for stage i of phase
19 x.50/51Pi.t_DropOut 0.000~100.000 s 0.000
overcurrent protection
(i=1~6)
Enabling/Disabling
stage i of phase
Disabled
20 x.50/51Pi.En_Volt_Blk - Disabled overcurrent protection
Enabled
controlled by voltage
control element (i=1~6)
The option direction
NonDirectional
characteristic for stage
21 x.50/51Pi.Opt_Dir Forward - NonDirectional
i of phase overcurrent
Reverse
protection (i=1~6)
Enabling/Disabling
stage i of phase
Disabled
22 x.50/51Pi.En_Hm_Blk - Disabled overcurrent protection
Enabled
controlled by harmonic
9 control element (i=1~6)
Enabling/disabling
Disabled stage i of phase
23 x.50/51Pi.En - Enabled
Enabled overcurrent protection
(i=1~6)
Enabling/disabling
stage i of phase
Trp
24 x.50/51Pi.Opt_Trp/Alm - Trp overcurrent protection
Alm
operate to trip or alarm
(i=1~6)

9-36 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Trp: for tripping
purpose
Alm: for alarm purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of operating
ANSILTV
characteristics curve
ANSILT
25 x.50/51Pi.Opt_Curve - IECDefTime for stage i of phase
IECN
overcurrent protection
IECV
(i=1~6)
IEC
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of dropout
characteristics curve
for stage i of phase
overcurrent protection
Inst (i=1~6)
26 x.50/51Pi.Opt_Curve_DropOut DefTime - Inst Inst: instantaneous
IDMT dropout characteristics
DefTime: definite-time
dropout characteristics
IDMT: inverse-time
dropout characteristics
Time multiplier setting
for stage i of
27 x.50/51Pi.TMS 0.040~20.000 - 1.000 inverse-time phase
overcurrent protection
9
(i=1~6)
The minimum
operating time for
28 x.50/51Pi.tmin 0.000~10.000 s 0.020 stage i of inverse-time
phase overcurrent
protection (i=1~6)
The constant “K” for
29 x.50/51Pi.K 0.0010~120.0000 - 0.1400 stage i of customized
inverse-time phase

PCS-978S Transformer Relay 9-37


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


overcurrent protection
(i=1~6)
The constant “α” for
stage i of customized
30 x.50/51Pi.Alpha 0.0100~3.0000 - 0.0200 inverse-time phase
overcurrent protection
(i=1~6)
The constant “C” for
stage i of customized
31 x.50/51Pi.C 0.0000~1.0000 - 0.0000 inverse-time phase
overcurrent protection
(i=1~6)

9.2.8 Earth Fault Overcurrent Protection (50/51G)


Access path: MainMenu  Settings  Protection Settings  ROC Settings

No. Name Range Unit Default Description


The characteristic angle of
1 x.50/51G.DIR.RCA -180~179 ° 45
direction control element
The minimum boundary in
2 x.50/51G.DIR.phi_Min_Fwd 10~90 ° 90 forward direction of earth
fault protection
The maximum boundary in
3 x.50/51G.DIR.phi_Max_Fwd 10~90 ° 90 forward direction of earth
fault protection
The minimum boundary in
4 x.50/51G.DIR.phi_Min_Rev 10~90 ° 90 reverse direction of earth
fault protection
The maximum boundary in
5 x.50/51G.DIR.phi_Max_Rev 10~90 ° 90 reverse direction of earth
fault protection
The minimum operating
6 x.50/51G.DIR.3I0_Min 0.050~1.000 In 0.050 current setting of direction
9 control element
The minimum operating
7 x.50/51G.DIR.3U0_Min 1.000~10.000 V 4.000 voltage setting of direction
control element
Enabling/Disabling earth
fault protection with direction
Disabled control element is blocked
8 x.50/51G.DIR.En_VTS_Blk - Disabled
Enabled by VT circuit failure when VT
circuit supervision is enabled
and VT circuit fails

9-38 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


The option of the residual
current used by earth fault
protection with direction
Ext control element
9 x.50/51G.DIR.Opt_3I0 - Ext
Cal Ext: the measured residual
current
Cal: the calculated residual
current
The coefficient of second
10 x.50/51G.HMB.K_Hm2 0.100~1.000 - 0.200 harmonics of harmonic
control element
The current setting of
11 x.50/51G.HMB.I_Rls 2.000~150.000 A 20.000 releasing harmonic control
element
The option of the residual
current used by earth fault
overcurrent protection with
Ext harmonic control element
12 x.50/51G.HMB.Opt_3I0 - Ext
Cal Ext: the measured residual
current
Cal: the calculated residual
current
The option of the residual
current used by earth fault
overcurrent protection
Ext
13 x.50/51Gi.Opt_3I0 - Ext Ext: the measured residual
Cal
current
Cal: the calculated residual
current
The zero-sequence current
14 x.50/51Gi.3I0_Set 0.050~200.000 A 15.000 setting for stage i of earth
fault protection (i=1~4)

15 x.50/51Gi.t_Op 0.000~100.000 s 0.100


The operating time delay for
stage i of earth fault
9
protection (i=1~4)
The dropout time delay for
16 x.50/51Gi.t_DropOut 0.000~100.000 s 0.000 stage i of earth fault
protection (i=1~4)
NonDirectional The option direction
17 x.50/51Gi.Opt_Dir Forward - NonDirectional characteristic for stage i of
Reverse earth fault protection (i=1~4)
Disable Enabling/Disabling stage i of
18 x.50/51Gi.En_Hm_Blk - Disabled
Enabled earth fault protection

PCS-978S Transformer Relay 9-39


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


controlled by harmonic
control element (i=1~4)
Disabled Enabling/disabling stage i of
19 x.50/51Gi.En - Enabled
Enabled earth fault protection (i=1~4)
Enabling/disabling stage i of
earth fault protection operate
Trp
20 x.50/51Gi.Opt_Trp/Alm - Trp to trip or alarm (i=1~4)
Alm
Trp: for tripping purpose
Alm: for alarm purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
ANSILTV The option of operating
ANSILT characteristics curve for
21 x.50/51Gi.Opt_Curve - IECDefTime
IECN stage i of earth fault
IECV protection (i=1~4)
IEC
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of dropout
characteristics curve for
stage i of earth fault
protection (i=1~4)
Inst
Inst: instantaneous dropout
22 x.50/51Gi.Opt_Curve_DropOut DefTime - Inst
characteristics
IDMT
DefTime: definite-time
dropout characteristics
9 IDMT: inverse-time dropout
characteristics
Time multiplier setting for
23 x.50/51Gi.TMS 0.040~20.000 - 1.000 stage i of inverse-time earth
fault protection (i=1~4)
The minimum operating time
24 x.50/51Gi.tmin 0.000~10.000 s 0.020 for stage i of inverse-time
earth fault protection (i=1~4)
The constant “K” for stage i
25 x.50/51Gi.K 0.0010~120.0000 - 0.1400
of customized inverse-time

9-40 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


earth fault protection (i=1~4)
The constant “α” for stage i
26 x.50/51Gi.Alpha 0.0100~3.0000 - 0.0200 of customized inverse-time
earth fault protection (i=1~4)
The constant “C” for stage i
27 x.50/51Gi.C 0.0000~1.0000 - 0.0000 of customized inverse-time
earth fault protection (i=1~4)

9.2.9 Negative-sequence Overcurrent Protection (50/51Q)


Access path: MainMenu  Settings  Protection Settings  NegOC Settings

No. Name Range Unit Default Description


The characteristic
1 x.50/51Q.DIR.RCA -180~179 ° 45 angle of direction
control element
The minimum
boundary in forward
direction of
2 x.50/51Q.DIR.phi_Min_Fwd 10~90 ° 90
negative-sequence
overcurrent
protection
The maximum
boundary in forward
direction of
3 x.50/51Q.DIR.phi_Max_Fwd 10~90 ° 90
negative-sequence
overcurrent
protection
The minimum
boundary in reverse
direction of
4 x.50/51Q.DIR.phi_Min_Rev 10~90 ° 90
negative-sequence
overcurrent
protection
The maximum 9
boundary in reverse
direction of
5 x.50/51Q.DIR.phi_Max_Rev 10~90 ° 90
negative-sequence
overcurrent
protection
The minimum
operating current
6 x.50/51Q.DIR.I2_Min 0.050~1.000 In 0.050
setting of direction
control element

PCS-978S Transformer Relay 9-41


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


The minimum
operating voltage
7 x.50/51Q.DIR.U2_Min 1.000~10.000 V 4.000
setting of direction
control element
Enabling/Disabling
negative-sequence
overcurrent
protection with
direction control
Disabled
8 x.50/51Q.DIR.En_VTS_Blk - Disabled element is blocked
Enabled
by VT circuit failure
when VT circuit
supervision is
enabled and VT
circuit fails
The
negative-sequence
current setting for
9 x.50/51Qi.I2_Set 0.050~200.000 A 15.000 stage i of
negative-sequence
overcurrent
protection (i=1 or 2)
The operating time
delay for stage i of
10 x.50/51Qi.t_Op 0.030~100.000 s 0.100 negative-sequence
overcurrent
protection (i=1 or 2)
The dropout time
delay for stage i of
11 x.50/51Qi.t_DropOut 0.000~100.000 s 0.000 negative-sequence
overcurrent
protection (i=1 or 2)
The option direction
9 characteristic for
NonDirectional
stage i of
12 x.50/51Qi.Opt_Dir Forward - NonDirectional
negative-sequence
Reverse
overcurrent
protection (i=1 or 2)
Enabling/disabling
stage i of
Disabled
13 x.50/51Qi.En - Enabled negative-sequence
Enabled
overcurrent
protection (i=1 or 2)

9-42 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Enabling/disabling
stage i of
negative-sequence
overcurrent
protection operate to
Trp
14 x.50/51Qi.Opt_Trp/Alm - Trp trip or alarm (i=1 or
Alm
2)
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
The option of
ANSILTE
operating
ANSILTV
characteristics curve
ANSILT
15 x.50/51Qi.Opt_Curve - IECDefTime for stage i of
IECN
negative-sequence
IECV
overcurrent
IEC
protection (i=1 or 2)
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage i of
negative-sequence
overcurrent
protection (i=1 or 2)
9
Inst
Inst: instantaneous
16 x.50/51Qi.Opt_Curve_DropOut DefTime - Inst
dropout
IDM
characteristics
DefTime:
definite-time dropout
characteristics
IDMT: inverse-time
dropout
characteristics

PCS-978S Transformer Relay 9-43


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Time multiplier
setting for stage i of
inverse-time
17 x.50/51Qi.TMS 0.040~20.000 - 1.000
negative-sequence
overcurrent
protection (i=1 or 2)
The minimum
operating time for
stage i of
18 x.50/51Qi.tmin 0.000~10.000 s 0.020 inverse-time
negative-sequence
overcurrent
protection (i=1 or 2)
The constant “K” for
stage i of customized
inverse-time
19 x.50/51Qi.K 0.0010~120.0000 - 0.1400
negative-sequence
overcurrent
protection (i=1 or 2)
The constant “α” for
stage i of customized
inverse-time
20 x.50/51Qi.Alpha 0.0100~3.0000 - 0.0200
negative-sequence
overcurrent
protection (i=1 or 2)
The constant “C” for
stage i of customized
inverse-time
21 x.50/51Qi.C 0.0000~1.0000 - 0.0000
negative-sequence
overcurrent
protection (i=1 or 2)

9.2.10 Thermal Overload Protection (49)


9 Access path: MainMenu  Settings  Protection Settings  ThOvLd Settings

No. Item Range Unit Default Description


Base current setting of thermal overload
1 x.49.Ib_Set 0.050~200.000 A 15.000
protection
Tripping setting of thermal capacity for thermal
2 x.49.K_Trp 1.000~3.000 - 1.200
overload protection
Alarm setting of thermal capacity for thermal
3 x.49.K_Alm 1.000~3.000 - 1.100
overload protection
4 x.49.Tau 0.100~100.000 min 1.000 Thermal time constant

9-44 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Item Range Unit Default Description


The convertor coefficient from the current to the
5 x.49.K_T_Diff 0.000~200.000 - 30.000
temperature
The cooling mode of transformer, usually,
6 x.49.Alpha_Cold 1.000~2.000 - 2.000 natural cooling: 1.6
forced cooling: 2
Heat dissipation time constant setting.
When the equivalent heating current Ieq is lower
7 x.49.C_Disspt 0.100~10.000 - 1.000
than 0.04In, the thermal time constant adopts the
value of [x.49.Tau]*[x.49.C_Disspt].
Disabled Logic setting of enabling/disabling thermal
8 x.49.En_Trp - Disabled
Enabled overload protection for trip purpose
Disabled Logic setting of enabling/disabling thermal
9 x.49.En_Alm - Disabled
Enabled overload protection for alarm purpose

9.2.11 Breaker Failure Protection (50BF)


Access path: MainMenu  Settings  Protection Settings  BFP Settings

No. Name Range Unit Default Description


The phase current setting of breaker failure
1 x.50BF.I_Set 0.050~200.000 A 1.000
protection
The zero-sequence current setting of
2 x.50BF.3I0_Set 0.050~200.000 A 1.000
breaker failure protection
The negative-sequence current setting of
3 x.50BF.I2_Set 0.050~200.000 A 1.000
breaker failure protection
The re-trip time delay of breaker failure
4 x.50BF.t_ReTrp 0.000~20.000 s 0.050
protection
The first time delay of breaker failure
5 x.50BF.t1_Op 0.000~20.000 s 0.100
protection
The second time delay of breaker failure
6 x.50BF.t2_Op 0.000~20.000 s 0.200
protection
Disabled
7 x.50BF.En - Enabled Enabling/disabling breaker failure protection
Enabled
Disabled Enabling/disabling re-trip function of breaker
8 x.50BF.En_ReTrp
Enabled
- Enabled
failure protection
9
Disabled Enabling/disabling first time delay of breaker
9 x.50BF.En_t1 - Disabled
Enabled failure protection
Disabled Enabling/disabling second time delay of
10 x.50BF.En_t2 - Disabled
Enabled breaker failure protection
Enabling/disabling phase overcurrent
Disabled
11 x.50BF.En_Ip - Disabled element of breaker failure protection via
Enabled
three-phases initiating signal
Disabled Enabling/disabling zero-sequence
12 x.50BF.En_3I0_1P - Disabled
Enabled overcurrent element of breaker failure

PCS-978S Transformer Relay 9-45


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


protection via single-phase initiating signal
Enabling/disabling zero-sequence
Disabled
13 x.50BF.En_3I0_3P - Disabled overcurrent element of breaker failure
Enabled
protection via three-phases initiating signal
Enabling/disabling negative-sequence
Disabled
14 x.50BF.En_I2_3P - Disabled overcurrent element of breaker failure
Enabled
protection via three-phases initiating signal
Enabling/disabling breaker failure protection
Disabled
15 x.50BF.En_CB_Ctrl - Disabled be initiated by normally closed contact of
Enabled
circuit breaker
Disabled Enabling/disabling abnormality check of
16 x.50BF.En_Alm_Init - Disabled
Enabled breaker failure initiating signal
Disabled Enabling/disabling current check criterion of
17 x.50BF.En_Curr - Enabled
Enabled breaker failure protection
Disabled Enabling/disabling contact check criterion of
18 x.50BF.En_CBPos - Disabled
Enabled breaker failure protection

9.2.12 Phase Overvoltage Protection (59P)


Access path: MainMenu  Settings  Protection Settings  OV Settings

No. Name Range Unit Default Description


The option of the voltage
criterion used by stage i of
3P phase overvoltage
1 x.59Pi.Opt_1P/3P - 3P
1P protection (i=1 or 2)
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of the
calculation voltage used by
stage i of phase
Up overvoltage protection (i=1
2 x.59Pi.Opt_Up/Upp - Upp
Upp or 2)
Up: phase voltage
9 Upp: phase-to-phase
voltage
The voltage setting for
stage i of phase
3 x.59Pi.U_Set 57.700~200.000 V 115.000
overvoltage protection (i=1
or 2)
The dropout coefficient for
stage i of phase
4 x.59Pi.K_DropOut 0.930~1.000 - 0.980
overvoltage protection (i=1
or 2)

9-46 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


The operating time delay
for stage i of phase
5 x.59Pi.t_Op 0.100~100.000 s 1.000
overvoltage protection (i=1
or 2)
The dropout time delay for
stage i of phase
6 x.59Pi.t_DropOut 0.000~100.000 s 0.000
overvoltage protection (i=1
or 2)
Enabling/disabling stage i
Disabled
7 x.59Pi.En - Enabled of phase overvoltage
Enabled
protection (i=1 or 2)
Enabling/disabling stage i
of phase overvoltage
Trp protection operate to trip or
8 x.59Pi.Opt_Trp/Alm - Trp
Alm alarm (i=1 or 2)
Trp: for tripping purpose
Alm: for alarm purpose
The option of operating
ANSIDefTime
characteristics curve for
IECDefTime
9 x.59Pi.Opt_Curve - IECDefTime stage i of phase
UserDefine
overvoltage protection (i=1
InvTime_U
or 2)
The option of dropout
characteristics curve for
stage i of phase
overvoltage protection (i=1
Inst
10 x.59Pi.Opt_Curve_DropOut - Inst or 2)
DefTime
Inst: instantaneous dropout
characteristics
DefTime: definite-time
dropout characteristics
Time multiplier setting for

11 x.59Pi.TMS 0.040~20.000 - 1.000


stage
phase
i of inverse-time
overvoltage
9
protection (i=1 or 2)
The minimum operating
time for stage i of
12 x.59Pi.tmin 0.000~10.000 s 0.020 inverse-time phase
overvoltage protection (i=1
or 2)
The constant “K” for stage i
13 x.59Pi.K 0.0010~120.0000 - 1.0000 of customized inverse-time
phase overvoltage

PCS-978S Transformer Relay 9-47


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


protection (i=1 or 2)
The constant “C” for stage i
of customized inverse-time
14 x.59Pi.Alpha 0.0100~3.0000 - 1.0000
phase overvoltage
protection (i=1 or 2)
The constant “α” for stage i
of customized inverse-time
15 x.59Pi.C 0.0000~1.0000 - 0.0000
phase overvoltage
protection (i=1 or 2)

9.2.13 Residual Overvoltage Protection (59G)


Access path: MainMenu  Settings  Protection Settings  ROV Settings

No. Name Range Unit Default Description


The option of the residual voltage used by
Ext residual overvoltage protection
1 x.59Gi.Opt_3U0 - Ext
Cal Ext: the measured residual voltage
Cal: the calculated residual voltage
The voltage setting for stage i of residual
2 x.59Gi.3U0_Set 1.000~200.000 V 50.000
overvoltage protection (i=1 or 2)
The dropout coefficient for stage i of
3 x.59Gi.K_DropOut 0.930~1.000 - 0.980
residual overvoltage protection (i=1 or 2)
The operating time delay for stage i of
4 x.59Gi.t_Op 0.100~100.000 s 1.000
residual overvoltage protection (i=1 or 2)
The dropout time delay for stage i of
5 x.59Gi.t_DropOut 0.000~100.000 s 0.000
residual overvoltage protection (i=1 or 2)
Disabled Enabling/disabling stage i of residual
6 x.59Gi.En - Enabled
Enabled overvoltage protection (i=1 or 2)
Enabling/disabling stage i of residual
overvoltage protection operate to trip or
Trp
7 x.59Gi.Opt_Trp/Alm - Trp alarm (i=1 or 2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose
9
9.2.14 Phase Undervoltage Protection (27P)
Access path: MainMenu  Settings  Protection Settings  UV Settings

No. Name Range Unit Default Description


The option of the
voltage criterion used
3P
1 x.27Pi.Opt_1P/3P - 3P by phase undervoltage
1P
protection
3P: 3-out-of-3 mode

9-48 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


1P: 1-out-of-3 mode
(i=1 or 2)
The option of the
calculation voltage used
by phase undervoltage
Up protection
2 x.27Pi.Opt_Up/Upp - Upp
Upp Up: phase voltage
Upp: phase-to-phase
voltage
(i=1 or 2)
The option of auxiliary
criterion mode for
phase undervoltage
protection
None: no check
Curr: check current
condition
None
CBPos: check normally
Curr
open auxiliary contact
3 x.27Pi.Opt_LogicMode CBPos - CurrAndCBPos
CurrOrCBPos: check
CurrOrCBPos
current condition or
CurrAndCBPos
normally open auxiliary
contact
CurrAndCBPos: check
current condition and
normally open auxiliary
contact
(i=1 or 2)
The voltage setting for
stage i of phase
4 x.27Pi.U_Set 5.000~120.000 V 80.000
undervoltage protection
(i=1 or 2)
The dropout coefficient
for stage i of phase
9
5 x.27Pi.K_DropOut 1.000 ~1.200 - 1.030
undervoltage protection
(i=1 or 2)
The operating time
delay for stage i of
6 x.27Pi.t_Op 0.100~100.000 s 1.000
phase undervoltage
protection (i=1 or 2)
The dropout time delay
7 x.27Pi.t_DropOut 0.000~100.000 s 0.000 for stage i of phase
undervoltage protection

PCS-978S Transformer Relay 9-49


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


(i=1 or 2)
Enabling/Disabling
stage i of phase
undervoltage protection
Disabled is blocked by VT circuit
8 x.27Pi.En_VTS_Blk - Disabled
Enabled failure when VT circuit
supervision is enabled
and VT circuit fails (i=1
or 2)
Enabling/disabling
Disabled stage i of phase
9 x.27Pi.En - Enabled
Enabled undervoltage protection
(i=1 or 2)
Enabling/disabling
stage i of phase
undervoltage protection
Trp
10 x.27Pi.Opt_Trp/Alm - Trp operate to trip or alarm
Alm
(i=1 or 2)
Trp: for tripping purpose
Alm: for alarm purpose
The option of operating
ANSIDefTime
characteristics curve for
IECDefTime
11 x.27Pi.Opt_Curve - IECDefTime stage i of phase
UserDefine
undervoltage protection
InvTime_U
(i=1 or 2)
The option of dropout
characteristics curve for
stage i of phase
undervoltage protection
Inst
12 x.27Pi.Opt_Curve_DropOut - Inst (i=1 or 2)
DefTime
Inst: instantaneous
dropout characteristics
DefTime: definite-time
9 dropout characteristics
Time multiplier setting
for stage i of
13 x.27Pi.TMS 0.040~20.000 - 1.000 inverse-time phase
undervoltage protection
(i=1 or 2)
The minimum operating
time for stage i of
14 x.27Pi.tmin 0.030~10.000 s 0.030
inverse-time phase
undervoltage protection

9-50 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


(i=1 or 2)
The constant “K” for
stage i of customized
15 x.27Pi.K 0.0010~120.0000 - 0.1400 inverse-time phase
undervoltage protection
(i=1 or 2)
The constant “α” for
stage i of customized
16 x.27Pi.Alpha 0.0100~3.0000 - 0.0200 inverse-time phase
undervoltage protection
(i=1 or 2)
The constant “C” for
stage i of customized
17 x.27Pi.C 0.0000~1.0000 - 0.0000 inverse-time phase
undervoltage protection
(i=1 or 2)

9.2.15 Overfrequency Protection (81O)


Access path: MainMenu  Settings  Protection Settings  FreqProt Settings

No. Name Range Unit Default Description


The phase-to-phase voltage setting used to
1 81Oi.Upp_Blk 10.000~150.000 V 70.000
block frequency protection (i=1~4)
The frequency setting for stage i of
2 81Oi.f_Set 50.000~65.000 Hz 52.000
overfrequency protection (i=1~4)
The time delay for stage i of overfrequency
3 81Oi.t_Op 0.100~100.000 s 0.300
protection (i=1~4)
Disabled Enabling/disabling stage i of overfrequency
4 81Oi.En - Enabled
Enabled protection (i=1~4)
Enabling/disabling stage i of overfrequency
Trp protection operate to trip or alarm (i=1~4)
5 81Oi.Opt_Trp/Alm - Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose
9
9.2.16 Underfrequency Protection (81U)
Access path: MainMenu  Settings  Protection Settings  FreqProt Settings

No. Name Range Unit Default Description


The phase-to-phase voltage setting used to
1 81Ui.Upp_Blk 10.000~150.000 V 70.000
block frequency protection
The frequency setting for stage i of
2 81Ui.f_Set 45.000~60.000 Hz 48.000
underfrequency protection (i=1~4)

PCS-978S Transformer Relay 9-51


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


The time delay for stage i of underfrequency
3 81Ui.t_Op 0.100~100.000 s 0.300
protection (i=1~4)
Disabled Enabling/disabling stage i of underfrequency
4 81Ui.En - Enabled
Enabled protection (i=1~4)
Enabling/disabling stage i of underfrequency
Trp protection operate to trip or alarm (i=1~4)
5 81Ui.Opt_Trp/Alm - Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

9.2.17 Frequency Rate-of-change Protection (81R)


Access path: MainMenu  Settings  Protection Settings  FreqProt Settings

No. Name Range Unit Default Description


The phase-to-phase voltage setting used to
1 81Ri.Upp_Blk 10.000~150.000 V 70.000
block frequency rate-of-change protection
The frequency rate-of-change setting for
2 81Ri.df/dt_Set -5.000~5.000 Hz/s 0.500 stage i of frequency rate-of-change
protection (i=1~2)
The pickup frequency setting for stage i of
3 81Ri.f_Pkp 45.000~65.000 Hz 50.000
frequency rate-of-change protection (i=1~2)
The time delay for stage i of frequency
4 81Ri.t_Op 0.100~100.000 s 0.100
rate-of-change protection (i=1~2)
Disabled Enabling/disabling stage i of frequency
5 81Ri.En - Enabled
Enabled rate-of-change protection (i=1~2)
Enabling/disabling stage i of frequency
rate-of-change protection operate to trip or
Trp
6 81Ri.Opt_Trp/Alm - Trp alarm (i=1~2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose

9.2.18 Distance Protection (21T)


Access path: MainMenu  Settings  Protection Settings  DistProt Settings

9 No. Name Range Unit Default Description


Current setting of DPFC current
1 x.21T.FD.DPFC.I_Set (0.050~40.000)×In A 0.100
fault detector element
Current setting of residual current
2 x.21T.FD.ROC.3I0_Set (0.050~40.000)×In A 0.100
fault detector element
Current setting of
3 x.21T.FD.NOC.I2_Set (0.050~40.000)×In A 0.100 negative-sequence current fault
detector element
The angle of directional line in the
4 x.21T.Ang_Alpha 5~30 ° 15
second quadrant for quadrilateral

9-52 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


phase-to-ground distance element
The angle of directional line in the
5 x.21T.Ang_Beta 5~30 ° 15 fourth quadrant for quadrilateral
phase-to-ground distance element
Angle setting of load trapezoid
characteristics, it should be set
6 x.21T.LoadEnch.phi 5~50 ° 12 according to the maximum load
area angle (φLoad_Max),
φLoad_Max+5°is recommended.
Resistance setting of load
trapezoid characteristics, it should
be set according to the minimum
7 x.21T.LoadEnch.R_Set (0.000~4Unn)/In Ω 40.000
load resistance, 70%~90%
minimum load resistance is
recommended.
Current setting for power swing
8 x.21T.I_PSBR (0.050~30.000)×In A 1.000
blocking releasing
Mho Characteristics option of
9 x.21T.ZG.Opt_Characteristic - Mho
Quad phase-to-ground distance element
Mho Characteristics option of
10 x.21T.ZP.Opt_Characteristic - Mho
Quad phase-to-phase distance element
Forward
Direction option for zone i of
11 x.21Ti.DirMode Reverse - Forward
distance protection (i=1~4)
Non_Directional
Real component of zero-sequence
12 x.21Ti.Real_K0 -4.000~4.000 - 0.660 compensation coefficient for zone
i of distance protection (i=1~4)
Imaginary component of
zero-sequence compensation
13 x.21Ti.Imag_K0 -4.000~4.000 - 0.000
coefficient for zone i of distance
protection (i=1~4)
Phase angle of positive-sequence
14 x.21Ti.phi1_Reach 30~89 ° 78 impedance for zone i of distance
protection (i=1~4)
9
Downward offset angle of the
reactance line for zone i of
15 x.21Ti.ZG.RCA 0~45 ° 12
phase-to-ground distance element
(i=1~4)
Impedance setting of zone i of
16 x.21Ti.ZG.Z_Set (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element
(i=1~4)
Shift impedance setting of zone i
17 x.21Ti.ZG.Z_Offset (0.000~4Unn)/In Ω 10.000
of phase-to-ground distance

PCS-978S Transformer Relay 9-53


Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


element (i=1~4)
Resistance setting of zone i of
18 x.21Ti.ZG.R_Set (0.000~4Unn)/In Ω 10.000 quadrilateral phase-to-ground
distance element (i=1~4)
Shift resistance setting of zone i of
19 x.21Ti.ZG.R_Offset (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element
(i=1~4)
Time delay of zone i of
20 x.21Ti.ZG.t_Op 0.000~10.000 s 0.200 phase-to-ground distance element
(i=1~4)
Enabling/disabling zone i of
Disabled
21 x.21Ti.ZG.En - Enabled phase-to-ground distance element
Enabled
(i=1~4)
Enabling/disabling zone i of
Disabled phase-to-ground distance element
22 x.21Ti.ZG.En_3I0 - Disabled
Enabled controlled by residual current fault
detector element (i=1~4)
Enabling/disabling zone i of
phase-to-ground distance element
Disabled
23 x.21Ti.ZG.En_NeuDir_Blk - Enabled blocked by direction control
Enabled
element of earth fault protection
(i=1~4)
Enabling/disabling zone i of
phase-to-ground distance element
Disabled
24 x.21Ti.ZG.En_NegDir_Blk - Enabled blocked by direction control
Enabled
element of negative-sequence
overcurrent protection (i=1~4)
Downward offset angle of the
reactance line for zone i of
25 x.21Ti.ZP.RCA 0~45 ° 12
phase-to-phase distance element
(i=1~4)
Impedance setting of zone i of
Ω
9 26 x.21Ti.ZP.Z_Set (0.000~4Unn)/In 10.000 phase-to-phase distance element
(i=1~4)
Shift impedance setting of zone i
27 x.21Ti.ZP.Z_Offset (0.000~4Unn)/In Ω 10.000 of phase-to-phase distance
element (i=1~4)
Resistance setting of zone i of
28 x.21Ti.ZP.R_Set (0.000~4Unn)/In Ω 10.000 quadrilateral phase-to-phase
distance element (i=1~4)
Shift resistance setting of zone i of
29 x.21Ti.ZP.R_Offset (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(i=1~4)

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Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


Time delay of zone i of
30 x.21Ti.ZP.t_Op 0.000~10.000 s 0.200 phase-to-phase distance element
(i=1~4)
Enabling/disabling zone i of
Disabled
31 x.21Ti.ZP.En - Enabled phase-to-phase distance element
Enabled
(i=1~4)
Enabling/disabling zone i of
phase-to-phase distance element
Disabled
32 x.21Ti.ZP.En_NegDir_Blk - Enabled blocked by direction control
Enabled
element of negative-sequence
overcurrent protection (i=1~4)
Enabling/disabling load trapezoid
Disabled
33 x.21Ti.LoadEnch.En - Enabled characteristics for zone i of
Enabled
distance protection (i=1~4)
Enabling/disabling zone i of
Disabled
34 x.21Ti.En_PSBR - Enabled distance protection controlled by
Enabled
PSBR (i=1~4)
Enabling/disabling zone i of
Disabled
35 x.21Ti.En_ReacLine - Disabled distance protection controlled by
Enabled
the reactance line (i=1~4)

9.3 Measurement and Control Settings

9.3.1 Function Settings

The symbol ”x” represents some side of transformer defined by user


through PCS-Studio software, which may be “HVS”, “HVS2”, “MVS”,
“MVS2”, “LVS”, “LVS2” by default.

Access path: MainMenu  Settings  Meas Control Settings  Function Settings

No. Setting Range Unit Default Remark 9


Threshold to limit the zero-drift influence of
power due to temperature or other
1 x.ZeroDrift_PQ 0.00~1.00 % 0.50 environmental factors. A measured value
less than this setting will be regarded as a
zero drift and ignored.
2 25.Ref.ZeroDrift_U 0.00~1.00 % 0.20 Threshold to limit the variation influence of
reference side/synchronization side voltage
3 25.Syn.ZeroDrift_U 0.00~1.00 % 0.20 due to temperature or other environmental
factor. A variation less than this setting will

PCS-978S Transformer Relay 9-55


Date: 2022-01-17
9 Settings

No. Setting Range Unit Default Remark


be regarded as a zero drift and ignored.
Threshold to limit the zero-drift influence of
DC current/voltage input due to
4 B**.ZeroDrift 0.00~1.00 % 0.20 temperature or other environmental factors.
A measured value less than this setting will
be regarded as a zero drift and ignored.

9.3.2 Synchronism Check Settings


Access path: MainMenu  Settings  Meas Control Settings  Syn Settings

No. Setting Range Unit Default Description

Selection of decision mode


for synchronism check

"Setting": the mode


depends on the setting
values of
1 25.Opt_ValidMode Setting or Config - Setting [CB**.25.En_SynChk] and
[CB**.25.En_DdChk];

"Config": the mode


depends on the input
values of "in_syn_chk" and
"in_vol_chk" terminals.
Logic setting for
synchro-check (valid only if
2 25.En_SynChk Disabled or Enabled - Enabled the setting
[25.Opt_ValidMode] =
Config)
Logic setting for dead
charge check (valid only if
3 25.En_DdChk Disabled or Enabled - Enabled the setting
[25.Opt_ValidMode] =

9 Config)
Percentage threshold of
4 25.U_UV 0.00~100.00 % 80.00 under voltage for CB
closing blocking
Percentage threshold of
5 25.U_OV 100.00~170.00 % 170.00 over voltage for CB closing
blocking
Percentage threshold of
6 25.f_UF 45.000~65.000 Hz 45.000 under frequency for CB
closing blocking

9-56 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Setting Range Unit Default Description


Percentage threshold of
7 25.f_OF 45.000~65.000 Hz 65.000 over frequency for CB
closing blocking
Ua, Ub, Uc, Uab, Ubc, Selection of voltage for
8 25.Opt_U_SynChk - Ua
Uca synchronism check
Threshold of voltage
9 25.U_Diff_Set 0.00~100.00 V 10.00 difference for synchronism
check
Threshold of frequency
10 25.f_Diff_Set 0.00~2.00 Hz 0.50 difference for synchronism
check
Threshold of frequency
11 25.df/dt_Set 0.00~2.00 Hz/s 1.00 variation for synchronism
check.
Threshold of phase
12 25.phi_Diff_Set 0.00~180.00 ° 15.00 difference for synchronism
check
Compensation angle of
13 25.phi_Comp 0.00~360.00 ° 0.00 phase difference for
synchronism check
SynDdRefDd
SynLvRefDd
SynDdRefLv
Selection of dead charge
14 25.Opt_Mode_DdChk RefDd - AnySideDd
check mode
SynDd
SynLvRefDd/SynDdRefLv
AnySideDd
Threshold for voltage dead
15 25.U_DdChk 0.00~100.00 V 17.32
check
Threshold for voltage live
16 25.U_LvChk 0.00~100.00 V 34.64
check
Threshold of duration for
17 25.t_Reset 0~60 s 5
synchrocheck
Circuit breaker closing time.
9
It is the time from receiving
18 25.t_Close_CB 0~2000 ms 20 closing command pulse till
the CB is completely
closed.
Logic setting for frequency
19 25.En_f_Diff_Chk Disabled or Enabled - Enabled
difference check
Logic setting for frequency
20 25.En_df/dt_Chk Disabled or Enabled - Enabled
variation difference check

PCS-978S Transformer Relay 9-57


Date: 2022-01-17
9 Settings

 25.Opt_Mode_DdChk

No. Setting Value Dead charge check mode

1 SynDdRefDd Dead check for both the reference and the synchronization sides

2 SynLvRefDd Live check for synchronization side and dead check for reference side

3 SynDdRefLv Dead check for synchronization side and live check for reference side

4 RefDd Dead check for reference side

5 SynDd Dead check for synchronization side

6 SynLvRefDd/SynDdRefLv Option 2 or 3

7 AnySideDd Option 1, 2 or 3

9.3.3 Double Point Status Settings


Access path: MainMenu  Settings  Meas Control Settings  DPS Settings

No. Setting Range Unit Default Description


Delay Pick Up (DPU) time, i.e. debounce time, for
1 CB**.DPS.t_DPU 0~60000 ms 500
CB DPS
Disabled
2 CB**.DPS.En_Alm - Disabled Logic setting for CB DPS alarm
Enabled
3 CB**.DPS.t_Alm 0~60000 ms 500 Operation time delay of CB DPS alarm
Delay Pick Up (DPU) time, i.e. debounce time, for
4 DS**.DPS.t_DPU 0~60000 ms 500
DS DPS
Disabled
5 DS**.DPS.En_Alm - Disabled Logic setting for DS DPS alarm
Enabled
6 DS**.DPS.t_Alm 0~60000 ms 500 Operation time delay of DS DPS alarm

9.3.4 Control Settings


Access path: MainMenu  Settings  Meas Control Settings  Control Settings

No. Setting Range Unit Default Description


Pulse Width (PW), i.e. holding time, for CB
1 CB**.t_PW_Opn 0~60000 ms 500
opening output
Pulse Width (PW), i.e. holding time, for CB
9 2 CB**.t_PW_Cls 0~60000 ms 500
closing output
Pulse Width (PW), i.e. holding time, for DS
3 DS**.t_PW_Opn 0~60000 ms 500
opening output
Pulse Width (PW), i.e. holding time, for DS
4 DS**.t_PW_Cls 0~60000 ms 500
closing output
Pulse Width (PW), i.e. holding time, for direct
5 DirCtrl**.t_PW_Opn 0~60000 ms 500
opening output
Pulse Width (PW), i.e. holding time, for direct
6 DirCtrl**.t_PW_Cls 0~60000 ms 500
closing output
7 84CSWI**.t_PW_Cls 0~60000 ms 500 Pulse Width (PW), i.e. holding time, for tap

9-58 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Setting Range Unit Default Description


position closing output
Pulse Width (PW), i.e. holding time, for tap
8 84CSWI**.t_PW_Opn 0~60000 ms 500
position opening output

9.3.5 Tap Position Indicator Settings


Access path: MainMenu  Settings  Meas Control Settings  TP Settings

No. Setting Range Unit Default Description


The option of the input code of
tap position indication (TPI)
Resv: direct input or DC analogue
channel
BCD: 6-bit BCD for max. 39
Resv
positions
BCD
Carry: 13-bit carry inputs for max.
Carry
1 84.Opt_Code - BCD 29 positions
Independent
Independent: 26-bit independent
BCD-PhSeg
contacts for max. 26 positions
Independent-PhSeg
BCD-PhSeq: 18-bit BCD for max.
39 phase-segregated positions
Independent-PhSeq: 24-bit
independent contacts for max. 8
phase-segregated positions
The Delay Pick Up (DPU) time, i.e.
2 84.t_DPU 0~6000 ms 500
debounce time, of TPI
Enabling/disabling the trip of tap
3 84.En_RunawayTrip Disabled or Enabled - Disabled changer motor power supply
during the situation "Tap runaway"
The holding time of output signal
for the trip of tap changer motor
4 84.t_RunawayTrip 0~60000 ms 500
power supply during the situation
"Tap runaway"
The number of the defined
5 84.Num_AI_Segment 0~48 - 1 segment, i.e. tap positions, in the 9
DC analog input range of TPI
The rated value corresponding to
6 84.Rated_AI_Segment** -220.00~220.00 - 0.00 the No.** segment in DC analog
input range of TPI
The rated value deviation
corresponding to the No.**
7 84.Devn_AI_Segment** 0.00~100.00 % 0.00
segment in DC analog input range
of TPI
8 84.Value_Segment** -50~50 - 0 The TPI number of the No.**

PCS-978S Transformer Relay 9-59


Date: 2022-01-17
9 Settings

No. Setting Range Unit Default Description


segment in DC analog input range

 [84.Opt_Code] = BCD

Max. 39 positions, Example: 17 = 01 0111 (BI_06 -> BI_01)

Validation condition (AND):

 The lower 4 bits represent a decimal number which is smaller than 9;

 At least one of the 6 bits appear to be 1.

No. Input Signal Description


1 84.in_tap01
2 84.in_tap02
Decimal number 0~9 of units
3 84.in_tap03
4 84.in_tap04
5 84.in_tap05
Decimal number 0~3 of tens
6 84.in_tap06

 [84.Opt_Code] = Carry (inputs)

Max. 29 positions, Example: 17 = 011 0001 0000 00 (BI_13 -> BI_01)

Validation condition (AND):

 Only one of the higher 3 bits, which represent units, tens and twenties, appear to be
1;

 Only one of the lower 10 bits, which represent decimal numbers, appear to be 1.

No. Input Signal Description


**: 01~10
1 84.in_tap**
Decimal number 0~9 of units
Validation for decimal number of units
2 84.in_tap11 1: valid
0: invalid
Validation for decimal number of tens

9 3 84.in_tap12 1: valid
0: invalid
Validation for decimal number of twenties
4 84.in_tap13 1: valid
0: invalid

 [84.Opt_Code] = Independent (contacts)

Max. 26 positions, Example: 17 = 0000 0000 0100 0000 0000 0000 00 (BI_26 -> BI_01)

Validation condition:

 Only one of the 26 bits appear to be 1.

9-60 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Input Signal Description


**: 01~26
1 84.in_tap** Decimal number 1~26
If all inputs are "0", they represent the decimal number 0

 [84.Opt_Code] = BCD-PhSeg

Max. 39 positions, Example: 17 = 01 0111 (BI_06 -> BI_01 and BI_12 -> BI_07 and BI_18 ->
BI_13)

Validation condition (AND, for each phase):

 The lower 4 bits represent a decimal number which is smaller than 9;

 At least one of the 6 bits appear to be 1.

Input Signal
No. Description
Phase A Phase B Phase C
1 84.in_tap01 84.in_tap07 84.in_tap13
2 84.in_tap02 84.in_tap08 84.in_tap14
Decimal number 0~9 of units
1 84.in_tap03 84.in_tap09 84.in_tap15
2 84.in_tap04 84.in_tap10 84.in_tap16
3 84.in_tap05 84.in_tap11 84.in_tap17
Decimal number 0~3 of tens
4 84.in_tap06 84.in_tap12 84.in_tap18

 [84.Opt_Code] = Independent-PhSeg (contacts)

Max. 8 positions, Example: 7 = 0100 0000 (BI_08 -> BI_01 and BI_16 -> BI_09 and BI_24 ->
BI_17)

Validation condition (for each phase):

 Only one of the 8 bits appear to be 1.

No. Input Signal Description


Phase A decimal number 1~8
1 84.in_tap** **: 01~08
If all inputs are "0", they represent the decimal number 0
Phase B decimal number 1~8
2 84.in_tap** **: 09~16
If all inputs are "0", they represent the decimal number 0

3 84.in_tap** **: 17~24


Phase C decimal number 1~8 9
If all inputs are "0", they represent the decimal number 0

9.3.6 Interlocking Logic Settings


Access path: MainMenu  Settings  Meas Control Settings  Interlock Settings

No. Setting Range Unit Default Description


Disabled Logic setting for interlocking logic control of
1 CB**.En_CILO_Opn - Disabled
Enabled CB opening output.
2 CB**.En_CILO_Cls Disabled - Disabled Logic setting for interlocking logic control of

PCS-978S Transformer Relay 9-61


Date: 2022-01-17
9 Settings

No. Setting Range Unit Default Description


Enabled CB closing output.
Disabled Logic setting for interlocking logic control of
3 DS**.En_CILO_Opn - Disabled
Enabled DS opening output.
Disabled Logic setting for interlocking logic control of
4 DS**.En_CILO_Cls - Disabled
Enabled DS closing output.
Disabled Logic setting for interlocking logic control of
5 DirCtrl**.En_CILO_Opn - Disabled
Enabled direct opening output.
Disabled Logic setting for interlocking logic control of
6 DirCtrl**.En_CILO_Cls - Disabled
Enabled direct closing output.
Disabled Logic setting for interlocking logic control of
7 84CSWI**.En_CILO_Opn - Disabled
Enabled opening output of tap changer.
Disabled Logic setting for interlocking logic control of
8 84CSWI**.En_CILO_Cls - Disabled
Enabled closing output of tap changer.

9.3.7 DC Measuring Transducers Settings


Access path: Main Menu  Settings  Meas Control Settings DCAI Settings

No. Setting Range Unit Default Description


Selection of DC analog
input type
0~10V Please refer to the
1 B**.DCAI.Opt_Type_Transducer** - 0~20mA
0~20mA corresponding jumper of
DC AI module to realize
the selection.
The minimal converted
2 B**.DCAI.Min_Transducer** -60000.000~60000.000 - 0.000
value (physical quantity)
The maximal converted
3 B**.DCAI.Max_Transducer** -60000.000~60000.000 - 250.00
value (physical quantity)

9.3.8 Energy Metering Settings


Access path: Main Menu  Settings  Meas Control Settings  Energy Metering Settings

No. Setting Range Unit Default Description


9 1 x.MMTR.U2n 0.00~200.00 V 100.00 The secondary rated voltage of metering
2 x.MMTR.I2n 1~ 5 A 5 The secondary rated current of metering

9.3.9 Automatic Voltage Regulation Settings


Access path: Main Menu  Settings  Meas Control Settings AVR Settings

No. Name Range Unit Default Description


1 90V.U_Target_1 0.00~160.00 V 100.00 The ATCC target voltage value 1
2 90V.U_Target_2 0.00~160.00 V 110.00 The ATCC target voltage value 2
3 90V.U_Target_3 0.00~160.00 V 120.00 The ATCC target voltage value 3
4 90V.U_Target_4 0.00~160.00 V 130.00 The ATCC target voltage value 4

9-62 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

No. Name Range Unit Default Description


The permissive bandwidth of the ATCC target
5 90V.U_Bandwidth 0.10~30.00 % 10.00
voltage
Ua
Ub
Uc
6 90V.Opt_U - Uab The phase option of the target voltage
Uab
Ubc
Uca
The upper limit of the regulatable tap position
7 90V.TP_Max 0~64 - 10
range of ATCC
The lower limit of the regulatable tap position
8 90V.TP_Min 0~64 - 0
range of ATCC
The threshold of the ATCC undervoltage
9 90V.U_UV 0.00~150.00 V 80.00
supervision function
Disabled Enabling /disabling the alarm function by ATCC
10 90V.En_Alm_UV - Enabled
Enabled undervoltage
Disabled Enabling /disabling the blocking function by
11 90V.En_UV_Blk - Enabled
Enabled ATCC undervoltage
12 90V.U_OV 0.00~150.00 V 120.00 The threshold of ATCC overvoltage
Disabled Enabling /disabling the alarm function by ATCC
13 90V.En_Alm_OV - Enabled
Enabled overvoltage
Disabled Enabling /disabling the blocking function by
14 90V.En_OV_Blk - Enabled
Enabled ATCC overvoltage
15 90V.I_OC 0.00~100.00 A 6.00 The threshold of ATCC overcurrent
Disabled Enabling /disabling the alarm function by ATCC
16 90V.En_Alm_OC - Enabled
Enabled overcurrent
Disabled Enabling /disabling the blocking function by
17 90V.En_OC_Blk - Enabled
Enabled ATCC overcurrent
Disabled Enabling /disabling the inverse-time
18 90V.En_IDMT - Disabled
Enabled characteristic of ATCC initial command
19 90V.t1_Intv1 0~600 s 30 The delay 1 of ATCC operation
20 90V.t2_Intv1 0~600 s 10 The delay 2 of ATCC operation

21 90V.En_LDCRX
Disabled
- Disabled
Enabling /disabling the line voltage drop 9
Enabled compensation function of ATCC
The line reactance of the line voltage drop
22 90V.X_LDC -100.00~100.00 ohm 0.00
compensation of ATCC
The line resistance of the line voltage drop
23 90V.R_LDC 0.00~100.00 ohm 0.00
compensation of ATCC
24 90V.t_ReguFail 0~3600 s 180 The judging period of ATCC failure
The limit of times of regulation in an ATCC
25 90V.Num_Regu 1~1000 - 48
process
26 90V.t_Period_Regu 1~24 h 24 The regulation period of and ATCC process

PCS-978S Transformer Relay 9-63


Date: 2022-01-17
9 Settings

9.3.10 Parallel Voltage Regulation Settings


Access path: Main Menu  Settings  Meas Control Settings PVR Settings

No. Name Range Unit Default Description


1 PVR.t_Wait 0~60 s 60 The waiting time of a tap changer operation of PVR
2 PVR.t_Stable 0~60 s 60 The waiting time of the stable state of PVR
The debounce time of the TPI consistency
3 PVR.t_UnmatchedTP 0~30 s 10
judgement of PVR
Forward
4 PVR.Opt_Dir_TP - Forward The option of the tap change sequence of PVR
Reverse

9.4 Logic Links

9.4.1 Function Links


Access path: MainMenuSettingsLogic LinksFunction Links

No. Name Range Unit Default Description


Disabled
1 Link_** - Enabled Enabling/disabling function link setting **
Enabled

9.4.2 GOOSE Sending Links


Access path: MainMenuSettingsLogic LinksGOOSE Send Links

No. Name Range Unit Default Description


Disabled Enabling/disabling GOOSE
1 @B**.Name_***[email protected]_Send - Enabled
Enabled sending link setting **

9.4.3 GOOSE Receiving Links


Access path: MainMenuSettingsLogic LinksGOOSE Recv Links

No. Name Range Unit Default Description


Disabled Enabling/disabling GOOSE
1 @B**.Name_***[email protected]_Recv - Enabled
Enabled receiving link setting **

9 Disabled
The reception function of
GOOSE message whose
2 GLink_RecvSim - Disabled
Enabled “Simulation”=1 is Disabled or
Enabled

@B**.Name_***_GCommLink@ is the set value of the corresponding label

setting (see Section 9.1.5).

9-64 PCS-978S Transformer Relay

Date: 2022-01-17
9 Settings

9.4.4 SV Receiving Links


Access path: MainMenuSettingsLogic LinksSV Recv Links

No. Name Range Unit Default Description


Disabled Enabling/disabling SV
1 @B**.Name_***[email protected]_Recv - Enabled
Enabled receiving link setting **

The reception function


Disabled of SV message whose
2 SVLink_RecvSim - Disabled
Enabled “Simulation”=1 is
Disabled or Enabled

@B**.Name_***_SVCommLink@ is the set value of the corresponding

label setting (see Section 9.1.5).

PCS-978S Transformer Relay 9-65


Date: 2022-01-17
Appendix A Glossary

Appendix A Glossary
The abbreviations adopted in this manual are listed as below.

BNC Bayonet Neill Concelman


A
BO Binary Output
"a" Contact Breaker auxiliary contact (ANSI
BIM Binary Input Module
Standard Device Number 52A) that closes
when the breaker is closed and opens when BOM Binary Output Module
the breaker is open.
C
AC Alternating current

A/D converter Analog-to-digital converter C37.94 IEEE/ANSI protocol used when


sending binary signals between IEDs
AI Analog input
CB Circuit breaker
ANSI American National Standards Institute
CID Configured IED Description
AR Autoreclosing
COMTRADE Standard Common Format for
ASDU Application Service Data Unit–An
Transient Data Exchange format for
ASDU can consist of one or more identical
Disturbance recorder according to IEEE/ANSI
information objects. A sequence of the same
C37.111, 1999 / IEC 60255-24
information elements, for example measured
values, is identified by the address of the CPU Central Processing Unit
information object. The address of the
CRC Cyclic Redundancy Check
information object defines the associated
address of the first information element of the CT Current Transformer
sequence. A consecutive number identifies the
CTS Current Circuit Supervision
subsequent information elements. The number
builds on this address in integral increments
D
(+1).

ATCC Automatic Tap Changer Control DBDL Dead Bus Dead Line

AVR Automatic Voltage Regulation DBLL Dead Bus Live Line

DC Direct Current
B
DFR Disturbance Fault recorder
"b" Contact Breaker auxiliary contact (ANSI
DLLB Dead Line Live Bus
Standard Device Number 52B) that closes
when the breaker is open and opens when the DNP Distributed Network Protocol as per IEEE
breaker is closed. Std 1815-2012

BFP Breaker failure protection DPFC Deviation of Power Frequency A


Component–In case of a fault occurred in the
BI Binary Input

PCS-978S Transformer Relay 1


Date: 2022-01-17
Appendix A Glossary

power system, the fault component could be I


analyzed into three parts: the power frequency
components before the fault, the power ICD IED Capability Description
frequency variables during the fault and the
IEC International Electrotechnical Commission
transient variables during the fault. DPFC is
the power frequency variable during the fault. IED Intelligent Electronic Device

DPS IEC 61850 data type: Double Point IRIG-B InterRange Instrumentation Group
Status Time code format B

DSP Digital Signal Processor


L
E
LAN Local Area Network

E2E End-to-End LCD Liquid Crystal Display

EHV Extra High Voltage LED Light-emitting Diode

EMC Electromagnetic Compatibility


M
F
MAC Media Access Control

FL Fault Location MCB Miniature Circuit Breaker

FR Fault Recorder MMS Manufacturing Message Specification

MOV Metal-oxide Varistor


G
O
G.703 Electrical and functional description for
digital lines used by local telephone
OLTC On-load Tap Changer
companies. Can be transported over balanced
and unbalanced lines OOS Out-of-Step

GIS Gas-insulated Switchgear


P
GOOSE Generic Object-Oriented Substation
Event P2P Peer-to-peer

GPS Global Positioning System PD Pole Discrepancy

PL Programmable Logic
H
PPM Pulse Per Minute
HMI Human-machine Interface
PPS Pulse Per Second
HSR High-availability Seamless Redundancy
PRP Parallel Redundancy Protocol
HV High-voltage
A PVR Parallel Voltage Regulation
HVDC High-voltage Direct Current
R

2 PCS-978S Transformer Relay

Date: 2022-01-17
Appendix A Glossary

RedBox Redundancy box, used for the SOE Sequence of Events–An ordered,
redundant connection of devices with only one time-stamped log of status changes at binary
interface to both network LAN A and LAN B inputs (also referred to as state inputs). SOE is
used to restore or analyze the performance, or
RMS Root Mean Square
an electrical power system itself, over a certain
RSTP Rapid Spanning Tree Protocol period of time.

RTD Resistance Temperature Detector SOTF Switch-Onto-Fault

RTU Remote Terminal Unit STP Rapid Spanning Tree Protocol

S T

SAS Substation Automation System TCS Trip Circuit Supervision

SCADA Supervision, Control And Data TCP/IP Transmission Control Protocol over
Acquisition Internet Protocol

SCD Substation Configuration Description TPI Tap Position Indication

SCL Substation Configuration Description


U
Language

SLD Single-line Diagram UDP User Datagram Protocol

SNMP Simple Network Management UTC Coordinated Universal Time


Protocol–An Internet standard protocol and
serves for the administration of nodes in an IP V
network.
VT Voltage transformer
SNTP Simple Network Time Protocol–A
protocol for the synchronization of clocks via VTS Voltage Circuit Supervision
the Internet. With SNTP, client computers can
synchronize their clocks via the Internet with a
time server.

A list of function numbers used to represent electrical protection and control element. The device
function numbers used in this manual include the following:

21 Distance element 49 Thermal overload element

24 Overexcitation element 50 Instantaneous overcurrent element

25 Synchronism-check element 51 Definite-time or inverse-time overcurrent


element
27 Undervoltage element
52 AC circuit breaker
32 Power element

37 Undercurrent element
59 Overvoltage element A
64 Restricted earth fault element
46 Phase-balance current element

PCS-978S Transformer Relay 3


Date: 2022-01-17
Appendix A Glossary

67 Directional overcurrent element 81 Frequency element

68 Power swing blocking element 85 Pilot element

78 Out-of-step element 87 Differential element

79 Reclosing element

These numbers are frequently used within a suffix letter to further designate their application. The
suffix letters used in this instruction manual include the following:

P Phase element

G Residual/Ground element

N Neutral/Ground element

Q Negative-sequence element

4 PCS-978S Transformer Relay

Date: 2022-01-17

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