Q81. How are the number of Buffer (logic) levels determined during CTS?

 Spread macros

 Spread standard cells

 Increase strap width

 Increase number of straps

 Use proper blockage

Q82. Which is better compared to buffer and inverter? If so, Why?

 Inverters, Since the Transition time is less for Inverters. It reduced current flow between VDD
and VSS rail and hence Power reduction. Better to use both with all drive strength to get
good skew and insertion delay.

 One other advantage of using inverters in a clock tree is the reduction of duty cycle
distortion. The delay models for a cell library are usually characterized at three different
operation conditions or corners: worst, typical, and best. But, there are other effects that are
not modeled at these corners. You can have clock jitter introduced by the PLL, variances in
the doping of PFETs or NFETs, and other known physical effects of a manufacturing
process.

Q83. While Doing CTS which buffer and inverters are used in the Design?
Clock tree synthesis uses buffers or inverters in clock tree construction. The tool identifies the
buffers and inverters if their Boolean function is defined in library preparation. By default, clock tree
synthesis synthesizes clock trees with all the buffers and inverters available in your libraries. It is not
necessary to specify all of them explicitly in the Buffers/Inverters.

Q84. How will you have built Clock tree for Gated Clocks?
Historically, separate trees are built for any net that drives clock gating elements as well as clock
leaves. The two trees diverge at the root of the net. This typically results in excessive insertion
delays and makes the clock tree more susceptible to failure due to on-chip variation (OCV).
By default, the clock tree synthesizer attempts to tap the gated branches into a lower point in the
clock tree, sharing more of the clock tree topology with the non-gated branches. It attempts to insert
negative offset branch points earlier in the main tree.

In many cases, this results in fewer buffers being inserted as well as lower clock insertion delays.
Sharing the clock tree topology between gated and non-gated branches typically also reduces the
local OCV impact on timing. You should disable the clock tap-in feature if too many buffers are
inserted or if the clock tree insertion delay is too large.

Q85. Explain Clock Tree Options for building better Clock Tree?
Five special clock options are available to address this situation. They greatly expand your ability to
control the clock building.

Clock phase:

 A clock phase is a timer event that is associated with a particular edge of the source clock.

 Each clock domain created with two clock phases:

 The rising edge

  The falling edge.

 The clock phases are named after the timing clock with R or F to denote rising or falling clock
phase.

 These phases propagate through the circuit to the endpoints, so that events at the clock pins
can be traced to events driven by the clocks defined.

 Because Tool is capable of propagating multiple clocks through a circuit, any clock pin can
have two or more clock phases associated with it.

 For example, if CLKA and CLKB are connected to the i0 and i1 inputs of a 2:1 MUX, all clock
pins in the fan-out of this MUX have four clock phases associated with them—CLKA:R,
CLKA:F, CLKB:R, and CLKB:F. (This assumes that you allow the propagation of multiple
clock phases).

Skew phase:

 A skew phase is a collection of clock phases.

 Each clock phase is placed into the skew phase of the same name.

 When a clock is defined, skew phases are also automatically created. They are created with
the same names as the clock phases that are created.

Skew group

 Clock tree skew balancing is done on a per-skew group basis.

 A skew group is a subdivision of a clock phase.

 Normally, all pins in a clock phase are in group 0 and are balanced as a group.

 If you have created a set of pins labeled as group 1,

For example,

 Then the skew phase containing these pins will be broken into two skew groups: one
containing the user-specified group, and one containing the “normal” clock pins.

 This feature is useful if we want to segregate certain sets of clock pins and not balance them
with the default group. We can now define multiple groups of pins and balance them
independently.

Skew anchor or Sink Point

  A skew anchor is a clock endpoint pin that controls downstream clock tree.

 For example, a register that is a divide-by-2 clock generator has a clock input pin that is a
skew anchor, because the arrival time of the clock at that clock pin affects the arrival times of
all the clocks in the generated domain that begins at the register Q pin.

Skew offset

 The skew offset a floating point number to describe certain phase relationships that exist,
when placing multiple clocks with different periods or different edges of the same clock
different phases into the same skew phase.

 Use the skew offset to adjust the arrival time of a specific clock phase when you want to
compare it to another clock phase in the same group.

Q86. How does a skew group relate to the clock phase and skew phase?
 A skew group is a set of clock pins that have been declared as a group. By default, all clock
pins are placed in group 0. So each skew phase contains one group.

 If the user has created a group of pins labeled by the number 1, for example, then the skew
phase that contains these pins will be broken into two skew groups:

(i) The “normal” clock pins

(ii) The user-specified group.

 This is useful for segregating groups of clock pins that have special circumstances and that
you do not want to be balanced with the default group.

 Skew optimization is performed on a skew-group basis that takes place after the basic clock
is inserted

Q87. Why to reduce Clock Skew?

 Reducing clock skew is not just a performance issue, it is also a manufacturing issue.

 Scan based testing, which is currently the most popular way to structurally test chips for
manufacturing defects, requires minimum skew to allow the error free shifting of scan vectors
to detect stuck-at and delay faults in a circuit.

 Hold failures at the best-case PVT Corner is common of these circuits since there are
typically no logic gates between the output of one flop and the scan input on the next flop on
the scan chain.
  Managing and reducing clock skew in this case often resolves these hold failures.

Q88. What are all the Checks to be done before doing CTS?
 Hierarchical pins should not be defined as a clock source

 Generated clock should have a valid master clock source A generated clock does not have a
valid master clock source in the following situations:

 The master clock specified in create_generated_clock does not exist.

 The master clock specified in create_generated_clock does not drive the source pin
of the generated clock.

 The source pin of the generated clock is driven by multiple clocks, and some of the
master clocks are not specified with create_generated_clock.

 Clock (master or generated) with no sinks

 Looping clock

 Cascaded clock with an un-synthesized clock tree in its fan-out

 Multiple-clocks-per-register propagation not enabled, but the design contains overlapping

clocks

 Clock tree exceptions should not be ignored.

 Stop pin or float pin defined on an output pin is an issue.

Q89. How will you synthesize clock tree?

 Single clock-normal synthesis and optimization

 Multiple Clocks-Synthesis each clock separately

 Multiple clocks with domain Crossing-Synthesis each clock separately and balance the skew

Q90. How many clocks were there in this project?

 It is specific to your project
 More the clocks more challenging!