Investigation of FDSOI and PDSOI MOSFET

characteristics
Cite as: AIP Conference Proceedings 2173, 020005 (2019); https://doi.org/10.1063/1.5133920
Published Online: 11 November 2019

Hui Wai Wei, and Siti Hawa Ruslan

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Preface: Advances in Electrical and Electronic Engineering: From Theory to Applications

(Series 2): Proceedings of the International Conference of Electrical and Electronic Engineering
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© 2019 Author(s).
 Investigation of FDSOI and PDSOI MOSFET
Characteristics
Hui Wai Wei b) and Siti Hawa Ruslana)

Faculty of Electrical and Electronic Engineering,

Universiti Tun Hussein Onn Malaysia,
86400 Parit Raja, Batu Pahat, Johor, Malaysia.
a)
Corresponding author: [email protected]
b)
[email protected]

Abstract. — Implementation of silicon on insulator (SOI) technology gives a great alternative to the miniaturization and
reduction of short channel effects, allowing microelectronic evolution to proceed. This paper investigate the
characteristics of n-channel partially depleted silicon on insulator (PDSOI) and fully depleted silicon on insulator
(FDSOI) metal oxide semiconductor field effect transistor (MOSFET). Both transistors are investigated in terms of
electrical characteristics which are the threshold voltage, leakage current and kink effect. Both PDSOI and FDSOI
MOSFETs are simulated by using Silvaco TCAD tools. The SOI MOSFET structures are simulated in Silvaco Atlas 2-D
numerical simulator. The threshold voltage and leakage current of PDSOI MOSFET with silicon film thickness of 0.2 μm
are found to be 0.6357 V and 0.013 pA respectively. As for FDSOI MOSFET with silicon film thickness of 0.08 μm, the
threshold voltage is 0.3642 V and leakage current of 0.034 pA. Additionally, the simulation result also shows that kink
effect only presents in PDSOI MOSFET. After analysing the results, it can be concluded that FDSOI MOSFET has better
performance than PDSOI MOSFET.

INTRODUCTION
In recent years, the industry of microelectronic is motivated by the demand of circuit with high performance and
devices for digital application. Most of electronic production requires high speed circuit and the size is becoming
smaller. For many years, bulk metal oxide semiconductor field effect transistor (MOSFET) has been considered as
the only feasible solution to fulfil Moore’s Law. The law states that the number of transistors are doubled every 18
months. Factually, the main method of semiconductor industry to optimize performances and productivity is device
scaling [1]. For the submicron technologies, complementary metal oxide semiconductor (CMOS) technology has
faced many challenges due to the reduction of the devices’ dimensions. Using bulk devices it is difficult for the
industry to satisfy the Moore’s Law due to short channel effect (SCE) which cause junction’s leakage current
increases. As channel length decreases, threshold voltage will also decrease.
In order to optimize the performance of bulk silicon transistors but keeping the leakage under control, the
fabrication of the transistors have become complex and costly since several steps are added in the manufacturing
process. Hence a planar process technology called silicon on insulator (SOI) is introduced as alternative due to its
simple manufacturing process but having the benefits of reduced silicon geometries.
However SOI thickness variation can create a serious problem because threshold voltage can fluctuate in fully
depleted SOI (FDSOI) MOSFET. As for the simpler to manufacture partially depleted SOI (PDSOI) device, the
threshold voltage is stable since it is built on a thicker silicon layer. Conversely, the PDSOI devices are affected by
kink effect which are not appear in FDSOI devices.
Today’s SOI wafer is equipped with a unique feature which is a buried silicon oxide (BOX). It is layer covering
the entire wafer with a certain thickness. There are a lot of improved characteristics that had been raised by having a
BOX structure in the regular metal oxide semiconductor (MOS) structure. For example it will have a better isolation,

Advances in Electrical and Electronic Engineering: From Theory to Applications (Series 2)

AIP Conf. Proc. 2173, 020005-1–020005-9; https://doi.org/10.1063/1.5133920
Published by AIP Publishing. 978-0-7354-1920-9/$30.00

020005-1
reduce short channel effect, less leakage current, improve latch up free operation, radiation hardness and improve
switching speed. All these are due to less drain body capacitance in BOX structure devices [2].
The fabrication steps of FDSOI and PDSOI are not simple as compared to the bulk transistors and the cost
involved is very high. Several fabrication parameters such as channel length, silicon film thickness and doping
concentration will affect the performance of the transistors. Hence before fabricating the FDSOI and PDSOI
MOSFETs, several of these fabrication parameters will be varied in order to examine the effect of the parameters to
the electrical characteristic of the transistors. This is done before the actual fabrication takes place. By doing a
simulation on FDSOI and PDSOI parameters, the fabrication cost can be cut and how the transistors can be used as a
new alternative to bulk transistors can be understood well.

SOI TECHNOLOGY
Even though SOI CMOS technology has reached maturity after starting as a niche market, there are still rooms
for improvement. The development of SOI technology first starts in the early 1980s for military and power
applications. In the late 1990s, SOI is widely adopt for high-performance computing application by the integrated
device manufacture (IDM) community. Currently, traditional CMOS technology has been challenged by SOI
technology based on bulk silicon wafers in every sectors of the field. The major advantages of this technology are
SOI delivers high performance in power and speed as compared to bulk devices. In terms of device scaling SOI is
also better, thus taking a small chip area. The CMOS manufacturing process is also simpler for SOI and it can be co-
integrate easily with different materials at the wafer level.
As mentioned before, the unique buried oxide layer of SOI CMOS devices is used to isolate the body from the
substrate. In SOI the body terminal is either tied to gate or left free for floating (floating body). During operation, the
body of the SOI CMOS devices may be floating if no extra body contact is added. This floating body effect can
cause a problems in the SOI CMOS devices especially the PDSOI MOSFET. Nevertheless this effect can be
suppressed using body-control techniques.

SOI MOSFET
PDSOI and FDSOI MOSFET are the two types of SOI MOSFET. Usually the silicon film thickness is kept more
than the maximum depletion width of the gate for a reason. A SOI layer thickness around 50 nm to 200 nm for
example can alleviate the constraint on device threshold voltage and its sensitivity [1][3].
PDSOI devices are much easier to manufacture since the process steps are less. It is also more compatible to
traditional bulk CMOS. Generally, PDSOI device is optimal for faster speed and is widely used for applications that
require high clock rate. However, the floating body effect or kink effect which is the undepleted portion of the body
which is not connected to anything, is the major issue of the PDSOI device. This kink effect might result in higher
current consumption.
FDSOI is a new form of technology that can help semiconductor manufacturing industry to face the big hurdle in
scaling further down after 28 nm without increasing cost. It is said that FDSOI can take Moore‘s law down to 10 nm
[4]. In FDSOI MOSFET, the channel is completely depleted from the majority carrier as the silicon layer is very thin
between 5-20 nm [6]. Therefore, the SOI layer thickness is smaller than the depletion width of the device and the
gate terminal is controlling the potential of SOI layer. With this FDSOI MOSFET has an advantage over the PDSOI
MOSFET because the floating body effect can be eliminated and provide better short channel behaviour due to there
are no carriers can be charged at the neutral region of the FDSOI MOSFET body.
The planar process of FDSOI is a technology innovation that will ensure the continuation of efficiency
improvements projected by Moore’s law. FDSOI provides power reductions, die size reductions, better performance
and increased functionality as projected by Moore’s Law without introducing more complex manufacturing
processes. These benefits allow designers and manufacturers to create the truly innovative, break-through products
to make new markets or dominate established ones. The parasitic capacitance between the drain and source as
exhibited by bulk transistor is able to be reduced by FDSOI buried oxide layer. The buried oxide layer also limits
electrons flowing from the source to drain thus significantly reduce the leakage currents. However the thickness of
the silicon and the amount of doping concentration must be in the right value.

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 METHODOLOGY
In this study, Silvaco TCAD tools are used to simulate the n-channel SOI devices. Three tools are used which are
as follows:
1. The first is DeckBuild. It is the software that provides the interface to write or change the codes and
parameters of the device to be simulated.
2. The second one is TonyPlot. It is used to plot the graph using data extracted from the simulation.
3. Lastly is Atlas as the main tool to simulate the SOI devices and extract data to be analysed.

Simulation Process
The types of information flowing in and out of Atlas is depicted in Fig. 1. There are two types of input files for
Atlas simulations. First is a text file that contains commands for Atlas to execute and the second is a structure file
that defines the device structure that will be simulated. After simulation Atlas will generate three output files. Run-
time output is the first output file that provides the progress, error and warning messages when the simulation
proceeds. The second type of output file is the log file that stores all terminal voltages and currents from the device
analysis while the last is the solution file that stores two dimensional (2D) and three dimensional (3D) data relating
to the values of solution variables in the device at a specified bias point.
The order of statements in the mesh definition, structural definition, and solution groups plays significant role.
Error or termination of the program may occur when failure to place these statements in appropriate order. Table 1
shows that there are five groups of statements that must take place in the right order.

FIGURE 1. Inputs and outputs of Atlas [5]

TABLE 1. Atlas design flow

Group Statements
Structure Specification Mesh, Region, Electrode, Doping
Material Models Specification Materials, Models, Contacts, Interface
Numerical Method Selection Method
Solution Specification Log, Solve, Load, Save
Result Analysis Extract TonyPlot

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 RESULT AND DISCUSSION
The simulation and investigation of electrical parameters of n-channel FDSOI and PDSOI MOSFET has been
carried out by using Silvaco TCAD simulation software. The SOI structures are created using Atlas syntax and the
simulation results are displayed in TonyPlot.

Simulation Result of n-channel FDSOI MOSFET Structure

In this study, n-channel FDSOI MOSFET structure has been designed and simulated using DeckBuild. The
simulation result of the SOI MOSFET device structure is displayed in TonyPlot and this device has a gate length of
1 microns. The thickness of different material is defined when specifying the structure region. From the structure in
Fig. 2, it can be analysed that the gate oxide thickness at region 1 is 0.017 ȝm, thickness of silicon film at region 2 is
0.08 ȝm and region 3 is the buried oxide with thickness of 0.42 ȝm. The view of device structure displayed in
TonyPlot can be changed by selecting different features and Fig. 2 shows the n-channel FDSOI MOSFET structure
with features of contours. Contours is the colour plotting of impurity values.

FIGURE 2. N-channel FDSOI MOSFET structure with features of contours

Simulation Result of n-channel PDSOI MOSFET Structure

The simulation result of the PDSOI MOSFET device structure is displayed in TonyPlot. The thickness and
material are defined when specifying the structure region. Figure 3 shows the PDSOI structure definition using
Atlas syntax. This device has a gate oxide thickness of 0.017 ȝm at region 1 and a gate length of 1 microns. Besides,
thickness of silicon film at region 2 is 0.2 ȝm and region 3 is the buried oxide with thickness of 0.4 ȝm. The view of
device structure displayed in TonyPlot can be changed by selecting different features and Fig. 3 shows n-channel
PDSOI MOSFET structure with features of contours which is the colour plotting of impurity values.

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 FIGURE 3. N-channel PDSOI MOSFET structure with features of contours

Electrical Characteristics Comparison of FDSOI and PDSOI MOSFET

By changing the silicon film thickness, the electrical parameters of SOI MOSFET are recorded as shown in
Table II. The results in Table II are analysed and graph of electrical characteristics versus silicon film thickness are
plotted. The silicon film thickness that exceeds 0.15 μm is considered as PDSOI MOSFET while silicon film
thickness that is below 0.1 μm is FDSOI MOSFET [6].

TABLE II. Electrical characteristics of SOI n-MOSFET at different silicon film thickness

Silicon Electrical Characteristics

Film Thickness Threshold Voltage, Vth (V) Leakage current (pA)
0.06 μm 0.221402 0.023311
0.08 μm 0.364155 0.034335
0.10 μm 0.498589 0.045267
0.12 μm 0.606591 0.037810
0.14 μm 0.628683 0.026860
0.16 μm 0.634400 0.019994
0.18 μm 0.635558 0.016385
0.20 μm 0.635683 0.012710

Figure 4 shows the comparison of Ids/Vgs characteristics between FDSOI and PDSOI n-MOSFET. The silicon
film thicknesses for the result shown in the graph are 0.08 μm for FDSOI and 0.20 μm for PDSOI. Initially, drain
current remains zero and the current raises as the gate voltage increases until it reaches the threshold voltage. With
technology scaling, smaller value of threshold voltage is needed to satisfy high performance of device [7]. The result
of threshold voltage extracted from simulation for FDSOI and PDSOI are 0.3642 V and 0.6357 V. The MOSFET

020005-5
gate threshold voltage, Vgs(th) can be defined as the voltage between the gate and source required to trigger the
MOSFET [8], meaning that FDSOI MOSFET will turn on when the threshold voltage is equal to 0.3642 V while
PDSOI MOSFET will turn on when threshold voltage is equal to 0.6357 V. From the result, it can be said that the
threshold voltage of FDSOI n-MOSFET is smaller than PDSOI n-MOSFET. FDSOI devices achieved highest gains
in speed of circuit and power reduction. The reason of fast operation is because of a sharper sub-threshold slope and
threshold voltage reduction which allows a more rapidly switching of MOSFET [9].

FIGURE 4. Comparison of Ids/Vgs characteristics between FDSOI and PDSOI N-MOSFET

By varying the silicon film thickness, the result of threshold voltage has been recorded and the graph of
threshold voltage versus silicon film thickness is plotted and shown in Fig. 5. From Fig. 5, it can be said that the
thinner the silicon film thickness, the lower the threshold voltage. As the threshold voltage increases to 0.63 V when
silicon film thickness is above 0.14 μm, the voltage is almost constant. The threshold voltages of the FDSOI
MOSFETs with silicon film thickness 0.06 - 0.10 μm are smaller because the random dopant fluctuation has been
strongly reduced by FDSOI, hence lower the threshold voltage variation [10].

FIGURE 5. Graph of threshold voltage versus silicon film thickness

020005-6
 The result of leakage current is inversely proportional to the threshold voltage [11]. This means that value of
leakage current becomes smaller with the increasing of threshold voltage. The higher the threshold voltage, the
smaller the leakage current. MOSFET device will fail when excessive leakage current occurs. Comparing the results
of FDSOI and PDSOI, as shown in Fig. 6, it can be found out that the leakage current in PDSOI is smaller but the
difference is extremely small due to the unit of both SOI is in pico ampere (pA). Large leakage current of
conventional semiconductor is caused by the electron-hole pair generation due to ionizing radiations.

FIGURE 6. Comparison of leakage current between FDSOI and PDSOI n-MOSFET

The existence of buried oxide layer in SOI is able to avoid the radiation impacts in devices and circuits [12].
Leakage current contributes to static power dissipation and leakage power dissipation is caused by current flow
when input transition is absent and transistor achieved steady state [13]. Leakage power dissipation is caused by
current flow when input transition is absent and transistor achieved steady state [13]. Thus, by having a smaller
leakage current, static power dissipation will be less. Thus, from the result the PDSOI will have a higher static
power dissipation than FDSOI.
The graph of leakage current versus silicon film thickness is shown Fig. 7. The figure shows the leakage current
of SOI MOSFET with the varying silicon film thickness.

FIGURE 7. Graph of leakage current versus silicon film thickness

020005-7
 In Fig. 7, initially the leakage current increases when the silicon film thickness is increased from 0.06 μm to 0.10
μm. On the other hand, the value of leakage current decreases when the silicon film thickness is further increased
from 0.10 μm to 0.20 μm. However, the variation of leakage current result is extremely small, the biggest difference
is only 32.56 ൈ 10-15 (0.045267 p – 0.0127210 p) when silicon film thickness is changing. Thin silicon films is
required for the reduction of SCE to remove the subsurface leakage paths. The source to drain current is not allowed
to flow in a region close to the gate for superior gate control in thin body MOSFET. It prevents from mobility
degradation problem caused by impurity scattering as well as threshold voltage fluctuation because it does not
depend on heavily doped channel for the suppression of SCE [14].
Figure 8 shows the comparison on the existence of kink effect between FDSOI and PDSOI N-MOSFET in the
graph of Ids/Vgs characteristics for Vgs=1V, 2V and 3V. Kink effect is the result of a sudden increase of saturation
current in strong inversion condition [6]. This effect is considered as the major drawbacks of SOI technology as the
body is left floating [9]

FDSOI N-MOSFET

Vgs=3V

Vgs=2V

Vgs=1V

FIGURE 8. Comparison of kink effect between FDSOI and PDSOI N-MOSFET

Kink effect presents in the results of PDSOI n-MOSFET. However, FDSOI n-MOSFET is considered to be free
of the kink effect. Kink effect absents in FDSOI because the majority carriers is able to penetrate easily into the
source, preventing accumulation of excess carrier. Decreases of drain electric field and of source potential barrier
achieves a dramatic decline of kink effect [15]. This effect exists in PDSOI MOSFET when drain potential
increased, the electrons of channel gain sufficient energy in the drain to generate electron hole pairs. The electrons
generated transfer into the channel when holes moves to lowest potential which is the floating body [1].

CONCLUSION
The simulation of the 2D structures of n-channel FDSOI and PDSOI MOSFET has been carried out by using
Silvaco TCAD simulation software. Comparison of electrical characteristics of FDSOI and PDSOI has also been
done. It is found that the threshold voltage increased with the increasing of silicon film thickness on SOI MOSFET.
FDSOI has a better threshold voltage which is 0.3642 V as compared to 0.6357 V for the PDSOI. Hence FDSOI
MOSFET has a faster switching speed than PDSOI MOSFET. Since the threshold voltage of FDSOI is smaller than
PDSOI, the transconductance was improved and this allows a lower operating voltages. A smaller value of leakage
current can ensure a low power consumption in transistor. In this aspect PDSOI is better, but the leakage currents are
very small for both SOIs as they are in pA (10-12). The result shows that FDSOI MOSFET does not have the kink
effect which presents in PDSOI MOSFET. From the results and analysis obtained, FDSOI MOSFET has a better
performance compare to PDSOI MOSFET due to its smaller threshold voltage and elimination of kink effect in the
device.

020005-8
 ACKNOWLEDGMENT
The authors would like to express gratitude for financial support from Ministry of Education Malaysia (MOE)
under Fundamental Research Grant Scheme (FRGS) vot number 1630. Also thanks to Research Management Centre
(RMC), Faculty of Electrical and Electronic Engineering (FKEE) and Nano Simulation Focus Group (NanoSIM) of
Universiti Tun Hussein Onn Malaysia (UTHM) for the resources used in this research.

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