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INTRODUCTION

Chapter at a Glance
components one
Computer Organization concerned with the way the hardware
is
to a
the computer system. It refers the
and

the way they are connected together to form

architectural specifications. Oreanion
units & their interconnections that realize the s
i.e. as a designer, one must kno
basically the designer view of the computer hardware how
and implemented, how they ar
the different hardware elements are designed be

they operate. It basically deals with the in-depth detailed view of

interconnected, how the
computer hardware and also verifies whether the
computer parts do operate as intended
behaviour of the various funectional
Computer Architecture is the study of the structure and
modules of digital computers as seen by a programmer and also
r
how they interact to provide
the instruction formats, instu
the processing needs of the user. Architecture includes struction
imn
attributes of the system that have a direct
sets, and addressing modes. refers to those
It
hardware needed, w
on the logical execution of the program i.e. what are the basic the
functions they do, what are the elements that are needed for the direct execution' of
compter
programs, etc. It is.basically the higher-level or top-level functional view of the
hardware. Architecture does not provide any information regarding the detailed
implementation of the hardware elements.
Parts of a digital computer: A digital computer consists of the following main parts:
Central Processing Unit (CPU), Memory Unit, Vo (input-output) Unit.

Central Processing
Unit
Instructions

Program Control
Unit
Memory
Input
Output
Unit
Unit

Arithmetic Logic
Unit
Data
Block Diagram of a Digital computer

Strueture and Functions of the Different Units of a Digital Computer the

(a) Memory Unit: Its purpose is to store both instructions& data. It is also calle at
ocation
Random-Access Memory (RAM) because the CPU can access any memory locau
random. Ocessing
(b) CPU: t acts as the brain of the computer and performs the bulk of data prod
operations in a computer. The two main units of a CPU are the Arithmetic LogC
the Program Control Unit. The important parts of CPU are: arithmetic
Arithmetic Logie Unit (ALU): It performs instructions related to arnt
etc.
operations like ADD, SUB, MUL etc. and logical operations like AND, OR e

C0-2
 COMPUTER ORGANISATION
Gi) Program Control Unit (PCU):
& sequences which instruction It
interprets&
in a program sequences instr
(ii) ister Sets: These
T are collections is to be executednstructions i.e., interprets
out (1/0) Unit: This of registers that first.
stem (computer) unit provides an efficient store data.
e centra & the outside mode
the must b entered into computer memory environment. Throughof communicatio tion between
data for processing& the I/O unit, programs &
utations must be recorded or displayed results obtained
from
to the user.
Operating Systems:
Operating Syste
stem is a program (or
system software)
An
user of a computer & the
t computer hardware. that acts as an intermediary
a Its purpose between
whic user can execute programs is to provide an enviroiment in
conveniently. So, an «

hardware in an efficient manner. O.S. helps to use the computer

tions of an Operating System: O.S. has the following
dinates the efficient use of the functions.
(a) O.S. hardware:
perating System contr & coordinates the use
Mication programs of the hardware among the various
applica (like compilers, database systems,
games etc.) for the various users (like
people, machines, and other computers).
)(b) O.S. provides an environment within which other programs can do
Operating System proVIdes the means useful work:
for the proper use of the resources
software& data) of a compuer system in (like hardware,
the meaningful & smooth operation
computer. of
the
(c) O.S. acts as a resource allocator:
0.S. manages the various resources (hardware and software) of a computer system &
allocates them to specific programs & users as necessary for their tasks.
() O.S. acts a control program:
As a control program O.S. focuses on the need to control the operations of the various input-
output devices & user programs i.e. it controls the execution of user programs to prevent
errors& improper use of the computer.
Von Neumann Concept:
Neumanin proposed the idea, known as the stored- program concept, which deals with making
the programming process easier by representing programs in a form such that they can be
Suitably stored in memory alongside the data. So, a computer could get its instructions by
Tcading them from memory & also a program coud be set or altered depending on the
memory vailues. Thus Von Neumann introduced the key concept of stored programs (ie.
rograms & their data were located in the same memory) in the first generation computers.
NEumann published the idea in 1945 while proposing a new computer,
the EDVAC
(Electronic Discrete Variable Computer) and in 1946.

Multiple Choice Type 9uestions

1.ThebasicC WBUT 20071
0asic principle of the von Neumann computer is
a program and data in separate memory
b 9
0Using pipelining.concept
Storing proggra data in the same memory
both and
d)
Using
Auswer:(c) a r of
large number of registe
registers

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can detect
2.From a Source Code, a compiler b) Logical errors
NBUT
a) Run-time error d) None of these 2
c) Syntax error
Answer: (c)

3. How many minimum, NAND gates are required to make a flip-flon? WBUT
ha.

a) 4 b) 3 c) 2 d)5 20
Answer: ()

4. The basic principle of a Von Neumann computer is WBUT

201
a) storing program and data in separate memory
b) using pipeline concept
c) storing both program and data in the same memory
d) using a large number of register
Answer: (c)

5. The logic circuit in ALU is WBUT

a) entirely combinational b) combinational cum sequential201
c) entirely sequential d) none of these
Answer: (a)

6. The Von-Neumann bottleneck is a problem, which occurs due to wBUT 20

a) small size main memory
b) speed disparity between CPU and main memory
c) high speed CPU
d) malfunctioning of any unit in CPU
Answer: (6)

7. The circuit used to store one bit of data is known as WBUT 201
a) Register b) Encoder c) Decoder d) Flip-flop
Answer: (d)

8. SIMD represents an organization that WBUT 2016)

a refers to a computer system capable of processing several programs at

same time
b) represents organization of sjngle computer containing a control u
processor unit and a memory unit
mmon
c) includes many processing units under the supervision of a cout
control unit
d) none of these
Answer: (C)

9. The ALU makes use of ..

a) Accumulators b) Resisters
o store the intermediate results. Twp
2010

c) Heap d) Stack
Answer: (a)

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 COMPUTER ORGANISATION

program is usually in WBUT 2019

ource
sou
10ASsembly language b) Machine level language
cHigh-level
language d) Natural language

Answer:(c)

Short Answer Type Questions

the role of operating system? [WBUT 2002, 2003, 2005, 2006, 2008, 2011)
Wha s
1.
Answer:
computer hardware in an efficient manner, each omputer must have an
to use ass a
n Orag SYstem in it. An Operating System is a program (can also be consid
operating yst
system soft )that acts as an intermediary between a user of a computer & ne
hardware.
computer

Block
Diagram

Userl User2 User3 User n

Application Programs

Operating System
.

Computer Hardware

Operating System
Abstract view of the components of an

O.S. following functions.

has the
use of the hardware
O.S. coordinates the efficient the use of the hardware among the
various
perating System controls & coordinates
games etc.) för the various users
programs (like compilers, database systems,
cation
uke people, machines, and other computers). useful work
environment within which other programs can do
provides an resources (like hardware,
proper use of the
ng System provides the means for the the
meaningful & smooth operation of
computer system in the
aata) of a
Software
Computer.

as a resource allocator &

Oacts
O.S. (hardware and software) of a computer system
m
allora es
the various resources
programs & users as
tasks.
necessary for their
specific
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d) O.S. acts a control program

need to control the operations of tha
As a control program O.S. focuses on the
input-output devices & user programs i.e. controls
it the execution of user Drao
prevent errors & improper use of the computer.
Which is
2. Compare. between centralized and distributed architecture. is the
WBUT best
architecture among them and why? 20M4
Answer:
In centralized architecture, all the processors
access the physical main memor
memory words. The den.Oy
uniformly. All processors have equal access time to all
interactions among tasks is high. Thus probability of bus
conflicts is high. ecause of hee
frequent sharing of codes between two processors, The architecture is sown in the
following figure:
Captions:
Mi
Inter
connection
P=CPU
M Memory
Network module

M Shared memory

Centralized system

In distributed system, a local memory is attached with each processor. All local memories
distributed throughout the system from a global shared memory accessible by all
processors. A memory word access time varies with the location of the memory word in
the shared memory. The degree of interactions among tasks is less. Thus probability of
bus conflicts is also less. The distributed system is depicted in figure.
Captions:
Inter P=CPU
connection LM Local
Network memory to a
CPU

LM, Distributed system

It is faster to access a local memory with a local processor. The access of remote mei
attached to other processor takes longer due to the added delay through the is
connection network. Therefore, the distributed system is faster and in this regard,
it t
better.

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 COMPUTER ORGANISATION

enle role of operating system in a computer

Explanthe system. WBUT 20171
ADSwer: system has three main functions:
ting
Operatin
nputer's resources, such as
comnp
ge the the central processing
AO unit, memory, di
ma printers,
and user interface, and
es,blish a
estaó and nd prOvide services for applications software.
B)execute

Long AnswerType Questions

Von Neumann
Von architecture?
hat iiss
.What WBUT 2002, 2003, 2004,
2007, 2008, 2009, 2011, 2012]
Neumann bottleneck?
is Von
Whatis [WBUT 2002, 2003, 2004, 2006,
2007, 2008, 2009, 2011, 2012]
OR,
Neumann
Neumann bottleneck? How can this be reduced? WBUT 2015, 2016]
Whatis von
AnSwer:

Part:
Von Neumann was a mathematician who was a consultant on the ENIAC project
onic Numerical Integrator and Computer), the world's first general-purpose
edecronic digital computer
Naumann proposed the idea, known as the stored- program concept, which deals with
naking the programming process easier by representing programs in a form such that

hey can be suitably stored in memory alongside the data. So, a computer could get its
nstructions by reading them from memory & also a program could be set or altered
depending on the memory values.

The computer designed based on the idea of stored-program concept proposed by Von

Neumann is known as the LAS computer. It was designed at the Princeton Institute for
Advanced studies in 1952

ALU

Main
Input-Output
Equipment
Memory

PCU

Structure of the lAS çomputer

Main
Features of the LAS
Computer
main mory, which stores both data & instructions.
b) An arithmetic-logica binary data.
t) A unit (ALU) capable of operating on
)A which interprets the instructions in memory &
causes them to be
unit,
executed.
Input
output (1/O) unit operated by the control unit.

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in nature.
(e) The memory is read-write
are addressable by location.
() The contents of this memory
a sequential fashion from one instruction
(g) Execution generally occurs in
s

Von Neumann 'architecture'

same general structure&
All of today's computers, generally, having the
thus referred to as Von Neumann machines and
rred nction
this design is referred
to as the
Neumann architecture. Vo
2nd
Part:
Bottleneck of Von Neumann 'architecture
Since, the CPU has much higher speed than the main memory (RAM), the CD. U
wait longer to obtain a data-word from the memory. This CPU-memory speed speed hasy
disparit
referred to as Von Neumann Bottleneck.
This performance problem is reduced by using a special type fast memory called
memory between the CPU and main memory. The speed of cache memory ie
same as the CPU, for which there is almost no waiting time of the CPU for the ren
data-word to come. Another way to reduce the problem is by using specia
computers known as Reduced Instruction Set Computers (RISC). The intension of
RISC computer is to reduce the total number of the memory references made by
CPU; instead it uses large number of registers for same purpose.
Bandwidth between CPU and memory is very small in comparison with the amom mouN
of memory.
The address modification scheme in the TAS computer was inefficient and so. h
restart a program, the original unmodified program must be reloaded into man
memory.
No facilities were provided for structuring programs e,g. instructions to link progzm
modules such as subroutines (procedures) that implement frequently used progran
steps.
Floating-point arithmetic was not implemented due to the cost of hardware needed
As in each word two instructions were stored, hence the program control unit and te
instruction set got highly complicated.

2. Describe the function of Major Components of a digital computer with diagram

WBUT 2003, 2007, 201
OR,
Draw block diagram to illustrate the basic organization of computer system
a
explain the function of various units. [WBUT 2006, 201
OR,
WBUT 2012
Draw a diagram for digital computer.
OR,
WBUT201
Explain the basic block diagram of Computer System.

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 COMPUTER ORGANISATION

uter system consists of an interconnected system of processor memory and

ABSWer
compute
digital devices.
output
oceSsor is
also cal.lled central processing unit. It is the heart of any computc
ly doe
does the whole job of program execution. The central cessing
The which actually
micro computers is also called microprocessor. Main memory and central
used mi mounted on a single board called the mother board. For the program .
in
unil are
ngunitsOurce program that is the program written by the user and the data
ting the
erui.
quired for
it must be
:stored in the computer memory. Only then central processing unit
progran
as
the
5 second di d the computer component is main memory which is referred to
The memory, primar nary storage or common storage. It holds the source code or
to
grimanyDrogram is defined as an ordered set of instructions which can be used
prOgra unit consists of
problem. It holds data which may be input data. The memory
solve a which may assume
storage locations or cells. Each cell is a tiny device
lisand
many
binary digits as zero or one. This state of the celi represents
digit a single bit. The
of
state of binary
the
derived from binary
digits.
ward bit is
Input

Input
Devices

Memory
Control
Arithmetic Unit
Unit
Unit

Output
Devices

Output

important parts of the CPU are: arithmetic operation

instruction related
Arithmetic and logic unit: It
perform a program is
sequences which instruction in
and
gram control unit: It interprets
to be executed first.

collections of registers that store data

gister set: these are

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3. Writeshort notes on the following:

a) Von Neumann architecture WBUT
OR, 209
IAS computer WBUT
201m
b) Data flow architecture WBUT
Answer: 20
a) IAS computer:
Refer to Question No. 1 (" Part) of Long Answer ype Questions.
b) Data flow architecture:
Dataflow architectures do not have any program counter and conceptuaily, ücp.
whether input arguments to instructions are available (i.e. only if an operand is a
instructions are executed), the executability of instructions is determined. This
contrast to the commonly used Von Neumann architectures or the control
architectures. Dataflow architectures find their usage in specialized hardware used
in
digital signal processing, data warehousing, network routing, parallel computin
ani
graphics processing purposes.

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 COMPUTER ORGANISATION

COMPUTER ARITHMETIC

Chapter at a Glance
rithmetic Logic Unit: The Arithmetic Logic Unit or ALU performs arithmetic and logical
operation s on data in a digtal computer. The various other units and devices of the computer
actually bring data into the ALU for its processing and then takes the results out from
stem
SALU. The ALU operation is mainly based on the use of simple digital logic devices that
binary digitsto perform various simple Boolean logic operations.
ell in brief, ALU is an important component in the CPU of the digital co computer that
erfoms various arithmetic and logical operations. ALU actually gets data and supplies the
perform
rocessed data from and to the various other units.
The various registers (temporary storage locations within the CPU) connected by signal paths
to
the ALU, actually hold the data sent to the ALU for computations and also the results of the
computations. The various flags (whose values are stored in CPU registers) are set by the
ALU as the result of an operation. The operation of the ALU as well as the data movement
into and out of the ALU is controlled by the signals provided by the control unit.

Diagrams:
Figure 1, shows the ALU inputs and outputs, whereas figure 2, shows the CPU and its various
components (control unit is not shown here).

Control Unit Flags

ALU.
Registers
Registers
Fig. I: ALU inputs and outputs

Internal Bus

AC TEMP Flag
register

Fig: 2 CPU and internal

ALU registers

use the floating-

TEEE representation of floating point numbers: All modern computers
pont representation that was specified in IEEE standard 754. Here as was discussed before
numbers are represented by a mantissa and an exponent.
ut of the multiple number of bit widths specified by IEEE standard 754 for floating-point
commonly used widths.
nu SIngle-precision and double-precision widths are the most
are 32-bits long with 8-bits of
C shows the two formats. Single-precision numbers numbers are 64-bits
POnent, 23-bits of fraction and1 sign-bit, whereas double-precision
With 11-bits of exponent, 52-bits of fraction and sign-bit.
1

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Exponent Fraction
Sign-bit

23Single - precision (32 bits)

Exponent Fraction
Sign-bit

I52
Double-precision (64 bits)

Fig: 3 IEEE 754 Floating-point formats

carm.
adder: This circuit basically speeds up the generation of
Carry look-ahead i are
Signals
for sum (s,) and carry-out (c;) of stage
logic expressions
The
+1 = A,B, + Ac + B,c, = A;B, + (A; + B,)c,= G, + P.c
S A,OB, 9; and c;
+
where G, A,B; andP, = A, B.
generate and propagate functions for.stage
The expressions G, and P, are called the i
i is equal to
I
1.e. if G, = 1, then e 4
respectivèly. So if the generate function for stage +l
(when both A, and B, are equal to 1).
an output carry when enther
The propagate function (P) means that an input carry will produce e
onl
formed independently and in parallel
of A or B is 1. So all G and P functions can be
in

can be realzed as P, = A; B, then

one logic gate delay. Now, if the propagate function
gates (to realize 3-in
simple circuit can be derived using a cascade of two 2-input XOR
XOR function).
procedure by which binar
Booth's multiplication algorithm: Booth's algorithm provides a
integers in signed-2's complement representation (i.e. multipliers can be positive or negative
can be multiplied.
represented in signed.
Division Algorithm: Division of two fixed-point binary numbers
magnitude form is done by successive compare, shift and subtract technique.
However in

division, it may give rise to an overflow result i.e. if the expected quotient of
is n-bits but the

actual quotient comes as nt] bits then that condition is an overtlow condition,
which must be

taken care of.

Multiple Choice Type Questions

can be
1. With 2's Complement representation, the range of values that
represented on the data bus of an 8 bit micrO-processor is given by: 2012
a) -128 to + 127 b)-128 to + 128 WBUT 2003,
c)-127 to 128 d)-256 to + 256
Answer: (a)
the
2. When signed numbers are used in binary arithmetic, then which one o
following notations would have unique representation for zero0? 200
WBUT 2003, 2007, 2008,
a) Sign Magnitude b) 1's complement
C) 2's complement d) None
Answer: (c)
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 COMPUTER ORGANISATION

ubtractor can beimplemented using WBUT 2006, 2012, 2015

adder b) complementer
a)both (a) & (b) d) none of these
c)
An$wer:(c)

bit
Maximur 2's complement number is [WBUT 2007, 2009, 2015, 2018, 2019]
b) 2"-1 c) 2-1 d) Cannot be said
a) 2
Answer:(c)
01101107
o11011012 to 10100010, in 8-bit 2's complement binary will cause an
Adding
6
overtlow:
WBUT 2007, 2009]
True
b) False
a)
Answer: (6)

version of (FAF. into octal form is WBUT 2008, 2013]

6. The b) 76575372 c) 76737672 d) 76727672
76767676
a)
Answer: (b)
WBUT 2009]
Which logic gate has the highest speed? d) DTL
1.

ECL b) TTL c) RTL

a)
Answer: (C)

computer arithmetic is used for WBUT 2009, 2011]

Booth's algorithm for
in sign magnitude form
8.

a) multiplication of numbers
b) multiplication of
numbers in 2's complement form
magnitude form
c)division of numbers in signcomplement form
d) division of numbers
in 2's
Answer: (b)
WBUT 2009]
8. The conversion (FAFAFB)16 into
octal form is d) None of these
c) 76737672
a) 76767676 b) 76575372
Answer: (d)
the binary
Approximately, how many wouldWBUT 2009]
A decimal no. has 30 digits.
0representation have? d) 90
c) 60
a) 30 b) 32
Answer: (d)
WBUT 2009]
1. The logic circuit in ALU is sequential
b) Entirely
a) Entirely combinational d) None of these
Combinational cum sequentia
Answer:
(c) WBUT 2011]
will be d) FAAFAF
12.
Equivalent hexadecimal of (76575372), FFFAAA
c)
a) FAFAFF b) FAFAFA
Answer:
(b)
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fol
13. If you convert (+46.5) into a 24 bit floating point binary number following
convention, what would be the exponent? NBUT ER
c) 1100010
a) 00011100 b) 0000011 d) none 21
Answer: (d) ofhe

14. The maximum number of additions and subtractions are required for.
Booth's algorithm WBUT which
the following multiplier numbers 2014,20 g
in
a) 01000 1111 b) 0111 1000 c) 0000 1111
d) 0101010
Answer: (d)
15. By logical left-shifting the content of a register once, its content is WR
BUT
a) doubled b) halved 2019
c) both (a) and (b) d) no such decision can be
made
Answer: (d)
16. Floating point representation is used to store WBUT
201
a) Boolean values b) Whole numbers
c) Real numbers d) Integers
Answer: (c)
17. A given memory chip has 12 address pins and 4 data pins. It hasshe
number of locations. [WBUT2016
a) 2 b) 212 c) 245
d) 2
Answer: (b)
18. (2FAOc)16 WBUT 2016|
a) (195084)10 b) (00101111101000001100)2
c) Both (a) and (b) d) None of these
Answer: (6)
19.In a normal n-bit adder, to find out if an overflow has occurred, we make use of
[WBUT2017
a) AND gate b) NAND gate c) NOR gate d) XOR gate
Answer: (d)
20. For which of the following multiplier numbers in Booth's algorithm maximu
no. of additions and subtractions are required? WBUT 2018
a) 01001111 b) 01111000 c) 00001111 d) 01010101
Answer: (c)

21. In straight binary code, N-bits or N binary digits can represent.. e

values WBUT 2019
a) 2N b) 2(N+1) c) 2 (N-1) d) 24N-1
Answer: (a)

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 COMPUTER ORGANISATION

Short Answer Type Questions

relative advantages &
plain the
Expt disadvantages of parallel
adder over
dder.
421
[WBUT 2002, 2003, 2006, 2012)
Answer:
narallel adder: It is faster than the
Advantages f ofof parallel adder:
serial adder.
nalvantages main disadvantages parallel
ful of adder is the propagai
fcarry bit one full adder to next higher position full adder.
delayof Sufficient time must De
so that carry bit produced by the adder of the
slowea LSB will be Propagate through the
available at the next higher position
full adder before the addition is
pertoned
complexity is more than serial adder.
cuit
Cird

Compare Restoring & Non-Restoring Division algorithms.

2 WBUT 2003, 2005, 2006, 20071
Answer:
Restoring division
division
Restoring div operates on fixed-point fractional numbers and depends on the
following assumptions:
D<N
0< ND< 1.
The quotient q are ormed
digis irom the digit set {0,1).
Non-restoring division
Non-restoring division uses the digit set {-1,1} for the quotient digits instead of {0,1}.
Restoring division technique is the hardware method of performing division operations.
Here after each division step, the partial remainder obtained,
restored by adding the
divisor to the negative difference. This is done to get back the
original AC valic or to
restore the value after every division step.
Non-restoring division technique, if the difference is negative then the
divisor is not
added directly to the partial remainder. It is added only after
shifting the negative
difference to the left i.e. suppose while performing division
by restoring division
A leads to a negative result
technique, subtraction of the divisor content in D from that of
(Le. an unsuccessful subtraction). Still the value of A
is to be restored. This is however

unE consuming and can be seen as an

unnecessary overhead.. This drawback of the
ESIOring division technique can be avoided in the
non-restoring division technique.

WBUT 2004, 2008, 2009, 2011, 2015]

What are guard bits$?
OR, WBUT 2017]
What is
the necessity of guard bits?
Answer:
Guard present in the ALU registers that load the exponent
are additional or extra bits Guard bits are
and sigS a floating point operation.
prior to
Dasically ant of each operand
sically used place) the right end or the Significant with
extra
0'sto pad to pad out (i.e. to add or
0Keep the length of the numbers fixed.
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4. a) Briefly explain the IEEE 754 pointrepresentation

standard format for floating point represene
WBUT 2007, 2009, 2017,
Answer:
2019
All modem computers use the floating-point representation that was specified
cified
in1EEE
standard 754.
The floating point number can be stored in this format in any type of computer
30 29...24 23 22 21.... ...
S |E M

Signbit |
Exponent Mantissa
Bit 31 sign bit
Bit 30 to 23 exponent
22 to 0 mantissa
S is used to represent sign of a number.
S=0 for positive number
S=1 for negative number
M is the Mantissa which is a fraction and 23 bit long. The Mantissa is normalized tha
means it does not contain zero in its leading bits. a
b) How NaN (Not a Number) and Infinity are represented in this standard.
WBUT 2007
Answer:
NaN: NaN or Not a Number is the symbol for any invalid operation result. For example
dividing 0 by 0 or subtracting an infinite value from another would produce invalid
results, which would be represented by NaN. A NaN result would allow an user to
re
check a decision and figure out the problem.
Tnfinity: An exponent of all 1s and a fraction of all Os are used to denote the values of
+infinity and -infinity. The sign bit is used to distinguish between negative and positive
infinity.

5. Write +710 in IEEE 754 floating point representation in double precision.

WBUT 2009
OR
Write +710 in 1EEE 32 bit format. WBUT 2015
Answer:
Bit 31 (sign bit) for the given number is 0 (positive sign).
Bits 23 to 30 (exponent field): 1000000.
Bits 0 to 22 (significant): 1.11000000000000000000.
Hence, converting to hex, the result becomes 40E00000.

6/What are the advantages of CLA over ripple carry adder? WBUT 2011
Answer:
A cascaded connection of n full adder blocks, can be used
to add two n-bit nuli
Since, the carries must propagate or ripple through this n is
cascade, this configura
called an Ripple Carry Adder.

CO-16
 COMPUTER ORGANISATION

circuit nmust speed up the generation of the ca

adder carry signals. In case of a carry
the carry does not have to depend
ahead4 explicitly preceding one and
ctions of relevant addend and augend on the
ed as functio
expressed
a bits. So, the overall delay is
anDelesserthan t conventio
than the parallel adder.
mah
Booth's algorithm multiply (-12) and (+6). WBUT 2011]
ing
Ush OR,
1
(-12) and (+6), using Booth's multiplication algorithm.
Moutiply 12) WBUT 2017]
wer:
representation of 00 = 00110(multiplier)
binary
The
binar
resentation of 12 = 01100
The representation
binary tation of -12 = 2's complement of 01100 = 10100 (multiplicand)
The

0.Q BR=01100 BR+1 = 10100 AC QR Qa+1

SC
Initial 0 0000 00110 1 01
lashr AC.QR ([ncluding Qnti) 10000 00011
(Subtract BR 00100 00011 00
10010 00001 011
ashr AC,OR (IncludingQn) 11001 00000 j0 10
Add BR 00101
10010 10000 001
ashr AC.OR (Including Qn+i) 11001 010000 000
The answer is: 1100101000

&Apply Booth's algorithm to multiply the two numbers (6)10 and (-9)10. Assume
the multiplicand and multiplier to be
5 bits each. [WBUT 2012]

Answer:
0 0110
X
Y
x 1 01 11
-I 10 0 -1
9
recoded multiplier

Add-A +1 1 0
10
Shift 11101 010
Shift Only
1
1110
Shift Only 1
1111 010
Add A 0
0
1
10
0 0 1
0 1
01 0
1 0
Shift 0 0 01 00 T0
1
1
0
Add-A +I
11i00 01010
1111 0 0 0-54
1 1

Shift

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 POPULAR PUBLICATIONS

9.Represent (-9.50) is 64 bit IEEE floating point representation. NBUT

Answer: 20
The IEEE-754 foumat is as follows:
Bit 63: sign bit
form
Next 11-bit biased exponent represented in excess-1023
Next 52-bit normalized mantissa (magnitude), where the decimal point is as.
(integer + fracdo
just on the right of the most significant bit in the real number
1
action)
-1001.1 =-1.0011 2 to the
* power +3
Now,-9.5=
So, bit 63 =1
Exponent part= 1023 +3 1026D = 100 0000 0010B
Mantissa part = 00110..0 (0011 followed by 48 0's)
Hence the representation is C023000000000000H. .

10. Explain IEEE single precision formats for representing 10.5. WBUT2014
Answer:
10.5 1010.102 1.01010x 2
=
=
127 130 10000010 f=01010
=le=3+
The single-precision representation is:
I
10000010 01010000000000000000000

11.Convert IEEE 32-bit format404000001 in decimal value. WBUT 2019

Answer:
The given number in IEEE 32-bit format is 4040000016
=0100 0000 0100 0000 0000 0000 0000 0000
Since the leading bit is 0, the number is positive.
Next higher order 8-bit indicates the biased exponent (E') and it is (1000 00000) = 128
Therefore, the original exponent E = E"'-127 =128-127 =
1

The leading bit in mantissa (after binary point) is1, so the actual mantissa is (1.1)
Thus, the decimal number is= +(1.1> x 2 =+(11)>= +310

12. For Booth's algorithm, when do worst case and best case occur? Explain wih
2016
2015,
example. WBUT
Answer:
Worst case is one when there are maximum number of pairs of (01)s or (10)5 n
multipliers. Thus, maximum number of additions and subtractions are encountered nu
worst case.
equinng
Best case is one when there is a large block of consecutive is in the multipliers, requ
minimum number of additions and subtractions.
WBUT 201
13. Use restoring method to divide10100011 by 1011.
Answer:
(Unsigned numbers division)
Divide 163 by 11 using restoring division method.
Dividend, Q=163 = 10100011

CO-18
 COMPUTERORGANISATION
=
M=11
M= 00001011, M2c = 11110101
Divisor,
Iteration Step/Action Accumulator (A) Dividend/Quotient Divisor/Remark
(Q) (M)
Initial values 00000000
10100011 00001011
Shift left A, Q 00000001
0100011
Subtract A-M 11110101
11110110
01000110 SA=1:Q=0
Restore A+M 00001011
00000001
01000110
Shift left A,Q 00000010 1000110
Subtract, M 11110101
11110111 10001100 SA=1:Q1=0
Restore A+M 00001011
000000010 100011 00
Shift left A, Q 00000101 000110 0
Subtract, M 11110101
11111010 000110 0 0 SA=1;Q20
Restore A+M 00001011
00000101 0011000.
Shift left 00001010 0011000
Sub: A-M 11110101
1111 00110000 SA1:Q=0
Restore A+M 00001011
00001010 00110000
Shift left 00010100 0110000
Sub: A-M 11110101
00001001 01100001 Sa=.Qu=0
Shift left 00010010 1100001
11110101
Sub: A-M
000000111 1000011 SaF1;Qs=0

Shift left
0000111 1000011
11110101
Sub: A-M
00000100 1000011 SA1,Q,=0
00001001 000011
Shift left
Sub:A-M 110101 SA=1;Q%=0
11111110 90001119
11111110 00001110
00001011
Restore A-M
00001001 Q00011I0
Quotient=14
Remainder = 9

Hence 163+11 gives,

Q=14 and R = 9

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 POPULAR PUBLICATIONS

14. Show how to implement a full adder, by using half adders. WBUT
20M8
OR,
How can a full adder be implemented using half adders?
alain wit
Explain with
WBUTproper
circuit diagram. 2019
Answer:

C
HA

HA
S

Fig: Block diagram of full-adder implementation viaa

pair of half-adders

A full-adder can be constructed from two half-adders and an OR gate, as shown own in
Figure below. The explanation of why this works.is as follows. (In this paragran
raph, +
denotes addition, not the OR operation.) Consider the addition of x+ y+z. This can be
grouped as (*+ y) + z where (x+ y) represents the output of the half-adder that receiv es
x and y. This partial sum is added to z by the other half-adder, yielding the comple
sum bit S. As for C, consider that there are two possible ways to make C =1: fist, i
x+y=2, then adding z can only make the total sum 2 or 3, and either way C=1. In this
case, the first half-adder's carry-out is a 1. Second, if x+y =1, then C will be I onlyi
1 to make the total sum 2. In this case, the second half-adder's carry output will be 1.
Thus we see that C = if and only if at least one of the half-adders produces a carry-out
1

of 1. This corresponds to the OR of the two partial carry bits.

15. What is the difference between carry look ahead adder and ripple carry adder?
WBUT 2017

Answer:
A system of ripple-carry adders is a sequence of stândard full adders that makes i
possible to add numbers that contain more bits than that of a single full adder. Each full
adder has a carrying (Cin) and a carryout (Co) bit, and the adders are connected by
connecting Cout on step k to Cin On step k+1.
Carry lookahead adder is faster than ripple carry adler (also known as carry propagaio
adder) since it consists of carry lookahead circuit and all its inputs
given by G(x) and k
generator functions are calculated simultaneously.
But cost of Carry Lookahead Adder should be more since cost in digital logic means
many gates we are using, what is the FAN-IN of those gates. So in carry lookahead ac
we have carry lookahead circuit that contains many gates compared to carry propaga
To be precise, no. of gates used in carry lookahead circuit = O(n) which is much lag

CO-20
 COMPUTER ORGANISATION

used in carry propagation

gales used adder which is O(n).So cost car
ol o
n0.
adder is viously larger.
at
Man
ad
(ka/ncad ad
FA

An 1
Bn- B A
Ao Bo
Fig: 1Block diagram of an n-bit
ripple-carry adder

Cs

C2

Co

C-1
Fig: 2 Logic diagram of a 4-bit carry look ahead circuit

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POPULAR PUBLICATIONS

16. Represent the decimal value (-7.5) in IEEE single precision format.
WBUT
OR,
2
Represent the decimal value - 7.5 in 1EEE-754 single precision floating
fina.
format. WBUT2
Answer:
Thedecimal number-7.5 =- 111.1 in binary=- 1.11 x 2
The 23-bit mantissa M =0.111000 000000 000000 0000
The biased exponent E' = E+ 127 = 129 = 1000 0001
Since the number is negative, the sign bit S = 1. Therefore, the IEEE single-nres
-precision
bit) representation
is
1 10000001 111000 000000 000000 00000"

A7. Multiply decimal number (-17) and (-9) using Booth's multiplication
with step by step explanation. metho
WBUT 2018
Answer:
Multiplication between -17 and-9 using booth's Algorithm:

1I10,1111 -17
1111 0111 -9
000-1 100-1 Recorded
multiplier
Add-A 0001 0001
shift 0000 0001
1

Shift only 0000 0 10001

Shift only 0000 00 10001
Add A 110 1:11
1

1
111000 1001
Shift I111 10001001
Add-A 0001 0001
0000 1001 1001
Shift 00000100 11001
Shift only 0000-0010 011 001
Shift only 0000 0001 001 1001
Shift only 0000 0000 10011 0011

(10011001)1o= 153 (Ans.)

18. Explain in brief about different memon WBUT 2018

access methods.
Answer:
In computer organisation, an access method is ismthat
a program or a hardware mecna displa
moves data between the computer and an outlying
device such as a hard disk oraa
terminals.
CO-22
 COMPUTER ORGANISATION

access method. They are

types ofa
are 2aCcess and
There i) Sequential access.
iRandom

en used to describe data fields. Both type of files have advantages and
often
I is
disadvantages
access is bett than sequential access.
Randon

oresent the decimal value-12.5 in IEEE single precision format. WBUT 2019
Represent
19
Answer:
1100.10% = 1.1001x 23
12.5
le=3+ 127= 130= 10000010f=01010
single-precision representation is:
The
10000010 01010000000000000000000

Long Answer Type Questions

Explain Booth's algorithm for multiplication of signed-2's Complement numbers

uSing a flowchart& show how the multiplication is accomplished using a suitable
example. WBUT 2003, 2004, 2005, 2007, 2009, 2010, 2012]
OR,
Explain Booth's Algorithm with flow-chart and suitable example. [WBUT 2006, 2011]
OR,
Present the Booth's algorithm for multiplication of signed 2's complement
number
in a flow chart and explain.
WBUT 2017]
WBUT 2010]
llustrate this with an example by multiplying (-9) * (-13).
Answer:
Booth's algorithm provides a procedure by which binary
integers in signed-2's
Complerment representation (i.e. multipliers can be positive or negative)
can be multiplied.

ardware configuration for Booth's multiplication algoritnm

Diagram
Sequence counter
BR register (SC)

Complementer and
parallel adder

QR register
AC register

Thefigure Booth's algorithm.

shows the rdware implementation for

CO-23
 POPULAR PUBLICATIONS

its sign-bit.
Kegister BR: It holds the multiplicand along with
each stage of multiplication.
Register AC: It holds the partial product after
sign-bit.
Register QR: It holds the multiplier along with its
multiplier.
n I designates the least significant bit of the
en+ This is a flip-flop with the purpose of double-bit inspection
of the multiplie
1in the multiplie
Sequence Counter (SC): Keeps track of the number of bits and
multiplicand.
decrements by after each multiplier bit is multiplied to the
I

Booth algorithm gives a procedure for multiplying binary Integers in signed ed -Ts
complement representation.
Multiplicand in BR
Multiply Multiplier in QR

AC-0
Qn1-0
SCn

10 = 01

QQn+
AC-AC+BR+1 AC- AC + BR

= 00
11

ashr (AC & QR)

SC- SC -
1

#0
SC

END
D

Example
The binary representation of 9 = 01001
ne binary representation of-9 2's complement of 01001= 10111 (multiplicand
The binary representation of 13 = 01101
CO-24
 COMPUTER ORGANISATION

resentation of -13 = 2's complement 01101

representa
Thebinary of = 10011(multiplier)

BR=10111 BR+1 = 01001 AC QR SC

Initial 0 00000 |10011 0 101
Subtract BR 0 1 001
0 j0 1001
ashr ACQR (Including Qnt1) 00100 L1001 00
ashr AC,QR (Including Qn+1) Jo 0010 0 100 1
011
Add BR |10111
|1 1001
Jashr AC.QR (Including Qn1) 100 010
ashr AC,QR (Including Qns1)
101100
11 10 01011 J0 0 01
Subtract BR 0 1001
j0 0111
ashr AC.OR (Including Qn:) 0001
11

io101 | 000
0001110101
The answer is:

2. Multiply-5 by -3 using Booth's Algorithm. WBUT 2007, 2009]

Answer: =
The binary representation of 5 0101
= 2's complement of 0101 1011(multiplicand)
The binary representation of -5
The binary representation of 3
= 0011
= 1101(multiplier)
The binary representation of-3 = 2's complement of 0011
AC QR Q SC
QQ1 BR=1011 BR+I =0101
Initial |0000 1101 0 100
10 Subtract BR 0101
0101
ashr AC,QR (Including Qati) 0010 1110L 011
Add BR 1011
1110 1111 010
ashr AC.QR (Including Qnr)
Subtract BR 0 101-
0011
ashr AC.QR (Including Qa+) 0001 1111 00
ashr AC,QR (Including Qnt1) 0 000 1111L 000
The answer is: 00001111
floating-point
in lIEEE 754 single precision
the decimal value 7.5
-
epresent [WBUT 2008, 2011]
format.
Answer:
The IEEE-754 format is as follows.
Bit 31:
sign bit
Bit excess-127 form
30-23: 8-bit biased exponent represented in

CO-25
POPULARPUBLICATIONS

Bit 22-0: 23-bit normalized mantissa (magnitude), where the decimal

numho. Poin
assumed to lie just on the right of the m0st significant bit in the real
al number
I

(integer
fraction).
Now, -7.5= -111.1 =-1.111 * 2 to the power +2
So, bit 31 = 1

30-23 127 +2 129D 10000001B

22-0 I110....0 (3 1's followed by 20 0's)
Hence the representation is COF00000H.
WBUT
4. a) Compare parallel adder with serial adder. 2008,2011
Answer:
Both are used for adding binary numbers.
Serial Adder Parallel Adder
--

1. Serial Adder adds one bit at a time. 1. Parallel Adder adds the whole thingat sance
2. Serial adder is comparatively slower than
parallel adder.
2.adder.
Parallel adder is much faster than serial

3. Hardware needed for serial adder is less. 3. Hardware needed for parallel adder is more
4. Circuit in serial adder is less complex. 4. Circuit needed for parallel adder is morn
complex.

b) Explain and draw the 4-bit binary decrementer circuit. WBUT 2003
OR,
Explain and draw binary decrement unit.
a WBUT 2011
OR,
Design a 4-bit combinational circuit decrementer using four full adders.
WBUT 2016, 2018
Answer:

GRD

2 Y

L Output

Output
c Output
Output S1
Output

CO-26
 COMPUTER ORGANISATION
floating-point binary
32-bit number has a
umbers in the mantissa bit plus a sig
sign for the exponent.
tive
Negativ
epresenta What are and exponent
the longest and smallest are in signed-magnitua
cluding zero? Explain with es that can be
positive qualities
ented exclu example.
rnlain with diagrams, Serial & Parallel dders.
ADD
A+B, 1 63.11236589 x 10 &B 0.002365991 x 1029. WBUT 2009
Answer:
the. 32-bit
floating-point number system, negative numbers
ln are represented in
)
complement orm, where the leading bit is the sign bit. If, 24
npand 8 bits are reserved for bits are reserved for
mantis signed exponent, then the maximum
mber is + (longest)
positive
number +[2-1]* (2) and the minimum (smallest) positive
number is (0)
228
Serial Adder:
b)
adder is a binary adder that adds the two numbers
serial adde
A bit-pair wise. Each bit-pairs
added in a single clock
ock pulse. The carry of each pair is propagated to the next pair.
are

Circuit diagram:

DFF

CARRY
ADDER CLK

CO

SUM

LI

full adder as stated

Serial done by, in simplest terms, a flip-flop and a
Binary addition is
that can be confusing. Whena
above. However, there are slight nuances to the addition

Seial adder performs its addition, it is partially

dependent on the clock cycle as a flip-flop
s asynchronous and the full adder is not. Thus, when
a timing diagram is done, the sum
which
the inputs are changed, relative to the previous clock cycle
put will change as
USed to determine the carry in bit.
Example
of operation
Denary 5+9=14
e5, Y=9, Sum=14
Binary 0101+1001=1110
Addition
ofeach step
aputs
Outputs
Sum Cout

cO-27
 POPULAR PUBLICATIONS

addition starts from lowest

Result=1110 or 14

Parallel Adder:
A parallel adder is a binary adder that
generates the arithmetic sum of of two
cascaded full-adder circuits. Here the Dinary
numbers of any lengths using multiple output
from one full-adder is connected to the input fullat Her
carry of the next high order full-adder. a
pulse.
the entire addition is done in a single

X
XY
Carry
Cout
C2 in in -input
Co)

8
3
(a)

41-bit
adder
out CIn

(b)

binary
Parallel adder is the digital circuit that generates the arithmetic sum of two
constitute a paralle! adet.
numbers of any lengths. Multiple cascaded full-adder circuits
next high orde
The output carry from one full-adder is connected to the input carry of thefull-adders. 1
full-adder and so on. So an n-bit parallel (binary) adder requires n
R1) whie n
augend bits of X (say, n data bits) come from one register (say, Register
addend bits of B (n data bits) come from another register (say, register SubsCr
addend bits.
R2). u
numbers from right to left designates the augend bits and the
higher-order bit. Inemultiple
denotes the lower-order bit while the subscript n denotes the
input carry to the n
are connected in a chain through the full-adders. Co is the eneralted

cascaded binary adders and Cout is the output carry. The required
sum bits are
t(Sy
regicontent)
full-adders. The sum can be stored either to a third
by the outputs of the
S
its previous
Register R3) or may be in any one of the source registers (replacing

CO-28
 COMPUTER ORGANISATION

operation
Cample ofce that
'10 1.e.
1010 is to be added to
5' i.e. 0101. So the augen bits of
Ao
SUpill be
re 0, 1,
0 and (1.e. Ag will input
I
0, A will input 1, A2 will input 0 and
hroug
t
1). Similarly, for B also (the addend
1111 (1.e. 15).
bits). Adding the two numbers will
1

as So the output line So will

the output 1, S will output
and.
and Sa will output 1. In the example
output I there are no carry-bits.
will
3.11236589 x 105 63112365890000000
c) 02365991 102.365991E-32
B=0.002
x

addition: 12622473
4731780000000
Result of

non-restoring division algorithm and explain

oin the hardwire diagren.
6.
Perform
the Restoring division operation with 19 divided by 8. WBUT 2010]
Answer:
Part:
Non-restoring division algorithm:
Nat-restoring division uses the digit set
(-1,1} for the quotient digits instead of {0,13.
Non-restoring division technique, if the difference is negative then the divisor is not
dded directly to the partial remainder. It is added only after shifting the negative
adde
diference to the left 1.e. suppose while performing division by restoring division
1echnique,subtraction of the divisor content in D from that of A leads to a negative result
e. an unsuccessful subtraction). Still the value of A is to be restored. This is however
time consuming and can be seen as an unnecessary overhead. This drawback of the
restoring division technique can b avoided in the non-restoring division technique.
Algorithm:

STEP 1: DOn TIMES

IF THE SIGN OF A IS 0, SHIFT A AND Q LEFT ONE BINARY
POSITION AND SUBTRACT M FROM A;
OTHERWISE, SHIFT A AND Q LEFT AND ADD M TO A. IF THE SIGN
OF A IS 0, SET Q0 TO 1; OTHERWISE SET Q0 TO 0.
STEP 2: IF THE SIGN OF A IS 1, ADD M TO A
The negative result is restored by adding, i.e., Ri
(R- M) +M (1)
and is followed by a shift left one (i.e., multiplication by 2) and subtract:
Ri+
2 R-M (2)
The two operations (1) and (2) are then merged into a single one: Ri+1

2 [(R- M)+M]-M= 2 Ri -M

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 POPULAR PUBLICATIONS
1 000
Initially A O 0000
M 0 0011 1
00O First cycle
Shift O 000
Substra 111011 0000
01 1 10
Set LSB
100
0 o0
Shift
1 1
Second cycle
Add 00011
Set LSB 1 111
1 1 1
10
o0O Third cycle
Shift
Add 00011 oolo1
Set LSB Go001
0001 O olo Fourth cycle
Shift
Subtract 11101
111
olo1 10
Set LSB 1
Quotient
1 1 1 11
Add Restore
00011 remainder
Remainder 0 0010

Hardwire Diagram of Non-Restoring Division:

Remainder r Quotient

ADD/SUB
SignL Control
Divisor

Shift left
2nd
Part:
An
dn-l
Dividend E

n+l bit Add/Subtract

adder

Control
Sequencer

dn- do
Divisor D

Fig: Circuits for restoring division technique the

Ma
Now, as the rule of the division goes, 5-bit registers are used for the divisor (or
remainder A. Also, the high-order bit of M and all the bits in A are initially cleareu
made 0).

CO-30
 COMPUTER ORGANISATION

initial
nitial values in 1001, in M 01000 (5-bit register) and that
Therefore,
register). 2's complement of M is = 11000 i
00000 (5-bhit considered while subtracting
A; qocleared if a is -ve and set
as explained below:
division steps are
The
Cycle:
Q Explanation
A
ao 94 93. 92 qi qo
2. aa 0 0 11 Initial Values
0 0
00 0 0 0
1
1 0 Shifted Left as a Pair (A and Q)
00 01 1
0 0 10 1
M is subtracted from A
110 00 0 0 10 1

n 0 00 0 10
Since result is -ve, A is restored (Add M to A)
qo is cleared
00
2 Cycle:

0 0 01 0 01
0 100
0 0
I/!! 1 1
Shifted Left as a Pair (A and Q)
M
0 is subtracted from A
II01
0 10 0 11 0 0 Since result is-ve, A is restored (Add M to A)
0
0 010 0 00
1
go IS cleared
00
00
Cycle:
1
0 0
/I
11
0 0 0
0
00
Shift Left as a Pair (A and Q)
M is subtracted from A
I 1100 11 0 00 Since result is -ve, A is restored (Add M to A)
0 0 00 00
1

1
1 1
0 0 0 go is cleared
00

Cycle:
0 00 Shift Left as a Pair (A and Q)
01 0 0 110
10 0 00 Mis subtracted fromA
00 0 0
1

1 Since result is +ve, 9o Is set.

0 0 0110 0 0
$Cycle:
1
0. Shift Left as a Pair (A and Q)
00 01 1
0 0 0
M is subtracted from A
I10 11 0 0 0 0
1

restóred (Add M to A)
Since result is -ve, A is
00 0 1 1
00 0010 Go is cleared
0 0 1
100 10
remainder (the extra sign-bit is not
00011 is the =

re, the final value in A

ISIdered) and that in Q=00010 is the quotient.
advantages of a carry look ahead adder
OUW the logic diagram and discuss
the [WBUT 2010]
over
conventional parallel adder
OR, principles of
With construction and working WBUT 2011]
diagram discuss the
assuitable block dia
u 6-bit
carry-look-ahead adder.
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POPULAR PUBLICATIONS

A
Answer:

B cell

Ji

Bit-stage cell

B3 A B2 B Bo

B cell B cell
B cell B cell
C C

S3
S2

P 2

Carry-lookahead logic

G2 G Go

4-bit carry-lookahead adder

to add two n-I

In case of parallel adders, cascading of n-full adders are required right to left an
adders from
numbers together. The carry signals thus ripple' through the to
delay) to respond
all the related logic gates take a non-zero time delay (propagation o
parallel adders, the resulit
change in the input. This is because in case of conventional
of the previoUS
an addition of two bits depends on the carry generated by the addition
bits. So, the sum of the most significant bit is only available after
the carry signal
significant slu
i
rippled through the adder from the least significant stage to the most
depend explicu
But, in case of a carry-look ahead adder, the carry does not have to
addend and augen
the preceding one and can be expressed as functions of relevant
So, the overall delay is much lesser than the conventional parallel adder.
[WBUT2014
8. Design and describe a 4-bit ALU and its operations.
OR, includis
201
Design a 4-bit ALU capable of performing 14 different micro operatioa1
WBUT
logical, arithmetic and shifting operations.

CO-32
 COMPUTER ORGANISATION

Answer
ally, the operation
Finctuonall of typical ALU is represented
nown in diagram beloW,
as shov
$3 $2 S1

A0
FO
Al-
A2-
F2
A3-
F3
ALU
BU
BI
Cn+4
B2-
B3 P

-G

Fig: Functional representation

of Arithmetic Logic Unit

Functional Description of 4-bit Arithmetic Logic Unit

Controlled by the four function select inputs (SO to $3) and the mode control input
M). ALU can perform all the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands.
When the mode control input (M) is HIGH, all intermal carries are inhibited and the
device performs logic operations on the individual bits. When M is LOW, the carries
are enabled and the ALU performs arithmetic operations on the two 4-bit words. The
ALU incorporates full internal carry look-ahead and provides for either ripple carry

between devices using the Cnt4 output, or for carry look-ahead between packages
uSing the carry propagation (P) and carry generate (G) signals. P and G are not
affected by carry in.

For high-speed operation the device is used in conjunction with the ALU carry look-
ahead circuit. One
carry look-ahead package is required for each group of four ALU
devices. Carry
look-ahead can be provided at various levels and offers high-speed
capability over extremely long word lengths. The comparator output (A=B) of the
CvIce goes HIGH when all four function outputs (FO to F3) are HIGH and can be
logic equivalence over 4 bits when the unit is in the subtract mode.
do toIS Indicate
an open collector output and can be wired-AND with other A=B outputs to
The open drain output A=B should be used
d Comparison for more than in4 bits. order to establish a logic HIGH level. The A=B
t external pull-up resistor
can
Ihe
also be used with the Cn+4 signal to indicate A> B and A < B.

operations that are performed without a carry

table lists the arithmetic
Cion
in select code LHHL
RenaCOming carry adds a one to each operation. Thus,
carry in and
Rtner A minus B minus (2s complement notation) without a
1

enerates
A minus when
a arry is applied.
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 POPULAR PUBLICATIONS
y add:
actually performed by complementary addilion
Because subtraction is carry IS generated when there (ls
carry out means borrow; thus, a isno
complement), a
when there is underfloW.
generated
under-tlow and no carry is active LOw inputs producin.
indicated, the ALU can be used with either outputs
Cing active
As active HIGH
HIGH inputs producing
LOW outputs or with active Active high inputs and
outputs
Mode select inputs Arithmetic
S0
Logic (M=H)
Ss S (M=L:C=H)
A
A
A+B
A+B +B
AB minus
logical0
A plus AB
AB A minus B minus
AOB
AB minus 1
AB A plus AB
A+B A plus B
H L AOB
|
H H B (A+B) plus AB

AB AB minus
logical 1 A plus A
(A+B) plus A
A+B
A +B A
H H L (A + B).plus
A minuS
H | H H
A
Notes to the function tables
1.Each bit is shifted to the next more significant position.
2. Arithmetic operations expressed in 2s
complement notation.
H=HIGH voltage level
L = LOW voltage level
sequence o
holds
A the 8-bit number 11011101. Determine the
9. Suppose register
by a circular shift-1g
binary values in A after an arithmetic shift-right, followed
and followed by a logical shift-left.
b) Describe Booth's multiplication method and use this
to multiply decln
WBUT 2015
numbers -23 and 9.
Answer:
a)

After Arithmetic Shift Right

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 COMPUTER ORGANISATION
Right
CircularShit
Rer

Left
ogicalShift

Q.Qn+1 BR=101001 BR+ 1

= 010111 AC QR Qa SC
Initial 000000 001001 0 110
10 Subtract BR 010111
O10111 001001
ashr(sc= sc-1) 001011 100100 101
01 Add BR 101001
ashr(sc sc-1) 110100 100100
111010 010010 0 100
00 ashr(sc= sc-1) 111101 001001 0 011
10 Subtract BR 010111
010100
ashr(sc= sc-1) 001010 000100 O10
Add BR 101001
110011 000100 001
ashr(sc SC-1) 111001 100010
00 ashr(sc sc-1) 111100 110001 000

The answer is:111100110001

1. Divide (-15) by (-3) using Restoring & Non-restoring Division algorithm.

[WBUT 2017]
AnSwer

keare no simple algorithms for directly performing division on signed operands that.
Comparable to the algorithms for signed multiplication. In division the operands can
Preprocessed to transform them into positive values. After using restoring or non-
g division method the results are transformed to the correct signed values as
ary Here if we divide (-15) with (-3) are will get "0' as remainder and 5 quotient.
0 00000
S 00101
Q-15
M=3
A 00000
Q-01111
M= 00011
M =11100
M+1=1110

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 POPULAR PUBLICATIONS

Restoring method:
M A Q
00000 01111
00011
1111 Shift AQ
00000
11101 A A-M
1101 11110 Qp-0
00011
11110 Restore
00000 A
00001 1110 Shift AQ
11101 A A-M
110 11100 Q0=0
00011
00001 11100 Restore A
00011 1100 Shift AQ

I1 101 A A-M

j0000 11001 Q10=1

00001 1001 Shit AQ
101 A=A-M
10010 ofol-0
00011
00001 10010 Restore A
00011 0010 Shift AQ

11 101
A =A-M

A= Remainder
000 00101 Qo-
Q-Quotient
M+1=11101

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 COMPUTER ORGANISATION
pf-restoring method
M A
00000
00011
01111
00000
1111
11101 Shift AQ
A=A-M
11110 Ql0-0
T1011
1110 Shift AQ
00011
A= A+M
11100 Qfo]=0
11101
1100
Shift AQ
00011

jo000 A A+M
11001
00001 1001
Shift AQ
11101
A=A-M
11110 10010 Qf0-0
11101
0010 Shift AQ
00011
A=A+M
0 0000 00101 ofo]=
ARemainder
0-Quotient

1. a) Divided 43 by 11 using Non-restoring algorithm (The tracing table must be

shown
clearly)
Wnat is meant by overflow and underflow in signed magnitude representation of
umbers?
WBUT 2019]

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 POPULAR PUBLICATIONS

Answer: below:
Algorithm for Non-restoring division is given in
a)
Start

A 0
M Divisor
Q-Dividend
Count N

yes

Shift Left A. Q
Shift Left A, Q
A=A+M A A-M

yes no
A<0

Count-Count-1

no
Count-0

yes
yes
A=A+M ASO

no

End

Here, Dividend (A)= 43 101011

= 11 =
Divisor (B) 1011

Initialization:
Set Register A = 000000
Set register Q= 101011
Set M Divisor 001011
M' 2's complement of M=110101
Set count= 6, since 6 digits operation is being done here.

CO-38
 COMPUTER ORGANISATION

Action
Initial 000000 Q Count
101011
SHL (AQ) 000001 6
A2.0 01011
A A-M 101010
01011
A000
A <0 SiiL (AQ)
101010
010100
010110
10110
A A+M 101011
10110
A<0-Qo=0 101011
101100
<0SHL (AQ) 010111
A=A +MM 101110
01100
A 01100
A<0Qo=0(AQ)
101110 011000
011101 3
A0SHL
=A +M1 110100
T1000
A 11000
A0Q=0(AQ) 110100
101001
110000 2
A<0SHL 10000
A=A+M 000000 10000
000000
A<0Q=0 100001

A>0 SHL (AQ) 000000 00000

A A+M 101001 00000
101001
A0Q%=1 00011 0
A0A+M
Quotient (Q)=3
Therefore,
Remainder Quotient

by
Overflow:
Overflow occurs when there are insufficient bits in a binary number representation to
portray the result of an arithmetic operation. Overflow occurs because computer

nthmetic is not closed with respect to addition, subtraction, multiplication, or division.

bverfow cannot occur in addition (subtraction), if the operands have different signs.
1o
detect and compensate for overflow, one needs ntl bits if an n-bit
number
bits are required to
presentation is employed. For example, in 32-bit arithmetic, 33
in addition (subtraction) by
compensate for overflow. This can be implemented
Or
ting a carry (borrow) occur into the sign bit.
Underflow:
operation result in a number that
wSrefer to floating point underflow, where an
i example, if the exponent part can
represent values
tO be representable. For
from than 2--127 may cause
-127 to 127, then any number with absolute value less
Underflow.

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POPULAR PUBLICATIONS

12. Write short notes on the following: WBUT

2007,
a) Adder-subtractor circuit NBUT 2008
D09
b) Non-restoring division method WBUT 2008
c) Booth's algorithm WBUT 2008
d) Carry Look-ahead Adder 2018
WBUT 2018
e) Design of 4-bit ALU WBUT
f)Overflow in Fixed-point Representation 2018
WBUT 2019
g) Resorting Division Algorithm WBUT
h) IEEE double precision format 2019
Answer:
a) Adder-subtractor circuit:
combined nto one Common cireute
The addition and subtraction operations can be t by
including an exclusive-OR gate with each full adder.
b b
sub

d2

Co
C Ca

S So
S
A 4-bit adder-subtractor circuit is shown in the above figure.
The mode input sub controls
the circuit becomes an
the operation. When sub=0 the circuit is an adder and when sub=I
inputs of b. When
subtractor. Each exclusive-OR gate receives input sub and one of the
input carry is 0, and
sub-0,we have b 9 0=b. The full adder receives the value of b, the inputs
a
the circuit performs plus b. When sub =1, we have b 1=b' and Co =1. The b
the
1 is added through the input carry. The circuit performs
are all complemented and a
gives (a-b) if a
operation a plus the 2's complement of B. For unsigned numbers, this
is (a-5) providco
or the 2's complement of (b-a) if a<b. For signed numbers, the result
that there is no overflow.

b) Non-restoring division:
Refer to Question No. 6 of Long Answer 1ype Questions.

c) Booth's algorithm:
Refer to Question No.
Il
of Long Answer Type Questions.

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 COMPUTER ORGANISATION

aok-ahead Adder:
Look-
CaryDuestion o. 7 ofLong Answer Type
Questions.
o
Rr
Designof
4-bit ALU:
No. 8 of Long Answer Type Questions.
Fixed-
Fixed-point Representation:
nOverllowin
in
Is an iimportant consideration when
handling is
Oerlow digital implementing signal
w
ypical digital signal processing CPUs processin
include hardware
fgorithms. support forharidiing
RISC process may
Some include in these modes.
wr
oWh
Overilow
2s complement integers occurs when the Tesult of an additionor
WIin 2's

tion is
larger the largest integer that can be represented, or smaller integer. In
fixea
represe he largest or smallest value depends
resentation, the on the format of the number.
int ASSume, 32 bit register, a CPU with saturation arithmetic
me. a 32
Suppose, would set the result
overtlo
on an overflow; corresponding to the integer values 0 x 800000000.
or +I

Resorting Division
Algorithm:
gRestoring division operates on IIXed-point fractional numbers and depends on the
divisi
following
assumptions:

D<N
ND < 1.
0< med from the digit set {0,1}.
The
q are
quotient digits
is the dware method of performing division operations.
Restoring division technique
Here
after each division step, the partial
remainder obtained, restored by adding the

ivisor to the negative diilerence.

his is done to get back the original AC value or to
1

rstore the value after

every division step.

b) IEEE double precision format:

Double-precision floating-point format is a computer number format,
usually occupying
a wide dynamic range of numeric values by
6 bits i coinputer memory. It represents
USing
a floating radix point.

FHOoating
point is used to represent firactional
values, or when a wider range is needed than
Bprovided by fixed point (of the same bit width),
even if at the cost of precision. Double
precision would be
may be chosen when the range or precision of single
Pesion
Insufticient.

E 1EEE 754 standard specifies a binary64 as having

'Sign bit: I bit
Exponent: 11 bits
Sgnificant precision: 53 bits (52 explicitly stored) number is zero,
e sign bit determines number (including when this
the sign of the
Which
is signed).

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 POPULARPUBLICATIiONS

unsigned integer from 0 to 2047, in biased form

is an 11-bit
The exponent field actual zero. Exponents range from-1022
exponent value of 1023
represents the
+1024 (all 1s) are reserved for special n1023
(all Os) and decimal digits ne
because exponents of-1023 15 to 17 significant
significant precision gives from significant digits
ecision
The 53-bit 15 is
x 10-16). If a
decimal string with at mOst convert
decimoled
(2-531.11 double-precision representation, and then converied back to a
to IEEE 754
digits, the final result should match the original strinng lf an
with the same number of string with
number is converted to decimal
a at least
IEEE 754 double-precision double-precision representation, the c
back to final
significant digits, and then converted
number.
result must mateh the original
having an impiicit integer bit of vaiue fevee
i

is written with the significant XCept

The format the fraction
eneoding below). With the 52 bits of (F)
for special data, see the exponent therefore h
format, the total precIsion is 53
significant appearing in the memory
= 15.955). The bits are laid out as folloue
(approximately 16 decimal digits, 53 loglO(2)
fraction
exponent
(52 bit)
(11 bit)
Sign

IIIIIIIIIIIIIIIIIIIIIIIIN
63 52
 COMPUTER ORGANISATION

INSTRUCTION
SET
Chapter ata Glance
Instru
tion set: Instruction set is the set of instructions
Instruction
cular machine has its own set of instructions that a machine is able to execuc.
Each parti i.e. an instruction set, which
instructions used in that particular consists
of ang computer, varies from computer
On the specific organization and architecture to computcr
of the computer.
depion
Instructio format: nstruction format deals with
ion has three parts. The opcode part, the looks of a basic instruction. Eacn
the 'addressing mode operands or
part and the op
address' (i.e. operand address) part. The operation field is called
the 'opcode or the
ation code. The operand/address fields contain either
the operands themselves or the
addresses of storage
age locations of the data or
arguments (i.e. addresses of operands) in main
or in the processor depending on the various addressing
modes () as specified in a
particular instruction.
Three, Two, one and zero address instructions:
) Three-address instructions:
to
these type of instructions, all operand addresses are explicitly defined. Here the instruction
farmat has three different address fields specitying a memory
or a processor register operand.
Advantages:
in short programs when evaluating arithmetic expressions.
0t results
(i) Less execution time.
(i) Two-address instructions:
Here the instruction format has two different address fields, each specifying either a memory
or a processor register operand.
Advantages: Less execution time compare to one-address instructions.
(ii) One-address instructions:
Such instruction format has a single explicit address field and uses an implied accumulator
(AC) register for all data manipulation.

Advantages
) Much less number of bits is required to specify the single operand address.
(i) Less complicated decoding and processing circuit is needed.
(iv) Zero-address Instructions:
PUSH and POP
uch instructions do not contain any explicit addresses (except for
operands required must be
nstructions). As the operands are stored in a pushdown stack (the
tnere in the top positions in the stack), hence no addresses are required.
Auvantages: Do not contain any explicit addresses. So instructions are simple.
Different types of addressing modes:
) Implied Mode
() Immediate Addressing Mode
(m) Register
Mode or Register Direct Mode
(v)Register Indirect
Mode
) Auto-increment
(vi) Auto-decrement
Mode
ode
(Vin)
Direct Address
Mode

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 POPULARPUBLICATIONS

Mode
(viii) Indirect Address
Address Mode
(ix) Relative Addressing Mode
Program Counter) Relative
(a) PC (i.e. Addressing Mode
Mode or lIndex Register Relative
(b) Indexed Addressing
(c) Base Register Addressing Mode
(x) Stack Addressing Mode

Multiple Choice Type Questions

WBUT 2006, 2007, 2011, 2012, 2015 2018)
1.Instruction cycle is b) decode-fetch-execution
a) fetch-decode-execution
d) none of these
c) fetch-execution-decode
Answer: (a)
WBUT 2007, 2011, 2015, 2018
2. Micro instructions are kept in
b) Control memory
a) Main memory
d) None of these
c) Cache memory
Answer: (6)
in the instruction PUSH B2
3. Which of the following addressing modes is used [WBUT 2008, 2011
b) Register
a) Immediate
c) Direct d) Register Indirect
Answer: (b)
the following addressing modes is used in instruction
RAL
4. Which of
WBUT 2012
a) immediate b) implied c) direct d) register
Answer: (b)
5. Which of the following address modes is used in the instruction 'POP B'?
WBUT 2013
immediate
a) b) register c) direct d) register indirect
Answer: (d)
WBUT 2014
6. A computer uses words of size 32-bit. The instruction
a) may or may not be one byte length
b) must always be fetched in one cycle with 2 bytes in the cycle
c) must always be fetched two cycles with one byte in each cycle
i

d) must be of 2 bytes length

Answer: (c)
WBUT 2014
7. The CPl value for RISC processor is these
a) 1 b) 2 c) 3 d) none of
Answer: (a)
toredi
8. In the processor, the address of the next instruction to be executed 5T 2015
WBUT 2015
a) stack pointer register b) index register
c) base register d) program counter register
Answer: (c)
CO-44
 COMPUTER ORGANISATION
stack-organised compute uses
struction of
Indirect Idressing WBUT 2016]
a) addressing b) Two addressing
c) Zero d) Index
addressing
Answer: (c)
performin
sorming a looping operation,
When the instruction
10. Registers gets stored in the
a) b) Cache
c)
System heap d) System NBUT 2017]
stack
Answer: (b)
of Zero-address instruction method
case of.
11. In the operands are stored in
Registers b) Accumulators WBUT 2017]
a) c) Stack
d) Cache
Answer: (c)

The addressing mode(s), which uses the PC instead of a general purpose

12.
register is [WBUT 2017]
a) Indexed with offset b) Relative
c) Direct d) Both (a) and (b)
Answer: (b)

13. How many memory locations can be addressed by a 32-bit computer?

WBUT 2018]
a) 64 KB b) 32 KB c) 4 GB d) 4 MB
Answer: (a)
14. The addressing mode of an instruction is resolved by WBUT 2018]
a) ALU b) DMA controller c) CU d) program
Answer: (b)

15. The addressing mode, where you directly specify the operand value is
WBUT 2019]
c) Definite d) Relative
a) Immediate b) Direct
Answer: (a)
WBUT 2019]
16. How address of base-register calculated?
is the effective
contents to the partial address in instruction
a By addition of base register
to the partial address in instruction
D By addition of implied register contents
contents to the complete address
in
c) By addition of base register
in
instruction
register contents to the complete address
y addition of implied
instruction
Answer:
(a)

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POPULAR PUBLICATIONS

Short Answer Type Questions

1. Explain the difference between three-address, two-address, one-ad
instructions & zero-address instruction with suitable examples. WBUT 2007,
2011,
OR, 2013
20s
Evaluate the following arithmetic expression into three-address, two-add.ress,
address, zero-address instruction format. WBUT
2015, ne 201
X=(4+B)**C
Answer:
Three Address Instructions:
In three-address instructions all operand addresses are explicitly defined
and
instruction format has three different address fields specifying a memory or a n
register operand. For example, evaluating X = (A+B)*C in a three-addresS macht
will
result to:
ADD T, A, B T-A +B
MULTIPLY X, C,T X-C*T
Use:
Cyber 170 is a commercial computer using three-address instructions.

Two Address Instructions:

In two-address instructions, the instruction format
has two different address fields, each
specifying either a memory or a processor register operand.
Evaluating X =(A+B*C ina
two-address machine will result to:
MOVE T,A T-A
ADD T, B T-T+B
MULTIPLY C,T X-C*T
Use:
Two-address instructions are used in all commercial
computers.
One Address Instruction:
For one-uddress instructions, the
instruction format has a single explicit address neu
and uses an implied accumulator (AC)
register for all data manipulation. Evauau
X=(A+B)*C in a two-address machine
will result to:
LOAD A
transfer certain memory content to accumulator
ADD B
AC -AC +B
STORE T
transfer AC Content to memory location
LOAD C
transfer C to accumulator
MULTIPLY T
STORE X AC-AC *T
transfer result to memory
location X

CO-46
 COMPUTER ORGANISATION

Intel 8085 machine

Instruction:
gero Address
es instructions
Zero-addr do not contain
POP
instruc ions). As the operands any explicit
are stored addresses
there in a pushdown (except for
or PUSH and
must be here in the top poSItions
x = (A+B)*C in a two-address
in the stack), stack (the operands require
Evaluating hence no
PUSH A machine addresses are
will result required.
PUSH B
to
ADD
PUSH C
MPY
POP X

Use:
In all stack-type computers.

Given an
a example and explain
Base-index Addressing.
Answer: [WBUT 2007,
2011, 2012]
In ase-Index addressing
mode, the effective
cific base register and
speci address is the
sum
addressing mode
that of the specific index register. of the contents of the
could be useful in accessing For example, such
elements of an an
reaister would hold the array. In
starting location of the this case, the base
would contain the location specified array and
of the offset. the index register

3.Compare and contrast RISC

and CisC architecture.
WBUT 2009, 2011, 2017,
Answer 2019]
RISC
i) Multiple
register sets, often consisting of CISC
more|i) Single register set, typically 6
than 256
registers. to 16 registers
i) Three register operands total.
allowed per instruction i) One or
(egadd Ri, R2, Ra) two register operands allowed
per
n) Parameter passing
instruction (e.g.add Ri, Ra)
through efficient on chipliü) Parameter
register windows. passing through inefficient off-
w) Single chip memory
cycle instructions (except for load and iv)
store). Multiple cycle instruction.
) Hardwired control.
vi) Highly
pipelined. v) Micro-programmed control.
vi) Less pipelined.
Simple instructions that are few in number.
Vin)
Fixed length vii) Many complex instructions.
instructions.
K) Complexity vii) Variable length instructions.
in compiler.
y load and store instructions can ix) Complexity in microcode.
memory access|x) Many instructions can access memory.
) Few addressing
modes. xI) Many addressing modes.
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POPULAR PUBLICATIONS
mode over direct addree
address
advantages of relative addressing [WBUT 2011
mode
4. What are the
to the address part
Answer: CPU register is added
operand (i.e. the effective addofth
content of the
In such modes the address of the
instruction to obtain the actual The
is usually a signed number (either
instruction, which
address part of the
the CPU register content, gives the effective addrve
ss whose
o
negative) on addition to next instruction.
in memory is relative to the address of the
position
Uses: instructions.
addressing mode is often used with branch-type
Relative format as the relativ
also results in shorter address field in the instruction
number of bits compared to the numherve
This mode
be specified with a smaller of bits
address can
memory address.
required to designate the entire
effective address of the operand is equal tot ne
Where as, in Direct addressing mode, the the
the instruction i.e. the address part of the instruction indicates
address part of
location containing the operand.
in brief. Explain PC-relative addresei.
5.Compare RISC and CISC architectures ssing
WBUT 2013]
mode with example.
Answer:
Type Questions.
Refer to Question No. 3 & 4 of Short Answer
32 bits each. A binar
computer uses a memory unit with 256 words of
K inary
6. A an
is stored in one word memory. The instruction has four parts:
instruction code
part to specify one of 64 registers
indirect bit, an operation code, a register code
and an address part. part and the
i) How many bits are there in the operation code, the register code
address part?
ii) Draw the instruction word format and indicate the number.of bits
in each part.

ii) How many bits are there in the data and address inputs of the memory?
WBUT 2013, 2016)

Answer:
is of 32 bits.
i) Memory has 256K words = 2 words so need 18bit address bus, word size
represent
So one instruction is also of 32 bits size. There are 64 registers, so 6 bits need to
the registerpart. Hencefor opcode part we need 32-(1+18+6) =7 bits.

ii)
indirect bit operation code register code address part
(1bit) (7 bits) (6bits) (18bits)

ii) There are 32bits data input and 18bits address input in memory.

CO-48
 COMPUTER ORGANISATION
indirect ad ress mode. How
Explain is the effective
address calculated in this
CAse? [WBUT 2016]
Answer:
Pstion No
Duestion No. Iof LongAnswer Type Questions.
Referto

h exampl Register Direct,

example:
Explain witn Register Indirect
mode. and Base registe
ressing
addres
WBUT 2018]
Answer:
1estion No. 1
of Long Answer Type
Questions.
Evaluate
te the following arithmetic expression
into (i) three address,
addres (ii) one address and (iv) zero address (in) two
instruction form
format X = (A
+D).
+ B)' (C
[WBUT 2019]
Answer:
Three-address machine:
ADDITION ADD X, A, B
ADDITION:ADD Z, C, D
X-A+B
Z-C+D
MULTIPLY: MUL 2, X,Z
Z-Z*X
machine:
(i) Two-address
MOV RI, A R1 M[A]
ADD , B RI RI+M[B]
MOV R2, C R2 C
ADD R2, D R2 = R2+D
MUL R1, R2 R1 =R1* R2
MOV X, R1 M[X]= RI

ii) One-address machine:

LOAD A
AC- A
ADD B

STOR X
AC - AC +B
X AC
LOAD C AC -C
ADD D
AC- AC +D
MUL X
AC X* AC
(v) Zero-address
machine:
PUSH
A TOP= A
PUSH
B TOP B
ADD
TOP A+B
PUSH
C TOP C
PUSH
D TOP D
ADD
TOP C+D
MUL
POP
TOP (C+D)*(A+B)
X M[X]= TOP

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Long Answer Type Questions

1. Describe briefly different addressing modes with suitable examples
WBUT es.
2003, 2005,
OR,
201%
Write down the type of addressing modes. Explain with examples.
WBUT
Answer: 2013
Addressing
Mode

Impiied Immediate Register Register Auto Auto Direct Indirect

Mode Mode Mode Indirect Relative
Increment decrement Address Address
Mode Mode Address Stack
Mode Mode Mode Addressing
Mode
Mode

PC Relative
Index
Addressng Register Base
Mode Register
Relative Addressing
Addressing
Mode
Mode
) Implied Mode:
In this mode the operands are specified
'implicitly' in the definition of the instructionie
the operands are implied instruction definition. Operands
need not be specified explicitly
Example:
Complement Accumulator: The above instruction is
an implied-mode instruction because
the operand in the accumulator register is implied in
the definition of the instruction. The
operand need not be specified explicitly.

(ii) Immediate Addressing Mode:

In this mode the operand is itself
specified in the instruction operand field. Here the
operand value is a constant.

Example:
LOADI 99 or LOADtmmediate
99
Instruction
This means that 99 (i.e. the data or the
LOADI 99 operand) are to be loaded in the
Accumulator as has been shown in the
figure. In this mode the instruction has an
Accumulator operand field rather than an address field.

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 COMPUTER ORGANISATION
Register Mode or Register Direct Mode:
4e
ilthismode the operands reside in registers
directly in the CPU registers.
that reside within
the CPUi
U i.e. the operands
reside

Example:
ADDRegister direct B
Register B
Here B is a
CPU register and the
99 content of which
is 99 i.e. this content
reside directly within
the CPU register
B (means
the address of this operand
is
the CPU register B).
Hence, this content
Accumulator must get added
to the content of the
accumulator.
CPU

Register Indirect Mode:

(iv)

his mode the instruction specifies

a register in
the CPU whose contents give
oddress of the operand in memory the
1.e. the content
of the CPU register is the address of the
operand's location in the memory.

Example:
ADDRegister Indirect 5
Memory
Register B
Here the content of the CPU register B
(i.e. W) is the memory location
that
contains the operand 99. So the register
99 w B contains the address of the operand
99. This operand (99) is to be added
to
Accumulator the accumulator content.

CPU memory location

(o)Autoincrement Mode (vi) Autodecrement Mode:

These two addressing modes are similar to the register indirect
mode except that the
register is incremented or decremented after or before
its value is used to access memory
1e. the content of the register (given in
the instruction) is incremented or decremented
accordingly and then that memory location (i.e. the resultant memory
location) is looked
upon for the actual
operand.
nen the address stored in the register refers to table of data in memory, it IS necessary
ncrement or decrement the register after every access to the table. The increment or
Oecrement instruction helps
to achieve this.
Example:

ADDAufoincrement/ Autodecrement B

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Suppose the CPU register B has in it the memory location address 2010
memory Let the
location has this address 2010 containing the operand 99. So this operand
c
Is
added to the accumulator content. Again if there is a table of memory locatio Wil
from address 2010 (and increasing downwards), then just incrementing hSarin
ng
content by 1(2010+1=2011), the operand in 2011 location can be accessed and registe
new accumulator content. This may continue until the operands in all all the tded
memory
locations in the table are added to the previous accumulator content.
If however memory is increasing in descending order, then the register content
conte needs
be decremented by each time.1

to

(vi) Direct Address Mode:

In this mode, the effective address of the operand Is equal to the
address parto
instruction i.e. the address part of the instruction indicates the memory of the
location
containing the operand.

Example:
LOAD Memory Direet X
Memory
Instruction
In the example, the memory
LOAD
location X contains the
operand 99 to be loaded in
the accumulator.
Accumulator

(vii) Indirect Address Mode:

In this mode the address field of the instruction
gives the address where the effective
address is stored in memory i.e. the address part
of the instruction indicates the memory
location whose content is the address of
the memory location containing the actual
operand.

Example:
LOAD Memory Indirect W
Memory
In the example, the memory
Instruction W location w
contains X, which is the memory location
LOAD W
whose content is the actual operand 99. This
operand is to be ultimately loaded in the
99 X
accumulator.
Accumulator

The remaining addressing modes require

that the address field of the instruction be
to the content of a specific register in
the CPU. The actual operand ae
effective address) in these modes is address
obtained from the following computation: e
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 COMPUTER ORGANISATION

ress part of instructiontcontent

addressaddress
of CPU register. Ised i in
compulation may be tne program counter, The CPU registe
an index register, or a
the ding on type offCPU
( register, the addressing base
modes are also different.
ddressing modes are called:
Such
Relative
Address Mode:
py
Kenodes mo the content ot the CPU register
such is added
In to obtain thee
the actual address of to the address part of the
instruction to the operand (i.e. the 1The
of the instruction which
the instruction, effective address).
ad
address part ol is usually a
signed number (either positive
negative)
on addition to the CPU register content,
gives the effective address whose
nory is relative to the address
position of the next instruction.

Uses:
addressing mode often used with branch-type
is
Knode instructions.
This mode
also resultsin shorter address field
in the instruction
can be specified with a smaller number format as the relative
of bits compared to the number of
required designate the entire memory address. bits

Relative address modes may be of the following

threetypes
(a) PC (i.e. Program Counter) Relative
this mode the content
Addressing Mode:
to of the program counter is
added to the address part
inctruction to obtain
instru the actual address of the operand (i.e. of the
the effective address).

Example:
ADDPC-Relaive 25

Instruction 99
ADDcRelane Memory
In this example, the
address part of the
instruction i.e. 25 is added
to the
content of the PC (i.e. 2050) and
the
memory location (i.e. 2050 +
2050
25
2075 2075) is looked
99 upon and its content
(i.e. 99) is added to the content
of the
accumulator and 1he
result after
addition is stored in the accumulator
Accumulator itself.
Uses: Same as in relative address mode.

(6) Indexed Addressing

Mode or Index Register Relative Addressing
n this mode
the content of the index register is Mode:
added to the address part
uSUruction to obtain
the actual address of the operand (i.e. of the
the effective address)
Example:
ADDindex
Relative 25

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Diagram and explanation of the example is same as the PC-Relative

PC-Relative Mode
Moda
only
CPU register is now an index register instead of the PC. h
that
the
Uses:
The index register can be used to access consecutive operands. This
This can
can be
incrementing the register contents. done
by
(c) Base Register Addressing Mode:
In this mode the content of the base register is added to
the address part
part of the
to obtain the actual address of the operand (i.e. the effective the;instruction
address).

Example:
ADDBase Register Relative
Diagram and explanation of the example is same
as the PC-Relative Mode tha.
CPU register is now base register instead the PC. onlv that
of the

Uses:
Such modes are used in computers to
facilitate the relocation or programs
in memory.
) Stack Addressing Mode:
Here the address of the operand is specified
by the stack pointer (SP). The
instruction is the shortest as it does length of
not include any address of the memory
mention any register just like implied location or
mode of addressing). After each stack
the contents of SP are automatically incremented operation.
or decremented. PUSH and POP the
two commonly used instructions of this are
type.

Example:
PUSH A To push the content of accumulator to the
top of stack (TOS).
Uses:
Useful when PUSH and POP instructions
are used in a program by the programmer.
When interrupt occurs the contents
of important registers are saved into
this stack addressing is used. the stack. For

2. Evaluate the arithmetic

statement X=(A*B)/(C+D) one, two and tnre
in
address machines.
Answer: WBUT 2008, 2011, 2018)
Three-uddress machine:
MULTIPLY T, A, B
ADD X, C, D T-A*B
DIV
X-C+DD
X, T, X
X-T/X

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 COMPUTER ORGANISATION

Two-adaresSS
machine
MOVE T, A
MULTIPLY T, B
T-A
MOVE X,C T-T B

X, D
X-C
ADD X-X+D
T,X
DIV X-T/X
One-addresS iachine
LOAD A transfer certain memory content accumulator
to
MULTIPLY B AC - AC *B
STORE T transfer AC content to memory location T
LOAD C transfer C to accumulator
AC- AC +D
ADD D
DIV T AC -ACIT
STORE X transfer result to memory location X.

Wite program to evaluate the arithmetic statement Y = (4-B+C)/(G+H).

a
n Using an accumulator type computer with one address instruction.
Using
i) a stack organized computer with zero-address instructions.
WBUT 2015, 2016]
Answer:
i) One address
instruction:
LOAD A
SUB B
STORE P
0ADC
ADD P
STORE Q
LOAD G
ADD H
DIVQ
STORE R

in) Zero address instruction:

PUSH A
PUSH B
SUB
PUSH C
ADD
PUSH G
PUSH H
ADD
DIV

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4. Discuss in detail the various factors that need to be considered while designi
the ISA of a processor. WBUT
2017
Answer:
The Instruction Set Architecture (1SA) is the part of the processor that is visihl.
soe e to
een software
programmer or compiler writer. The ISA serves as the boundary between the
hardware. The ISA of a processor can be described using catagories:
5 and

Basic ISA Issues

Registers
We probably want to have some registers, so that we don't have to keep goinooing out
slow memory, but how many registers do we want or need? t0
More registers is probably better, but this will make implementing the Cp
more
complicated, ie. we tradeoff ease of programming against case of buildingtheCP
PU.
and we need bits in each instruction to encore the register number: 8 registers
bits etc. S=3
It also means we have to save out more registers when we switch between propra
and we do want to support a system where multiple programs can be runningat
the
same time
On the other hand, too few registers means that we will have to go out
to main
memory more often.
Another issue is how we deal with the special registers like the Program Counter
(PC): do we want these registers visible and accessible to the programmer?
this would allow the programmer to change the PCs value by hand, which
could
be useful.
or do we provide special instructions to manipulate these in only limited
ways?
Most modern ISAs have 8 to 32 registers.

Bus Sizes
What size data bus do we want? This effectively sets the natural word size the
of
ISA.
And because the CPU will want to fetch in word units, this also
influences the size of
our instructions.
generally, each instruction will be word at minimum, or a multiple the word
1
of
size.
What size address bus do we want? This determines how much
memory the CPU Can
address.
But then we need the ability to express every
address in some way.
If the address size is too big, it can make the instruction size
For example, if the address bus is 64 bits, how too big.
will we encode the operation: 10au
word from address X into register R3?
The instruction will be at least 64 bits
long to hold the address, plus DIs
describe the load operation and the register
which is the destination.

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operattons
manyoperations do we want to have?
ave lots, this provides
a rich
I set of operations that rogrammer can
perforn but it will make implementing them the progr
in silicon much
need more bits in each instruction more difficult
We will also i

32 operations, 6 bits=> 64
to encode the operatio
ation:
bits operations etc.
we mignt choose to
On the other hand, have only a small
may force the programmer set of simple instructio
This to have to combine
something done, but the advantage is fewer
2 or more instructions to get
bits required to encod
code an operation, and
simpler CPU design.
a

Operands?
How Many
pWith the number of instructions decided, how
many operands will each
require?
operatro
If the CPU gets most or Its data from registers, then we probably
want to have
some 3-operand instructions like
ADD RI, R2, R3, 1.e. Add R2 and R3, and save the result
into RI
so the instruction format needs to have bits set aside to identify each of the three
registers.
Other 3-operand instructions include instructions which compare and then divert the
PC to a new instruction, e.g.
BGT RI, R2, 100, i.e. if RI> R2, branch the CPU to instruction at current PC + 100
Not all instructions have 3 operations. Examples of 2-operand instructions include:
LOAD R3, 4000, 1.e. get the value from memory location 4000 and load it into
register R3.
SAVE R4, 5000, i.e. write R4's value out to memory location 5000.
SET R6, 23, i.e. set R6 to the literal value 23 (not the value at location 23).
And, of course, a CPU designer may think of l-operand instructions, such as:
INCR R4, i.e. increment the value in R4. The Java equivalent is R4++.
Later on, we will talk about the various addressing modes which a CPU designer
might wish to use.

Literal Values
Many instructions require literal values.
e.g. in Java when we write for (1=0; iIKI00; 1t+), there are two literal values: 0
and 100.
Are we going to be able to find space. in each instruction to put in literal values?
If so, that will be great, but it will be wasted space if programs dont have many
literal values.
to have to be stored
can't find space, then each time there is a literal, it is going
Iwe to memory to fetch the literal value.
dregister, or we are going to have to go out

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Instruction Format operation, operan

Each different instruction has to be encoded dilterently: Viteral
values, where to place the result, size of the data being operated on etc litea
to look like?
What is the instruction format going same size, or are som instructions
Can we make each instruction the o:.
going
to be
different sizes?
Is there going to be a single format, which makes
the decoding in silicon easy,
en.
we going to have several different instruction types, each with different forman
a

A Hypothetical Example
Before we go any further. Iet's make the above concrete by doing some ISA desi
a
Let's design an ISA with 8 registers, a 16-bit data bus and word siže, and
address bus: quite suitable for an embedded CPU, C.g. in a microwave or eno
4
engine
control system.
Let's also have 3-operand instructions where the operands are all sters:
Rdest-Rsrc1 OP Rsrc2
We need 3 bits to encode each register's number, so that's 9 bits out of 16 used e
up,
leaving 7 bits.
Let's use 1 bit to encode the size of the data being manipulated: 8-bit byte or 16-hit
int. That leaves 6 bits. t
We could go for a single instruction format:
OperationSize Rdest RsrclRsrc2
6 bits
bit 1 bit 3 bits 3 bits3bits
But now there's no way to copy values between the regiIsters and the main memory,
nor is there any way to put literal values into an instruction.
Let's add a second instruction format, still 16-bits long, but which contains a literal
value:
Inst 1ype Operation Size RdestRsre1 Rsrc2
0 5 bits |1 bit 3 bits 3 bits 3 bits

Inst Type Operation Size Register Literal Value

10 2 bits 1 bit 3 bits 8 bits
This allows us to do things like SET RO, 26, where the 26 is
stored in the 8-bit literal
section.
But we still don't have a way to access locations in
memory, so there is one final
instruction format:
Inst Type Operation Size Register Memory
11
Location
2 bits
I bit| 3 bits
This instruction format is 2 words long, and
24 bits
the memory address is specified asa
bit value. This allowS us to do things like LOAD RO,
We now have: 4000 and SAVE R4, S000.
o a 1-word instruction format with
25-32 possible operations on 3 reE ster
operands,

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 COMPUTER ORGANISATION
1-word
instruction tormat
forma
a with 22=4 possible
operations on one
8-bit literal
8-b1
value, and register and an
instruction format
with 22=4 possible
memory location operations on one1 register and a
24-bit

pecision
akiugwe
havent considered how we
are going
p can deviate from the normal "next to modify the value in the
r
t instruction" flow
of execution.
eed a way
ay to skip Over instructions, based on a decision,
statement so as to implementr

We also
eed to branch bacKward, based on
a decision, so as
constructs. nplement loop
to impl
need to Jump to the start of a function, and also know
e how to return back to
where we left.
Allof
of the above change the default PC behaviour: move
to the address of the next
instruction.
What decisions are we going to provide?,
<
<=,>,>=?
ome of these we could leave out, e.g. if (R3 < R4) is the
same as if (R4> R3).
ral choices here. We could design
There are several an instruction mat which
encodes:
two operands to be compared,
what type of comparison to make,
what change to make to the PC if the comparison is true.

5. short notes on the following:

Write
a) Addressing modes
WBUT 2007, 2008, 2012, 2017]
b) Classify MRI and non-MRI instructions
[WBUT 2011]
c) Instruction Format
[WBUT 2018]
d) RISC WBUT 2018]
Answer:
) Addressing modes: Refer to Question No. I of Long Answer Type Questions5.

b) Classify MRI and non-MRI instructions:

The instruction field specifies a machine instruction or pseudo instruction. The
instruction field in an assembly program may specify one of the following:

0 A memory-reference instruction (MRI)

i) A register-reference or input-output instruction (non-MRI)
(1i) A pseudo instruction with or without an operand

ory-reference instruction occupies two or three symbols separated by spaces.

he first must be three letter symbol defining an MRI operation code such as AND,
third symbol, which may or
LDA, STA etc. the second is a symbolic address.theTheline denotes a direct address
be present, is the letter I. If is missing,
I
Ot
instructio
the symbol I denotes an indirect address instruction.
he presence
I
of

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A non-MRI is defined as an
instruction that does not have an address pait. A cno
program by any one of the three-letter RI
recognized in the instruction field of a
the register-reference and input-output instructions. A symbol
address in the is
ction
for

an operand. Ihis location must must be defined

field specifies the memory location of
as a label in the first column.
Somewhere in the program by appearing again

c) Instruction Foriat:
an instruction, an instruction
An instruction format defines the layout of the bits of
zero or more operandt
must include an opcode and implicitly or explicitly, S. An
instruction is normally made up of a combination of an operation code and an ooperand
most commonly by its location or address in memory. An instruction set architectur e is
Opcode Mode Address or operand

an abstract model of a computer, it is also referred as architecture or compto

architecture. The main components of an instructions are-
i) Opcode: It defines which instructions to be executed.
ii) Operands: It defines the data on which instruction to be executed.

d) RISC:
RISC stands for Reduced Instruction set computer
It is a microprocessor that is designed to pertform a smaller number of types of comuter
instructions so that it can operate at a higher speed. Some advantages of RISC are-
A new microprocessor can be developed and tested more quickiy 1t one of its aims is
to be less complicated.
Operating systems and application program who use the microprocessor's
instructions will find it easier to develop code with a smaller instruction set.
The simplicity of RISC allows more freedom to choose how to use the space on a
microprocessor.
Higher level language compilers produce more efficient code than formerly because
they have always tended to use the smaller set of instructions to be found in a RISC
computer.
The characteristics of RISC Architectures are
i) It is highly pipe lined.
ii) It has fixed length instructions and few addressing
mode
iii) it is mainly controlled by hard wired.
iv) It has single cycle instructions, and three
register operands allowed per instruCuO
(Exampleadd Ri, R2, Ra)

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 COMPUTER ORGANISATION

MEMORY ORGANIZATION

Chapter ata Glanc

=

MOS: MOS can be of the following

ypes 3 types:
PMOS: The p-channe (+ve) MOS which depends
on
S: The n-channel (-ve) MOS which depends the flow of holes.
(b) v used in circuits with on the flow of electrons.
These ai
comi only one type of MOS
MOS: The complementary transistor.
MOS (CMOS)
(Cors Connected ina complementary fashion technology uses both PMOS and NMOS
tra in all circuits.
classification and hierarchy:
Memory can
be broadly classified into three
the cache memory, the main memory
and the auxiliary
memory. The cache memory 1ies
the CPU and the main memory and
is the fastest, smallest
he memory units. Ihe auxiliary or
the secondary memory
and the most expensive o
least expensive of all the memory
units. The main memory
unit is the slowest, largest an
lies in between the two0.
Memo Classification; Memory can be classified accordingly
Memory

Cache Main
Memory Memory Auxiliary/ Secondary
Memory

LI Cache L2 Cache
Memory Memory RAM ROM Magnetic
Magnetic Magnetic
(primary cache (secondary Disk
1ape Disk
memory) cache memory)

(CD-ROM)
Static Dynamic
RAM RAM Hard Floppy
Disk Disk
Flash
Memory

PROM EPROM EEPROM

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follows:
of memory hierarchy is,as
Memory Hierarchy: The block diagram
Magnetic
tapes Main
I/0
processor memory
Auxiliary memory
Magnetic
disks

CPU
Cache

Fig: Memory hierarchy in a computer system

tactors on which.
Factors on which Memory Hierarchy depends: There are various the
basic hierarchy of memory depends. These are cost, storage capacity (size), and speed. and
access time.
Memory read/write access:
Flow chart of the memory read operation: In the
Particular
address External address
memory chip,
CPU decoder of the
out of many, aaaress decoder of

read pulse
main memory is selected by the chip
system the chip
select(CS)

Required word is
sent to the data bus Through the Activities the
Required via the bit lines,
sense/write required word
word is sent .sense/write
to the CPU circuits, 'read line
Circuits, data
pulse is given
Output line

Flow chart of the memory write operation:

In the
address External Particular address address
decoder of memory chip, decoder
CPU the main out of many, is of the
memory selected by the chip
write pulse
system chip select (CS)

Data gets Required

Through the
stored in data is sent Activates
the to the bit sense/write the
Circuits,
required lines via required
memory the data
write pulse word line
is given
cells input line,
activated sense
Write

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&Dynamic RAM:
Stalic
StaticRAM:
' of intermal flip-flops that store the binary
consists information. Stor information
long as poweris applied to the unit. Stored remains
idas RAM: A dynamic RAM
Dyamic loses its stored information
though tne power in a very shortrt time (a few
milliseconds) even supply is on.
Cach memory 1S
Cache
or: Cache
memory: a very small
but very fast memory. t but
mong all other memory It is the
iastest
units. A very-high-speed
cneed of processing memory, it is sometimes to
by making current programs u
increa
it lies between the cU andthe main memory
and data availablele to the CPU at
1

rapid unit.
a
CPU Cache
Memory Main
Memory
memory: It is a tecnnique thal allows
the execution of processes that may not
in main memory. his concept used in
Com
user to
construct programs as thougn a
programm
e
some large computer systems permit the
large memory space is ava able.
Virtual memor 5
mmers the illusion that
used to give they have a very large memory at their disposal.
eventhoughoh the computer actually has a relatively small main memory.
Diugranm
The below figure shows the organization that implements virtuak memory.
Processor

Virtual address
Data IMMU

Physical address
Cache

Data Physical address

Main memory

DMA transfer

Disk storage

Fig: Virtual memory organization

Multiple Choice Type Questions

technique of placing software in a ROM semiconductor chip is called

1.
The
WBUT 2003, 2008]
a) PROM b) EPROM c) FIRMWARE d) Microprocessor
Answer: (c)

2. Cache
memory WBUT 2006, 2008, 2011, 2013]
a) increases
performance b) reduces performance
C)
machine cycle increases d) none of these
Answer:
(a)

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3.Associative memory is a WBUT 2006, 2008,

b) pointer addressable
2011,
a) very cheap memory mory,2013
c) content addressable memory d) slow memory
Answer: ()

4. How many RAM chips of size (256 K * 1 bit) are requiredto build
memory? WBUT 2006, 2009, ME
2015
a) 8 b) 10 c) 24 d) 32 201a
Answer: (d)

5. How many address bits are required for a 1024 x 8 memory?

WBUT 2007,
2011, 20131
a) 1024 b) 5 c) 10 d) None of
Answer: (c) these

6. The principle of locality justified the use of BUT 2007, 2012, 2015,201
a) Interrupt b) Polling
c) DMA d) Cache memory
Answer: (d)

7. A major advantage of direct mapping of a cache is its simplicity. The

main
disadvantage of this organization that WBUT 2007
a) It does not allow simultaneous access to the intended data
and its tag
b) It is more expensive than other types of cache organizations
c) The cache hit ratio is degraded if two or more blocks
used alternately man
ap
onto the same block frame in the cache
d) Its access time is greater than that of other cache
organizations
Answer: (c)

8. The purpose of ROM in a Computer System is

WBUT 2010]
a) to store constant data required for computers
own use
b) to help reading from memory
c) to store application program
d) to store 0,s in memory
Answer: (a)

9. Which one dose not posses the characteristics of a memory element?

a) A toggle switch [WBUT 2010]
b) A lamp
c) An AND gate
d) None of these
Answer: (c)

10. Data from memory location

after fetching is deposited by memory
a) MAR in 2010
b) MDR WBUT
c) IR
Answer: (b) d) Status Register

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 memory COMPUTER ORGANISATION
Virtual i system allOws
More than address space the employmentof
c) More than hard disk capacity b) The full WBUT 2010]
address space
Answer: (a) d) None of
these

12. A
system nas 48-bit
48-bit virtual
virtua address,
How many virtual 36-bit physical
memol and physical address and 128 MB main
pages can
the address space suppor
a) 2, 24 b) 22, 236
c) 24, 234 [WBUT 2010]
Answer: (b)
d) 24, 236

13.
Maximum
imum number of directly
sor having
processor addressable
10 bits wide locations in the memory
control bus, 20 OT a
is bits address bus
and 8 bit data ous
a) 1K b) 2 K
c) 1 M WBUT 2012]
Answer: (C)
d) none of these
Periodic refreshing is
14.
needed
a) SRAM b) DRAM [WBUT 2012]
Answer: (b) c) ROM
d) EPROM

Physical memory
15.
broken down into groups
a) page b) tag of equal size
is called [WBUT 2012]
Answer: (c) c) block/frame
d) index

16. Bi-directional buses use

a) tri-state buffers WBUT 2012]
b) two tri-state buffers in
c) two back to back
cascade
connected tri-state buffer in
d) two back to
back connected buffers parallel
Answer: (c)

17.
Micro Instruction are
kept in
a) main memory
c) cache memory b) control memory BUT 2012]
Answer: (5) d) none of these

18.
Size of virtual
memory is equivalent to the size
a) main memory of WBUT 2013]
c) secondary memory b) cache memory
Answer: d) both (a) and (c)
(c)
19.The
sociative access mechanism is followed in
a) main memory [WBUT 2014]
c) magnetic b) cache memory
Answer: disk d) both (a) and (b)
(d)

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WBUT
by 2014
of memory is supported c) both d) none of
20. The users view these
b) segmentation
a) paging
Answer: (a) WBUT
is due to 2014
accessing data on disk rotation time
in
21. The largest delay b)
a) seek time d) none of these
c) data transfer time
Answer: (a) me
data needs to be deposited in memory
location for fetching
22. Address of memory [WBUT 2014
in c) IR d) status register
c) MBR
a) MAR
Answer: (a)
of WBUT 2014
is equivalent to the size
23. Size of virtual memory c) floppy disk d) none of these
a) hard disk b) CPU
Answer: (a)
n be the size of each register, then
in ordar
24. If k be the number of registers and of
construct n-line common bus system using tri-state buffers, the total number
to WBUT 2015]
would be
tri-state buffers and the size of decoder b) n'k and log2 k-to-k
a) n'k and 2-to-4
d) n'k and log2 n-to-n
c) k and log2 n-to-n
Answer: (6)
RAM) when WBUT 2016]
25. RAM is called DRAM (Dynamic
a) it is always moving around data
b) is requires periodic refreshing
c) it can do several things simultaneously
none of these
d)
Answer: (6)
memory
26. In order to execute a program instructions must be transferred from
8 bit byte can be
along a bus to the CPU. If the bus has 8 data lines, at most one in this case to
transferred at a time. How many memory accesses would be needed WBUT 2016
transfer a 32 bit instruction from memory to the CPU?
b) 2 c) 3 d) 4
a) 1

Answer: (d)
many p
27. A computer's memory is composed of 8K words of 32 bits each. How
are required for memory address if the smallest addressable memory un 2016]
WBUT
word?
a) 13 b) 8 c) 10 d) 6
Answer: (a)

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 COMPUTER ORGANISATION
memory refers to
ache
a0cheap memory
memory that can
be plugged into [WBUT 2016]
2 memor the mother board
pres to expand mau
fast memory present on the processor
b accessed data chip that is
used to store recent
on of main memory
erved portion
spe area of memory on the used to save important data
acial
d) a chip that is used
data to save frequently usea
Answer: (b)

Write Through technique IS used in which memory

29. memory for updating the data?
a) Virtual b) Main memory
Auxiliary memory [WBUT 2016]
c) d) Cache memory
Answer: (d)

is generally
generally used
********* to. increase the apparent size
30. memory of physical memory
a) Seconaary b) Virtual memory
WBUT 2017]
c) Hard disk d) Disks
Answer: (b)

delay between two successive initiations

Thetime
t
31. of memory operation is
a) Memory access time b) Memory search time WBUT 2017]
c) Memory cycle time d) Instruction delay
Answer: (c)

12. A 24 bit address generates an address space of . . locations

[WBUT 2017, 2019]
a) 1024 b) 4096 c) 2448 d) 16,777,216
Answer: (d)

3. To get the physical address from the logical address generated by CPU we use
WBUT 2017, 2019]
a) MAR b) MMU c) Overlays d) TLB
Answer: (b)

34. During transfer of data between the processor and memory we use
[WBUT 2017]
a) Cache b) TLB c) buffers d) Registers
AnSwer: (d)

. Ihe return address of the Sub-routine is pointed to by

WBUT 2017]
a) IR b) PC
c) MAR d) Special memory registers
Answer:
(b)

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R1, 45 does WE
36. The instruction, Add and stores 45in
in that asUT
20.
a) Adds the value of 45 to
the address of R1 address2019
R1
b) Adds 45 to the value
of R1 and stores it in
45 and adds that content to that of R1
c) Finds the memory location
d) None of these
Answer: (b)
on chip cache memory for an n-add
37. What could be the maximum size of 1-address
WBUT bit
processor? 2019
a) 0 b) 2 c) infinite d) decided by manufactur
Answer: (c)

Short Answer Type 9uestions

1. Given the following determine the size of the sub fields (in bits) in the add.
for Direct Mapping, associative and set associative mapping cache schemes:
We have 256 MB main memory and 1 MB cache memory.
The address space of this processor is 256 MB.
The block size is 128 bytes.
There are 8 blocks in a cache set. WBUT 2004, 2007, 2012, 20131
Answer:
As the size of the main memory is 256 MB hence there are 28 bits (as 256 =2 and MR 1

2 bytes and hence 256 MB 2' X 2 2) in the main memory addres orthe
address size of main memory is 28 bits.

Size of the sub-fields for associative mapping cache schemes:

Each block size is 128 bytes or 2 bytes. Hence number of main memory blocks 212
2. So number of bits in the tag field is 21 and that in the word field is 7 (as block size
is 128 bytes). Tag Word

21

Main Memory Address

Size of the sub-fields for direct mapping cache schemes:

Now size of cache memory is MB = 2 bytes. Hence number of cache memory DiovCkS
1

=
2 /2 = 2. So number of bits in the block field 13. Now out of the totai
memory address size of 28 bits, word field contains 7
bits and the block field conlau
bits. Hence, the number of bits the tag
in field is 28-(13 +7)=8.
Block Tag Word

Main Memory Address

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 COMPUTER ORGANISATION
eub-fields for set-assOCiative
su
e ofthe ere are 8 blocks per mapping cache schemes:
ca cache set
this the cache memory are and the total numbers of cache blocks are 2.
Innumber oI sets inthe
o number of bits
Hence
bi in the set 2/8 23/2=20
field is 10 and that
in the word field is 7. So number
thetag field 28-(10+ 7)= 11.
=
Set Tag Word
10 11
7
Main Memory Address

What is dirty bit?

2 WBUT 2006, 2010]
Answer:
To
cope up with the storage capacity of the main memory,
m pages are swapped in and out
memory and the secondary memory.
the main When a particular|page is required in the
of
main memory and ifthat
page is not there in the main memory.it
is wapped in from the
lary storage area. Dirty bits are used in the page table to keep track of individual
S whether the particular page is modified ever since it is brought in
the main
Whenever the contents of a page is modified (i.e. something is written on tne
its respective dirty bit is set. If a particular page needs to be swapped out of the
e),memory,
main the O.S checks its dirty bit to see whether the page is regularly used (or is
inISe). If it is regularly used or is in use currently, the particular page js not swapped out.

3. Discuss with suitable logic diagram the operation of an SRAM cell. WBUT 2006]
OR,
SRAM celI. WBUT 2013]
Draw the internal cell diagram of
Answer:
type of semiconductor memory where the
a
random access memory (SRAM)
1S
Static
word static indicates that, unlike
dynamic RAM (DRAM), it does not need to be
bit. SRAM
periodically refreshed, as SRAM uses
bistable latching circuitry to store each
that data is
remanence, but is still volatile in the conventional sense
exhibits.data.
eventually lost when the memory is
not powered.

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WL

Vad

M2 M

Ms
M Ms

BL BL

Each bit in an SRAM is stored on four transistors that form two cross-coupled inverten
This storage cell has two stable states which are used to denote 0 and 1. Two additional
nal
access transistors serve to control the access to a storage cell during read and wrie
operations. A typical SRAM uses six MOSFETs to store each memory bit. In aditiont
such 6T SRAM, other kinds of SRAM chips use 8T, 101, or more transistors per bit. This
is sometimes used to implement more than one (read and/or Write) port, which
may be
useful in certain types of video memory and register files implemented with multi ported
SRAM circuitry.
Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the
cost of processing a silicon wafer is relatively fixed, using smaller cells and so packing
more bits on one wafer reduces the cost per bit of memory.
Memory cells that use fewer than 6 transistors are possible- but such 3T or 1T cells are
DRAM, not SRAM.
Access to the cell is enabled by the word line (WL in figure) which controls the two
access transistors Ms and M, which, in turm, control whether the cell should be connected
to the bit lines: BL and BL. They are used to transfer data for both read and write
operations. Although it is not strictly necessary to have two bit lines, both the signal and
its inverse are typically provided in order to improve noise
margins.
During read accesses, the bit lines are actively driven high and low by the inverters in tne
SRAM cell. This improves SRAM bandwidth compared to
DRAMs-in a DRAM, the Dit
line is connected to storage capacitors and charge sharing
causes the bitline to swIng
upwards or downwards. The symmetric structure of SRAMs also
allows for differen
signaling, which makes small voltage swings more easily
detectable. Another differen
with DRAM that contributes to making SRAM faster is
that commercial chips accep
address bits at a time. By comparison, commodity
DRAMs have the address mulup
in two halves, i.e. higher bits followed by lower bits, order
over the same package pin5
to keep their size and cost down.
The size of an SRAM with m address lines and n data x S
lines is 2" words, or 2
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 COMPUTER ORGANISATION

concept of virtual memory.

4Whatis
OR, WBUT 2007]
tual memory? Why is it called virtual?
What WBUT 2008,
AnSwer: hierarchy 2010, 2012, 2014]
memory system, program and
na data are first
a program or data are brought
tions ol memory
memory is a into main memory stored in auxiliary memory
Virtual concept used as they are needed by the
CPto nstruct program grams as though in some large computer
er a large memory systems that permit tne
of auxiliary memory. Each address space is available, equal
tolality
from that is referenced to tnc
address mapping
om the so-called virtual by the CPU goes through
address an
memory. Virtual memory is used to
give programmers to a physical address in main
memory at eir disposal, even the illusion that they
arge though the computer have a very
memory. A virtual memory system actually has a relatively
ain provides a mechanism small
nto correct main memory
ed address into for translating gram-
progr
are locations. This
programs are being executed in the is
CPU. The translation done dynamically, while
atically by the hardw by means of a mapping or mapping is handled
table.
Processor

Virtual Address
Data MMU

Physical Address
Cache

Data
Physical Address

Main Memory

DMA Transfer

Disk Storage

5. A disk drive has 20sectors/track, 4000 bytes/sector, 8 surfaces all

Outer
diameter of the disk is 12 cm and together.
0.1
mm. What is
inner diameter is 4 cm. Inner-track space is
the no. of tracks, storage capacity of the disk
ransfer rate there drive and data
from each surface? The disk rotates at 3600 rpm. WBUT
Answer: 2012]
d1al distance covered by all the tracks lying on a surface =12-4/2=4 cms.
u, number
oftracks/surface = 4* 10 mm/.1 mm= 400.
4ge capacity of the entire disk drive = number of surfaces in the drive * number
of
l bytes=256
4000
Surtace number of sectors / track * number
*
of bytes/ sector = 8 * 400 20 *
*
Number MB
of bytes transferred
umber from each surface during one revolution of the disk =
me of
me per bytes / track =20* 4000 bytes = 80, 000 bytes.
revolution=
So,
datatransfer 60/3600 sec 1/60 sec
rate from each surface of the disk drive = 60 * 80 kb = 4.8 mbytes/ sec.

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memory? WBUT
mean by Stack 20
6. What do you OR,
WBUT
CPU.
Explain stack based 2018
Answer: most computers is a STACL
useful feature that is included in the CPU of
A stores information m suL lasti
first-out (LIFO) list. A stack
is a storage device that
is the first one to be retrieved. Stack is
a manmer

thatthe last item stored in a stack one-v

and only one information can be
accessed at a time. A set of registersconstittay i
A stack can be placed in a portion of
a large memory or it can be orpanack
or registers. this is known. as
collection of a finite number of memory words a
stack. A stack can exist as a stand-alone unit or can be implemented in a randoSter
om-access
memory attached to a CPU. This is known as memory stack. The stack in digital
computers essentially a memory unit with an address register that can count only
is
o
register that holds the address for the stack is called the stack pointer (SP)
because its
value always points at the top item of the stack.
The two basic operations that can be performed on a stack are the insertion
and delet
eletion
of items. In the insertion operation, which is also known as push, information stored stoe
is
the top of stack (TOS) position in the stack and in the deletion operation, known nein
as pop.
information from the TOS is retrieved.
Figure shows a 64-word stack organization. The stack grows
upward from location 0 th
location 63, which is the final TOS. On addition of every new
element, the TOS value is
incremented by one until the stack is full, marked by
FULL 1(FULL is flip-lan
a
which is 1 when the stack is full and EMTY is
a flip-flop which is 1 when the
stack is
empty). The first element is pushed in the stack
at the SP 1 location i.e. the fint
location. So when
SP-0, it means that the stack is full and hence FULL is 1. So EMTY
is 0i.e. stack not empty.

The steps for the PUSH

operation are as follows:
Initially, SP is cleared
to 0, EMPTY is set
to the word at address 0 tol and FULL is cleared to 0,so that SP points
and the stack is marked empty
fullif FULL=0),a new item is inserted and not full. If the stack is no
implemented with the with a PUSH operation. The PUSH operaion s
following sequence
SP-SP+1 of microoperations:
M[SP]- DR Stack pointer is incremented.
ltem, from data register, is
If (SP 0) then (FULL
EMTY -0 -1) To check if stack
stored on the 10>
is full.
Mark the stack
is not empty.
The steps of POP
operation are as follows:
A new item is
deleted from the
operation consists stack the stack
of the following if is not empty(If TY=0). The
POP
DR M[SP] sequence of microoperations: EMPII
SP-SP-1 Item from TOS
is popped and
stored in the daa register.
If(SP0) then (EMTY Stack pointer
is decremented.
+1) To check stack
if is empty.
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 COMPUTER ORGANISATION
Mark the stack
paill-o
0 is not full.

FULL EMPTY 63

DR

What do you meanby Logical address space and Physical address

1.
space?
Answer:
WBUT 2014]
An add
ddress generated by the CPU is commonly
referred to as a logical address,
whereas an address seen by the memory unit
-that is, the one loaded into the
omorv-address register or the memory-
me is commonly referred
address.
to as a physical
The compile-time and l0ad-time address-binding
methods generate identical logical
and physical addresses.
However the execution-time address-binding scheme results in differing logical and
physical addresses. In this case, we
usually refer to the logical address as a virtual
address.
,The run-time mapping from virtual to physical addresses is done by a hardware
devicecalled the memory-management unit (MMU).
In MMU, the value in the relocation
register is added to every address generated
by a user process at the time it is sent to memory.
The user program deals with logical addresses;
it never sees the real physical
addresses.

relocation

-
register
14000
logical physical
address address
CPU
memory
346

MMU

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256 x 4. Desinnn a 2K x
RAM chips each of size
we are given building block.
Draw a net logic diagram 8RAM
8. Suppose as the WBUT ofyo
chip
system using this 2015,
implementation. 2
Answer:
bytes in the RAM
2KB 2*8 chips of 256*4 which means these are 256 rc ws with4b
We have RAM in
nibble of data.
each row that is one
= *2=2**2=8 *2.
(2 8/(2' *4) (2) columns of 256 * 4 chips.
needing 8 rows and2
So we will be selected
rows, rest Will be same and the chips wiil be
selected on the
t
show two basis
Below we
decoder output.
74189

2 iCS WR

WR
<CS
74189

74189

<<CS WR

WR-

CS WR

74189

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 COMPUTER ORGANISATION
escribe stack based CPU
9.
Answer:
WBUT 2015]
nswe
Stack-base computer operates
instructions,
stack list of data words
PU of most
with a Last-In,based on a data structure called stack. A
included in the CPU computers. First-Out
acsive A portion (LIF0) access me method that is
successive locations can be of memory
in address for the top most considered as unit used to store operands
the operand in the a stack in computers. The register ster that holds
rations performedd on the operands stack is called
stored in a stack a stack point
ointer (SP). The two
end only,
erands are pushed
oper: are the PUSH
or popped. H and POP. From one
operandat at the
the top of stack and it The PUSH
decreases the operation results in inserting
eleting
results in del one operand
from the top
stack pointer on
register. The POP operation
register. of stack and it increases
ample, the stack pointer
For example, Figure showS a stack
of four data words
structions require an address field in the memory. PUSH
each. The PUSH and POP
PUSH <memory address instruction has
the format:

SP
Top data of the stack

Stack
-21
56
Bottom data

2-1

Fig: A stack of words in memory

The PUSH instruction inserts
the data word at specified address
The POP instruction has the format: to the top of the stack.
POP <memory address>
The POP instruction
deletes the data word at the top of the
The stack pointer stack to the specified address.
is updated automatically in either
implemented as case. The PUSH operation
can be
SP-SP-1 decrement the SP by 1
SP memory address> store the content of specified memory address
into SP,
The POP i.e., at top of stack
operation can be implemented as
memory
address>-SP transfer the content of SP (1.e., top most data) into
SP-SP+1 specified memory location
Increment the SP by 1

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rganizations
general-register based CPU organization
There are three main advantages of over
stac
based CPU organizations.
CPU organizations, reading a register does not no affect
(a) In general-register based
organizations reading value from the
value its
content, whereas, in stack based CPU topofthe
stack.
stack removes the value from the
any register from register fil
(b) In general register-based CPUU organizatiDns,
chosen to keep values while writung a program; whereas,
in stack baso a
nat CPU
organizations, accessing values is limited by the LIFO (last-in first-out) nature
of the
stack.
(C) Since, fewer memory references are made by programs Written in general register.reo
based CPU organizations, the effective execution is faster than that in stack
CPU organizations, where generally stack is implemented by memory locations
and
locations are accessed in LIFO nature.

10. Two 1024x4 bits RAM chips are given. Design a memory of size 2048x4 bits
[WBUT
2017
Answer:
In a 1024x4 memory has 1024 word capacity and it can store 1024x4 = 4096 bits T
expand the memory size from 1024x4 bits to 2048x4 bits, two 1024x4 RAM ICs are
required. Figure I shows the connection of two 1024x4 RAM to develop a 2048x4 RAM
Ten-address lines Ao to A are directly connected with memory IC terminals. The chin
select line is connected with most significant bit address line Ajo and inverted MSB is
connected with chip select line of the next IC. So that memory addresses from 0 to 1023
are located first memory IC, and memory addresses from 1024 to 2047 are also located in
memory IC2. One memory will be selected at a time and data out from one memory only.
Therefore, corresponding output terminals are connected together for output.
Address inputs
Ag Ay

Data input
RAS
CAS
RIW D D, D, D

CS 1024 x4 RAM CS 1024x4 RAM

Q Q Q Qu

Data output
Fig: Two 1024x4 RAMs
expanded to design a 2048x4RAMs

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 COMPUTER ORGANISATION

Define latencytime of a memory.

11. WBUT 2017, 2018]
Answ access mem
memory latency (RAM latency)
Random refers to the delay that occurs in uatd
transmiss as data moves between computer RAM
fetch data fron RAM than it takes to retrieve it and the processor. It takes more
from cache memory.
ime to
Wha are the advantages of associative mapping
over direct
12.a)
Considdor a series of address
references given: 2, 3, 11, 16, 21,mapping
13, 64 and 48.
)
Assumingg rect mapped cache with 8 one-word blocks
a dire
reference
nce in the list as a hit or a miss and that is initially empty,
label each show the finál contents of the
cache WBUT 2017]
Answer:
mapping is more flexible than direct mapping. An Main
Associative mory block
an mapped anywhere in cache memory
be

b index=address % 8
tag address /8
Address reference Index Tag Hit/Miss
2 0 Miss
0 Miss
Miss
16 0
21
Miss
Miss
13
Miss
64 Miss
48 0 Miss

Index Hit/Miss
48

Explain with an example, how

5t canWhat is the limitations of direct-mapped cache? WBUT 2018]
be improved into set-associative cache?

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Answer:
Part:
The limitations of direct-mapped cache:
Each block of main memory maps to a fixed location in the ne cache,
cache herefore
different blocks map to the same location in cache and they are continually if
two blocks will be continualy swapped in and out, which known as Thrashing
is Thrashi

2md
Part:
We are dividing both main memory and cache memory into blocks of Same size
bytes ie.n
Therefore, cache size = (Number of sets) * (size of each set)* (cache line size
So, using the above formula we can find out the number of sets in the cache men
2 (Number of sets)* 2*2
Number of sets 2/ (2*2)=25
When an address is mapped to a set, the direct mapping scheme is used 4 then
associative mapping IS used within a set.

14. Average memory access time depends on which factors? WBUT 20

Answer:
The average memory access time depends on three parameter. It is a common metrie trieto
h
analyze memory system performance. It depends on, hit or
time hit latency, miss rate an

miss penalty provide a quick analysis of memory systems.

Hit latency is the time to hit in the cache. Miss rate is the frequency of cache miss
while average miss penalty is the cost of a cache miss in tems of a time

15. a) If a direct mapped cache has a hit rate of 95%, a hit time of 4ns, and a miss
penalty of 100ns, what is the average memory access time?
b) If an L2 cache is added with a hit time of 20ns and a hit rate of 50%, what is the
new average memory access time? WBUT 2019

Answer:
a) In a direct mapped cache,
Hit rate= 95%
Hit time =4 ns
Miss penalty = 100 ns
Miss Rate 1- Hit rate =1-95%=0.05
:. Average memory access time = Hit time + (Miss rate x Miss penalty)
= 4+ (0.05x100) = 9ns

b) Average Memory access time

FHit timeLI t Miss rate x (Hit timeL + Miss rate2 x Miss Penalty2
=4 +0.05 x (20 +0.5 x 100)
7.5 ns

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 COMPUTER ORGANISATION

Cache
he memory has 2K blocks. Block 32 bit
16.
is provided. The machine is byte size is of 4 words 16 bytes.
address
is the bit length for each field in addressable.
What length for Direct Mapping?
the
the bit length for each field
What isis thethe bit length for each
in 2-way set associative mapping
Whatis field in 4-way set associative mapping
i) [WBUT 2019]
Answer:
length foreach field in direct mapping =x (left)
i) it = words 4x
:Block size 4 16 bytes
bytes 2° =6 bit
64
Block size of 4 words 16 bytes 2 bytes
i)
Therefore, Number of bits in the Word field= 4
heche size = 22K-byte =2" bytes, Number of cache blocks per set= 2
umber ofsets che size/ (Block size Number of blocks per set)
- 2 (2
* 2) 2
Therefore, Number ofbits in the Set field 6
Total number of address bits 32
=

Therefore, Number of bits in the 1Tag field =

32-4-6 22

i Block size of 4 words = 16 bytes 2 bytes

Therefore, Number of bits in the Word field 4
Cache size = 2K-byte = 2" bytes, Number ofcache blocks per set = 4
For 4 way set-associative mapping,
Number of sets (Cache size / Block size*Number ofblocks per set)
(2/2 *4) 2
Therefore, Number of bits in the Set field 5
Total number of address bits =32
Therefore, Number of bits in the Tag field = 32 -4-5 23

Long Answer Type Questions

1. explain the two write' policies: write through and write back for cache
a) Briefily
design. What are the advantages and disadvantages of both the methods?
WBUT 2004, 2006, 2007, 2010]
OR,
Briefly explain write-through and write-back policies.
WBUT 2009, 2011, 2012, 2019]
OR,
what are 'write through' and write back' policies in cache memory?
WBUT 2013, 2014, 2015, 2018
Answer:
is to update main
write Through: The simplest and most commonly used procedure
with cache memory being updated in
Ory With every memory write operation, address. This is called the write-through
Cit it the word at the specified
contains
policy.
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Advantage
1. Simple and easy to implement and hence it is most commonly used ache
method. write
2. Main memory and cache memory always contain the same data in them.
3. Effective in DMA transfers as the /0 device communicating ng with
with main
main memoy
always receive the most recent updated data from the main memory.

Disadvantage:
. Slow (time consuming), as always two memories(cache and main memory) ory) no
need
get updated simultaneously to
2. The policy will not work if the specified address location in the cache memory
memor
does
not hold the required word to be updated.

Write Back: In this method only the cache location is updated during a write
operation
ation.
The location is then marked by a flag so that later when the word is removed froms
the
cache it is copied into main memory.

Advantage:
1. Faster than the previous policy as cache and main memory 1ocations
do not get updated
simultaneously with every write operation with only the cache memory getting regularly
updated and the final copy of the updated word gets stored at the main memory

Disadvantage:
1.In a write back policy, data (modified or not) is written to the main memory finally
Now supposc if the data is not modified at all, then the same data (unmodified) will be
again written to the main memory i.e. same data will get overwritten in the main memory.
But this is time consuming and henee acts as an overhead.

b) Explain the difference between full associative and direct mapped cache
mapping approaches. WBUT 2004, 2007, 2009, 2011, 2014, 2015, 2019
Write the advantage of virtual memory. [WBUT 2008, 2010]
Answer:
1s Part:
Differences between full associative (i.e. set-associative) and direct mapped cacnc
mapping approaches areas follows:
Direct mapping Full-Associative mapping
Suffers from contention probiem as Choice of block replacement is more and hence
provides few choice of block replacement. Suffers much less from contention
problem.
2. Slow process. Much faster compared to direct mappi
|technique.
3.Less expensive (har fware). Much less expensive than direct mapping

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Part:
Advantage
efficien
rOvides fficiently the total available memory
ammer is not required to
programn space to shared by different users.
The take care of storage allocation while Writlns
programs.
The accesS
rate is high
progran execution is made independent
The of capacity and configuration of
memory.

Discuss the concept of associative memory unit using

2 suitable example.
[WBUT 2005, 2015, 2018]
Answer:
Based on the
eed of the
need t hierarchical memory organization,
of pyramid which gives a clear
a the different memories are
ged in the fform
ranthe different factors (ike cost, speed, storagevision
between
of the existing relationships
capacity, access time etc.) among
the
ferent memories
ries in the hierarchical pyramid.
The memory hierarchy pyramid, on
hich
whi are the registers while at the bottom lie
topof the magnetic tapes, is as shown
below:

size
access time Registers
(min) speed cost
(min)
(max) (max)
Cache
L2 Cache

Main Memory

Flash Memory

Magnetic Disk

Optical Disk

Magnetic Tapes

max max) (min) (min)

lhe above Pyramid shows the different memories in a memory hierarchy. The
Telationship between cost, speed and capacity are as follows: Cost of the memories
decreases downwards the pyramid with the registers being the costliest and the magnetic
lapes the cheapest.
Speed decreases downwards the pyramid with the registers being the
2stest and the magnetic
tapes the slowest. Capacity (size) increases downwards with the
sters being the smallest and the magnetic tapes having the highest capacity. Apart
om these, access time (inversely proportional to speed) increases downwards with the
Crs having the minimum access time and the magnetic tapes the maximum.
ead Only Memory
can be used as a virtual Random Access Memory.

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A ROM cannot work as a RAM. Although, it is possible to write data data

ROM etc., they are not RAMs (which is a volatile memorinROMs
RoM
EEPROM, Flash
RAM or random access memory refers to the method by which the data i
mory). e
memory. Random Access means data can be accessed from memory in a Tanedfro
in which we are ommanne
i.e. in any order irrespective of the order storing the data. "

he
term for RAM is Sequential access memory or SAM. i.e, data can be accesse oppositg
kind of media in a sequential manner only. Tape drives are claslassic examples d from
of SAN th
Sequential access

Y 7 8

Random access

1
6 5

In Read Only Memory or ROM data is accessed in sequential manner. RAM

is
faster but expensive also. Moreover data can be read as well as written in RAM much
hich
not possible for ROM as it can be read only. So in both the way a ROM can not be RA is
RAM

Content-addressable memory (CAM) is a special type of computer memory

used in
certain very high speed searching applications. It is also known as associative memory
Content-addressed or associative memóry refers to a memory organization in which the
memory is accessed by its content (as opposed to an explicit address). Thus, reference
clues are "associated" with actual memory contents until a desirable match (or set of
matches) is found. Production systems are obvious examples of systems that employ such
a memory. Associative memory stands as the most likely model for cognitive memories,
as well. Humans retrieve information best when it can be linked to other related
information. This linking is fast, direct and labyrinthine in the sense that the memory map
iS many-to-many and homomorphic.

Content-addressable memory is often used in computer networking devices, For exampl

when a network switch receives a data frame from one of its ports, it updates an intermal
table with the frame's source MAC address and the port it was received on. It then loos
up the destination MAC address in the table to determine what port the frame needs to
forwarded to, and sends it out on that port. The MA address table is usualy
implemented with a binary CAM so the destination port can be found very quidk
reducing the switch's latency.

3. Give examples of non-destructive read out memory

and destructivea051
memory. WBUT2005
OR
Explain destructive read out & non-destructive read out of memory
systT
WBUT2010
2010

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 COMPUTER ORGANISATION
Answer:
le of non-destrucuve read-Out memory:
Example
Static Semiconductor memories
Access Memory (SRAM).Static
Ranductor memory where the word random access memory (SRAM)
static indicates that, unlike namic RAM
(DRAM), it does not neea to be periodically dynan
refreshed, as SRAM uses bistable
circuitr to store each bit. SRAM exhibits latchin
nse that data is eventually data remanance, but is still volatile in the
tional sense
cO le of destructive read-out memory:lost when the memory is not powered.
These are magnetic-core
core memories. memories or ferrite
"core" comes from conventional
erm "core
The term transformers whose windings surround a
gnetic core. In corore memory the wires pass
once through any given are
single-turn devices.
vices. The magnetic material for en core-they
a core memory requires a high degree of
netic remanance, the ability to stay highly magnetized,
c energy is required to change the magnetization and a low coactivity so that
direction. Magnetic-core memory was
the predominant forn of random-access computer memory
magnetic tororoids (rings), the cores, through which for 20 years. It uses tiny
wires are threaded to write and read
information. Each core represents one bit of information.

4. a) Explain the reading and writing operations of a

basic Static MOS cell.
[WBUT 2007]
Answer

Word Line
Bit Lines
Memories that consists of circuits that capable of retaining their state as long as power is
applied are known as static memories. Figure shows a static MOS cell. Two inverters are
cross connected to form a latch. The latch is connected to two bit lines by transistors T
and T2. These transistors act as switches that can be opened or closed under control of the
word line. When the word line is at the ground level, the transistors are turned off, and
the latch retains its state.

Read Operation:
line is activated to close
Order to read the state of the static MOS cell, the word b is high and the signal in
T and T,.If the cell is in state 1,the signal on bit line
Ches cell is in state 0. Thus b and b' are
ine b is low. The opposite is true if the

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Sense/write cirCUits at the end of the bit lines monitor

complements of each other. accordingly
set the output
state of b and b' and

Write Operation: appropriate value on bit line

is set by placing the
The state of the cell
and then activated the word line.
This forces the celldi the
complement on b', generated by the
signals on the lines are seWite
corresponding state. The required
circuit.
are needed to construct a memory canar
16 RAM chips must h 0f
b) How many 128 x many lines of the address bus
word)? How
4096 words (16 bit is one many lines
memory of 4096 words? For chip select, how ust be
to access a WBUT 2007
decoded?
Answer: 128 x 16
needed are: 4096 words/
The number of RAM chips
= 4096 x 16 bits/128 x 16 2x 2/2' 2=2
x 32.

As, 4096=2", hence 12 lines address bus should be used.

and 6 lines in the vertical direction
should be
he
For chip select, 6 lines in the horizontal
decoded. to their use.
in a digital computer according
5. a) Classify memory system WBUT 2007]

Answer:
Following are the types of memory;
1) CPU registers:
working memory for temporary storage
The high speed registers in the CPU serve as the
a general purpose register file for storing
data
of instructions and data. They usually form register
is typical of a register file and each
as it is processed. A capacity of 32 data word
within a single clock cycle.
can be accessed that is, read from or written into,

2) Main (primary) memory: use

large, fairly fast external memory stores programs and data that are in active
This
by the CPU's load and store
storage locations in main memory are addressed directly
MB 2 bytes Is
instructions. Main memory capacity is typically between and 2
1

referred to as a gigabyte (1 GB). Access times of five or more clock cycles usual.

3) Secondary memory:
main memoy
This memory type is much larger in capacity but also much slower than
arc
Secondary memory stores system programs. Large data files and the like that
capae
continuously required by the CPU. It also acts as an overflow memory when the
to De a
of main memory is excused. Information in secondary storage is considered nation
line but it is accessed indirectly via input/output programs that transfer inodan
between main and secondary memory. Representative technologies for Selow
memory are magnetic hard disks and CD-ROMs, both of which have relatively
electromechanical access times are measured in milliseconds.

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 COMPUTER ORGANISATION
st computers now have another level
Most
Cache: ealled cache memory, of IC memory-sometimesSvveral
levels which in positioned
main memory. A caches storage logically between the CPU
ngisters nd capacity is less than that of
access
cess time of one to three cycles, main memory,
ith an
with som the cache is much faster than main
emory because
bult Ise some of all or it can reside on the
nonents of high-periormance computers that same IC as the CPU. Caches a
essentialco aim to make CPI S
1.
CPU

Cache Cache
Regist Main Secondary
(level 1) (level 2)
file memory memory

(microprocessor)
ICs2: m
1

IC
TCs m n

Conceptual organization or a muiilevel memory system in a Head disks, etc.

computer

aA random access memory moduie of capacity 2048

nnuter and mapped between 2000
and 27FF
bytes is
H Explain
be used in a to
aaram with the help of a block
diagra the address decoding schema assuming 16 bit address
bus. [WBUT 2007]
Answer:
RAM capacity= 2048 bytes = 2"" bytes.
Thusthe RAM has an 11-bit internal
decoder which decodes the RAM address 0 through
2-1 (i.e. 2047).
is desired to select this RAM chip
It
(using its CS input) with an external decoder such
thatthe RAM occupies the 2 addresses, 2000H through 27FFH
Clearly, the highest 5 bits
of the address, namely, Ais, A14. Aia A12, A should be chosen
equal to the base address
00100B, so that the 2K byte RAM chip occupies the desired
addresses (i.e. 2000H through 27FFH) in the 64
bytes.

Diagram:
Aio-0

A14
ADDRESS
Ais To CHIP SELECT CS
input of the RAM chip
2KB RAM

A CS

To MAR of the RAM DATA

chip

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c) How do the following influence the performance of a virtual memory

memor
system?
a) Size of page NBUT
b) Replacement policy 200
Answer:
fala
(a) Size of a page: lf the size of a page is large then less number of page faults
will
But this will lead to increase in the page transfer time.
(b) Replacement policy: The least recently used frame (1.e. the main
memo o
oryblosk
the least frequently referenced frame must be replaced.
Because if a frame that is the most recently used or the most frequently used,
used isrep
then it may lead to more faults.

6. a) Draw the internal cell diagram of PROM and explain its functionality
WBUT
2000
Answer:

ADDRESS
DECODER

ADDRESS
BUS

02 D1 DO

Programmable Read Only Memory (PROM)

A programmable read-only memory (PROM) or field programmable read-only memon

(FPROM) or one-time programmable non-volatile memory
(OTP NVM) is a form u
digital memory where the setting of each bit is locked
by a fuse or antifuse. Such Pr
are used to store programs permanently. The key thatthe
difference from a strict ROM 15u
programming is applied after the device is
constructed.
A typical PROM comes with all bits reading nming
as 1. Burning a fuse bit during
causes the bit to read as 0. The memory profer
can be programmed just
manufacturing by "blowing" the fuses,
which is an irreversible process. Blo
fs
ame
opens a connection while programming name
an antifuse closes a connection (henco

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 COMPUTER ORGANISATION
cell is programmedby applying
The bit across the gate a high-voltage
aorma peration and substrate pulse not encountered luring
Oxide, or 30M V/cm) of the thin oxidetran
transistor (around 6V for
to break down
a 2nn itive voltage on the
The ransistor's gate formsthe oxide between gate and strate.
Phe gate, causing
below theadditional a tunneling current to flowan inversion channel in the substrac
roduces additic traps in the oxide, through the oxide. The current
melting the oxide and formingincreasing the current through rough the oxide and
ultumant a conductive
currer required to form the conductive channel from gate to suosrat
The channel
breakdown occurs in approximately 100us or is around 100uA/100nm. m2 and the
less.
memory? How
cache me
b) What is does it increase the
What is hit ratio? performancee of a computer??
OR, WBUT 2008]
What is locality
ity of reference? Explain
the concept of cache memory
withit.
OR, [WBUT 2009]
What is Cache memory? Why is it needed?
OR, WBUT 2012]
Alhat is cache memory? what do you mean by
hit ratio 75%? WBUT 2013]
Answer:
1 Part:
Locality of referencethe property that shows for large
is
number of programs, references
to memory at any given interval of time tend to be confined
within a few localized areas
in memory.

2nd
Part:
Cache memory is random access memory (RAM) that a
computer microprocessor can
access more quickly than it can access regular RAM. As the.
microprocessor proceses
data, it looks first in the cache memory and if it finds the data
there (from a previous
reading of data), it does not have to do the more time-consuming reading
of data from
larger memory.

CPU Cache Main

Memory
/O Processor
Memory

A special very high-speed memory called a cache is sometimes used to increase the speed
processing by making current programs and data available to the CPU at a rapid rate.
Ihe cache memory is employed in computer systems to compensate for the speed
difterential between main memory access time and processor logic.CPU logic is usually
Taster than main
memory access time, with the result that processing speed is limited
primarily by the speed of main memory. A technique used to compensate for the
in operating speeds is to employ an extremely fast, small cache between the
dcn
and the main memory whose access time is close to processor logic clock cycle
he cache is used for storing segments of programs currently being executed in the
CPU and
temporary frequently needed in the present calculations. By making
data
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1S possible to increase
the perfar
performar
available at a rapid rate, it
programs and data rate
of the computer. tastest, smallest but the
most expensive among the
Cache memory is the frequentlu
program segments and data that are needed CPU
devices. It stores
current executions.
the
n
measured in terms of e
of memory Is frequently
Hit ratio: The performance find the word in the cache, if the word i found
i
the CPU needs to
called hit ratio when the cache, it is in
its produces a hit if the word is not found in n
then main
the cache
of number of hits is divided by
the total CPU r
memory as counted miss the ratio ference
is called hit ratio.
of memory
ratio=number hits/(number of hits+ number of
miss)
hit of
total times the CPU accesses memory is hit
So if hit ratio 75% then 75% of the
is
will get the desired data
For example if CPU accesses memory for 12 times ihen CPU ed
for 9 times and won't find it 3 times.

access time of 5 nsec and die

c) A three level memory system having cache .
40 nsec, has a cache hit ratio of 0.96 and main memory hit ratio
access time of of
to achieve an overall accaee
0.9. What should be the main memory access time
WBUT 2008, 2012
time of 16 nsec?
Answer:
Obviously, there is some mistake in the problem. A disk can never have a 40 nsec access
time. However, let us first solve the problem with the given data.
Let the main memory access time be t nsec.
Considering a particular memory access request, the probability that it has a hit in the
cache is 0.96, a hit in the main memory is (1 0.96) 0.9 = 0.036 and, finally, a hit in the
*

disk is (1 -0.96 -0.036) = 0.004. Note that the sun of the probabilities is
1.

Hence, 16 = 0.96 * 5+0.036t + 0.004 * 40.

So,t= 306.6 nsec
Clearly, this is impossible because in the memory hierarchy, the main memory occupies
the middle level and not the end level. So 40 nsec must be the access time for the main
memory and the access time for the disk has to be found out. This is done below.
16= 0.96 *5+0.036 *40 +0.004t
Hencet= 2440 nsec

7. Giventhe following, determine the size of the sub-fields in the address for direct
mapping, associative mapping and set-associative mapping cache schemes:
WBUT 2008
Main memory size 512 MB
Cache memory size 1MB
Address space of processor 512 MB
Block size 128 B
8 blocks in cache set.

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 COMPUTER ORGANISATION

Answer:
the main ory is 512 MB hence
e size of 2 there are 29 bits (as 512 MB
2
1

As 512 MB2 2" x

hence S12 MB = X 2 =2) and
bits; main
memory is 29 bits. in the main memory address i.e. tnC a
sizeof
SIZe the sub-fields for direct mapping scheme:
f cache
memory 1s T
MB=2 bytes. Hence number cache memory
NoW723, So of o S
2/22. So number of bits in the block
afsthe total
NoW O
field =
main memory address size
13.
of 29 bits, word field contains
128B) and the block field
block contains 13 bits. Hence,
is 29-(13 + 7)=9. the number of bits in the
tagfield

Tag Word
Block

139 7
Main Memory Address

Size of the sub-fields for associativ mapping

scheme:
block size is 128 bytes or 2 bytes. Hence number of
22 So number of bits in the tag field is 22 and that in themain memory blocks=212
word field is 7 (as block size
is 128 bytes).
Tag Word
2
Main Memory Address

Size of the sub-fields for set-associative mapping scheme:

In this case, there are 8 blocks per cache set and the total numbers
of cache blocks are 2
So number of sets in the cache memory is 23/8 23/23-20
Hence, number of bits in the set field is l10 and
that in the word field is 7. So number of
bitsin the tag freld =29 (10+7)= 12.
Tag Word

12
Main Memory Address

8. Can a ROM be also a RAM? Justify your answer.

a)
D)
WBUT 2009, 2017]
Explain the memory hierarchy pyramid, also explain
speed and capacity.
the relationship of cost,
Answer:
WBUT 2009, 2013]1

efer to Question No. 2 of Long Answer Type Questions.

erarchical cache-main memory subsystem has the following specification:

Cache access item of 160ns
Main memory access time
960n
Hit ratio of cache memory
Calculate is 0.9
the following:
Average
D)
access time of the memory syste
Efficiency of the memory [WBUT 2009]
system.
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Answer:
a) Given: Hit ratio (h) 0.9, cache memory access time (tcache) = 160ns.O ns, man
access time (main)960 ns memory

Now, to access a word, the average required access time (vernge) is given by:
averageh.ache+(-h)main
So, taverage0.9 x 160 + 0.1 x 960 = 240 ns.

b) Avg. access time presence of cache memory 240 ns.

Now if a cache memory is not there,
Then h - 0,

main 960ns
960-240 720
system effieiency = x100 % = x100 1% = 75%
960 960
. System efficiency=75%
9. a) State L1 and L2 cache policies with
suitable figure. WBUT 2009
Answer:
CPU

LI Cache Memory

L2 Cache Memory
Main
DRAM
Memory

System Interface

Fig. LI and L2 cache

LI Cache
LI cache lies on the same
chip as the processor. It is smaller nas
lower hit rate and higher number in size and faster. it
of misses as size is small.
L2 Cache:
L2 cache lies external to the processor
chip. It is larger in size er.
It has higher hit rate and low and comparatively sio
number of misses as size is comparatively
large
b) How many 256 x 4 RAM
chip are needed to provide a memory
bytes? capaciuy2009
Answer:
The number of RAM chips needed
are: 2048 bytes / 256x4 =
16 chips.

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a CPU has 8-bit data bus & 16-bit connection

If CPU with four256*8 RAM & oneaddress bus dra the
104 512*8 ROM. [WBUT 2010, 2018]
diagral
bus connection with a CPU to
Show the a ROM chip of 51. *8 bit connect four RAM chips of size 256
eac address size. Assume the CPU has 8-bit data bus
16-bit
addre bus. Clearly specity generation of chip select signals.
and
[WBUT 2010, 2013, 2014]
Answer:
helow shows the required bus connection between CPU and four 256 x 8 bit
The tig re
nd one 512 x 8 bit ROM chip. The decoder has four
RAM address bus each whereas the ROM chip has bits. The RAM chips
have S6
9 bit address bus. Each of the five
c a data bus of 8 bits. CSI and CS2 are select lines.

Address bus CPU

16 12 11 10 9 8 1 RD WR Data Bus

Decoder

2 CS1
CS2 256x8
RD Data
RAM1
R
AD8

| CSI
CS2 256 x 8

RD RAM 2 Data
WR
AD8

CS
CS2 256x8
RD Data
RAM 3
WR
ADo

CSI
C'S2 256 x 8
RD Data
RAM 4
WR
AD8

CSI
CS2 512x8
Data
ROM
AD
us connection to the CPU connecting four RAM chips and one ROM chip
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11. a) Explain the difference between assOCiative & set associativo

ciative
cache
technique. emapying
b) With
the help of following information, determine the size of suh. fields
in the address for Direct mapping. Associative mapping&Set (iny
mapping: associa
ciatv
512 MB main memory & 2 MB cache memory
The address space of this processor is 256 MB
The block size is 256 bytes
There are 16 blocks in a cache set. WBUT
Answer: 2010
a) The difference between associative & set associative cache
mapping tech
Associative Mapping: ique:
In associative cache mapping, the data from any location in RAM
h
n be
can
any location in cache. stored
When the processor wants an address, all tag
p
fields in the cache
determine if the data is already in the cache. as cked
Each tag line requires circuitry to compare
the desired address with the
All tag fields are checked in parallel tag field
The lower log2(line size) bits define which
byte in the block
The remaining upper bits are the tag field.
For a 4 GB address space with 128 KB
cache and 32 byte blocks
Tag (27bits) Offset (5bits)

Set Associative Mapping

Set associative mapping is a
mixture of direct and associative
The cache lines are grouped into sets mapping
The number of lines in a
set can vary from 2 to 16.
A portion of the address is used
to specify which set will
The data can be stored in any hold an address.
of the lines in the set.
Tag (19bits) Set(7 bits) Offset (6 bits)
b) As thesize ofthe main memory
MB is 512 MB hence there are
2
address
bits; hence 512 MB =
2 X 2=2") in
29 bits (as.512=2 anu
size of main memory the main memory address LE
is 29 bits.
Size of the sub-fields
for direct mapping
Now size of cache scheme:
memory is 2 MB
= 212 2, So number of bits in 2 bytes. Hence number of cache memo blocks
the block
main memory address field=13.
Now out of the total
block size is 256B) size of 29 bits, word
field contains
andthe block field
tag field is 29-(13+8)-8. contains 13 bits.
Hence, the number o ohe
Block
Tag Word
13

Main Memory Address

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 COMPUTER ORGANISATIÓN

sub-fields for assoCiative mapping scheme:

sizeck size is 256 bytes or 2 bytes. Hence number of main memory blocks 22/2
EaC So number a bits in the tag field is 21 and that in the word field is 8 (as block size
of
So number
2.256 bytes). Tag Word
is 21 8
Main Memory Address

thesub-fields for set-associative mapping scheme:

Size of
this case, there are 8 blocks per cache set and the total numbers of cache blocks are 2
In memory is 2/8 23/2=210
number of sets in the cache
number of bits in the set field is 10 and that in the word field is 8. So number of
Hence,number
tag field 29-(10 +8) 12.
bits in the Set Tag Word
10 11
8 Main Memory Address

12. What is Belady's anomaly for page replacement technique? Explain with
example. WBUT 2010]
Answer:
Deladv's anomaly, introduced in 1969, is a very common concept discussed in context of
naoe faults.
It proved that while dealing with page faults, it is possible to have more page
faults when increasing the number of page frames if a first-in first-out (FIFO) method of
frame management is used.
The explanation is as follows:
In a computer memory, information is loaded in the main memory
in the form of pages,
which are specific sized storage chunks. It is possible to load only a limited number of
is need
pages at a time in the memory. For each page to be loaded, an equal sized frame
in the main memory. If a required page is not found in the main memory,
a page fault
occurs and that page is brought from the disk or secondary
memory. It might happen that
there is no free or empty frame in the main memory at the time of
occurrence of the page
it is required
fault to accommodate the new page in the main memory. In such instances,
to free a frame to accommodate the new page. Before
the introduction of Belady's
anomaly, it was acceptable that the common page replacement
algorithm producing
acceptable results was the FIFO one. But, the anomaly proved that
wrong.
3 2 0 1
3 2 4 2
Page Requests 0
2 1 3 2 4 4 4
Newest Page 3
3 2 1
0 3

Oldest Page
2 32 4
4
Page Requests 0 3 2
Newest Page 3 2 1
0 0
1
0 2
3
3

3 3
Oldest Page

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frames, 9 page
anomaly: Using three page
An example of
Belady's
page frames causes l0 page taults to occur. Page faults are
OCCur
faults
Increasing to four inbold
italics.
m
a main memory of 64K * 16 and a cache nemory
13. a) A computer has of
uses direct mapping with a block size of 4 words K
words. The cache in tag, index, block and word
fields?
How many bits are there
cache word?
What is the size of one
accommodated in the cache? WBUT
How many blocks can be 2013
OR mem
a memory unit of 64K x 16 and a cache mory 1K
A digital computer has
words. The cache uses direct
4
mapping with a block size of words. How
formabits
m0
block and words fields, of the address
are there in the tag, index,
calculate address format for associative
mapping and for 4-way set ociative
aseas
WBUT 2015
mapping.
Answer:
Direct Mapping
16 bitaddresses (can address 64K words memory)
4 words block (offset is 2 bits)
IK words of cache
Number of lines IK/2 2
Bits to specify which line = loga(2°)=8
6bits 8bits 2bits
|
Tag Line/Index Offset

In word field there is 16 bits.

In this case, there are 4 blocks per cache set and the total numbers of cache blocks are 2
2°.
/4-2. So number of sets in the cache memory is 2/4 2°/2=
Hence, number of bits in the set field is 6 and that in the word field is 2. So number of
bits in the tag field= 16-(6+2) =8.
8bits 6bits 2bits
Tag Set Offset

b) A processor's TLB has a hit ratio of 80% and it takes 20 ns to search the TLB
and 100 ns to access main memory. What will be the effective access time?
WBUT 2013]
Answer:
Effective access time 20 ns + (100 x 20%) ns = 40 ns

14. a) Write down difference between Dynamic RAM and Static RAM. [WBu
Answer:
Dynamic RAM is the most common type of memory in use today. Inside a u namic
RAM chip, each memory cell holds one bit of information and is made up of [wO Pparts:
and
a transistor and a capacitor. These are, of course, extremely small
transiso holds
capacitors so that millions of them can fit on a single memory
chip. The capac
CO-94
 COMPUTER ORGANISATION
intormation a 0 or a 1.
bil ot The transistor
the on the memory chip read the capacitor acts as a swito
cutryO
Iike
like a small or change its itch that lets the control
acitor is bucket that is state.
Capa
the bucket able to store electrons. To store a l in the
ory cel, he
A is lilled with
bucker electrons. To
itor's bucket is that it has
capacitors store a 0, it is emptied.
a leak. In The probien
ith theDecomesmes empty
empty. heretore, for a matter of a few milliseconds a
hckel controller has to come dynamic memory un
ory along and recharge all to work, either the CPU Or
heme discharge. To do this, the memory of the capacitors holding a
Rlore controller reads
back. This refresh operation
"

Writesit right happens automatically the memory and then

secona. thousands of times per
operation is where dynamic
ynam
ret
This
refreshed all of the
time
RAM gets its name.
or it forgets what Dynamic RAM has to be
hing is that it takes time and
refreshi it is holding.
ofthis slows down the memory. The downside of all
Static RAM uses a completely different technology.
In static RAM, a form
holds each bit of memory (see How Boolean Gates Work of flip-flop
memory cell takes 4 or 6 for detail on flip-flops). A tlip-
flop or a transistors along with some
efreshed.
refre This makes statie RAM Significantly wiring, but never has to
faster than dynamic
because it has more arts, a static memory RAM. However,
cell takes a lot more space
yna
namic memory cell.
hererore you get less memory on a chip than a
RAM a lot more expensive.
per chip, and that makes static
Co
static RAM is fast and expensive, and
dynamic RAM is less expensive
Therefore static RAM is used to create and slower.
the CPU's speed-sensitive cache,
RAM forms the larger system RAM while dynamic
space.

b A disk pack has 20 surfaces. Storage area on

each
diameter of 20 cm and outer diameter of 30 cm. Maximum surface has an inner
track is 2000 bits/cm and
storage density on any
minimum spacing between tracks is 0.50 mm.
WBUT 2014, 2017]
Answer:
Gven, no. of surfaces = 20
Innertrack diameter = 20cm
Outertrack diameter
=30cm
So0,total
track width = (30- 20/2 cm= Scm
Irack separation 0.50mm
=

Ihus, no. of tracks/surface = (5*10)/0.50= 100

Munimumtrack circumference=
20 * 3.14 = 62.8cm
amum track storage density 2000bits/cm, which will be on innermost track.
ala storage capacity/track =62.8 * 2000 bits = 125.6 Kbits
Disk
speed =
, Totation 3600 rpm
time 1/3600 minute = 16.67 msec
torage capacity= 20*100*125.6 Kbits = 251.2Mbits= 31.4 Mbytes
Thieata transfer rate = 125.6 Kbits/16.67msec =7.53 Mbits/sec
Is the
mum data transfer rate excluding seek time and rotational latency.
maximun

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128-Byte lines and is 4-way Sos

15. a) A cache has 64 KB capacíty, memASSOcatve.
generates 32-bit address for accessing data in the
The CPU
and Sets does the cache have?
() How many Lines required for tag?
(ii) How many entries are
(ii) How many bits of tags
are required in each entry in the tan
b) A hierarchical Cache-Main
Memory subsystem has the followinay?
Time 80 ns fication
() Cache Memory Access
(ii) Main Memory Access Time 150 ns
(ii) Hit ratio of Cache. Memory is 0.9.
Calculate the following:
(a) Average access time of the memory system
(b) Efficiency of the memory system
(c) Define addressing mode. WEUT
Answer:
a) () No. of lines = 64KB/128bytes 512
21
So No. of tag entries= 512
No. of sets= 512/4 128
(i) Since one tag entry is required for each line, the tag array needs 512 entries
(i) As there are 128 sets, 7 bits are needed to select the set.
As the line size is 128 bytes other 7 bits are needed for selecting
word in a line SaT.
bits = 32-7-7=18

b) (a) Given: Hit ratio (h) = 0.9, cache memory access

time (teache)80 ns, main memn
access time (tmain)150 ns nory

Now, to access a word, the average required access

time (taverage) 1S given by:
Taverageh.kache t(h) Imain
S0, average
0,9 x80 +0.1 x 150 87 ns.

(b) Avg. access time presence of cache memory 87 ns.

Now if a cache memory is not there,
Then h 0,
etage0xlache +h)x1man=main15ns

system effieiency=50-87-x100
150 %=x100%=
150
42%
.System efficiency= 42%

(c) Addressing modes are an

aspect of the instruction set central
processing unit (CPU) designs. architecture in
The various addressing given
instruction set architecture modes that are definea a
define how machine
identify the operand (or language instructions in that a chitectue
operands) of each instruction.

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 COMPUTER ORGANISATION
ogic
aw the logic diagr of the cell of
diagram
logic. one word in associative
read and write memory including
tive memoaIT
the
Answer:
WBUT 2016]
2016]
of Associative Me
Input

Write

R Match
To M,
Read ogic

Output

A two-way set assOciative cache memory

an accommodate a total oT 2048 words from uses blocks of four words. The cache
17.
the main memory. The main memory
size is 128Kx32.
How many bits are there in the tag, index block and word [WBUT fields
2016]
address format? of the
i) What is the size of the cache memory?
Answer:
128 (2 power 17); for a set size of 2, the index address has 10 bits to accommodate
2048/2 1024 words of cache.
7
17 Bits

TAG INDEX

block Word
8 bits 2 bits

7 32 7 32

Tagl datal tag2 data2

SIZeofthe cache is 1024*2(7+32) 1024*78

16. A
hierarchical Three-Level Memory (Cache, Main memory, Hard Disc) system
has the following specifications:
Cache Memory Access Time is 10nsec
i) Disc Access Time is 150nsec
ii) Hit ratio of Cache Memory is 0.97
V) Hit ratio of Main Memory is 0.9
What
20Snould be the Main Memory access time to achieve an overall access
20nsec?
time of
WBUT 2016]
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Answer: +(1-h,)01-h,)h3 (1+th + t)

Teff-ht1-h,)hat1 p) * 0.1 * 1*(t,+ 160)
10+0.03 * 0.9 *(10+ t2) +0.03
20 97* +.003(1, + 160)
10.3 0.027*(10 +1,)
0.27 +0.027 t,
+0.003 t, +.48
10.3
So t= 318.33 nsec
WBUT
memory-hierarchy. Memory? Jue 2018
2018
19. a) Explain
Memory be also a Random Access stiy your
b) Can a Read Oniy
arswer.
Answer: memory such that
enhancement to organize the t can
a) Memory Hierarchy is an based
memory Hierarchy was developed on a nr
minimize the access time. The
behaviour known as locality of references. The
figure clearly demonstrates the erent diea
levels of memory hierarchy.
into 2 main types:
This memory hierarchy design divided
is

1. External Memory: Comprising of magnetic disk,

optical disk, Magnetic Tape which
are accessible by the processor via I/O Module
2. InternalMemory: Comprising of main memory, cache memory and CPU register
This is directly accessible by the processor.

The characteristics of the memory Hierarchy design are:

i) Capacity: It is the global volume of information the memory can store.
ii) Access Time: It is the time interval between the read/write request and the availabilitvy
of the data.
i) Cost per bit: We move from bottom to top in the Hierarchy, the cost per bit increass
i.e. Internal memory is costlier than external memory.

CPU
Level 0
registers

Cache memory
(SRAMs) Level 1
Increased capacity
and accesS time
Main memory Increased cost
(DRAMs) Level 2

Magnetic disk
Level 3

Optical disk
Level4
Magnetic Tape

Fig: Memory Hierarchy

b) Read only memory is used for permanent data on the
storage. Random access memouy
other hand, can only hold data temporarily. of
Rom is generally several megao s
storage, while RAM is several gigabytes.

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 COMPUTER ORGANISATION
short notes of the following:
organization
a) Stack
ache Replace ement Policies
WBUT 2007]
tual address to real address mapping [WBUT 2008]
Static and dynamic memory WBUT 2009]
d)Paging
e) WBUT 2011, 2017]
Answer: WBUT 2012]
ory: Refer to Question No.
a)Sta 6 of Short Answer
Type Questions.
Cache Replacement Policies:
decision of the right block
The getting replaced is
factor. The objective is to keep the blocks in the an important system
performance
(needed by the CPU) in the near future. cache that are likely
As per the property to be referenced
said that the blocks
said of 'locality
can be that have been referenced of reference' it
So when a block to be overwritten,
1S recently will be referenced again
Snoest time without being réferenced. itThis is needed to
overwrite the one that has gone
block is called the
block
(LR
hile
and the technique is called
the LRU replacement
least recently used
algorithm
Whil using the LRU algorithm, the cache or policy.
ac controller must track references
computation proceeds. A counter to all blocks
is used to track the
Denending on the
number of references tracked by references to each block.
hits and misses) each counter (i.e. by the number of
it is decided which block is used
recently used block). the longest time back (i.e. the least
rec And that block
aloorithms can
is then replaced. Though very effective LRU
lead to poor performance when accesses
are made to sequential elements
of an array that is slightly too large to fit into the
cache.
Other replacement algorithms are however
not as effective as LRU. Another algorithm
that replaces the particular block in the cache
set that has been in the cache for the
period of time is called the first-in-first-out longest
(FIFO) algorithm. The third algorithm that
replaces the particular block in the cache set that has
experienced the fewest references is
called the least-frequently used (LFU) algorithm.
Apart from these, using an algorithm
that randomly chooses
the blocks be replaced, is also getting effective.
to

) Need for Mapping of Addresses:

10 execute
programs (instructions and data), they must be physically present in the main
memory. If a virtual address issued by
the CPU refers to a part of the program or data
pace that is currently in the physical memory, then those contents
are accessed
mmediately in the main memory. Else, if the referenced address is not in the main
mory, 1ts contents must be brought into a suitable location in the main memory before
they can be
used.

Pages
and Frames:
h
physical (main) memory is broken down (i.e. memory space is divided) into groups
down (i.e.
addS1ze called blocks or frames while logical (virtual) memory is brokenframes
udress
be of
space is divided) into grou of equal sizes called pages. Pages and must
equal sizes.

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Need for Pages and Frames:

simplity the implementation of memorv table
Such divisions are done to pages. When a foraddres
considered to be split into
mapping. Programs are
executed, its pages fronm the auxiliary
memory are loaded (mapped or trane.
anslated) tob
intoa
is
available memory frames.

Mapping a Virtual Address to a Physical Address

may not be in contio
In the main memory, portions of programs and data \ocaione
and empty spaces (to bring programs from the disk) may be available in
locations in memory. With help of mapping it is deçided exactly where to nlaate
data to be brought in from the disk. The mapping hardware organization thenes
virtual address register that contains the virtual address provided, a memoeSs of,
mapp
table that will keep track of the available frames and map them as needed to the
pages, a memory table buffer register to hold the trame number where the page
r
is
mapped, a main memory address register that holds the physical address and t to
man
memory. The figure below shows the hardware organization.

Memory
Virtual address Main memory Main memory
mapping table
register address register

Memory table
buffer register Main memory buffer
register

Fig: Memory Table for mapping a virtual address

The mapping from address space to memory space is facilitated

if each virtual address s
considered to be represented by two numbers: a
page number address and a line within
the page. Suppose the address space capacity is 8K and the
memory space capacity is 4K
Splitting each into groups of IK words, 8 pages and
4 blocks/frames are obtained
respectively. Now 8K =2" and IK =
2= 1024 words. So a virtual address has 13bis
(as 8K = 2") and each page has 1024 words.
Let the high-order three bits
of the virtual address specify one of the 8 pages and
low-order 10 bits give the line address within i
the page. The page number to u
number mapping is required. As shown in figure
below, the memory-page table conso
of 8 words, one for each page. The virtual
address has got two parts, the page nuo and
the line number. The page table address
denotes the page number and the content o
word gives the block number
where that page is stored in
In the table pages 1, 2, 5, and main memory.
6 are shown to be available blocks34
1, and 2 respectively. in main memory in
Thepresence bit in each location, 1,
has been transferred from if indicates that particuhd
auxiliary memory to main dicates t
particular page is not available memory and, it u,
page tabl at the page number
in main memory.
The content of the word mem0
address is read out into
the memory table bu
i ite.
the presence bit is a l, the block rder b
number thus read is transferred
of the main memory address to the two higAress
addres
register. The line
number from the vinu
CO-100
 COMPUTER ORGANISATION

transtemed intc
into the 10 1oW-order bits of the memory address register (main memory
space has 4K= 2 words 1.e. 2 bit block
ddress nal number and 10 bit line num0ci A
to main memory then transfers the content of ory
sig
read regist ady to be used by the CPU.
the word to the ma
bufter presence
However, the bit
the word read from the page table is it signifies that the
in
wor 0,
the word reterenced
content ofthe by the virtual address
does not reside in main memO1
age fault' occurs if that page is needed in the main memory and it is needed to
Then
fetch
nage
that page
from
from the disk to the main memory to resume
further computation.
Diagram:
Page No. Line number

0 1
01 01 00 1 1

Virtual
Table address
address Presence
Dit

000
001 11

010 Main memory

00
011 Block 0
100
101 01 01 0101010011 Block 1

110 J0 Main memory Block 2

address register
111 Block3

MBR

Memory page table Fig: Memory table in paged system

d) Static memory:
It
of internal flip-flops that store the binary information. Stored information
consists
remains valid as long as power is applied to the unit
satic memories, consisting of Static RAM chips are memories consisting of circuits
Capable of retaining their state as long as power is on.

Dynamic memory:
aynamic RAM loses its stored information in a very short time (a few
milliseconds)
Even though
the power supply is on.
is stored in a dynamic memory cell in the
form of charge on a capacitor and
Laon can be maintained only for a very few milliseconds.
As the charge on the
ge gets turned off after the
Citors leak away as a result of normal leakage, the capacitor
for a much longer time, the cell's
Con secConds. So, to retain the cell information
be periodically refreshed to restore the
capacitor charge to its full value.
st

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e) Paging:
Paging is a concept of transfer of pages between main
memory and an
ary
like the hard disk. So, in paging, relatively inactive pages are removedfrom store
for om
memory to make places for pages, which are needed by the memory for execution
phe
physi
instruction. For example, nowadays all Windows O.Ss come with built-inlon
ilt-inpagingof
ng
Page files are in megabytes, created during the WindowS XP installation fles
the hard drive. The actual size of the page fileis based on how much RAM isinstallet
amount
the computer. By default, XP creates a page file that is 1.5 times the amount ll
ofinstal
RAM and places it on the hard drive where XP is installed. stalet
 COMPUTER ORGANISATION

CONTROL UNIT

Chapter at a ance
Au Instructie
Ai instruction Cycle consists
Instruction cycle: of one or multiple machine cycles.
Examl
A sequence of operations involved in
processing an instruction constitutes an
ction cycle. It has 2 major phases:
inst
ecle: during this phase instruction is obtained from the main memory.
ecution
(i)
cycle: this phase includes decoding
erforming the operation specified by
the instruction, fetching any requuc
operands,I the instruction's opcode.
Awired control unit: In a hardwired control
unit, all control signals are generated by
Haaf hardware using conventional simple logic
design techniques. Each step in nc
ence of control signals is executed in one clock period.
e hasic units of the hardwired control are: (a) A clock (b)
A counter (c) A decoder (d) An
encoder
ach micro program Comprises
Eac! or a sequence of micro operational
steps. Each micro
nerational steps comprise or one or more micro operations
and needs a number of control
signals to be activated. The control signals needed to execu each micro
operational step are
nenerated simultaneously. So, in each clock state a
micro operational step is performed i.e. in
ch clock state, the necessary control Signals are generated & the corresponding micro
each
operations are performed.
Micro-programmed control unit: This is a control unit whose binary variable (i.e. the
control functions that specities a microoperation) remains stored in memory i.e.
such type of
control unit is software (1.e., microinstruction) based.
Control Words:
Control words are words whose bits are used to control certain specified microoperations or
eneral' operations, These are basically string of 1's and 0's. Each of the bits in different
Cne
cotrol words generates different microoperations related to the instruction. Control words
,are generally stored within control memory.
Routine: Meaningful sequence of instructions is called a routine (or a program).
Microroutine: Microinstructions are stored in control memory in groups. Each of these
groups specifies a microroutine. So a meaningful sequence of microinstructions constitutes a
microroutine. Now the microinstructions within a microroutine must be sequenced and there
must be options of branching from one routine to another.
Microinstructions: Microinstruction is an instruction whose bits carry out a of
set
microoperations at the same time.
Microprogram: A meaningful sequence of microinstructions constitutes a microprogrant.

Multiple Choice Type Questions

Micr0-processor, the address of the next instruction to be executed, is
stored in WBUT 2003, 2011]
a) Stack
pointer b) Address hatch
c) Program
counter d) General purpose register
Answer:
(c)

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example of NBUT
2. A UART is an ship 201
asynchronous data transmission
a) serial
b) PIO
controller
c) DMA
d).none of these
Answer: (8)

Control program
memory can be reduced by WBUT
3. b) Vertical format nicro-program201
a) Horizontal format d) None of these
c) Hardwired
control unit
Answer: (b)

WBUT
4. The cylinder in a disk pack
is
2018
a) collection of all tracks in a surface
b) logical view of same radius tracks on different surfaces of disks
c) collection of all sectors in a track
d) collection of all disks in the pack
Answer: (c)

Short Answer Type Questions

1. What are the advantages of microprogramming control over hardwired control

WBUT 2008, 2011, 2014
Answer:
It should be mentioned that most computers today are micro-programmed. The reason is
basical one of flexibility. Once the control unit of a hard-wired computer is designed
and built, it is virtually impossible to alter its architecture and instruction set. in the cax
of a micro-programmed computer, however, we can change the computer's instruction sat
simply by altering the micro-program stored in its control memory. In fact, taking our
basic computer as an example, we notice that its four-bit op-code permits up to 16
instructions. Therefore, we could add seven more instructions to the instruction set by
ou
simply expanding its micro-program. To do this with the hard-wired version of
computer would require a complete redesign of the controller circuit hardware
Another advantage to using micro-programmed control is the fact that the task o
designing the computer in the first place is simplified. The process of specitying u
architecture and instruction set is now one of software (micro-programming) as oppos
to hardware design. Nevertheless, for certain applications hard-wired computers are
used. If speed is a consideration, hard-wiring may be required since it is faster to have ul
s
hardware issue the required control signals than to have a "program" do it
mmed
2. Draw the block diagram and explain the functionality of micro-progrendl
2010 WBUT
control unit?

CO-104
 COMPUTER ORGANISATION

Answer:
Next address Control
Control
generator address Control data
Memory Control word
(Sequences) register register
(ROM)

Next address information

|Instruction Starting
register (IR) address
generator PC: It is basically the CMAR
Control Store: It is the Control Memory.
The CMDR is not shown here, as it Is
optional

Clock
Cl APC

The rts of
the microprogrammed control unit are Control Memory Address Register
HAR), Next Address Generator(sequencer), Control Memory Data Register(CMDR),
(CMA
Control Memory.

Working of a Microprogrammed Control Unit:

teps:
Instruct is fetched from the main memory and is stored in the IR.
Opcode
Opco portion of the IR, which holds the operation part of the instruction, is decoded
with a decoder.
1
Decoding the opcode, gives the address or the starting address of the microinstructions
in the control memory.

The starting address then comes to the 'next address generator

From there, it goes to the CMAR.
Then the control memory is accessed and 1 microinstruction from the starting address
location in the control memory is sent to CMDR.
The CMDR now holds the microinstruction. Simultaneously, the CMDR asks for the
1

next address information to the next address generator.

While asking for the next address information, the CMDR executes the present control
Word stored in it.
signal is generated.
On outputof the microinstruction, the respective required control
Meanwhile, the next address generator on getting next-address
information' signal from
tne CMDR, generates the next location address of the next
microinstruction in the control
memory &sent it to the CMAR.
(1.e., execution of one
s cycle continues till the execution of the current microprogram
instruction) is over.
starts for the next instruction.
CXeCution of one instruction is over, execution

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Microinstruction. NBUT
3. Write short
note on 2017a
Answer: control Signals that must
stbe assermed
microinstruction defines a set of aatapath
Each means, we assert the control.
a microinstruction in
spedfie
given state. Executing
by that microinstructi0n. microinstruc
tructions
the control unit as a program composed of
Designing Is alle
"microprogramming.
have and
of fields a microinstruction should and which .

We can choose the number format:

by each field. In choosing the Co
signals should be affected
(a) simplify the representation
Ex: The mnemonics Add, Subt and Func
can represent the function to
to be
he
periormed
ALU. h
understand microprogram.
(b) try to make it easier to write and
Example: It is useful to have one field controlling the AlLU, two fields to determin
ALU T e t
two sources for the ALU, and one field to determine the destination of result
(c) make it difficult to write inconsistent (if requires a control signal
it to be set
ettotwo
different values !) microinstructions
Ex: From the three write signals RegWrite, MemWrite and IRWrite only one
must h
asserted in a given cycle. If the mnemonicS of these three signals share the
microinstruction field, we can place only one mnemonics to that field, restrictino t
thes
three signals to one at a time.
In selecting the microinstruction format for our MIPS subset multi clock
implementation, we can assume that signals that are never asserted simultaneoush m
rl
sharethe same field. We can thus define the following 8 fields:
ALU SRCI SRC2 ALU Memory Memory PCWrite Sequencing
Control Dest. Reg. Control
Mapping from instruction code to microinstruction format:
The format for an instruction is shown below:

I |Opcode Address

Now the format for a microinstruction is also the same

as the above instruction format
3-bit 3-bits 3-bits 2-bits 2-bits 7-bits

Opcode
Address
FI F2
F3 CD
BR AD
Fig: Microinstruction code
format (20 bits)

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 COMPUTER ORGANISATION

you mean by instruction cycle. WBUT 2012]

What do
Answer:
Cycle: cone
Instruction
Instruction Cycle consists of one or multiple machine
cycles.
A sequence or operations involved
An
in processing an instruction constitutes an
Exaon Cycle. It has 2 major phases:
structe: during this phase instruction is obtained from
n fetcuion the main memory
execution cycle: this phase includes decoding
the instruction, fetching any
any required
perannerforming the operation specified by the instruction's opcode.
il
circuit diagram for
Sho the implementing the following register
transe
operation. If (ab
If 1) then
6.
R1-R2 else R1 R3, where a and b are Contro
variables. [WBUT 2008]
wer:
AnSstion
question (particularly the meaning of 'ab = 1') is
The not very clear. It looks like the
uit is a MU
UX which has 2 inputs, r2 and r3, and one oútput rl. If the MUX control
Cab
inputa is a 1, then content of r2 is transferred to rl and, otherwise, content of rš IS
transferred to rl.

6.VMhat do you mean by instruction cycle, machine cycles and T states?

WBUT 2008, 2011]
Answer:
lnstruction Cycle: Refer to Question No. 4 of Short Answer Type
Questions.
Machine Cycle:
One or multiple clock cycles make a machine cycle.
Example: Generally one memory read (i.e. CPU placing
address on address bus and then
nemory sending 'data back to the CPU. via the data bus) or one
memory write (i.e. CPU
placing 'data' to be written on the data
bus, the address of the memory location where
data is to be written on the address bus and
then sending 'write' pulse on the control bus)
cycle constitute a machine cycle.
So, these sequences may occur within one clock cycle or may
take multiple clock cycles.
T states:
AT-State is one clock period.
A clock frequency = 1/clock period= 1/T.

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Questions
Long Answer 1ype
memory read operation. WBUT
1. Draw time diagram for OR, 200
writing operations
of basic memory read and
Give the timing diagrams WBUT
200m
OR,
WBUT 2008,
diagram for memory write operation. 2011,201
Draw the time
Answer: signal is issued by the CPU clock ia mer
In synchronous data transfer the timing
the CPU clock. This type of data
oy
transfer occurs mainlv between
operates according to
CPU & main memory.

Synchronous data transfer is mainly of two types:

memory):
(a) Memory Read (i.e. CPU reading from

CLOCK

Address
Address
(from master

Read Status
Control (trom slave )
(Irom master)

Data
Data (from slave )

Steps:
sends the address of the
As shown in figure above, in the 1" clock period, (T1) CPU
memory location to be read, in the address bus.
At the same time (in T), CPU places 'read signal in the control line.
sends back the
On getting the "read' signal as well as the address from the CPU, memory
is because,
required data to the CPU via the data bus in the next (T,) clack period. This
tor une
there is sufficient delay in main memory in receiving the CPU signals, searching
the ne
required data and then placing the data in the data bus. So, data is sent back in
clock period.
to resyu
The 'status' signal is optional. It indicates whether the main memory is ready
to the CPU request or not.
So, only if the main memory is ready to response, it will place a 'status Signariu
the control bus on getting the CPU request. Then the main memory will place da data
the

main memory is not ready to response, it will not place the data u
on
Hence if the
bus.

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 COMPUTER ORGANISATION

Memory W
Write (i.e. CPU writing to
the memory):
T

CLOCK

Address
Address
(from master)
Write
Control
(from master

Data Data
(from master)
Steps:
CPU sends 'address of the memory location to write,
in the 1s T-state (T).
CPU then sends the write' control signal.
eDI
after some delay, sends data to be written, in the next (T2) clock
period/T2 state.
. Drawand explain the instruction state cycle. WBUT 2013]
OR,
Fxolain the various phases of instruction cycle in a basic computer. [WBUT 2016]
OR,
Explain Instruction Cycle with suitable flow chart. WBUT 2018]
Answer:
The basic phases of an instruction cycle (generally it consists of instruction fetch cycle
and instruction execution cycle) are:
To fetch an instruction from the memory.
To decode the instruction.

fit is an indirect address instruction, then the effective address is to be read from the
memory (i.e. the operands needed to be fetched from the memory one by one).
To execute the instruction.

The first three phases constitute the instruction fetch cycle and the last phase is the
instruction execution cycle. On completion of step (d), the control again goes back to the
step (a) to repeat the same cycle for the next instruction. This continues until a HALT

instruction in encountered.
ne instruction cycle has got two main phases: the instruction fetch phase (this has three
Sub phases) and instruction execution phase. The flowchart shows the instruction cycle of
any processor.

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Start
SC0
AR-PC.

T
IR-[AR], PC - PC+1

12
Decode operation code in IR (12-14)
AR-IR (0-11), I-
IR (15)

(Register or 1/0) 1

=0 (Memory reterence)

(I/0) =1 0 (register) (ind irect)Y

0 (direct)

3 T T
Execute Execute AR-M[ AR] Nothing
Input- output Register- reference
Instruction Instruction
SC-0 SC-0

Execute
Memory-reference
Instruction
SC-0

The different steps of an instruction cycle

are as follows:
Steps:
(a) The address of the first instruction in
the program is loaded in the PC.
(b) A sequence counter (SC) is kept
to track the different steps i.e. to keep track whetner
the steps are performed sequentially
and correctly. The SC is incremented by o
after each clock pulse (clock period).
So, initially the SC is cleared to 0.
(c) In the first clock period (To), the
contents of PC are placed to the AR (1.e. nc
address register or MAR).
(d) In the second clock period (T), the
content of the desired memory location (a given
in the PC) is placed in the IR. Also
the PC is loaded with the address of ui nex
instruction.
(e) In (T2), the IR content is decoded from
(i.e. the opcode of the instruction fetci 1
memory is decoded).
The flip-flop I hold the indirect bit npu-
[this specifies whether the instrucuo
output reference or register reference direct) in
or memory reference (direct or in
CO-110
 COMPUTER ORGANISATION
o1 The address pat
natui of the operands
transferred to the AR. (to be fetched from memory) are again
memoiy
Depe
nding on the l-bit
of the instruction,
(0 icter reterence
reference or input-output it is decided whether the instruction is
règister reference or direct-indirect her
nature memor
nory reference in
ca
if the opcode is Tti then it is either
ference instruction, eise a register reference or
it is a memory a input-ou
000 through 10).
1
reference instruction (i.e.
from opcode vaii
Provided it is a input-Output
(g) reference instruction
Ethen at (T3), the input-output (i.e. if opcode is 111 and I
instruction is executed. ),
leared to 0 (as it completes the After this the SC 1is again
Current instruction
the beginning ot the next instruction cycle and the control goes back to
cycle).
(h) Also if is register rererence instruction (i.e.
it a
(T), the registerter reference instruction if opcode is 111 and I = 0),
is executed. After
then at
cleared to 0. this,
his, similarly, the SC is
On the other hand, it it is a direct memory
reference instruction (i.e.
from 000 through I10 but = 0), then1 if opcode varies
it is not needed to do anything as the operand
effective address 1s already
there in AR and so
the instruction can be directly
s
executed. Then again the SC
is to be cleared
to 0.
For indirect memory reference instruction (opcode
= 1), it is needed to fetch
varies from 000 through 110 but I
the effective address again from
fetching the actual operand from the memory. So only after
the memory, the instruction
this the SC is cleared to 0. can be executed. After
Steps (i) and ()) are performed at clock
period (T3). However for indirect memory
reference instructions it may continue till T
(k) Hence on completion of
execution of the current instruction, SC is
address of the next instruction gets loaded cleared aind iie
in the PC and the same cycle continues.
3. Differentiate between hardwired
control and micro programmed control. Draw
the block diagram of a basic hardwired
control organization with two
sequence counter and a number of control logic decoders, a
gates. WBUT 2015, 2016]
Answer:
part:
The differences are as follows:
No. Hardwired control unit
I.
Microprogrammed control unit
Hardware implemented. Software (microinstructions) implemented.
Non-programmable (done by logic Programmable.
design)
. Faster
Slower
4 Not flexible.
. Implementation is complex.
Flexible.
Simple and easy to implement.

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POPULAR PUBLICATIONS

2nd part:
(IR)
lnstuuction register
13 11 Other inputs

3 x8
decode
6513,21
Do
Combinational
D7 Control Conte
loaic snals
TL

tt14..
15 2 10

16
f decoder
Clear
4-bt Cloc
(SC COnte
 COMPUTER ORGANISATION

BUS STRUCTURE

Chapterat a Glance
is a set of wires/cables designed to
Bus: A bus transfer all bits of a w-bit word from a
source to
to a specified destination.
specified The source & destination are ypically registers.
spe
So
s is a communication pathway connecting
two or more registers within the system
modules namely CPU, Memory, /O etc. A bus structure consists
or of a set of common
each bit of a register, through which binary information transferred
one is one bit at a time.
may be unidirectional 1.e. capable of transmitting
data in one direction only, or t ay
A bus
ectional i.e. capable of ansmitting data in both direction.
be
Register B Register CC
Register A
Register D

Date Lines

Bus
Address
Lines

JUL Control
Lines

1
Fig:

Data, Address and control lines of bus:

Data Lines: These lines provide a path for moving
data between registers, These are designed
in parallel. So, they either consist of two sets of n-
to transmit all bits of an n-bit word
unidirectional lines or a single set of n-bi-directional
lines.
is usually a multiple of 8,
Data lines collectively called the data bus. This bus of size 'n'
are
with n= etc. separate lines.
8, 16 or 32
to transfer the addresses of the source
Address Lines: Address lines of the bus are used lines are
destination register receiving the data. Address
register sending the data and the
collectively called the address bus.
access to the
control signals, are used to control the
Control Lines: These lines, transmitting registers, will
which register, out of the multiple
0ata & address lines i.e. control lines select
transmit its information through the bus.

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 PUBLICATIONS
POPULAR
some.
constructed with multiplexers has us disa
Tri-state buffer: Bus system connected by the bus, multiplexers cannot co
registers are support
If more number of registers (connected to the bus) draw some
me urTent that
Also as all
and voltages drop. the bus voltage drops and thusfrom
not transmitting at that time, the
even if they are thettans
becomes unreliable. tri-sto
these problems a device (or a digital circuit) called -state buffer
So to counter
exhibits three states, two inputs and
0, logic
one
I
output. The output can
and a high-impedance' state.
be in one
of is
thethree
stat
(signal values) namely, logic

Multiple Choice 1Type Questions

1. The logic circuitry in ALU is WBUT

a) entirely combinational b) entirely sequential 200a
c) combinational cum sequential d) none of these
Answer: (c)

2. A single bus structure is primarily found in wBUT 2008,

2011
a) main frames b) super computers
c) high performance machines d) mini and micro-computers
Answer: (d)

3. Toconstruct an n-line common bus using MUX for k registers of n bits

each , the
number of MUXs and size of each MUX are WBUT 2014
a) k and nx1 b) n and 2 c) n and kx1 d) k and 2
Answer: (c)

4. The main purpose for using single Bus structure is [WBUT 2017
a) Fast data transfer
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) none of these
Answer: (c)

5. The main advantage of multiple bus organisation

a) Reduction in the number over single bus is
of cycles for execution WBUT 2017
b) Increasse in size of the
registers
c) Better connectivity
d) none of these
Answer: (a)

6. The maximum propagation

delay for n-bit CLA is WBUT 2018
a) A
b) A*n
Answer: (b) c) 6*A d) n

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 COMPUTER ORGANISATION

Short Answer Type

Questions
aigitalcomputer has a common bus system for 16 reaisters of 32-bits eac
1.a s I5any
a) A constructed with multiplexers.
selection inputs are there in
The Howi
) What size of multiplexers are needed2? each multiplexer?
i) many iplexers are there in
i) lowmost computer have a Commonthe bus??
Why do bus system? WBUT 2010]
b importanco
OR,
ce of a common bus system in a computer. 2017]1
lain the ter.[WBUT 2011,

Ansher
a)i)
Num of selection lines= 4 (as 216), since there are 16 registers.
The size of multiplexers will depend on the number of input lines, Number of data
lines = numb
mber of registers. Hence 16 data input lines must be there. So, the
input
multiplexers will be 16:1.
size of
The number of multiplexers needed to construct the bus
number of bits in each
register. Hence 32 multiplexers are needed.

is a communication pathway connecting two or more registers within the system

b)A hus namely CPU,.Memory,
A

modules I/Oetc.
Early microcomputer Dus systems were essentialy a passive backplane connected
irectly or through bufter amplifiers to the pins of the CPU. Memory and other devices
uOuld be added to the bus using the same address and data pins as the CPU itself
used,
comnected in parallel. Communication was controlled by the CPU, which had read and

writen data from the devices

as if they are blocks of memory, using the same
instructions, all timed by a central clock controlling the speed of the
CPU. A common
bus system reduces the number of wire
network. This creates an organized and clear
connection structure between certain devices. By using latches,
same bus can be used for
transferring of data or instructions as well. These may lead to simple
system structure.

connects 4 registers of 4-bit

2 Draw the logic diagram of a common bus which WBUT 2010]
each using tristate buffers.
Answer:
the 4 registers connected through the 4-
Consider the diagram below. A, B, C & D are flip-
of
(D-ends the flip-flops) & outputs (Q-end of the
iInes system. Both the inputs
bus
sending
are connected through the bus system.
Tristate buffers are there at both the
ps)
& receiving
ends of the registers.

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Receive C

Receive
D.DD,D B D:DDD
CLK A D;D;D,Do
CLK B
CLK C DD.DD
Q:0.00 Q0:00 Q:0:010 CLK
D
O090

Send A Send B Send C Send D

Bus line 0

Bus line 1

Bus line 2

Bus line 3

Fig: Bus system constructed with Tristate Buffers

3. What is tri-state buffer? Construct a single line common bus system using t
state buffer. WBUT 2015
Answer:
1" part:
A tri-state gate is a digital circuit that exhibits three states out of which two
states are
normal signals equivalent to logic 1 and logic 0 similar to a conventional gate.
The third
state is a high-impedance state. The high-impedance state behaves like an open cireuit
which means that no output is produced though there is an input signal and does have
not
logic significance. The gate is controlled by one separate control input C. IfC is high the
gate behaves like a normal logic gate having output or 0. When C is low, the gate does
1

not product any output irrespective of the input values. The graphic symbol of a tri-state
buffer gate is shown in Fig. 1.
Normal input X Output Y = X ifC = 1
High-impedance if C =0
Control input C

Fig: 1
Graphic symbol for a tri-state buffer gate
2nd Part:
A common bus system with tri-state buffers is described in Fig. 2. The outputs of tour
buffers are connected together to form a single line of the bus. The control inputs to tne
buffers, which are generated by a common decoder, determine which of the four no
inputs will communicate with the common line of the bus. Note that only one buffer
ecoder
be in the active state at any given time. Because the selection lines So, Si of the dec
the
activate one of its output lines at a time and the output lines of the decoder ac a then
control lines to the buffers. For example, if select combination SSo is equal to u

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 COMPUTER ORGANISATION
decod
oder will be activated,
output of the which then activates
and thus the bus line content will the top-most tri-st
hutler be currently Ao, 0th
bit of A register.
0 line of common bus

Bo

Co

Do -

Decoder
-to-

Fig: 2 A single line

of a bus system with tri-state buffers

,Adigital computer has a common bus system for 16

The
bus is constructed with multiplexers? registers of 32 bits each.
A HOw many
selection inputs are there in each
How many multiplexers are there in the multiplexer?
bus? wBUT 2015, 2016]
Answer:
Refer 1o Question No. I (a) of Short Answer Type
Questions.
5.Why 1/0 bus is different from a system bus?
Answer: WBUT 20171
Computers have two major types of buses:
1.
System bus: This is the bus
that connects the CPU to main memory
motherboard. The system bus is also caled the front-side on the
bus, memory bus, local bus, or
host
bus.

2.A number of 1/O Buses, (1/O is an acronym tor input

output), connecting various
peripheral devices
to the CPU. These devices connect to the system bus via
a "bridge'
implemented in the processors
chipset. Other names for the 1/0 bus include "expansion
hus",
"external bus" or "host bus".

DIOCK set-associative cache consists of a total of 64 blocks divided into 4

KS Sets. The main memory contains 4096 blocks, each consisting of 128
Words.
How many
) How many bits are there in a main memory address?
dny bits are there in each of the TAG, SET and Word fields? [WBUT 2018

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 POPULAR PUBLICATIONS

Answer:
The main memory size = 4096 blocks 2
Hence, the tag and set field combine will have 12 bits.
Each block consist of 128 words =2'words.
Hence, the word field length will be 7 bits.
Hence, total size of main memory in word length = 2x2 219

Hence there will be I19 bits in the main memory.

i) There will be 19 bits in a main memory
ii) There are 12 bits in each of the TAG and SET fields and 7 bits in Word
ensgh
fiela.
ieldlengh
Long Answer Type Questions
1. What is bus? Draw and describe the bus architecture for a digital compt
puter.
WBUT
Answer: 2012
1" Part: Refer to Chapter at a Glance.

2nd Part:
Bus can be of 4 types,
Internal bus: This runs within the CPU. Internal bus connects all the registers within th
CPU.

Register Register Register

A

T
B C

Internal Bus

External/ System bus: This runs outside the CPU i.e. the external bus connects all he
three subsystems (i.e. connects all the registers within the CPU,
Memory and I/O unit) or
a digital computer. This is a set of shared communication
lines via which the regisie
inside the Input-Output processors& the CPU share a
common access path to man
Memory registers.

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 COMPUTER ORGANISATION
Memory
CPU 1/0
/O

JI ILII External / System Bus

SharedBus
are Several registers can
Here be connected via a single
common bus with the restriction that
anly one register can senu data at any time.
Co here
the number ot buses and thus the number
of cables required are much less. Cost
Cables required, hence, 1S much less. However, shared
buses do not permit
cintultaneous data transters between different pair
of registers, so this leads to a loss of
nerformance compared to dedicated buses. To implement shared buses,
more complicated
logic circuits are needed.

Dedicated Bus
It unique source and a unique destination i.e. within each pair of registers there is a
has a
pair of dedicated bus for both way transmission of information.

f 'n' registers are interconnected by buses in all possible ways, then the number of
dodicated buses required is 'n (n-1)'.
Here the number of wires required is more. The number of wires required however
varies
with the number
of registers to be connected. More the number of registers to be
Connected, more the number of wires needed.
As the
number of system components and thus the number of buses to be connected
ncreases, the number
of pin requirements and the cost of cables along with the cost of
complicated circuits also increases.
Here the simultaneous transfer of information between different pair of devices is
possible.

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Register A

Register B
Register DD

Wires/cables
Register C

Diagram of dedicated buses connecting

the registers
2. Write short note on 'Bus organization using tristate
buffer
WBUT 2007 2009,
Answer: 2012,2017
2017
Bus system constructed with
multiplexers has some serious disadvantages,
number of registers are connected by Ie .
the bus, multiplexers cannot More
voltages drop. Also as all registers support that load
(connected to the bus) draw some and
even if they are not transmitting current fromthe
at that time, the bus voltage drops and DUS

becomes unreliable. thus the tran

ranster
So to counter these problems device
a (or a digital circuit) called tristate buffer
exhibits three states, two inputs is used.
t
and one output. The output can
states (signal values) namely, logic 0, logic lI be in one of the
and a high-impedance' state. While thte
typically correspond to two electrical voltage 0&
levels, e.g. 0 & SV, the "high-impedance'
state represents the state of a line that is
electrically disconnected from all voltage sources
i.e. an open-circuited line.
This high-impedance state is very useful in
building the bus in the computer because the
registers that are interconnected through
the bus (i.e, communicate through the bus) do
not draw any current through the bus unless
they either transmit or receive data over the
bus lines.

Functioning
The tri-state buffer has three output states namely
logic 0, logic 1 and a high-impedane
state. It has two inputs (figure a). The inputs
A (normal input) and C (control input)
ordinary binary signals that assume only the values
0 & 1; the output Y can assumi
it
values 0, 1& high-impedance.
The special input line C, called the 'output enable'
or 'control input' when set to figure 1

b), the output Y A i.e. acts as a close-circuited

line with what given in the
comes to the output Y. (i.e. if A = 0 then Y =
0 or if A 1 then Y 1) but if
disables the output line Y by placing it in
the high-impedance state.

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 COMPUTER ORGANISATION
Normal input A
Normal input A
-Y
Control input C
Y=A
(a) logic symbol
C-1
(b) close-circuit, when C is enabled

Inputs Output

A
Normal input A
0 0
Y high-impedance 1
state

0 0 Z
Control input
C0 0 Z
(c) open-circuit, when C is disabled (d) truth table
 PUBLICATIONS
POPULAR

INPUT-OUTPUTORGANIZATION

Chapter at a Glance
com
Input-Output (VO) organization of a puter
Input-output organisation: The world i.e. with 0Vides
the computer and the outside help
mode of communication between The I/O devices that are attached ofthe
with the computer.
1/0 devices, users can interact to the
computer are also known as peripherals.
commonly used in a computer are:
Some of the I.O devices that are
Joystick, Scanner etc.
Input Devices: Keyboard, Mouse,
Output Devices: Printer, Monitor etc.
transfer occur between
Direct memory Access (DMA): In programmed /0 data ad
occurs between 1/0 devices and the
the peripherals. However in DMA, data transfer
only initiates the transfer by sunnio
unit without direct intervention by the CPU. CPU
is to be transferred and the number
starting address of the memory location from where data
of words (bytes) to be transferred.
DMA Controller:
Address bus

Address Bus Buffers

Data Bus Buffers
Data bus

Address register

DMA select DS
Word count register
Internal bus
Register select RS

Read RD Control register

Control
Write WR logic
DMA request
Bus request BR
1/0 device

Bus grant BG

lnterrupt DMA acknowledge

Interrupt

Interrupt: Interrupt is a signal from an L/O device to let the CPU know that it is reauy
this
transfer data and that it is requesting service fron the CPU. As soon as CPU recei
vice's
signal, it leaves its current unfinished task as it is and branches to the interrupting del
agaln
interrupt service routine and executes it to process the transfer. When finishea,
comes back to its unfinished task and continues with it.

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 COMPUTER ORGANISATION
Differer types of
lnterrupts: There
Cyernal nterrupis: Such type are generally three types of interrupts, w
(a) m of interrupts may
from 1/0 devices when they are ready come from any exte xternal sources like,
atthe time of an event is over, it
to transfer
may occur due
data, from a timing devtcee signify
nternal Interrupis: Such type of to some power failures c
erroneous conaitions in interrupts, called
the program (i.e. traps, may occur due to som
program). illegal or erroneous
in the use of instructions o u
Software Interrupts: Such type
of interrupts
(9rooram
progr as an instruction by a programmer may be incorpora orated or embedded in the
instruction (interrup and are thus initiated by execu at
nstruction). So the programmer
interrupt procedure at any desired if want to initiate any sort
point in the program,
instruction at that point in the program. he may write an
n
ple of software interrupt is: INT 32
Examp
(say). On execution
control branches to the ISR of the number 32 of this interrupt 1nstructto
interrupt (i.e. 32 number
aVectored Interrupt: In this method, the interrupt line).
branch address (i.e. address
oned to a fixed location in the memory and
assign of the ISR) 1s always
location.
particular
the processor always branches to ae
Vectored Interrupt: In this method, the branch
the interrupting address (i.e. address of the ISR) is supplied by
I/O device itself and the processor
branches accordingly.
Pipelining: Pipelining is a technique of decomposing
a sequential task into subtasks, With
each subtasks, with each subtask being executed in
a special dedicated stage (segment) that
onerates concurrently with all other stages. Each
the way the task is partitioned.
stage performs partial processing dictated by
Result obtained from a stage is transferred
to the next stage in
the pipeline. The final result is obtained after the instruction
has passed through all the stages.
All stages are synchronized by a common
clock. Stages are pure combinational circuits
performing arithmetic or logic operations over the
data stream flowing through the pipe. The
stages are separated by high-speed interface latches (i.e., collection
of registers). Figure below
shows the pipeline concept with k stages.

L
S. S L

I/P *********
O/P

Clock
(L: Latch, S: ith stage)
Concept of pipelining

Multiple Choice Type Questions

1. In
stored
a micro-processor, the address of the next instruction to be executed, is
in [WBUT 2008]
a) stack b) address latch
pointer
c) program counter d) general purpose register
Answer:
(c)

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Memory mapped I/O scheme is used for the allocation of addressto

2. addres.
memore
and I/O devices is used for NBUT otie
a) small system b) large system
d) very large system 206
c) both large and small systems
Answer: (a)

3. For BIOS (Basic input/output system) and 1oCS (input/output cont

ontrol
which one of the following is true? system
NBUT
a) Bios and lOCS are same
b) BIOS controls all devices and IOCS controls only certain 20
c) BIOS is not a part of operating system and 1ocs is
devices
a part of
system
d) BIOS is stored in ROM and iOCS is stored in RAM
Answer: (c)

4. A priority interrupt may be accomplished by

a) Pollingg WBUT
2010
b) Daisy chain
c) Parallel method of priority interrupt
d) All of these
Answer: (a)

5. BIOS is
a) a collection of l/O driver programs WBUT 2013
b) part of OS to perform /O
operation
c) firmware consisting of l/O driver programs
d) a program to control one of
the l/O
peripherals
Answer: (6)

6. In DMA the term cycle

stealing means
a) controller gets opportunity to WBUT 2014
b) CPU transfer only one word in a timeslot
releases the bus and DMA controller can
c) 100 bytes are allowed to use endlessly
be transferred
d) none of these
Answer: (a)

7. The contention
for the usage of a hardware device
a) structural hazard is called WBUT 201
c) deadlock b) stalk
Answer: (a) d) none of these

8. The periods of time

when the unit is idle WBUT 2019
a) Stalls is called as
c) Hazards b) Bubbles
Answer: (d) d) Both Stalls and Bubbles

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 COMPUTER ORGANISATION
MA transfer is initiated by
The WBUT 2019]
S Processor
a) devices b) The process being executed
c)/O d) OS
Answer: (c)

Short
Answer Type Questions
What are the different hazards in Pipeline?
1. OR, WBUT 2007, 2019]
Explain
lain
Pipelining and Hazards
WBUT 2017]
nswer:
line hazards are situations that prevent the next instruction in the instruction streai
PIpvecuting
executing duri
during its designated clock cycle.
from There are three types of pipeline
hazards:
i) Control hazards
i) Structural hazards
Data hazards
i)
Controlhazards: They arise from the pipelining of branches and other instructions that
content of program counter (PC) register.
han the
euctural hazards: Structural hazards occur when
Struc resource
a certain (memory
nctional unit) is requested by more than one instruction at the same time.
Data hazards: Inter-instruction dependencies may arise to prevent the sequential (in-
order) data flow in the pipeline, when successive instructions overlap their fetch, decode
and execution through pipeline processor. This situation due to inter-instruction
dependencies is called data hazard.

2. What are the different types of interrupt? Give examples. WBUT 2008]
Answer:
Refer to Chapter at a Glance.

3.What is interrupt? WBUT 2009, 2011]

What are the differences between vectored and non-vectored interrupt?
[WBUT 2009, 2011, 20181
Answer:
Part: it is ready to transfer
lerrupt signal from an I/O device to let the CPU know that
is a
4ata and that it is requesting service from the CPU.
is and
it leaves its current unfinished task as it
5 Soon as CPU receives this signal,
service routine and executes it to process
dnches to the interrupting device's interrupt
to its unfinished task and continues
uranster. When finished, CPU again comes back
with it.

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2 Part: Non-Vectored
Interrupt
Vectored Interrupt
address (1.e.1. In this method, the hranaanch address
branch
1. In this method, the ISR) alwa
by the addresS of the is always
address of the ISR)
is supplied
assigned (
processor fixed location in the memory
to
interrupting /O device itself and the
processor always branches to that and
branches accordingly. thatparticiula
location.
2. The address of the service routine is
hard- 2. The address of the service
routiner
be supplied externally by the device
Wired.

4. a)Where does DMA mode of data transfer find its use? WBUT
2009,2014
Answer:
In interrupt-driven I/O (as well programmed /0) transfer of data between memory
an 1/0 module takes place with the active intervention of the CPU. The sDeeda
data transfer is often limited by the speed with which the CPU services a vice.
transfer of small volume of data such CPU intervention (and thus limited speed |
transfer) is ok, but transfer of large volume of data via the CPU takes a lot timo
of
while transfer of large volume of data between memory and I/O module by DMA h
I/0 method, CPU is removed from the path (CPU only initiates the transfer)
flows very fast directly between the memory and the concerned I/O module(s) and lata t
with
VO device managing the memory buses. e
Also during interrupt-driven I/0 method, CPU, along with handling
busy handling other tasks. This to some extent
/O tasks, is alta
hampers the 1/O transfer rate. Howeyer
with DMA based I/O method nothing of that sort occurs.
Hence in the above two circumstances DMA mode of
data transfer find its use.
b) What are the different types of DMA controller and how
functioning?
do they differ in their
[WBUT 2009, 2010, 2012, 2014
Answer:
There are three types of DMA controller:
(i) Cycle Stealing DMA, (ii) Burst Mode DMA,
(iii) Flyby DMA.

Their functioning:
() Cycle Stealing DMA:
In this mechanism, DMA
controller transfers le
control of the bus to the CPU. Then word at a time and then returns tne
again after a CPU cycle, the control comes
the DMA controller, which again backu
send one word, and gives
CPU. This carries on until back the bus control to
the entire block of
virtually 'steals' one memory data is transferred. So, DMA Ua
in between every CPU
cycle.
(ii) Burst Mode DMA:
Burst Mode DMA, in
contrast, generally
addresses can take transfers assumes that the destination SOurce
as fast as the controller a
up the controller, and can generate them. The 1Ses
then (perhaps after
the entire source block is a single ready indication prou
copied to the destination. from a poelsive
The DMA controller gains
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 COMPUTER ORGANISATION
the bus for the duration of the
CCESS
Sshut do
transfer, during
efectively down. Burst mode DMA which time the program
whi is
can transfer data
very rapidly indeea.
DMA:
Flyby
gi) DMA, somnething
mething that is not supported
on many controllers,
The MA Controller gains access to the is a beast of a difierei
color Then, bus and puts the sourc
urce or destination
en, it initiates what iS in
addressout. etfect a read and
read from the source address, a write cycle simultaneousiy
Tiheda and written to the destination,
nlies that either the sOurce or
implies destination does not at1the same time.
This
ely that both would use the same. require an address, since it 1s
very An example might
o a FIFO port the source address (a be copyingg data from
mem pointer to memory) increments on eac
hile the destination is always the same FIFO. Flyby
read/write cycle pair iS transactions are very Tast
Since the reuced to a single cycle. Both burst and
synchronous
es of transfers can be supported.
What
Ihat are differences between Serial and Parallel
i. transmission? [WBUT 2012]
MSwer:
rial transmission, bits are sent sequentially on the
same channel (wire) which reduces
for wire but also slows the speed of transmission. Also,
for serial transmission,
come Overhead time is neeaea since bits must be assembled and sent as a unit and then
disassembled at the receiver.
In parallel transmission, muitiple bits (usually 8 bits or a byte/character) are sent
simultaneously on difterent channels (wires, frequency channels) within
the same cable,
radio path, and synchronized to a clock. Parallel devices have a wider data bus than
serial devices and can therefore transfer data in words
of one or more bytes at a time. As
result, there is a speedup in parallel transmission bit rate over serial transmission bit

6. What are the advantages of Interrupt l/0 over programmed l/0?

WBUT 2013, 2015, 2016]
Answer:
Program med I/O
Slowest in speed.
Leastexpensive.
Simple to design.

astage of CPU cycle degrades the performance of the computer,

Interrupt-initiated I/OO
Medium
in speed.
Medium
cost.
Slightly
complicated.
PU cycle is
not wasted.

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"pipeline architecture"? How does it improve the

7. What is meant by WBUTspeed
execution of processor? 2013 of
Answer: computers to
a technique used in the design of incre: se th
An instruction pipeline is can be executed in a
number of instructions that
instruction throughput (the
up into a series called a pipeline Rath
The basic instruction cycle is broken
processing each instruction sequentially (one at a time, finishing one instr
tion
tha
an
before
r
up into a sequence of steps so ferent
starting the next), each instruction is split
circuitry) and in parallel (at the s
can be executed concurrently (by different
stages in the pipeline
The ideal speedup froma pipeline is equal to the number of e.
Time per instruction on unpipelined machine
Number of pipe stages

8. Explain with diagram the daisy chaining priority interrupt technique

WBUT 2013,
2014
Answer:
A daisy chain is an interconnection of computer devices, peripherals, or network nodes
ne in
series, one afier another. It is the computer equivalent of a series electrical cireuit
personal computing, examples of "daisy-chainable" interfaces include Small mputer
System Interface (SCSI) and Fire Wire, which alloW computers to communicate
ith
peripheral hardware such as disk drives. tape drives, CD-ROM drives, printers, and
scanners faster and more flexibly than previous interfaces.
The daisy-chaining method of establishing priority consists of a serial connection of all
devices that request an interrupt. The device with the highest priority is placed in the first
position, followed by lower priority devices up to the device with the lowest priority,
which is placed last in the chain. This method of connection between three devices and
the CPU is shown in the figure below.
Processor Data Bus

VADI VAD2 VAD3

Devicel Device2 Device3

P PO PI PO PI PO To Next
Device

Interrupt request
INT
CPU

Interrupt Acknowledgge INTACK

Daisy-Chain Diagram

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 COMPUTER ORGANISATION

ntage of the daisy chain is its

dvantage
main n simplicity. Another advantage
The add more nodes anywhere along is
USer sCSI-3, the chain, up to a certain maxin
aximum (16in
for example). A daisy-chain
m network can be long in terms of the
sl tros one end to the other, but is not well
suited to situations where
tance ere nodes must
ed all over a geographic region. In such a case,
escateal
sca
overall leng
nd the between
length of the network
can become
the cables must 21g-zag around,
huge compared with the actual
ween the nodes. This can cause
distances the network to operate slowly
wly for users near
nOsite ends of the chain.

you mean by memory-mapped l/O

What alo and /O mapped l/0? WBUT 2014J
Answer:
mapped I/0, all peripherals are
treated as memory locations.
nT
addresses are assigned to I/O ports. The This means tnat
CPU just reads and writes data to a
ocation, and the 1/0 controller automatically
e transte
ferring data from memory to port and
maps the does the updating part,
from port to memory. This way or
apping allows the use of full instruction set of a CISC
computer directly on peripherals,
to
hecause the CPU (or program), they are just simple
ia not have I/O specific instructions.
memory locations. Such systems
10 mapped 1/0, the peripheral
devices are addressed directly
by the CPU using the
f addresses. The length of port address is generally
less than the length of a memory
dress. There are specific
instructions for carrying out input
wrts.
This method of mapping does not
and output tasks at the
facilitate the use of memory oriented
nstruction set directly on port addresses. complex

10. What is pipelining? Describe pipeline hazards.

[WBUT 2014]
Answer:

Part: Refer to Chapter at a Glance.

"Part: Refer to Question No. 1 of
Short Answer Type Questions.
1 Explain the different kinds of data hazards in pipelining
with suitable examples.
AnSwer:
[WBUT 2019]
UAla
hazardsoccur when two instructions in a pipeline
refer to the same register and at
aone of them writes to the register. Compiler writers
use the phrase "data
gndences" to cover the same
kind of problem, but their terminology refers to what
you
Se In an instruction
stream without considering the pipeline.
CXecution circuitry is usualy broken up into multiple functional
erformi units, each
different
Operations types of operations. These functional units can be performing
us in paralel. More complex operations may take several cycles to
lustrate complete. To
ne
div.d
difficulties that result, consider the following MIPS code snippet.
$t0, Sf2, Sf4
mul.d
$f6, Sf8, SfO
add.d
Iheuse Sfo, $Sf10, Sf12
ofregs
sSCr StO can give rise to three different kinds of problems in this code.
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 PUBLICATIONS
POPULAR
dependences
hazards, also known as true
(RAW) dependences
Read after Write hazards, also known as output
(WAW)
Write after Write anti-dependences
Read (WAR) hazards, also known as
Write after supposed to happen. That
Thot
these hazards is based on what is is,
follows SOon a WAR
The naming of writes to a register
an instruction that
hazard occurs when precedes the read tha
then the
reads from the same register. If the write
instruction that
with the wrong data value.
fir
instruction (the read) is working
deal with hazards
There are two ways to hazard so it d
Removal - add hardware and/or complexity to work around the esot
) bypassing/forwarding or speculation.
exist. This can be achieved by
Sacrifice performance to prevent the hazard irom ocCurring
Stallino
2) Stall-
"bubbles".

12. Explain Cache Coherence. WBUT 2019

Answer:
In a shared memory multiprocessor system, all processors share a common, memon
Na
Also, each processor may have a local memory, part or all of which may be a cache
preseice of multiple caches in the system means that copies of shared data may reside in
several caches and also in the common memory. If any of the processors make any
changes in its own copy of the shared variable (1.e. in ts own cache), all other cache
memories (in other processors) containing a copy of that variable must be informed abot
that change so that all the copies of that shared variable (in all other caches) get updated
at a time. This type of situation in which all cached copies of the shared variable (data
have the same value at all times, is termed as the cache coherence concept.

Probable Solutions to the Cache-Coherence Problem:

The cache coherence concept as discussed is a problem in the multiprocessor
system. The
probable solutions to this problen may be:
(a) To disallow local cache memories for each
processor and have a shared cache
memory associated with main memory. Every
data access is made to the shareu
cache. However this scheme increases
the average memory access time.
(b) To allow only non-shared and read-only
data (called as cachable data) to be stored l
the local caches. The shared writable
data (called as non-cachable data) are to e
stored in main memory. So measures
must be taken to identify whether a aala
cachable or non-cachable.
(c) Allowing writable data to exist in
at least one cache. This method enploys&
centralized global table that
stores the status of memory k Is
identified as read-only blocks. Eacn
identified as RO. Only
(RO) or read and write
(RW). All caches can ls
RW block. So
one cache (which
stores writable data) can have
havefa
if the data are updated in the cache a ther
caches are not affected with the RW block, the
because they do
not have a copy of this
block.

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 COMPUTER ORGANISATION
are and hardware means are used
(d) to solve the problem
software-based schemes. also. Methods an
The snoopy-cache 0
protocol uses the hardwar
based schemes.

Long Answer Type

Questions
is interra
What
errupt? What are the differences
1.
interrupt?
between vectored and non-vectored
[WBUT 2009]
nswer:
fer to Question No. 3 of Short Answer Type Questions.

2 How
does polling work?
[WBUT 2012]
Answer:
Alihing the priority of simultaneous interrupts can be
Establ
done by software or hardware.
alling procedure is used to identify the highest priority source by software means. n
method there is one common branch address for all interrupts.
Theprogram that
takes
s of interrupts begins at the branch address and
care
polls the interrupt sources in
ence. The order in which they are tested determines
seq
The
the priority of each interrupt
highest priority source is tested first, and if its interrupt
signal is on, control branches
service routine for this source. Otherwise, the
next-lower-priority source is tested,
and
so on. Thus the initial service routine for all interrupts consists
of a program that tests
the interrupt sources in sequence and branches to one of many possible
service routines.
The particular service routine reached belongs to the highest priority
device among all
devices that interrupted the computer. The disadvantage of the software
method is that if
here are many interrupts, the time required to poll them can exceed the time available to
service the /O device. In this situation a hardware priority-interrupt
unit can be used to
speed up the operation.

1. a) Give the main reason why DMA based /O is better in some circumstances
than interrupt driven l/O. WBUT 2007]
Answer:
In
interrupt-driven I/O (as well programmed I/0) transfer of data between memory and
an
O module takes place with the active intervention of the CPU. The speed of such
data
transfer is often limited by the speed with which the CPU services a device. For
tansfer of small volume of data such CPU intervention (and thus limited speed of data
tasfer) is ok, but transfer of large volume of data via the CPU takes a lot of time. So
hile transfer of large volume data between memory and /O module by DMA based
of
0 method, CPU is
removed from the path (CPU only initiates the transfer) and data
lows very
fast directly between the memory and the concerned l/O module(s) with the
device managing the memory buses.
during interrupt-driven 1/0 method, CPU, along with handling I/O tasks, is also
ndling other tasks. This to some extent hampers the 1/0 transfer rate. However
DMA based 1/O method nothing of that sort occurs.

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 PUBLICATIONS
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is better than into
above two reasons DMA based l/O method P-di
Hence for the
large volume of data between memory andnd I/o module.
/O iven
I/O method while transfer of

Memory Access (DMA) operation for

trans
b) Explain the basic Direct sfer of
peripherals. wBUT 2007, 2008, 2010, data
between memory and 2015,2016
bytes OR,
Explain in detail the Bus Arbitration
techniques in DMA. WBUT
2017n
Answer:
is the data transfer technique directly betwea.
Direct Memory Access or DMA
peripheral devices (line magnetic disk) and the
memory unit through the mee fas

without the direct intervention of the CPU. The transfer

occurs as follows:

Steps:
(a) An 1/0 device when ready to transfer data to the memory, it sends a DMA reguee.
the DMA controller it is attached to.
(b) On getting the request, the DMA controller enables the BR line to request the CPI
releasethe bus.
(c) Now two cases will arise:
BG 0 means buses are still not released by CPU and CPU will communicate wit
the DMA controller. CPU writes (with the help of the WR line of the DMA
controller) into DMA address register the initial address of the memory location from
where data is to be transferred, CPU writes the number of words to be transfeed
into the DMA word count register, CPU specifies the mode of control whether read'
or 'write'. Also CPU reads the status of the DMA controller through the RD 1ine
means that CPU has granted the DMA controller's request
BG=I of releasing the
bus and responds by enabling the bus grant line. The bus is now free and DMA
controller can now control them.
(d) Now the bus is under the control of the DMA controller. CPU now opts out of the
transfer and carries on with other tasks.

DMA controller now places the initial address of the memory

location from where tne
data to be transferred into the address bus from its address register. Then the controer
is
sends an acknowledgement to the 1/O device, which has requested for
the DMA transter
Based on the content of the control register, DMA enables
the RD or WR line i.e. it dala
is to be transferred from I/O device to memory then
will be enabled else the RD line will be
it's a write operation and w
enabled.
On transfer of each word, the word count register
in the DMA controller decreme
one.
Ifthe entire block of data is transferred or if the word count register count dow Zero
the DMA stops the transfer.
It then removes the bus request by
disabling the BR line. CPU then disables tne
and again takes control of the bus. The thatthe
DMA controller may also inform the
transfer is over and it has released
the bus by sending an interrupt
CuCPU.
signal to e
u
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 COMPUTER ORGANISATION
ecks whether the transfer
checks
then has been
completed successfully
count register. The by reading
zero value
done successful, in the register
indicates that the transfer
below shows the entire DMA
re process:
Thei
Interrupt
BG CPU Random access
BR memory (RAM)

RD WR Address
Data
RD WR Address Data

Read Control

Write Control

Data Bus

Address Bus

Address
Select

RD WR Address Data
DS
Direct memory DMA acknowledge
RS access controller
I/0
BR (DMA) Peripheral
BG DMA request Device

Interrupt

) What is programmed 1/0 technique? Why is it not very useful?

WBUT 2007, 2010]
OR,
hat is programmed l/O
Answer:
technique? WBUT 2008]
Ugrammed /0 transfers are initiated as a result of /0 1instructions written
in the
pucr program. Once the transfer is initiated, the CPU has to constantly
monitor the
Ce units of the I/O devices to see when the transfer can be actually made i.e. when
E device will be
ready to transfer data.
Carvery useful, as this constant monitoring of the devices by the CPU requires lot of
the in these times, the CPU remains idle, as it cannot do any other work but to
theck
whether
athis n the 1/0 device is ready to transfer data or not. Lot of CPU time is wasted
0 and
and
anism. So for this reason this technique is the slowest compared to interrupt
A mechanisms and thus degrades the computer performance.
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4. Differentiate between memory mapped l/O and l/O mapped l/O

WBUT 2008,2010,2013
OR, 2010,
2n
Compare and contrast Memory mapped I/O and I/O mapped 1/0. WBUT
OR, 201
What is the difference between isolated l0 and memory mapped l/0? WR
Answer: T209
Isolated 1/O Memory mapped I/O
1. In Isolated 1/0 or 1/0 mapped /0, 1VO|1. In memory mapped 1/0,
a chunt
devices are handled distinctly by the CPU | CPU's address space is reserved for
athe
ccessing
and hence occupy a separate chunk of | I/O devices.
addresses predetermined by the CPU for
VO.
2. In VO mapped Vo we use specific 2. In memory mapped 1/0 the data trancf
command and I/O port is not mentioned as a ansfer
like between two memory segments. ie is
memory address. 1/O port is referred by a memory he
address.
3. 1/0 mapped VO (also known as
port3. Memory mapped l/0 is mapped into the
mapped VO) uses a separate, dedicated same address space as program memory
andVor
address space and is accessed via a user memory, and is accessed in
the same way.
dedicated set of microprocessor instructions.
4. Microprocessor or microcontroller that 4.
Microprocessor or microcontroller that
doesn't support 1/0 mapped I/O. supports /O mapped /0.
5. In 1O mapped I/O we use 8-bit address
interface I/O.
to5. n memory mapped /0 we use locations of
memory interfaced as an address
to /0
devices
6. In I/O mapped I/O we can use only two 6. In memory
mapped 1/0 we can use al
instructions i.e. IN and OUT instructions for data flow.
5. Why do peripherals need interface circuits with
them? WBUT 2013, 2018
Answer:
1/0 interface units are special hardware components that lie
between the I/O devices and
the processor bus. These devices serving as special communication
links, between the
CPU and the peripherals, actually synchronize and supervise i.e.
control all input and
output transfers.
Certain differences between the characteristics (functional
and behavioral) of
peripherals and the CPU (and also memory) exist. Interface
units are needed to resu
the differences, which are:
Operations of the peripherals, which are either anical
electromagnetic or electromecnaus
devices, are different from that of the
CPU and memory, which are g erally
electronic devices. So a signal conversion between the one by
two is required and is
the interface unit between them.
The interface unit has to synchronize the slow
data transfer mechanism between
peripherals and the fast CPU.
Interface units handle the differences
between the data codes and
peripherals and the CPU or memory
word formats.

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 COMPUTER ORGANISATION
Exp different hazards in
6 a) vector interrupts? pipelining.
How are WBUT 2015]
interrupts? they used in
teruesDeedup, throughput implemenoLT hardware
20151
What is and efficiency WBUT 2015]
e) of a pipelined architecture
Answer: WBUT 2015, 2018]
erto Question No. 10 ofShort Answer
Type Questions.
vectored interrupt 1/0 method,
b)in a inforr
ormation (i.e., the source device
the starting address that interrupts, supplies the
branch
CPU. This
information is called of interrupt
the interrupt vector,
service routine (ISR) to the
location. which is not any fixed memory
To impl
ment interrupts, the CPU uses
a signal, known
the interrupt handler as an interrupt request est (INTR)
signal to or controller hardware,
ce at can issue an interrupt to it. Here, which is connected
cted to each 1/0
en that
interrupt controller
hehalf of I/O devices. Typically, interrun
ealy, interrupt controller
is
makes liaison with the
also assigned an interrupt
acknowledge (INTA)TA) line that the CPU uses to
signal the controller
and begun to process the interrupt request by that it has received
below employing an ISR. The following
shows the hardware lines for implementing figure
interrupts.

CPU
INTA

INTR

Interrupt controller
IMR

Device Device 2
1.
Interrupt from interrupt controller when data transfer is needed.
2. Using IE flip-flop, CPU detects interrupt.
3. CPU branches to a respective device's ISR after enabling INTA.
Ite
interrupt controller uses a register called interrupt-request mask register (IMR) to
ec any interrupt from the /0 devices. If there is n number of I/0 devices in the
em, then IMR is n-bit. register and each bit indicates the states of one I/O device. Let
MR
Content be
denoted as E,E,E. When E, =I then device 0 interrupt is
g1zed; When E 1, then device interrupt is recognized and so on. The processor
1

tlag bit known as interrupt enable (1E) in its states register (SR) to process the
upt. When this flag bit is 1', the CPU responds to the presence of interrupt by
it NA line; otherwise not. When the INTA is accepted by a device, device puts
Nn interrupt vector address (VAD) to the data bus using interrupt controller

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c) ldeally, a linear pipeline of k stages can process n tasks in k+(n-1.

where k cycles are needed to complete the execution of the very ery first
first task
remaining n-1 tasks require n-l cycles. Thus the total time required is and
T-[k+(n-1
where r is the clock period. Consider an equivalent-function non-pipelino
processor
which has a flow-through delay of kr. The amount of time it takes to execu
cute n tasks
this non-pipelined processor is 1 =nkr. on

Speedup Factor: The speedup factor of a k-stage pipeline over an equivala

Pipelined processor is defined as ent non

S =nkr
kr+(n-1)r
nk
k+(n-1)

Efficiency and Throughput: The efticiency E of a linear k-stage pipeline is def

ned
as

E,
k+(n-1)
Obviously, the efficiency approaches when n0,
1
and a lower bound on E, is 1/k
when n =1. The pipeline throughput H, is defined as the number of tasks (operations
performed per unit time:

k(-1)k+(n-1)
The maximum throughput
=
f occurs when E>1 as no.
Note that H, E, f=E,/T=S, /k
7. a) What are the hazards of instruction pipelining? How are these taken care of
b) Explain the Strobe Control method of Asynchronous data transfer. What are tne
disadvantages of this method?
oWhatdo you understand by the term Program Interrupt ? Explain with the2016 helo
of suitable diagrams. WBUT
Answer:
a) Structural Hazards
vare
Structural hazards occur when two instructions in a pipeline need the same
naha
resource at the same time. Structural hazards can be avoided by stalling, duplicating
resource, or pipelining the resource.
For example, suppose the processor only has a single port to memory usea 10 h data
or
and instructions. Then there is a structural hazard between the MEM phase o load fime
store instruction and the IF phase of the instruction that needs to be fetched at that TwO
This hazard can be avoided by either stalling the instruction fetch or by nav

CO-136
 COMPUTER ORGANISATION
y rts. Most modern processors
e oives them two memory ports. have
YC separate
Separate data and instruction
eftect, giv caches which,
addition, real processors nave some
long latency instructions
execution step cannot be completed in a Cney instructions- instructions whose
modified multipiy single cycle. One
circuitry, example is an integer multiply.
WIions without stalling the second. you cannot handle two successt
instruction.
ssive multiply
ith
with long latency
Todeal units, instructions, the
execute circuitry
onal each handling a small Circuitry is generally divided up into
func number
nits can he
pipelined by adding of similar instructions. These functiona
pipeline registers.
nsiructhoils very cycle. This lets you start long latency

Control Hazards
Control Hazards occur when conditional
branches interfere
Pireh The problem is that it is not with instr
struction fetches ina
known whether
taken until some time after the cycle for fetching or not a conditional branch will be
targetaddress needs to be computedift the next instruction.
branch is taken. Also, the branch
control hazard could
c be handled
A by stalling the
significant impact on performance, next instruction fetch.
a
especially in tight However that has
dmuch of their time. A common technique loops, where many pro programs
ntrol hazards is speciiattve for reducing the stalis associated
and
execufion guess whether with
nd fetch the next instruction or not the branch will
based on the guess. be taken
ables containing intormation To do this, the machine
about recent branches: needs two
,A branch history table records bits
about recent branch history,
a branch was taken. T that is, whether or not
he processor uses these
will be taken. bits to guess whether or not a branch
.A branch target table holds target addresses for recent branches.
the time needed to
determine the branch target address. This table reduces
Speculative execution
also requires a mechanism for
executed based on backing out of instructions
incorrect guesses and resuming
sequence execution of the correct instruction

Data Dependences and Data Hazards

Datahazards occur
when two instructions a pipeline refer to the same
east one
of them writes to the register. Compiler register and at
ependences" to cover the writers use the phrase "data
same kind of problem, but their terminology
an see in an
instruction stream without considering refers to what you
AiS0,
the pipeline.
execution circuitry is usually
broken up into multiple functional units,
roning different types of operations. These functional each
units can be performing
ralions in parallel. More complex operations may
take several cycles to complete. To
irate the difficulties
div.d Sf0,
that resuit, consider the following MIPS code snippet.
Sf2, Sf4
mul.d $f6,
Sf8, Sf0
add.d
Sf0, Sf10, Sf12
Iheuse
of r
Tegister SfO can give rise to three different kinds of problems in this code.
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Read after Write (RAW) hazards, also known as true dependences

Write after Write (WAW) hazards, also known as output dependences
Write after Read (WAR) hazards, also krnown as anti-dependences
The naming of these hazards is based on what is supposed to happen. That :
hazard occurs when an instruction that writes to a register follows SOon WA
instruction that reads from the same register. If the write precedes the read
sa
thter
instruction (the read) is working with the wrong data value. first
There are two ways to deal with hazards
1) Removal - add hardware and/or complexity to work around the hazard
so:
0 does
exist. This can be achieved by bypassing/forwarding or speculation. not
2) Stall-- Sacrifice performance to prevent the hazard from occurring Stailing
Staline
"bubbles" Causes

b) Strobe Control Technique A single control line is used by the strobe control
merl
asynchronous data transfer to time each transfer. The strobe may be activated
the source of the destination unit. A source-initiated transter is depicted in figure y either
below. The source takes care of proper timing delay between the actual data sipnai(Ist)
the strobe signal. The source places the data first, and after some delay, and
generates t
strobe to inform about the data on the data bus. Betore removing the data,
the SOurce
removes the data. By these two leading and traiing end delays, the
system ensures
reliable data transfer.
Similarly, the destination can initiate data transfer by sending a strobe
signal to the source
unit as shown in figure(2) below. In response, the source unit places data
on the dath
bus. After receiving data, the destination unit removes the strobe signal. Only
after
sensing the removal of the strobe signal, the source removes the data from the data bus.
The disadvantage of the strobe method is that the source unit that initiates
the transfer
cannot know whether the destination unit has actually received the data item what was
placed in the bus. Similarly, a destination unit that that initiates
the transfer cannot know
whether the source unit has actually placed the data o the bus.

)
Source Destination
unit
unit
(a) Block diagram

Data bus
-Valid data
Strobe
(b) Timing diagram
Fig 1: Source-initiated strobe for data
transfer

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 COMPUTER ORGANISATION

Source Data bus

Strobe Destination

(a) Block diagram

Strobe
Valid data
Data bus
(b) Timing diagram
Fig 2: Destination initiated
strobe for data transfer

Program interrupt, a hardware mechanism that allows

events to get serviced, can interrupt
ution
execo of an ongoing task. An event can interrupt,
the it suspends ution of the
task and allocates resources to the
ongoing event that has interrupted, orovided the
interrupting event is of of high
higher priority than the one
currently under execution.
ate
acil
this, the processor checkS for interrupts at the
end of every instruction berore
moving on to the
t next instruction. If any interrupt is
pending, the processor matically
ches off to interrupted program. Saving the status (mainly the address to which the
ecsor should return) of the interrupted program is
process
essential for returning to
MIDted program after servicing the request. This
entire sequence is similar to calling a
tine and returning from a subroutine. The only difference is that a subroutine call
sarOrammed,
progr while the interrupt call is random from the hardware
or software.
Like subroutines,
serviCing of interrupts can be nested. This means that at any point
of
fime, events with higher priority can interrupt the servicing
of events with lower priority.
Fach time a processor receives an interrupt, the interrupted program status is saved in a
first-in/last-out stack and the restoration of the interrupted program
takes place in reverse
squence. The RTOS manage the interrupt hierarchy.

examples of hardware-generated events that can interrupt are as follows:

Typical

Diagnostic error in functional modules

Change of state in digital input module
Counter becoming full in pulse input module
Counter becoming empty in pulse output module
Message-in buffer becoming full in communication module
Message-out buffer becoming empty in communication module

pical examples of software interrupt are as follows:

limer or time-of-day interrupts for servicing time-based event
Frogramming errors, such as division by zero
Genera
h all modes of task scheduling are employed in today's RTOS for different
Tequirements.

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Interrupt handler
User program

Interrupt
Occurs here i+l

Fig: Transfer of Control via Interrupts

speed up will be K. WBUT 2017n
8. What is speed up? Prove that maximum
Answer:
1 part:
Speedup is the ratio of the average instruction time Without pipelining
to the average

instruction time with pipelining.

2" part:
Consider a k' segment pipeline with clock cycle time as Tp. Let there
be 'n' tasks to he
to take 'k cvcles
completed in the pipelined processor. Now, the first instruction is going
will take only 1' cycle each.
tocome out of the pipeline but the other 'n -1 instructions in a pipelined
ie., a total of 'n -1 cycles. So, time taken to execute 'n instructions
processor:
ETpipeline
=ktn-l cycles Tp
(k +n-1)
instructions will be:
In the same case, for a non-pipelined processor, execution time of 'n
ETnon-pipelinen *k Tp'
*

when "n taskS

So, speedup (S) of the pipelined processor over non-pipelined processor,
are executed on the same processor is:
S= Performance of pipelined processor /Performance of Non-pipelined processor
tincg
As the performance of a processor is inversely proportional to the execution
have,
S =ET non-pipeline 1El pipeline
=>S = [n *k* Tp]/[(k+n- 1) * Tp]
S [n *k]/ [k tn- 1]

When the number of tasks 'n' are significantly larger than k, that is, n >K
S n*k/n
S=k
where 'k are the number of stages in the pipeline.

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 COMPUTER ORGANISATION

short notes on the followin

Writecontroller
9. DMA WBUT 2011]
hand,shaking in lO operation [WBUT 2011]
Concept of
D) hazards [WBUT 2009]
Pipeline ne Pipeline [WBUT 2017]
Instruction
dProgrammed l/OAccess WBUT 2017]
e)Diredct Memory WBUT 2019]
9 2swer:
An Controlle Refer to Question No. 4(b) of Short Answer Type Questions.
DMA Controller:
a)
Concept of hand shakingi in 10 operation:
b) handshakhaking method of asynchronous data transfer solves the problem of strobe
The
ethod. This is acknowledgment based i.e. in this mechanism, each data item
trol metho
Ctransferred is accompanied by a control signal to indicate the presence of data in
SAlso the destination unit responds back with a control signal to acknowledge the
has ben received successfully. This method uses a second control
rce ithat the data
l to provide a
reply to the other unit. Hence handshaking method uses two control
ines.

This method also of two types:

is

(a) Source-initiated transfer

using handshaking:
Here the source unit initiates transfer. Two handshaking lines, 'data valid' and data

accepted are used here.

Steps:
0 The source unit places data on the data bus and enables the data valid control line to
indicate the destination that the data is placed on the data bus.
data, enables the data accepted signal to let the
) The destination unit on receiving the
source know that the data has been received
successfully.
.

(ii) On getting this acknowledgement from the destination,

the source unit disables the
data valid signal and then removes the data
from the.bus.
(v) When the destination sees that the "data valid' signal
is disabled, understanding that

the acknowledgment signal has been received,

it disables the 'data accepted' signal
source.
and gets ready to accept another data from the

and the corresponding timing diagram:

gure(a) and (b), shows the entire process
Data bus
Destination
Source unit unit
Data valid

Data accepted
Fig:
1
(a)

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Rising edge indicates

is there in the that the
data bus data
a
valid pulse is active. and data
Data bus
Valid data

Data valid

Data accepled Fig: 1 (b)

(6) Destination-initiated transfer using handshaking:

Here the destination unit initiates the
data transfer. In this case, the source
data on the data bus only after knowing unit
that the destination unit is s

Two handshaking lines, 'data valid'

and 'ready for data' are
to.aes
ready toaccept the
Steps: used here. data

) The destination unit gets ready to accept

data and thus enable the
control signal to let the source 'ready for d
place the data on the data data
i) The source on getting this signal, places bus.
the data on the data bus
valid' signal to inform the placement and enables the
of a valid data on the data bus. 4data
(i) The destination unit then accepts the data and
iv) The source understands that the data disables the "ready for data'
signal.
has been successfully received
the 'data valid' signal and and thus disable
removes the data from the s
data bus.
Figure 2 (a) and (b), shows.
the entire process and the
corresponding timing diagram:
Data bus
Source unit
Data valid
Destination unit

Ready for data

Fig: 2 (a)

Rising edge indicates

that the destination unit
is ready to accept data
Ready for data
now from the source

Data valid

Data bus
Fig: 2 (b)
Valid data

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 COMPUTER ORGANISATION
hazards:
Pipeline wont hazards
differ (problems) that
The
lelay its normal cause an instruction pipeline deviate rom its
or delay
peration
conflicts
operation are
the following: to
Resource
ResO
Such
rds are caused wnen two segments
oth instruction and data are tries to access memory
simultaneou
SupPon is fetched and in stored in the same memory
instruction another segment data and in one segment
So this
ll
wil lead to resource contlict. Using separate
is fetched from the memory y at a time.
problem. instruction and data mer can
solve this memories

Jastruction hazards (dependency)

Such haz ards occur when instructions tries
to read or write in registers
instructions. These are of four types: used by Ounc

Read-after-read (RAR) hazards

ie Occurs when twO instructions try t0 read from the same
register.
Read-after-write (RAw) hazards
Such types of hazards are aiso
known as data dependencies
or true dependencies as these
ecur when
OC an instruction needs to use the result of a previous instruction
which is not
vet available. Here an instruction reads a register that was written by a previous
truction. A situation called the pipeline stall or bubble
instruc
occurs, as the 'read' instruction
annot proceed past the read stage of the pipeline because the
result to be sent by the
write instruction is not available yet. So this
condition delays the entire pipeline
execution. Techniques to resolve such hazards are:

Hardware interlocks
Interlock is a circuit, which further delays the instruction that is stalled (for non-
availability of results) thus resolving the conflict.

Operand forwarding
This method after detecting the conflict by means of special hardware, avoids it by
routing the data through special paths within the pipeline segments.

Delayed load
In such technique, compilers detect the data hazards and handle them accordingly.

Write-after-read (WAR) hazards and Write-after-write (WAW) hazards:

uCh hazards, also called name dependencies, occur when an instruction's output
gster, has either been read or written by a previous instructio.

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Branch difficulties
Such conflicts occur from branch
instructions or other such instruction changing
instruction (both conditiona and uncond
change the PC value. The branch .
that
normal sequence of flow of instruction stream and thus instructionnal)
ction brealk
the pipeline
difficulties in operation. fao

Some of the methods of handling branch hazards are:

Prefetching the target instruction
In this method, both the target instruction and the instruction following the
prefetched and saved until the branch is executed. Provided the branchorancha
branch condition
succesful, pipeline continues from the branch target instruction. tion
is

Use of branch target buffer (BTB)

This is a sml, high speed associative memory placed in the fetch
ment
pipeline. Due to this previously occurred branch instructions are readily availahia of the

pipeline when needd. IBM 360/91 uses this approach.

Loop buffer
This very small register file placed in the fetch segment, stores any
detected rogram
loop, which can be executed directly if needed. If the buffer
is large enough to contain all
the instructions required in a loop, then those instructions
need to be fetched fro
memory only once, for the first iteration. So it is very effective
for loops and called lao
buffer.

Branch detection/ Branch prediction

in this method, additional logic is used to guess
t pre-execution result of a conditional
branch instruction and its predicted path.
Correct prediction sometimes eliminates the
wasted time caused due to branch penalties. Various
techniques of prediction are predict
never taken, predict always taken, predict
by opcode, taken/not taken switch, branch
history table etc.

d) Instruction Pipeline:
We know that an instruction execution
cycle may consist of many operations like, re
instruction, decode instruction, fetch
operands, execute instruction, and write-back
result into memory. These operations
of the instruction execution cycle can be
u
through the pipelining concept. realli
Each of these operations
Each operation may require forms one stage of a Pip
one or more clock periods
instruction type, processor and to execute, depenaing nthe
memory architectures 1on
ofthe operations through the pipeline provides used. The overlapping ofexc
Thus, the pipeline used
for instruction cycle nomal execution
a speedup over the normal
A typical instruction pipeline operations is known as rpeline
is shown in figure instrucuo (
fetches instructions from
memory, presumably struction fetch stage
below. The instr
stage (1D) resolves one per cycle. The instru ction-deco
the instruction function performed an
identifies the operands like, add or subtract,
needed. The operand etc., to be pernoaes
fetch stage'(OF) fetches oper
the
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 ORGANISATION
COMPUTER

cution into processor registers.

executi the
Tor ored operand values. The execute stage (EX) executes
rded write
structions
registers or tage (WB) is used to
The last write-back stag
sters memory.,All high-performance
into computers are now equipped wi
sults
pupeline
this nput Output

Fig: A 5-stage instruction

pipeline
Programmed I/O:
ons
operations will mean a data ranster between an ry or ween
1/O device and memory
0 ovice and the processor. I in any computer system 1/0 operations are completely
9n d
ntrolled by the
proceSsor, nen that system is said to be using 'programmed I/0". When
a tech
technique 1s UsCa, processor executes programs that initiate, direct and terminate
such a
erations, including sensing device status, sending a read or write command and
the/O
ring the data. lt 1s the responsibility of the processor to periodically check
ransferril
status
af the 1/0 system until it Iinds that the operation is complete. Let us onsider the
following
example.
processors softwa tware checks each of the 1/O devices ever so often. During this
The
if any device needs servicing. Figure shows the
check, thehe microprocessor Tests to see
B andC. fhe
achart for this. 1 his is a simple program which services /O ports A, status of i/O
tine checks the status of i/O ports in proper sequence. It first transfers the
Outi to
f A into
2ort.
the accumulator, I hen the routine block checks the contents of accumulator
is called. Atter
eeif
the service request bit is set. If it is, I/0 port A service routine
eompletion of service routine for /O
port A, the polling routine moves on to test port B
port
and the process is repeated. Ihis
test and service procedure continues until all the l/O
registers are tested and all the I/0 ports requesting service are serviced. Once this is
status
tO execute the normal programs.
done, the processor continues
routine is started, the
The routine assigns priorities
to the different 1/0 devices. Once the
checked first. Once port A is checked,
port B is
service request bit at port A is always
can be changed by simply changing the
checked, and then port C. However, the order
routine priorities.
and thus the from
processor fetches I/O related instructions
When programmed IO technique is used,
I/O system to execite the
instruction. The form of
memory and issues I/O commands to
1.e. memory mapped
the instruction depends on the
technique used for 1/0 addressing,
TO or mapped I/O.

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Start 1/0
routine

Get 1/O port A

status register

Is servicee Yes Call the I/0 port A

request bit set? service routine

Got /O port B
status register

Is service YesCall the 1/0 port B

request set?
bit service routine

Got I/O port C

status register

is service Yes Call the I/O port C

request bit set? service routine

End

Fig: Flowchart for I/O service routine

Direct Memory Access: Refer to Chapter al a Glance.

 QUESTION 2015
Group-A
(Multiple Choice Type Questions)
correct alternatives for the following following
noosEmum
Che maxim number of additions and subtractions are required for which of the
1.
The numbers in Booth's algorithm?
) plier
01001111 b) 01111000 c) 00001111 d) 01010101
a)
processor, the.address of the next instruction to be executed is stored in
he register b) index register
a)stack pointer
d) program counter register
c) base register

logical left-shifting the content of a register once, its content is

inaical
i)By doubled b) halved
a)
both (a) and (b)
c)
d) no such decision can be made

numbe of registers and n be the size of each register, then in order to

construct n-
the ber
v) Ifk be of
common bus system using tri-state buffers, the total number of tri-state buffers and the size
line
decoder would be
a) n'k and
2-to-4 b) n'k and log2 k-to-k
log2 n-to-n d) n'k and log2 n-to-n
c)k
and
locality justifies the use of
The principle of b) polling c) DMA d) cache memory
a) interrupt

vi Instruction cycle is
b) fetch-execution-decode
a) fetch-decode-execution
d) none of these
) decode-fetch-execution

vi) Subtractor can be implemented using

b) complementer
a) adder
d) none of these
c) both (a) and (b)

bit) are required to build 1M Memory?

many RAM chips of size (256 K x
1
vil) How
a) 24 b) 10 c) 32 d)8
0)Maximumn bit 2's complement number is cannot be said
a) 2
b) 2-1 c) 2-1 d)

Micro instructions are kept in

cache memory d) none of these
a) main memory
b) control memory c)
POPULAR PUBLICATIONS

Group-B
(Short Answer Type Questions)
a line common bus system using tri
usina tri-state
2.a) What is tri-state buffer? Construct single buffer
b) What are guard bits?
STRUCTURE, Short Answer Type Question No. 3.
a)'See Topic: BUS
b) See Topic: COMPUTER ARITHMATIC, Short Answer Type Question No. 3,

3. Describe stack based CPU

Answer Type Question No. 9,
See Topic: MEMORY ORGANIZATION, Short

4. a) Write+710 in IEEE 32 bit format.

b) Convert IEEE 32-bit format 4040000016 in decimal value.
a) See Topic: CoMPUTER ARITHMATIC, Short Answer Type Question No.5.
b) See Topic: COMPUTER ARITHMATIC, Short Answer Type Question No. 11..

5. Evaluate the following arthmetic expression into three-address, two-address, one adts
address instruction format. X = (4+B)*C
See Topic: INSTRUCTION SET, Short Answer Type Question No. 1.

6. a) Explain the difference between full associative and direct mapped cache memoy ma
nappng
approaches.
b) What are "write back' and "write through" policies in cache?
a) See Topic: MEMORY ORGANIZATION, Long Answer Type Question No. 1(b).
b) See Topic: MEMORY ORGANIZATION, Long Answer Type Question No. 1(a).

Group-C
(Long Answer Type Questions)
7. a) Suppose register A holds the 8-bit number 11011101.
Determine the sequence of binary
values in A after an arithmetic shift-right, followed by a circular shift-right
and followed by a logica
shift-left. 3
b) Describe Booth's multiplication method and use this to multiply
decimal numbers -23 and 9.
c) Suppose we are given RAM chips each of
size 256 4. Design a 2K x 8 RAM system using ths
x
chip as the building block. Draw a net logic diagram
of your implementation.
a) &b) See Topic: COMPUTER ARITHMATIC, Long
Answer Type Question No. 9.
c) See Topic: MEMORY ORGANIZATION,
Short Answer Type Question
No. 8.

8. a) For Booth's algorithm, when do worst

case and best case occur? Explain with example
b) What are the advantages of Interrupt l/O over
programmed l/0?
c) Discuss the concept of associative
memory unit using suitable example.
a) See Topic: COMPUTER ARITHMATIC,
Short Answer Type Question No. 12.
b) See Topic: INPU'T-OUTPUT ORGANIZATION,
Short Answer Type Question No. 6.
c) See Topic: MEMORY ORGANIZATION,
Long Answer Type Question
No.2.
9. a) Write a program to
evaluate the arithmetic statement Y =
(A-B+C)/(G+H):
) Using an accumulator type computer with
one address instruction.

CO-148
 COMPUTER ORGANISATION

-#ack Organizedcomputer with zero-address

usingn Neumann bottleneck? How can this instructions.
Wha omputer has a memory unit of be reduced?
digital 64Kx 16 and
and a cache memory of 1K words.
The cache
Adirect mapping with a block SIze of 4 words. How
many bits are there in the tag, index, block
Uses fields address
of the ado format. Also calculate
and
words
assoCiativ mapping address format for associative mapping and
vay set
for
4 INSTRUCTION SET, Long Answer
:
Type Question No. 3.
See INTRODUCTION, Long Answer Type
Question No. 1.
hSec
Topic:
: MEMOR ORGANIZATION,
MEAIORY Long Answer Type Question. No. 13(a).
See
c)
ifferentiate between hardwired control and micro programmed control. Draw the block
basic hardwired control organization O
10. 3f oraanizetia
diagram of a basic with two decoders, a sequence counter and a
control logic gates
number of
digital has a common
ital computer has bus system for 16 registers of 32 bits each. The bus IS
b) A
constructed with multiplexers?
How many selection inputs are there in each multiplexer?
(HOw many multiplexers are there in the bus?

( Explain
in thei
the basic DMA operations for transfer of data between memory and peripherals
c) Topic: CONTRO UNIT, Long Answer Type
See Question No. 3.
a)
See Topic: BUS STRUCTURE, Short Answer Type Question No. 4.
Topic: INPUT-OUTPUT ORGANIZATION, Long Answer Type Questipn No. 3(b).
Se
Explain different hazards in pipelining.
11. a)
H What are vector interrupts? How are they used in implementing hardware interrupts?
c)What is speedup, througnput and efficiency of a pipelined architecture?
Se Topic: INPUT-OUTPUT ORGANIZATION, Long Answer Type Question No.6.

QUESTION 2016
Group-A
(Multiple Choice Type Questions)
1. Choose the correct alternatives for the
following
RAM) when
) RAM is called DRAM (Dynamic
a) it is always moving around data
b) is requires periodic refreshing
d) none of these
) it can do several things simultaneously

i) Floating point representation is used to store

b) Whole numbers
a) Boolean values
d) Integers
c)Real
4 data pins. t has the *****" * number of
has 12 address pins and
***

given memory chip

A
locations.
d) 2
a) 2 b) 22 2

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POPULAR PUBLICATIONS

program instructions must be transferred from memon.

v) order to execute a
In
at most one 8 bit byte can be transferred at
CPU If the bus has 8 data lines,
case to transfer a 32 bit instruction t time.
a
memory accesses would be needed in this from memOry
CPU? t0th
b)2 c) 3
a) 1
d)4
many
yA computer's memory is composed of 8K words of 32 bits each. How many bits
bts are
if the smallest addressable memory unit is a word? required
memory address
a) 13 b)8 10 d)6
vi)Cache memory refersto
a) cheap memory that can be plugged into the mother board to expand main
memon
1ory
b) fast memory present on the processor chip that used to store recently acCesee
is

aa reserved
special
portion main memory used to save important data
memory on
of
d) area of the chip that is used to save frequently used data

vil) SIMD represents an organization that

a) refers to a computer system capable of processing several programs
at the same tima
b) represents organization of single computer containing a
control unit, processor unit
memony unit and a

c)
includes many processing units under the supervision of a common
control unit
d) none of these

vii) The circuit used to store one bit of data known

is as
a) Register Encoder
b) c) Decoder
d) Flip-flop

i) (2FAOC)16
a) (195084)10
b) (00101111101000001100)2
c) Both (a) and (b)
d) None of these

x) The addressing mode used in an instruction

of the form ADD X Y is
a) absolute b) indirect
c
index d) none of thee
xi) Write Through technique is used in which
memory for updating the data?
a) Virtual memory
b) Main memory
c) Auxiliary memory
d) Cache memory
xii) A stack-organised
computer uses instruction of
a) Indirect addressing
b) Two addressing
c) Zero addressing
d) Index addressing

Group-B
(Short Answer Type Questions)
2. Explain indirect address
mode. How is the effective
See Topic: INSTRUCTION address calculated in this case
SET, Short Answer Type
Question No. 7.

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 COMPUTER ORGANISATION

Combinational
comb
Design a
COM
na 4-bit circuit decrementer
PIITER ARITHMATIC, using four full adders.
3 Topic: Long Answer Type
See Question No. 4{D)
computer has common
digital computer has a bus system for i
muitiplexers 16 registers of 32 bits eacn. The bus
ructed with
selectio
ction inputs are there in
How many each multiplexer?
Ho many multiplexers are there in the bus?
i) 21S STRUCTURI
STRUCTURE, Short Answer
Topic: BUS Type Question No. 4.
See

Write a programi o evaluate the arithmetic statement

Y=(4-B +C)/{G + H)-
nulator type computer with
using an accumula one address instruction.
Using a stackorganized computer with zero-address
instuction.
NSTRUCTION
opic: I SEt, Long Answer Type Question
No.3.
ee

how to impiement a full adder,

howt by using half adders.
6.Show
aw
cOMPUTER ARITHMATIC, Short Answer Type
Question No. 14.

Group-C
(Long Answer Type Questions)
1.a) A computer uses a memory unit with 256 Kwords of 32 bits each: A binary instruction code is
rad in one word of memory. Ihe instruction has four parts: an indirect bit, an operatiorn code, a
register code part to specity one of 64 registers, and an address part
0 How many bits are there in the operation code, the register code part, and the address
part?
Draw the instruction word format and indicate the number of bits in each part
) How many bits are there in the data and address inputs of the memory?
b) Use restoring method to divide 10100011
by 1011.

c Suppose we are given RAM chips each of size 256x4. Design a 2Kx8 RAM system using this
chip as he building block. Draw a net logic diagram of your implementation.

a) See Topic: INSTRUCTION SET, Short Answer Type

Question No. 6.
b) See Topic: COMPUTER ARITHMATIC, Short Answer Type
Question No. 13.
e) See Topic: MEMORY ORGANIZATION, Short Answer
Type Question No. 8.

8. For Booth's algorithm, when do worst case and best

a) case occur? Explain with example.
D)
What are the advantages of Interrupt I/0 over Programmed l/0?
memory including the read and
c Draw the logic diagram of the cell of one word in associative
wrte logic.
Type Question No. 12.
3) See Topie: COMPUTER ARITHMATIC, Short Answer
Answer Type Question No. 6.
9) See Topic: INPUT-OUTPUT ORGANIZATION, Short 16.
Type Question No.
) See Topic: 1EMORY ORGANIZATION, Long Answer

in a basic computer.
Explain the various phases of instruction cycle
) What is Von Neumann bottleneck? How can this be
reduced

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c) A two-way set associative cache memory uses blocks of four

words
accommodate a total of 2048 words from the main memony. The main memony s Thecache
.
How many bits are there in the tag, index block and word fields ofthe are 1286
the address
i)What is the size of the cache memory? forman
a) See Topic: CONTROL UNIT, Long Answer Type Question No. 2.
b) See Topic: INTRODUCTION, Long Answer Type Question No. 1.
c) See Topic: MEMORY ORGANIZATION, Long Answer Type Question No. 17.

10. a) Differentiate between hardwared control and micro-programmed control D

of a Draw
diagram basic hardwared control organization with two decoders, a sequenco the
he
number of control logic gates. cOunter dos
anda
b) A hierarchical Three-Level Memory (Cache, Main memory, Hard Disc)
system has
specifications: tha fokowing
s..

i)Cache Memory Access Time is 10nsec

i) Disc Access Time is 150nsec
i) Hit ratio of Cache Memory is 0.97
iv) Hit ratio of Main Memory is 0.9
What should be the Main Memory access time to achieve an
overall access time oi 20nse
c)Explain the basic DMA operations for transfer of data between memory
and peripherals
a) See Topic: CONTROIL UNIT, Long Answer Type Question No. 3.
b) See Topic: MEMORY ORGANIZATION, Long
Answer fype Question No. 17.
c)See Topic: INPUT-OUTPUT ORGANIZATION, Long Answer
Type Question No. 3.b).

11. a) What are the hazards of instruction pipelining? How are these taken care
of?
b) Explain the Strobe Control method of Asynchronous
data transfer. What are the disadvantages
of this method?
c) What do you understand by the term Program
Interrupt ? Explain with the help of suitable
diagrams.
See Topic: INPUT-OUTPUT ORGANIZATION, Long
Answer Type Question No. 7.

QUESTION 2017

Group-A
(Multiple Choice 'Type Questions)
1. Choose the correct alternatives
for any ten of the following:
)The main purpose for using single Bus structure is
a) Fast data transfer
b) Cost effective connectivity
and speed
c) Cost effective connectivity and ease of attaching
peripheral devices
d) none of these

i) The ALU makes use of .

****
to store the intermediate results.
a) Accumulators b) Resisters c) Heap d) Stack

CO-152
 . Sgenera
aenerally used to increase the
. Secondary memoy
a)
c)
Harddisk
b) Virtual memory
d) Disks
COMPUTER ORGANISATION

apparent size of physical memory.

av between two successive initiations

delaj
time of memory operation is
Thea)Memory access time b) Memory search timne
cycle time
Memor d) Instruction delay
c)
main
advantage of multiple bus organisation over single bus is
The Reduction iin the number of cycles for execution
a) registers
Increase in size of the
b) connectivity
c)Better
d)
none of these

When perfor
Derforming a looping operation, the instruction gets stored in the
v Registers b) Cache c) System heap d) System stack
a)

vi) In se of Zero-address instruction method the operands are stored in

case
b) Accumulators c) Stack d) Cache
a) Registers

addressing mode(s), wnich uses the PC instead of a general purpose register is

a The
a) Indexed
with offset b) Relative
d) Both (a) and (b)
c) Direct

of
MIn a normal n-bit adder, to find out if arn overflow has occurred, we make use
b) NAND gate c) NOR gate d) XOR gate
a) AND gate

A 24 bit address generates an address space of

.. ocations
b) 4096 c) 248 d) 16,777,216
a) 1024

by CPU we use
To get the physical address from the logical address generated
c) Overlays d) TLB
a) MAR b) MMU

and memory we use

x) During transfer of data between the processor
c) buffers d) Registers
a) Cache b) TLB

)The return address of the b-routine is pointed to by

d) Special memory registers
a) IR b) PC c) MAR

B
Group-
Questions)
(Short Answer Type representation.
standard format for floating point number
henyexplain the IEEE 754 IEEE single preciSIon format.
the decimal value (-7.5) in
esent COMPUTER ARITHMETIC, Short Answer Type
Question No. 4(a).
hsopie:
bj See Short Answer Type Question No.
16.
COMPUTER ARITHMETIC,
C
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a memony of size 2048x4 bits

3 Two 10244 bits RAM chips are given. Design
See Topic: NMEMORY ORGANIZATION, Short Answer Type Question No. 10,.

4 What is the difference between carry look ahead adder and ripple carry adder? Explain
of operating system ina computer system. heroe
" Part: See Topic: COMPUTER ARITHMETIC, Short Auswer Type Question No. Is
2 dpart: Se Topic: INTRODUCTION, Short Answer Type Question No. 3.

5. Explain Pipelining and Hazards. Define latency time of a memory.

1"part: See 1Topie: INPU'T-OUTPUT ORGANZATION, Short Answer Type QuestionNo.
N.
2 d part: See Topic: MEMORY ORGANIZATION, Short Answer Type Question No. I.
1.
6. a) What are the advantages of associative mapping over direct mapping?
b) Consider a series of address references given: 2, 3, 11, 16, 21, 13,64 and 48. Assumi
erence in
mapped cache with 8 one-word blocks that ís nitially empty, label each reference in the dre
the list as
or a miss and show the final contents of the cache. att
See Topic: MEMORY ORGANIZATION, Short Answer Type Question No. 12.

Group-C
(Long Answer Type Questions)
7. a) Present the Booth's algorithm for multiplication of signed 2s complement number in a flow
a
chart and explain.
b) Multiply(-12) and (+6), using Booth's mutiplication algorithm.
c) Divide(-15) by (-3) using Restoring & Non-restoring Division algorithm.
a) Sce Topic: COMPUTER ARITLMETIC, Long Answer Type Question No. 1.
b) See Topic: COMPUTER ARITHMETIC, Short Answer Type Question No. 7.
c) See Topic: COMPUTER ARITHMETIC, Long Answer Type Question No. 10.

8. Discuss in detailthe various factors that need to be considered while designing the ISA
fa
processor. Compare and contrast of RISC and CISC architecture.
1" part: See Topic: INSTRUCTION SET, Long Answer Type Question No. 4.
2d part: See Topic: INSTRUCTION SET, Short Answer Type Question No. 3.

9. Explain in detail the Bus Arbitration techniques in DMA

See Topic: INPUT-OUTPUT ORGANIZATION, Long Answer Type Question No. 3(b).

10. a) Can ROM be also a RAM? Justífy your answer.

b) What is speed up? Prove that maximum speed up will beeK.
c) A disk pack has 20 surfaces. Storage area on each surface has an inner diameter of 22cm a
outer diameter of 33cm. Maximum storage density on each track is 2000 bits/cm and maxm
spacing between tracks is 0.25mm.
) What is the storage capacity of the pack?
i) What is the data transfer rate in bytes per second at a rotational speed of 7200r.p.m.
d) What is the necessity of guard bits?
a) See Topiec: MEMORY ORGANIZATION, Long Answer Type Question No. 8(a).
b) See Topic: INPUT-OUTPUT ORGANIZATION, Long Answer Type Question No.8.

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 COMPUTER ORGANISATION

MEMORY ORGANIZATION, Long Answer

Topi Type Question No. 14(b).
See Topic: OMPUTER ARITHMETIC, Short Answer Type
) C Question No. 3.
See
d)
advantages of relative addressing mode over direct addressing mode?
adva
What are the
and contrast Memory mapped l/O and /O mapped l/O.

See
b)See
To
.
Con re importance.of a common
b)Explain the
c)
systembus?
.INSTRUCTION

e)1pa.t: See
2
part: See
Topic:
Topic
BUS
IS STRUCTURE,
bus system in a computer. Why l/O bus is different from a

SET, Short Answer Type Question No.

INPUT-OUTPUT ORGANIZATION, Long Answer
STRUCTURE, Short
Short
Answer
Answer
4.
Type Question No. 4.
Type Question No. 1(b).
Type Question No. 5.

Write short notes

on any three of the following:
12.
a)
Addressing modes
b) Static and dynamic memory

c)
Instruction pipelining
Concept of programmed /O
d)
e) Bus organization
using tri-state
NSTRUCTION
Topic: INST SET, Long Answer.Type Question No. 5(a).
a) See Topic:
See MEMORY ORGANIZATiON, Long Answer Type Question No. 20(d).
b)S
e) See
Topic: PUT-OUTPUT ORGANIZATION,Long Answer Type Question No. 9(d).
See Topic: INPUT-OUTPUT ORGANIZATION, Long Answer Type Question No. 9(e).
el See Topic:
BUS STRUCTURE, Long Answer Type Question No. 2.

QUESTION 2018
Group-A
(Multiple Choice Type Questions)
1.Choose the correct alternatives of the
foliowing:

The principle of locality justifies the use of

a) Interrupt b) Polling c) DMA d) Cache memory

i) Instruction cycle is
b) fetch-execution-decode
a) fetch-decode-execution
c) decode-fetch-execution d) decode-execution-fetch

x 1 bit) are required to build 1M Memory?

m) How many RAM chips of size (256K
a) 24 b) 10 c) 32 d)8

Maximum value on n bit 2's complement numberis

a) 2 b) 2" -1 c) 21 d) Cannot be said

) Micro instructions are kept in

a) Main memory b) Control memory c) Cache memory d) Secondary storage

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propagation delay for n-bit CLA is

vi) The maximum c) 6*A
a) A
b) An d) n

disk pack is
vi) The cylinder in a
all tracks in a surface
a) collection of surfaces of disks
logical view of same radius tracks on different
b)
collection of all sectors a
in track
c)
d) collection of all
disks in the pack

which of the following multplier numbers in Booth s algorithm maximum

m no. of
vi) For additio
and subtractions are required?
01001111
a) b) 01111000 c) 00001111 d)01010101

ix) How many memory locations can be addressed by a 32-bit computer?

a) 64 KB b) 32 KB c) 4 GB d) 4 MB

x) The addressing mode of an instruction is resolved by

a) ALU b) DMA controller c) CU d) program

Group-B
(Short Answer Type Questions)
2. Multiply decimal number (-17) and (-9) using Booth's muitiplication method with step
y step
explanation.
See Topie: COMPUTER ARITHMETIC, Short Answer Type Question No. 17.

3. Explain stack based CPU.

See Topic: MEMORY ORGANIZATION, Short Answer Type Question No. 6.

4. What is the limitations of direct-mapped cache? Explain with

an example, how it can be
improved into set-associative cache?
See Topic: MEMORY ORGANIZATION, Short
Answer Type Question No. 13.

5. Define speedup, efficiency and throughput of

a pipelined processor Design a 400
Combinational circuit decrementer using four full
adders.
" Part: See Topic: INPUT-OUTPUT ORGANIZATION,
Long Answer Type Question No. 6{¢%
2d Part: See Topic: COMPUTER ARITHMETIC,
Long Answer Type Question No. 4(b)

6. Explain with example: Register

Direct, Register Indirect
See Topic: 1NSTRUCTION SET, and Base register addressing mou
Short Answer Type Question No.
8.

Group-C
(Long Answer Type Questions)
7. a) Explain the basic
block diagram of interface
circuits with them?
Computer System. Why do peripheras ned

Part: Se Topie: INTRODUCTION, Long Answer

2nd Part: See Topic: INPUT-OUTPUT Type Question No. 2.
ORGANIZATION, Long 5.
Answer Type Question
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 COMPUTERORGANISATION

set-associative
tive cache consists of a total
DIOCk of 64 blocks divided into 4 blocks sets. The
contains 4096 blocks, each consisting
) A men
nemory of 128 words.
man many bits are there in a main memory address?
oW many bits are there in each of the TAG, SET and
Word fields?
How STRUCTURE, Short Answer Type
i) BUS Question No. 5.
opic
See
write through and write back' policies in cache memory?
Whatare ORGANIZATIO
ORGANIZATION, Long Answer Type Question No. 1(a).
c) Topic:MEMORY
See

Eva ate the

arithmetic statement X=(A*B)/(C+D) in one, two and three addreSS
3)
8machines.
ont the decima precision floating point format. Explain
in
Represent the decimal value 7.5
in lEEE-754 single
b) ferent memory access methods.
differe
bniefabout
Explain ruction Cyclewith suitable flow chart.
) Topic: INSTRUO CTION SET, Long Answer Type Question No. 2.
See Type Question No. 16.
See Topic: OMPUTER ARITHMETIC, Short Answer
Db)
Part: Topic: COMPUTER ARITHMETIC, Short Answer Type Question No. 18.
See
Answer Type Question No.2.
Coe Topic: CONTROL UNIT, Long
See
)
Diagram for this CPU
CPU has 16 bit addres bus and 8 bit data bus draw the connection
l lf a 512x8.ROM:
RAM and one including logical,
with four 256x8
ALU capable of performing 14 different micro operations
A Desian a 4-bit
operations. memory access
arithmetic and shiftüng non-vectored interrupt? Average
between vectored and
cWhat is the difference
on which factors?
time depends No. 10(a).
MEMORY ORGANIZATION, Long Answer Type Question
a) See Topic: Question No. 8.
COMPUTER ARITHMETIC, Long Answer Type No. 3(2nd
b) See Topic: ORGANIZATION, Short Answer Type Question
INPUT-OUTPUT
1 Part: See Topic:
Question No. 14.
Part). ORGANIZATiON, Short Answer Type
Part: See Topic: MEMORY
memory-hierarchy. your answer.
10. a) Explain
a Random Access Memory? Justify
Memory be also example.
b Can a Read Only memony unit using suitable
of associative
) Discuss the concept memory. 19(a) & (b)
d) Define "latency time" in a Type Question No.
ORGANIZATION, Long Answer No. 2.
)& b} See Topic: MEMORY ORGANIZATION, Long Answer Type Question
Question,No. 11.
See Topic: MEMORY ORGANIZATION, Short Answer Type
See Topie:
MEMORY
0
of the folloWing
1. Write short notes on any three
a) Instruction Format
b) Carry Look-ahead Adder
c)Design of 4-bit ALU
d) RISC
Representation
e Overflow in Fixed-point
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Type Question No. 5(c).

INSTRUCTION SET, Long Answer
a) See Topic: ARITHMETIC, Long Answer 1ype Question No. 12d)
COMPUTER
b) See Topic:
COMPUTER ARITHMETIC, Long Answer Type Question No. 2(e).
c)See Topic: Type Question No. 5(d).
INSTRUCTION SET, Long Answer
d) Sce Topic: Answer Type Question No. 12/0
Topic: COMPUTER ARITHMETIC, Long
e) See

QUESTION 2019

Group- A
(Multiple Choice Type Questions)
following
1
Choose the correct alternatives for any ten of the
uSually in
) A source program is
b) Machine level language
a) Assembly language
d) Natural language
c) High-level language

i) In straight binary code, N-bits or N binary digits can represent.. different values

a) 2N b) 2(N+1) c) 2 (N-1) d) 2N-1

i) Maximum n bits 2's complement number is

a) 2'n b) 2n-1 c) 2(n-1)1 d) Cannot be
sad

iv) The addressing mode, where you directly specífy the operand value is
a) Immediate b) Direct c) Definite d) Relative

v) How is the effective address of base-register calculated?

a) By adition of base register contents to the partial address in instruction
b) By addition of implied register contents to the partial address in instruction
c) By addition of base register contents to the complete address in instruction
d) By addition of implied register contents to the complete address in instruction

vi) The instruction, Add R1, 45 does

a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c)Finds the memory location 45 and adds that content to that of R1
d) None of these

vii) A 24 bit address generates an address space of

*****ssesnar 1Ocations.
a) 1024 16,777,216
b) 4096 C) 2* d)
Vin) What could be the maximum size of on chip cache memory ssor?
for an n-address bit proce
a) 0 manufacture
b)2" c)infinite d) decided by

ix) To get the physical address from the logical

address generated by CPU we use
a) MAR b) MMU d) TLB
c) Overlays

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 COMPUTER ORGANISATION

usaa
for the usage of a hardware device is called
contention
sian

The structural hazard b) stalk

c) deadlock d) none of these
N
/a)
of time
ods of
penOds
time when the unit is idle is called as
)TheStalls b) Bubbles Both (a) & (b)
C) Hazards d)
transfer is initiated by
DMA
The
i) Processor b) The process being executed
a) devices ) OS
c) /O
Group-B
(Short Answer Type Questions)
cana full adder be implemented using half adders? Explain with proper circuit diagram.
a fui
How ncOMPUTER
2 ARITHMETIC, Short Answer Type Question No. 13.
Topic
See

different kinds of data hazards in pipelining with suitable examples.

nlain the
3SeenicTopic INPUT-OUTPUT ORGANIZATION, Short Answer Type Question No. 11.

754 format for floating point representation of numbers.

riefly explain IEEE
Riefly
resent the decimal value-12.5 in lEEE single precision format.
S Topic:CoMPUTER ARITHMETIC, Short Answer Type Question No. 4(a).
Topic: cOMPUTER ARITIHMETIC, Short Answer Type Question No. 19.
of 100ns
5 lal lf a direct mapped cache has a hit rate of 95%, a hit time of 4ns, and a miss penalty
what is average memory access time?
the
with a hit time of 20ns and a hit rate of 50%, what is the new average
(b) If an L2 cache is added

memory access time?

See Topic MEMORY
ORGANIZATION, Short Answer Type Question No. 15.

Group C
(Long Answer Type Questions)
6. Write short notes on the following:
a) Resorting Division Algorithm
b) Direct Memory Access
c) double precision format
JEEE
a) See Topic: COMPUTER ARITHMETIC, Long Answer
Type Question No. 12(g).
by See
Topie: INPUT-OUTPUT ORGANIZATION, Long
Answer Type Question No. 9().
J See Topie: COMPUTER ARITHMETIC, Long Answer
Type Question No. 12(h).

direct mapping technique.

Explain the difference between full associative inand
0 Explain the write back and write through policies cache
= bytes. 32 bit address is provided.
memory has 2K blocks. Block size is of 4 words 16
TTE
Ihe machine
is byte addressable.
the bit length for each field in Direct Mapping?
Is the bit length for each field in 2-way set associative
mapping?
i) WIS associative mapping?
the bit length for each field in 4-way set
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a) See Topic: MEMORY ORGANIZATION, Long Answer Tlype Question No. 1(hic .1b)
b) See Topic: MEMORY ORGANIZATION, Long Answer Type Question No. 1(al
(" Part)
ary
16.
c) See Topic MEMORY ORGANIZATiON, Short Answer Type Question No.

8. a) What is the difference between isolated l/O and memory mapped /0?
b) Explain Cache Coherence
c)Explain the different hazards in pipelining
a) Sce Topic: INPUT-OUTPUT ORGANIZATION, Long Answer Type Question No. 4
b) See Topic: INPUT-OUTPUT ORGANIZATION, Short Answer Type Question No. 12
e) See Topic: INPUT-OUTPUT ORGANIZATION, Short Answer TypeQuestion No.1.

9 a) What are the different addressing modes?

b) Explain with suitable examples of each of themodes
c)Evaluate the following arithmetic expression into () three address, (i) two addresses
address and (iv) zero addressinstructionformat X= (A+B)* (C+D). (Oh
a)&b) See Topic: INSTRUCTION SET, Long Answer Type Question No. 1.
c) See Topic: INSTRUCTION SET, Short Answer Type Question No. 9.

10. a) What are the differences between RISC and CISC?

b) Divided 43 by 11 using Non-restoring algorithm (The tracing table must be shown clear
c)What is meant by overflow and underflow in signed magnitude representation of numbers?
a) See Topic: INSTRUCTION SET, Short Answer Type Question No. 3.
b)& e) See Topic: COMPUTER ARITHMETIC, Long Answer Type Question No. 11(a) & (bj.