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ECE3002 Assignment2

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Sidharth Gupta
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28 views

ECE3002 Assignment2

Uploaded by

Sidharth Gupta
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 2

Consider four designs of a 6-input AND gate shown in Fig. 1. Develop an expression for the delay of
each path if the path electrical effort is H. What design is fastest for H = 1? For H = 5? For H = 20?
Explain your conclusions intuitively.

1.

Fig. 1
Consider the two designs of a 2-input AND gate shown in Fig. 2. Give an intuitive argument about
which will be faster. Back up your argument with a calculation of the path effort, delay, and input
capacitances x and y to achieve this delay.

2.

Fig. 2
Consider the path from A to B involving three two-input nand gates shown in Fig. 3. The input
capacitance of the first gate is C, and the load capacitance is also C.
(a) What is the least delay of this path, and how should the transistors be sized to achieve least delay?
(b) Find the least delay achievable along the path from A to B when the output capacitance is 8C.

3.

Fig. 3
Size the circuit in Fig. 4 for minimum delay. Suppose the load is 20 microns of gate capacitance and
that the inverter has 10 microns of gate capacitance.

4.

Fig. 4
Size the circuit properly in Fig. 5 to obtain the least delay along the path from A to B when the
electrical effort of the path is 4.5.

5.

Draw the transistor level static CMOS logic circuits that realize the boolean functions listed below:

6.

Use Euler’s path for optimum gate ordering of logic circuits and draw the stick diagrams for the circuits
implemented. Draw the layout of the circuits and mark the dimensions in terms of lambda

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