Arka Educational & Caltral Trast (Reed) Jain Institute of Technology, Davangere Department of Computer Science & Engineering Academic year 2023-24 (odd Semester) Assignment on module 1 . Subject: Digital Design and Computer Organization Sub Code : BCS302 List the postulates and theorems of Boolean algebra‘ por . Prove the following by using the basic identities. a, X#XSX b.X.X=X ¢.XH=1 d.X+XY=K 3, State and prove De Morgan's theorem for two variables using truth table. 4, Simplify, the following Boolean functions to minimal number of literals” and implement the simplified expressions. Yea. xyztx’yexyz? (x+y)’ (ty) a'c'xaber ac’ abc'd + a’bd + abed (wy’+2)' 42+ xy +w2 eaors Find the complement of F= WX+YZ then show that F.F” =0 and FHF” =1. 6. Find the compiement of the following expressions and implement the same. a xyexy — b.ztz'(vwixy) 7. For the Boolean function, F= xyz + x’y'z + w'xy + wx'y + wx Obtain the truth table of F. Draw the logic diagram using original expression. ‘Use k-map to simplify the F. Draw the logic diagram for the simplified expression. pe oP 8. Simplify the following boolean functions using the k maps & implement the same. [Note: Have to write the essential prime implicants table.) FOxy.t)= 5 (2.36.7) F(AB,CD)= 5 (4, 6.7.15) F(xy.2)=¥ (0.1,5,7) F(wxy.z)= 5 (1,3,4,5,6,7,9,11,13,15) pose ic! + b’ed? + a’bed + ab'c’ and draw the 9. Simplify the'following using K-map F= logic circuit. 10. Simplify the foliowing using K-map F (x,y,z) = Z (1.2,3.4,5,7) draw the NAND- NAND circuit and NOR-NOR circuit. . FACULTY HOD«Ata Educational & Cultura Trust (Regd) Jain Institute of Technology, Davangere Department of Computer Science & Engineering Academic year 2023-24 (odd Semester) Assignment on module 2 Subject: Digital Design and Computer Organization Sub Code : BCS302 1. Design and explain combination of circuit for BCD to access 3 code. 2. Design and explain combinational circuit of Half Adder. 3. Design and explain combinational circuit of Full Adder. 4, Design and explain carry look ahead generator 5. Design and explain four bit adder- subtractor. Explain thiee t6 éight lle Decoder. 7. Explain 2 to 4 line Decoder with enable input. 8. Explain 4 X 16 Decoder using two 3 x8 decoder. . 9. . Implement the following using decoder a) Full adder using decoder b) =Y (0,1,8) F2=E (2,3,10) F3=Y (6,7,15) 10. Explain priority encoder. 11. Define multiplexer explain 4 to 1 line multiplexer 12. With neat diagram explain D, T, SR and JK flip flops also derive the characteristic equation of all the flip flops 13. Write the verilog code of the following 2) 2to4 line decoder )4 bit ripple carry adder ¢) priority encoder 4) D SR &IK flip flop 14, Write the verilog code for 4:1 mux using data flow model and conditional statements FACULTY a«___ ARKA Educational & Cultura Trust Regd) Jain Institute of Technology, Davangere Department of Computer Science & Engineering Academic year 2023-24 (odd Semester) Assignment on module 3 Subject: Digital Design and Computer Organization Sub Code : BCS302 1, With a neat diagram explain basic functional units of computer. 2. With a neat diagram explain basic operational concepts of computer or Explain connection between processor and memory. 3. Write a note on I)byte addressability, 2)Big Fndian 3)Little Endian assignment 4, Write the bast’ pérfornidide equation, Explain the role of each of the parameters in the equation on the performance of the computer. Also describe SPEC rating. 5,, What is an addressing mode Explain different generic addressing modes with an example for each. 6. Explain Bus structure with diagram. 7. With example explain basic instruction types.(one address instruction, two address instruction, three address instruction). 8. Writea instructions to solve the equation E=(A+B) * (C+D) Using one address, two address and three address instructions. a adare FACULTY HOD on, dareea ane ___ ARKA Eduction &Cutart Ts Ree) Jain Institute of Technology, Davangere Department of Computer Science & Engineering Academic year 2023-24 (odd Semester) Assignment on module 4 ‘Subject: Digital Design and Computer Organization Sub Code : BCS302 . Explain the concept of accessing of input output devices in detail. Define Interrupt? With example illustrate the concept of interrupts and enabling and disabling of interrupts. With neat sketches, explain various methods for handling multiple interrupt requests 1)Polling 2) Interrupt nesting 3) Daisy chain 4) vectored interrupt _5)simultaneous request Define Exceptions. Explain two kinds of Exceptions. What is DMA? Explain the registers in DMA and Working of DMA with neat figure. What is bus Arbitration? With neat diagram, explain centralized and distribution arbitration method Show with diagram the memory Hierarchy with respect to Speed, Size and Cost. ‘What is a Cache? Explain the different Cache Mapping functions with neat sketches. (Direct mapping, Associative mapping and set associative mapping) FACULTY op‘Arka Educational & Cultural Trust (ttegd,) - Jain Institute of Technology, Davangere Department of Computer Science & Engince Academic year 2023-24 (odd Semester) Assignment on module 5 Subject: Digital Design and Computer Organization Sub Code + BCS302 1. Explain with neat figure single bus organization of the processor unit and register transfer, 2. Write and explain the control sequences for execution of following instruction 1) MOVE R2,R1) 2) Add (R3),R1_ 3) Add R1, R2, R3 3. Explain with neat figuie the' register transfer in processor. 4, Explain the steps involved in Fetching Instruction from memory with Timing Signals. 5. Write the control sequence for an unconditional branch instruction. 6. Explain the basic operation of pipelining processing, Also explain the 4 stage pipelining concept. 7. Explain the role of cache memory in pipelining. 8. Explain pipelining performance. FACULTY Hop