®

ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

BENEFITS and FEATURES GENERAL DESCRIPTION

• Wide input voltage range The ACT88430 PMIC is an integrated ActivePMU™
• Vin = 2.7V to 5.5V power management unit. It is designed to power a wide
range of processors, including video processors,
• Complete integrated power solution FPGA’s, peripherals, microcontrollers, and solid-state
• One 4A DC/DC Step-Down (Buck) Regulator drive applications. It is highly flexible and can be
• Three 2.5A DC/DC Step-Down (Buck) reconfigured via I2C for multiple applications without the
Regulators need for PCB changes. The low external component
• One 800mA LDO count and high configurability significantly speeds time
• Two 200mA LDOs to market. Examples of configurable options include
output voltage, startup time, slew rate, system level
• Space Savings sequencing, switching frequency, sleep modes, operat-
• Fully integrated ing modes etc. ACT88430 is programmed at the factory
• High Fsw =2.25MHz or 1.125MHz with default configuration. These settings can be
• Integrated sequencing optimized for a specific design through the I2C interface.
The ACT88430 comes in several default configuration.
• Easy system level design Contact the factory for specific default configurations.
• Configurable sequencing
The core of the device includes four DC/DC step down
• Seamless sequencing with external supplies
converters using integrated power FETs, three
• Buck 1 Bypass Mode for 3.3V system level low-dropout regulators (LDOs), and an optional load
compliance switch. Each DC/DC regulator switches at 2.25MHz,
requiring only three small components for operation.
• Highly configurable The LDOs only require small ceramic capacitors. All are
• uP interface for status reporting and controllability highly configurable via the I2C interface.
• Programmable Reset and Power Good GPIO’s
• Flexible Sequencing Options The ACT88430 PMIC is available in a 5 x 5 mm 40 pin
QFN package or in a 4.17 x 3.17 mm 48-ball WLCSP
• I2C Interface – 1MHz package.

The ACT88430 can be optimized for many different pro-

APPLICATIONS cessors including, but not limited to the following. The
• Computer Vision ACT88430 has CMI variations specifically designed to
power the following.
• Microcontroller Applications
Processor Processor Application
• Solid-State Drives
Vendor Controller
• FPGA
HiSilicon HI3519 Video
• Video Processor
Silicon Motion SM2258 Solid State Drive
Silicon Motion SM2258H Solid State Drive

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

TYPICAL APPLICATION DIAGRAM

ACT88430 MCU
BUCK1 (4.0A)

BUCK2 (2.5A)

BUCK3 (2.5A)

DC/DC PG BUCK4 (2.5A)

REGULATOR
ENABLE LDO1 (800mA)

LDO2 (200mA)

LDO3 (200mA)

SCL
SDA
nRESET
IRQ

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 ®
ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

FUNCTIONAL BLOCK DIAGRAM

ACT88430
Supply VIN

VIN VIN_B 1
MODE
Supply
VIN
GPIO

IO Supply VIO_IN

FB_B1 Buck1 and 1µH

Vref Bypass SW_B1

PWREN VIO_IN Controller FB_B1 2x22µF

VIO_IN
PGND_B 1
SCK

Digital
VIO_IN
SDA VIO_IN

VIO_IN
IRQ VIN_B2
Supply
VIO_IN

VIO_IN
nRESET_AUX1

nRESET_AUX2
Core FB_B2
1µH
VIO_IN Buck2 SW_B2
nRESET Vref
Controller FB_B2 22µF
VIO_IN
POK
VIO_IN
PG PGND_B2

VIN_B3
EXT_EN VIO_IN Supply
ENABLE
EXT_PG VIO_IN
Power _Good FB_B3
1µH
Buck3 SW_B3
Supply VIN_LDO23 Vref
Controller FB_B3 22µF

Vref PGND_B3
OUT_LDO3

1µF
VIN_B4
Supply

Vref
FB_B4
OUT_LDO2 1µH
Buck4 SW_B4
1µF Vref
Controller FB_B4 22µF

VIN_LDO1
Supply PGND_B4
Vref

OUT_LDO1

1µF

AGND

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

ORDERING INFORMATION
Device ID
PART NUMBER Vin VOUT1 VOUT2 VOUT3 VOUT4 VLDO1 VLDO2 VLDO3 0x7Dh
Package

ACT88430QJ101-T 3.3/5V 0.95V 0.95V 0.95V 1.2V 1.8V 1.8V 2.5V 0x01h 5x5 40 pin

ACT88430QJ102-T 3.3V 0.74V 0.88V 1.8V 1.2V 0.9V 1.2V 2.5V 0x00h 5x5 40 pin

ACT88430QJ105-T 3.3/5V 3.3V 1.5/1.35V 1.8/1.2V 1.2/1.0V 3.3V 1.8V 1.8V 0x05h 5x5 40 pin
4.17x3.17 48
ACT88430VM106-T 3.3V 3.3V 1.15V 1.5V 1.2V 3.3V 1.8V OFF 0x06h
balls
4.17x3.17 48
ACT88430VM109-T 3.3V 2.5V 0.75V 1.5V 1.2V 2.5V 1.8V 2.5V 0x09h
balls
3.0V/ 4.17x3.17 48
ACT88430VM113-T 3.3V 0.9/0.8V 1.2V 1.2V 1.2V 2.5V 1.8V 0x13h
2.5V balls
3.0V/ 4.17x3.17 48
ACT88430VM114-T 3.3V 0.9/0.8V 1.1V 1.2V 1.2V 1.8V 1.8V 0x14h
2.5V balls
4.17x3.17 48
ACT88430VM118-T 3.3V 2.5V 0.8V 0.8V 1.8V/1.2V 1.8V 1.8V 1.8V 0x18h
balls
ACT88430QJ120-T 5V 3.8V 1.35V 1.3V 3.3V 3.3V 3.3V 3.15V 0x20h 5x5 40 pin

ACT88 430 QJxxx-T

Product Number
Package Code
Pin Count
CMI Option
Tape and Reel

Note 1: Standard product options are identified in this table. Contact factory for custom options, minimum order quantity required.
Note 2: All Qorvo components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor
products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
Note 3: Package Code designator. “Q” represents QFN. “V” represents CSP.
Note 4: Pin Count designator. “J” represents 40 pins. “M” represents 48 pins.
Note 5: “xxx” represents the CMI (Code Matrix Index) option The CMI identifies the IC’s default register settings.

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 ®
ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

PIN CONFIGURATION - QFN

VIN_B1
VIN_B1

VIN_B4
SW_B1
SW_B1

SW_B4
FB_B1
TOP VIEW

GPIO
VIN

PG
40
39
38
37
36
35
34
33
32
31
IRQ 1 30 MODE
PGND1 2 ACT88430 29 FB_B4
PGND1 3 28 PGND4
POK 4 27 PGND3
PGND2 5 EXPOSED 26 SW_B3
PAD
SW_B2 6 25 VIN_B3
VIN_B2 7 24 FB_B3
FB_B2 8 23 OUT_LDO3
OUT_LDO1 9 22 VIN_LDO23
VIN_LODO1 10 21 OUT_LDO2
11
12
13
14
15
16
17
18
19
20
SCL

AGND
SDA

EXT_EN
nRESET_AUX2
nRESET_AUX1

PWREN
nRESET

EXT_PG
VIO_IN

QFN
Figure 1: Pin Configuration – Top View – QFN55-40

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 ®
ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

PIN CONFIGURATION - WLCSP

A B C D E F G H
1
2
3
4
5
6
Top View (Bumps Down)
Figure 2: Pin Configuration – Top View – WLCSP-48

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 ®
ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

PIN DESCRIPTIONS
PIN Ball (CSP)
NAME DESCRIPTION
(QFN)
1 C4 IRQ Interrupt IRQ Open Drain Output indicates a fault occurred.

2,3 A1, A2, A3 PGND1 Dedicated Power Ground for BUCK1 Regulator.
C3 Power OK Open Drain Output, indicates Overvoltage or Undervoltage on VIN in-
4 POK
put supply.
5 B3 PGND2 Dedicated Power Ground for Buck 2 Regulator.

6 A4, B4 SW_B2 Switch Pin for BUCK2 Regulator.

7 A5 VIN_B2 Dedicated VIN power input for BUCK2 Regulator.

8 B5 FB_B2 Feedback for BUCK2 Regulator. Connect to the BUCK2 output.

B6 Output for LDO1 Regulator (Leave unconnected if LDO1 is not used and disa-
9 OUT_LDO1
bled).
10 A6 VIN_LDO1 Dedicated VIN power input for LDO1 Regulator.
C5 A configurable auxiliary reset signal. Open Drain Output (configurable as an in-
11 nRESET_AUX2
put).
C6 A configurable auxiliary reset signal. Open Drain Output (configurable as an in-
12 nRESET_AUX1
put).
13 D6 SCL I2C Clock Input.

14 D5 nRESET nRESET Open Drain Output. This pin is configurable.

15 E6 SDA I2C Data Input and Output.

16 D4 AGND Analog Ground.

17 F6 PWREN Power Enable Digital Input. This pin is configurable.

18 E5 EXT_EN External Regulator Enable Push-Pull Digital Output.

19 F5 EXT_PG External Power Good Digital Input. This pin is configurable.

G5 Digital Input Reference Voltage Input. Connect a 0.1uF ceramic capacitor be-
20 VIO_IN
tween VIN_IN and AGND
G6 Output for LDO2 Regulator (Leave unconnected if LDO2 is not used and disa-
21 OUT_LDO2
bled).

22 H5 VIN_LDO23 Dedicated VIN power input for LDO2 and LDO3 Regulator.

H6 Output for LDO3 Regulator (Leave unconnected if LDO3 is not used and disa-
23 OUT_LDO3
bled).

24 G4 FB_B3 Feedback for BUCK3 Regulator. Connect to the BUCK3 output.

25 H4 VIN_B3 Dedicated VIN power input for BUCK3 Regulator.

26 G3, H3 SW_B3 Switch Pin for BUCK3 Regulator.

27 H2 PGND3 Dedicated Power Ground for BUCK3 Regulator.

28 H1 PGND4 Dedicated Power Ground for BUCK4 Regulator.

29 F2 FB_B4 Feedback for BUCK4 Regulator. Connect to the BUCK4 output.

30 F3 MODE Configuration input pin. This pin is read at power up to configure BUCK1.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

31 G1, G2 SW_B4 Switch Pin for BUCK4 Regulator.

32 F1 VIN_B4 Dedicated VIN power input for BUCK4 Regulator.

33 F4 GPIO Configurable General purpose input/open drain output.

34 E4 PG Power Good Output. This pin is configurable. Open Drain Output.

35 E3 FB_B1 Feedback for BUCK1 Regulator. Connect to the BUCK1 output.

36 D3 VIN Analog Input supply monitored by POK thresholds.

37,38 D1, D2, E1, E2 VIN_B1 Dedicated VIN power input for BUCK1 Regulator.

39,40 B1, B2, C1, C2 SW_B1 Switch pin for BUCK1 Regulator.

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 ®
ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE UNIT
All I/O and Power pins except PGND_B1, PGND_B2, PGND_B3, PGND_B4, GND -0.3 to 6 V

Grounds: Any PGND referenced to GND -0.3 to +0.3 V

SW_Bx to PGNDx -0.3 to VIN + 1 V

FB_Bx to PGNDx -0.3 to VIN + 0.3 V

OUT_LDOx to PGNDx -0.3 to VINx + 0.3 V

EXT_PG -0.3 to VIN + 0.3 V

EXT_EN -0.3 to VIO_IN + 0.3 V

SW1 HBM ESD (Note 2) -2 to 1.6 kV

MSL Rating – QFN package MSL3

MSL Rating – WLCSP package MSL1

Junction to Ambient Thermal Resistance, QFN (Note3) 26 °C/W

Operating Junction Temperature -40 to 125 °C

Storage Temperature -55 to 150 °C

Note1: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect
device reliability.
Note2: All other pins meet +/- 2kV HBM ESD
Note3: Measured on Qorvo Evaluation Kit

RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN, VIN_B1, VIN_B2, VIN_B3, VIN_B4, VIN_LDO1, VIN_LDO23 2.7 5.5 V

VIO_IN 1.62 5.5 V

VIN_LDO1 2.4 5.5

VIN_LDO23 1.62 5.5 V

SW_B2, SW_B3, SW_B4 1.6

Average lifetime operating current. QFN. (Note 1) A
SW_B1 3.2

Operating Junction Temperature -40 125 °C

Note1: This temperature range is used for lifetime reliability testing.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

DIGITAL I/O ELECTRICAL CHARACTERISTICS

(VIO_IN = 1.8V, TA = 25°C, unless otherwise specified.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PWREN, EXT_PG Input Low VIO_IN = 1.8V 0.4 V

PWREN, EXT_PG Input High VIO_IN = 1.8V 1.25 V

PWREN, EXT_PG Input Low VIO_IN = 3.3V 1.0 V

PWREN, EXT_PG Input High VIO_IN = 3.3V 2.3 V

POK, IRQ, nRESET, nRESET_AUX1, nRESET_AUX2,

Output = 5V 1 µA
PG_B4 Leakage Current
POK, IRQ, nRESET, nRESET_AUX1, nRESET_AUX2,
IOL = 5mA 0.35 V
PG_B4 Output Low

EXT_EN Output Low IOL = 1mA 0.35 V

VIO_IN
EXT_EN Output High IOH = 1mA V
- 0.35

MODE, GPIO Input Low VVIN = 3.3V 1.0 V

MODE, GPIO Input High VVIN = 3.3V 2.3 V

MODE, GPIO Input Low VVIN = 5.0V 1.5 V

MODE, GPIO Input High VVIN = 5.0V 3.5 V

EXT_PG, MODE Deglitch Time 10 µs

PWREN Deglitch Time 2 µs

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

SYSTEM CONTROL ELECTRICAL CHARACTERISTICS

(VIO_IN = 1.8V, TA = 25°C, unless otherwise specified.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply Inputs Voltage Range:
VIN_B1 referenced to PGND_B1
VIN_B2 referenced to PGND_B2 2.7 5.5 V
VIN_B3 referenced to PGND_B3
VIN_B4 referenced to PGND_B4

VIN_LDO1 referenced to AGND 2.4 5.5 V

VIN_LDO2 referenced to AGND

1.62 5.5 V
VIN_LDO3 referenced to AGND

VIN_LVL=0 2.6 2.7 2.8 V

UVLO Threshold Falling (Note 1) VIN_LVL=1, VIN_FULL_RANGE = 0 3.35 3.5 3.65 V

VIN_LVL=1 VIN_FULL_RANGE = 0 2.6 2.7 2.8 V

VIN_LVL=0 50 100 150 mV

UVLO Hysteresis (Note 1) VIN_LVL=1 VIN_FULL_RANGE = 1 250 300 350 mV

VIN_LVL=1 VIN_FULL_RANGE = 0 50 100 150 mV

VIN_LVL = 0, VIN_FULL_RANGE = 0 3.86 3.98 4.10 V

OV Threshold Rising (Note 1) VIN_LVL = 0 VIN_FULL_RANGE = 1 5.60 5.85 6.00 V

VIN_LVL = 1 5.60 5.85 6.00 V

VIN_LVL = 0, VIN_FULL_RANGE = 0 50 100 150 mV

OV Hysteresis (Note 1) VIN_LVL = 0, VIN_FULL_RANGE = 1 100 150 200 mV

VIN_LVL = 1 100 150 200 mV

Thermal Shutdown Temperature

Temperature rising 150 165 180 °C
TSD_SHUTDWN

Thermal Shutdown Hysteresis 20 °C

start of first regulator output assuming

Startup Delay after initial VIN 335 400 µs
start delay=41usec minimum (Note 2)
Temperature rising - Referenced to TSD_SHUTDWN
Thermal Interrupt Threshold, TSD_ALERT °C
TSD_SHUTDWN - 30

Thermal Interrupt Hysteresis 15 °C

POK_SET=00 (91% of 3.3V) 2.90 3.00 3.10

POK UV Interrupt Threshold Falling - 3.3V POK_SET=01 (88% of 3.3V) 2.80 2.90 3.00 V
Input Setting (VIN_LVL=0) POK_SET=10 (84% of 3.3V) 2.67 2.77 2.87
POK_SET=11 (Disable) N/A N/A N/A
POK_SET=00 (88% of 5V) 4.26 4.40 4.54
POK UV Interrupt Threshold Falling - 5V
POK_SET=01 (86% of 5V) 4.16 4.30 4.44 V
Input Setting (VIN_LVL=1,
POK_SET=10 (84% of 5V) 4.06 4.20 4.34
VIN_FULL_RANGE = 0)
POK_SET=11 (Disable) N/A N/A N/A
POK_SET=00 (91% of 3.3V) 2.90 3.00 3.10
POK UV Interrupt Threshold Falling - 3.3V
POK_SET=01 (88% of 3.3V) 2.80 2.90 3.00
Input Setting (VIN_LVL= 1, V
POK_SET=10 (84% of 3.3V) 2.67 2.77 2.87
VIN_FULL_RANGE = 1)
POK_SET=11 (Disable) N/A N/A N/A

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

POK_SET=00 (110% of 3.3V) 3.53 3.63 3.73

POK OV Interrupt Threshold Rising - 3.3V
POK_SET=01 (112% of 3.3V) 3.6 3.7 3.8 V
Input Setting (VIN_LVL=0,
POK_SET=10 (114% of 3.3V) 3.66 3.76 3.86
VIN_FULL_RANGE = 0)
POK_SET=11 (Disable) N/A N/A N/A
POK_SET=00 (110% of 5V) 5.33 5.50 5.67
POK OV Interrupt Threshold Rising – 5V
POK_SET=01 (112% of 5V) 5.43 5.60 5.77 V
Input Setting (VIN_LVL=0,
POK_SET=10 (114% of 5V) 5.53 5.70 5.87
VIN_FULL_RANGE = 1)
POK_SET=11 (Disable) N/A N/A N/A
POK_SET=00 (110% of 5V) 5.33 5.50 5.67
POK OV Interrupt Threshold Rising - 5V POK_SET=01 (112% of 5V) 5.43 5.60 5.77 V
Input Setting (VIN_LVL=1) POK_SET=10 (114% of 5V) 5.53 5.70 5.87
POK_SET=11 (Disable) N/A N/A N/A

POK Deglitch Time OV or UV 5 µs

Notes:
1. All Under-voltage Lockout, Overvoltage measurements are referenced to the VIN Input and AGND Pins
2. This delay can be affected by programming sequence, soft-start ramps, and startup delays

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

BUCK1 ELECTRICAL CHARACTERISTICS, REGULATOR:

(VIN_B1 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 2.7 5.5 V

Configured for 9.375mV steps 0.6 3.0

Output Voltage Range V
Configured for 12.5mV steps 0.8 4.0

Maximum Output Current 4 A

Low Power Mode Enabled
Supply Current, Standby 50 µA
Regulator Only, No Load (VOUT = VSET*1.05)
Supply Current, Shutdown Regulator Disabled 0.1 1 µA

Output Voltage Accuracy – PWM Default output voltage, IOUT = 2A -1% VNOM 1% V
Default output voltage, IOUT = 1mA,
Output Voltage Accuracy - PFM -1% VNOM 1% V
Average Ripple Voltage
Default output voltage, VIN_B1 = 3.3V to 5.5V,
Line Regulation 0.02 %/V
PWM mode
Load Regulation Default output voltage, PWM Mode 0.04 %/A

Power Good Threshold VOUT_B1 Rising 92 93 94 %V NOM

Power Good Hysteresis VOUT_B1 Falling 3 %V NOM

Overvoltage Fault Threshold VOUT_B1 Rising 107.5 110 112.5 %V NOM

Overvoltage Fault Hysteresis VOUT_B1 Falling 3 %V NOM

2.15 2.25 2.36

Switching Frequency VOUT_B1 ≥ 20% of VNOM MHz
1.075 1.125 1.18

Soft-Start Period – Programmable Configurable in 50us Steps

150 300 485 µs
Range 10% to 90% VNOM
Soft-Start Period Variation from set point -25 +25 %
B1_ILIMSET=00 5.3
Internal High Side Peak Current B1_ILIMSET=01 4.6
A
Limit (Cycle-by-Cycle) ILIMSET B1_ILIMSET=10 3.8
B1_ILIMSET=11 3.0
At default ILIMSET -10% ILIMSET +10%
Internal High Side Peak Current
Limit (Cycle-by-Cycle) Tolerance
At other set points -15% ILIMSET +15%

Above ILIMSET = 00 +15% +22.5% +30%

Above ILIMSET = 01 +15% +22.5% +30%

Internal High Side Peak Current
Limit, Shutdown Level
Above ILIMSET = 10 +15% +22.5% +30%

Above ILIMSET = 11 +12.5% +22.5% +32.5%

Below ILIMSET = 00 -17.5% -25% -32.5%

Internal High Side Peak Current
Below ILIMSET = 01 -17.5% -25% -32.5%
Limit, IRQ Triggered Level
Below ILIMSET = 10 -17.5% -25% -32.5%

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Below ILIMSET = 11 -15% -25% -35%

Internal High Side Peak Current
16 consecutive clocks at 2.25MHz 6.78 7.11 7.44 µs
Limit IRQ Signal Deglitch Time
PMOS On-Resistance ISW = -1A, VIN_B1 = 3.3V 0.025 0.040 Ω

NMOS On-Resistance ISW = 1A, VIN_B1 = 3.3V 0.025 0.045 Ω

SW Leakage Current – NMOS VIN_B1 = 5.5V, VSW = 5.5V 12.5 µA

SW Leakage Current – PMOS VIN_B1 = 5.5V, VSW = 0V 1 µA

B1_SLEW=00 Not allowed

B1_SLEW=01 14.0
Dynamic Voltage Scaling Rate mV/µs
B1_SLEW=10 3.50
B1_SLEW=11 0.88
VIN_B1 = 5V
3.5/5.6
B1_DRVADJ=00
2.8/4.5
Switching Rise / Fall Times B1_DRVADJ=01 ns
2.5/3.6
B1_DRVADJ=10
2.3/3.0
B1_DRVADJ=11
Output Pull Down Resistance Enabled when regulator disabled 2.75 4.4 8.75 Ohms

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

BUCK1 ELECTRICAL CHARACTERISTICS, REGULATOR: – BYPASS MODE OPTION

(VIN_B1 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER CONDITIONS MIN TYP MAX UNIT

Bypass Mode

Input Voltage Range for By-Pass

2.7 3.3 3.7 V
Mode
ISW = -1A, VIN = 3.3V
PMOS On-Resistance 0.025 0.040 Ω
Max=125°C at TJunction
Internal PMOS Current Detection Triggers Interrupt on IRQ Pin 1.4 3 4.6 A
Internal PMOS Current Detection
10 µs
Deglitch Time
Shuts down after deglitch time and stays
Internal PMOS Current Shutdown 4.8 6 7.2 A
off for Off Time
Internal PMOS Current Shutdown
10 µs
Deglitch Time
Internal PMOS Current Shutdown
100 ms
Off time
Internal PMOS Softstart Only used with 3.3V Input 5.94 6.6 7.26 mV/us

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 ®
ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

BUCK2 ELECTRICAL CHARACTERISTICS, REGULATORS:

(VIN_B2 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 2.7 5.5 V

Configured for 9.375mV steps 0.6 3.0 V

Output Voltage Range
Configured for 12.5mV steps 0.8 4.0 V

Maximum Output Current 2 A

Low Power Mode Enabled
Supply Current, Standby Regulator Only, No Load 40 µA
(VOUT = VSET*1.05)
Supply Current, Shutdown Regulator Disabled 0.1 1 µA

Output Voltage Accuracy – PWM Default output voltage, IOUT = 1A -1% VNOM 1% V
Default output voltage, IOUT = 1mA,
Output Voltage Accuracy - PFM -1% VNOM 1% V
Average Ripple Voltage
Default output voltage, VIN_B2 = 3.3V to
Line Regulation 0.02 %/V
5.5V, PWM mode
Load Regulation Default output voltage, PWM Mode 0.04 %/A

Power Good Threshold VOUT_B2 Rising 92 93 94 %V NOM

Power Good Hysteresis VOUT_B2 Falling 3 %V NOM

Overvoltage Fault Threshold VOUT_B2 Rising 107.5 110 112.5 %V NOM

Overvoltage Fault Hysteresis VOUT_B2 Falling 3 %V NOM

Switching Frequency VOUT_B2 ≥ 20% of VNOM 2.15 2.25 2.36 MHz

Soft-Start Period – Programmable Configurable in 50us Steps
150 300 485 µs
Range 10% to 90% VNOM
Soft-Start Period Variation from set point -25 +25 %
B2_ILIMSET=00 4.0
Internal High Side Peak Current B2_ILIMSET=01 4.0
A
Limit (Cycle-by-Cycle) ILIMSET B2_ILIMSET=10 3.0
B2_ILIMSET=11 2.0

Internal High Side Peak Current At default ILIMSET -10% ILIMSET +10%
Limit (Cycle-by-Cycle) Tolerance At other set points -15% ILIMSET +15%
Internal High Side Peak Current
Above ILIMSET = all settings +15% +22.5% +30%
Limit, Shutdown Level
nternal High Side Peak Current
Below ILIMSET = all settings -17.5% -25% -32.5%
Limit, IRQ Triggered Level
Internal High Side Peak Current
16 consecutive clocks at 2.25MHz 6.78 7.11 7.44 µs
Limit IRQ Signal Deglitch Time
PMOS On-Resistance I = -500mA, VIN_B2 = 3.3V
SW 0.08 Ω

NMOS On-Resistance I = 500mA, VIN_B2 = 3.3V

SW 0.05 Ω

SW Leakage Current – NMOS VIN_B2 = 5.5V, VSW = 5.5V 1 µA

SW Leakage Current – PMOS VIN_B2 = 5.5V, VSW = 0V 1 µA

B2_SLEW=00 not allowed
Dynamic Voltage Scaling Rate mV/µs
B2_SLEW=01 14.0

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

B2_SLEW=10 3.50
B2_SLEW=11 0.88
VIN_B2 = 5V
3 / 5.5
B2_DRVADJ=00
2.6 / 3.7
Switching Rise / Fall Times B2_DRVADJ=01 ns
2.4 / 3.3
B2_DRVADJ=10
2.3 / 3.0
B2_DRVADJ=11
Output Pull Down Resistance Enabled when regulator disabled 6.25 9.40 20 Ohms

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

BUCK3 ELECTRICAL CHARACTERISTICS, REGULATORS:

(VIN_B3 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 2.7 5.5 V

Configured for 9.375mV steps 0.6 3.0 V

Output Voltage Range
Configured for 12.5mV steps 0.8 4.0 V

Maximum Output Current 2 A

Low Power Mode Enabled
Supply Current, Standby Regulator Only, No Load 40 µA
(VOUT = VSET*1.05)
Supply Current, Shutdown Regulator Disabled 0.1 1 µA

Output Voltage Accuracy – PWM Default output voltage, IOUT = 1A -1% VNOM 1% V
Default output voltage, IOUT = 1mA,
Output Voltage Accuracy - PFM -1% VNOM 1% V
Average Ripple Voltage
Default output voltage, VIN_B3 = 3.3V to
Line Regulation 0.02 %/V
5.5V, PWM mode
Load Regulation Default output voltage, PWM Mode 0.04 %/A

Power Good Threshold VOUT_B3 Rising 92 93 94 %VNOM

Power Good Hysteresis VOUT_B3 Falling 3 %VNOM

Overvoltage Fault Threshold VOUT_B3 Rising 107.5 110 112.5 %VNOM

Overvoltage Fault Hysteresis VOUT_B3 Falling 3 %VNOM

Switching Frequency VOUT_B3 ≥ 20% of VNOM 2.15 2.25 2.36 MHz

Soft-Start Period – Programmable Configurable in 50us Steps
150 485 µs
Range 10% to 90% VNOM
Soft-Start Period Variation from set point -25 +25 %
B3_ILIMSET=00 4.0
Internal High Side Peak Current B3_ILIMSET=01 4.0
A
Limit (Cycle-by-Cycle) ILIMSET B3_ILIMSET=10 3.0
B3_ILIMSET=11 2.0

Internal High Side Peak Current At default ILIMSET -10% ILIMSET +10%
Limit (Cycle-by-Cycle) Tolerance At other set points -15% ILIMSET +15%
Internal High Side Peak Current
Above ILIMSET = all settings +15% +22.5% +30%
Limit, Shutdown Level
Internal High Side Peak Current
Below ILIMSET = all settings -17.5% -25% -32.5%
Limit, IRQ Triggered Level
Internal High Side Peak Current
16 consecutive clocks at 2.25MHz 6.78 7.11 7.44 µs
Limit IRQ Signal Deglitch Time
PMOS On-Resistance ISW = -500mA, VIN_B3 = 3.3V 0.08 Ω

NMOS On-Resistance ISW = 500mA, VIN_B3 = 3.3V 0.05 Ω

SW Leakage Current – NMOS VIN_B3 = 5.5V, VSW = 5.5V 1 µA

SW Leakage Current – PMOS VIN_B3 = 5.5V, VSW = 0V 1 µA

B3_SLEW=00 not allowed
Dynamic Voltage Scaling Rate mV/µs
B3_SLEW=01 14.0

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Advanced PMU for Microcontrollers and Solid State Drive Applications

B3_SLEW=10 3.50
B3_SLEW=11 0.88
VIN_B3 = 5V
3 / 5.5
B3_DRVADJ=00
2.6 / 3.7
Switching Rise / Fall Times B3_DRVADJ=01 ns
2.4 / 3.3
B3_DRVADJ=10
2.3 / 3.0
B3_DRVADJ=11
Output Pull Down Resistance Enabled when regulator disabled 6.25 9.40 20 Ohms

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

BUCK4 ELECTRICAL CHARACTERISTICS, REGULATORS:

(VIN_B4 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 2.7 5.5 V

Output Voltage Range Configurable in 12.5mV steps 0.8 4.0 V

Maximum Output Current 2 A

Low Power Mode Enabled
Supply Current, Standby Regulator Only, No Load 40 µA
(VOUT = VSET*1.05)
Supply Current, Shutdown Regulator Disabled 0.1 1 µA

Output Voltage Accuracy – PWM Default output voltage, IOUT = 2A -1% VNOM 1% V
Default output voltage, IOUT = 1mA,
Output Voltage Accuracy - PFM -1% VNOM 1% V
Average Ripple Voltage
Default output voltage, VIN_B4 = 3.3V to
Line Regulation 0.02 %/V
5.5V, PWM mode
Load Regulation Default output voltage, PWM Mode 0.04 %/A

Power Good Threshold VOUT_B4 Rising 94 95 96 %VNOM

Power Good Hysteresis VOUT_B4 Falling 2 %VNOM

Overvoltage Fault Threshold VOUT_B4 Rising 107.5 110 112.5 %VNOM

Overvoltage Fault Hysteresis VOUT_B4 Falling 3 %VNOM

Switching Frequency VOUT_B4 ≥ 20% of VNOM 2.15 2.25 2.36 MHz

Soft-Start Period – Programmable Configurable in 25us steps
25 204 µs
Range 10% to 90% VNOM
Soft-Start Period Variation from set point -25 +25 %
B4_ILIMSET=00 4.0
Internal High Side Peak Current B4_ILIMSET=01 4.0
A
Limit (Cycle-by-Cycle) ILIMSET B4_ILIMSET=10 3.0
B4_ILIMSET=11 2.0

Internal High Side Peak Current At default ILIMSET -10% ILIMSET +10%
Limit (Cycle-by-Cycle) Tolerance At other set points -15% ILIMSET +15%
Internal High Side Peak Current
Above ILIMSET = all settings +15% +22.5% +30%
Limit, Shutdown Level
nternal High Side Peak Current
Below ILIMSET = all settings -17.5% -25% -32.5%
Limit, IRQ Triggered Level
Internal High Side Peak Current
16 consecutive clocks at 2.25MHz 6.78 7.11 7.44 µs
Limit IRQ Signal Deglitch Time
PMOS On-Resistance ISW = -500mA, VIN_B4 = 3.3V 0.08 Ω

NMOS On-Resistance ISW = 500mA, VIN_B4 = 3.3V 0.05 Ω

SW Leakage Current – NMOS VIN_B4 = 5.5V, VSW = 5.5V 1 µA

SW Leakage Current – PMOS VIN_B4 = 5.5V, VSW = 0V 1 µA

B1_SLEW=00 not allowed
B1_SLEW=01 14.0
Dynamic Voltage Scaling Rate mV/µs
B1_SLEW=10 3.50
B1_SLEW=11 0.88

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

VIN_B4 = 5V
3 / 5.5
B1_DRVADJ=00
2.6 / 3.7
Switching Rise / Fall Times B1_DRVADJ=01 ns
2.4 / 3.3
B1_DRVADJ=10
2.3 / 3.0
B1_DRVADJ=11
Output Pull Down Resistance Enabled when regulator disabled 6.25 9.40 20 Ohms

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

LDO1 ELECTRICAL CHARACTERISTICS

(VIN_LDO1 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 2.4 5.5 V
Output Voltage Range Configurable in 25mV steps 0.8 4 V
VIN_LDO1 = 2.7V to 5.5V, LDO1_ILIM=11 0.75 A
Output Current
VIN_LDO1 = 2.4V to 2.7V, LDO1_ILIM=1X 0.4 A
At default output voltage setting
Output Voltage Accuracy -1 VNOM 1 %
VIN_LDO1 - VLDO1_OUT > 0.4V
VIN_LDO1 - VLDO1_OUT > 0.4V
Line Regulation VIN_LDO1 = 2.7V to 5.5V 0.005 %/V
ILDO1_OUT = 1mA
Load Regulation ILDO1_OUT = 1mA to 750mA 0.15 %/A
Regulator Enabled No Load 25 42
Supply Current µA
Regulator Disabled 0 1
LDO1_SS=00 (Default) 226
LDO1_SS=01 VLDO1_OUT = 10% to 90% 323
Soft-Start Period µs
LDO1_SS=10 VLDO1_OUT = 1.8V Setting 440
LDO1_SS=11 570
Power Good Threshold VLDO1_OUT Rising 92 93 94 %VNOM
Power Good Hysteresis VLDO1_OUT Falling 3 %VNOM
Overvoltage Fault Threshold VLDO1_OUT Rising 107.5 110 112.5 %VNOM
Overvoltage Fault Hysteresis VLDO1_OUT Falling 3 %VNOM
Discharge Resistance Enabled when regulator disabled 10 25 75 Ω
ILDO1_OUT = 200mA, VIN_LDO1 > 2.7V 200 mV

Dropout Voltage ILDO1_OUT = 400mA, LDO1_ILIM=1X 300 mV

ILDO1_OUT = 750mA VIN_LDO1 > 2.7V
400 mV
LDO_ILIM=11
LDO1_ILIM=00 350
LDO1_ILIM=01 500
Output Current Limit -15% +15% mA
LDO1_ILIM=10 630
LDO1_ILIM=11 1000
Additional startup delay required before soft start
Startup Delay 31 44 65 µs
ramp LDO1_SS=00

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

LDO1 ELECTRICAL CHARACTERISTICS – LOAD SWITCH

(VIN_LDO1 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 2.7 5.5 V
PMOS On-Resistance VINL1 = 2.7V, VOUT_L1_SET = 3V, I_Load = 200mA 180 220 mΩ
Output Current VIN_LDO1 = 2.7V to 5.5V, LDO1_ILIM=11 0.75 A
Load Switch Enabled No Load 25 42
Supply Current per Output µA
Load Switch Disabled 0 1
Soft-Start Slew Rate 12 mV/µs
LDO1_ILIM=00 1415
LDO1_ILIM=01 1503
Output Current Limit -15% +15% mA
LDO1_ILIM=10 1626
LDO1_ILIM=11 1904

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

LDO2 ELECTRICAL CHARACTERISTICS

(VIN_LDO23 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 1.62 5.5 V
LDO2_RANGE=0
2.000 3.575 V
Configurable in 25mV steps
Output Voltage Range
LDO2_RANGE=1
0.800 2.375 V
Configurable in 25mV steps
Output Current VIN_LDO23 = 2.7V to 5.5V, LDO2_ILIM=1X 0.1 A
At default output voltage setting
Output Voltage Accuracy -1 VSET 1 %
VIN_LDO23 - VLDO2_OUT > 0.4V
At default output voltage setting
Output Voltage Accuracy -2 VSET 2 %
VIN_LDO23 - VLDO2_OUT > 0.4V
VIN_LDO23 - VLDO2_OUT > 0.4V
Line Regulation VIN_LDO23 = 2.7V to 5.5V 0.007 %/V
ILDO2_OUT = 1mA
Load Regulation ILDO2_OUT = 1mA to 100mA, LDO2_ILIM=1X -1 %/A
Regulator Enabled, No Load 15 µA
Supply Current (each LDO output)
Regulator Disabled 0 1 µA
LDO2_SS=00 VLDO2_OUT = 10% to 90% 60 130 255
LDO2_SS=01 VLDO2_OUT = 2.5V Setting 90 133 255
Soft-Start Period µs
LDO2_SS=10 135 170 255
LDO2_SS=11 180 220 270
Power Good Threshold VLDO2_OUT Rising 92 93 94 %VNOM
Power Good Hysteresis VLDO2_OUT Falling 3 %VNOM
Overvoltage Fault Threshold VLDO2_OUT Rising 107.5 110 112.5 %VNOM
Overvoltage Fault Hysteresis VLDO2_OUT Falling 3 %VNOM
ILDO2_OUT = 150mA
Dropout VIN_LDO23 > 2.7V 200 mV
LDO2_ILIM=11
Discharge Resistance Enabled when regulator disabled 20 50 125 Ω
LDO2_ILIM=00 110
LDO2_ILIM=01 150
Output Current Limit -35% +35% mA
LDO2_ILIM=10 210
LDO2_ILIM=11 315
Additional startup delay required before soft start
Startup Delay 20 36 55 µs
ramp LDO2_SS=01

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

LDO3 ELECTRICAL CHARACTERISTICS

(VIN_LDO23 = 3.3V, TA = 25°C, unless otherwise specified.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Operating Voltage Range 1.62 2.7 5.5 V
LDO3_RANGE = 0
2.0 3.575 V
Configurable in 25mV steps
Output Voltage Range
LDO3_RANGE = 1
0.8 2.375 V
Configurable in 25mV steps

Output Current VIN_LDO23 = 1.8V to 5.5V, LDO3_ILIM = 11 160 mA

Output Voltage Accuracy VIN_LDO23 - VLDO3_OUT > 0.4V -1 VNOM 1 %

VIN_LDO23 - VLDO3_OUT > 0.4V

Line Regulation VIN_LDO23 = 2.7V to 5.5V 0.01 %/V
ILDO3_OUT = 1mA

Load Regulation ILDO3_OUT = 1mA to 100mA, LDO3_ILIM = 1X -1.8 %/A

Power Supply Rejection Ratio See Graphs dB

Regulator Enabled No Load 15 µA

Supply Current (each LDO output)
Regulator Disabled 0 1 µA

LDO3_SS = 00 VOUT = EN to POK 15 36 60

LDO3_SS = 01 VOUT = 0.9V Setting 40 64 90
Soft-Start Period µs
LDO3_SS = 10 60 96 140
LDO3_SS = 11 80 126 180

Power Good Threshold VLDO3_OUT Rising 92 93 94 %VNOM

Power Good Hysteresis VLDO3_OUT Falling 3 %VNOM

Overvoltage Fault Threshold VLDO3_OUT Rising 107.5 110 112.5 %VNOM

Overvoltage Fault Hysteresis VLDO3_OUT Falling 3 %VNOM

Discharge Resistance Enabled when regulator disabled 20 50 125 Ω

ILDO3_OUT = 150mA VIN_LDO3 > 1.8V

Dropout Voltage 500 mV
LDO3_ILIM = 11
LDO3_ILIM=00 -35% 130
LDO3_ILIM=01 -35% 183
Output Current Limit +35% mA
LDO3_ILIM=10 -35% 255
LDO3_ILIM=11 -28.5% 390
Additional startup delay required before soft start
Startup Delay 8 16 25 µs
ramp LDO3_SS = 01

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

OVERALL SYSTEM TIMING REQUIREMENTS

(Full timing requirements to follow)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ONDLY=000 32.6 41 88
ONDLY=001 101 113 165
ONDLY=010 196 213 270
Regulator Programmable Startup Delay Timings ONDLY=011 291 313 375
µs
between turn on events ONDLY=100 386 413 480
ONDLY=101 481 513 585
ONDLY=110 576 613 690
ONDLY=111 671 713 795
nRESET_DLY=000 199
nRESET_DLY=001 313
nRESET_DLY=010 427
nRESET_DLY=011 540
nRESET Delay Timing µs
nRESET_DLY=100 654
nRESET_DLY=101 768
nRESET_DLY=110 57
nRESET_DLY=111 996
nRESET_AUX1_DLY=000 398
nRESET_AUX1_DLY=001 626
nRESET_AUX1_DLY=010 853
nRESET_AUX1_DLY=011 1081
nRESET_AUX1 Delay Timing
nRESET_AUX1_DLY=100 1308
nRESET_AUX1_DLY=101 1536
nRESET_AUX1_DLY=110 1764
nRESET_AUX1_DLY=111 1991
nRESET_AUX2_DLY=000 199
nRESET_AUX2_DLY=001 313
nRESET_AUX2_DLY=010 427
nRESET_AUX2_DLY=011 540
nRESET_AUX2 Delay Timing µs
nRESET_AUX2_DLY=100 654
nRESET_AUX2_DLY=101 78
nRESET_AUX2_DLY=110 882
nRESET_AUX2_DLY=111 57
Setting nRST_DLY=110
nRESET, nRESET_AUX2 Min Delay Timing1 40 60 µs
Setting nRESET_AUX2=111
nRESET Max Delay Timing1 Setting nRST_DLY=111 920 996 1080 µs
nRESET_AUX1 Max Delay Timing1 Setting nRESET_AUX1_DLY=110 823 882 942 µs

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

I2C INTERFACE ELECTRICAL CHARACTERISTICS

(VIO_IN = 1.8V, TA = 25°C, unless otherwise specified.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SCL, SDA Input Low VIO_IN = 1.8V 0.4 V
SCL, SDA Input High VIO_IN = 1.8V 1.25 V
SCL, SDA Input Low VIO_IN = 3.3V 1.0 V
SCL, SDA Input High VIO_IN = 3.3V 2.3 V
SDA Leakage Current SDA = 5V 1 µA
SDA Output Low IOL = 5mA 0.35 V
SCL Clock Frequency, fSCL 0 1000 kHz
SCL Low Period, tLOW 0.5 µs
SCL High Period, tHIGH 0.26 µs
SDA Data Setup Time, tSU 50 ns
SDA Data Hold Time, tHD (Note1) 0 ns
Start Setup Time, tST For Start Condition 260 ns
Stop Setup Time, tSP For Stop Condition 260 ns
Capacitance on SCL or SDA Pin 10 pF
SDA Fall Time SDA, Tof Device requirement 120 ns
Pulse Width of spikes must be suppressed on SCL and SDA 0 50 ns

Note1: Comply to I2C timings for 1MHz operation - “Fast Mode Plus”.
Note2: No internal timeout for I2C operations, however, I2C communication state machine will be reset when entering RESET, IDLE, OVUVFLT, and
THERMAL states to clear any transactions that may have been occurring when entering the above states.
Note3: This is an I2C system specification only. Rise and fall time of SCL & SDA not controlled by the device.
Note4: Device Address is 7’h5A
tSCL

SCL

tST tHD tSU tSP

SDA

Start Stop
condition condition

Figure 3: I2C Data Transfer

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

SYSTEM CONTROL INFORMATION data input and output. SDA is open drain and must have
a pullup resistor. Signals on these pins must meet tim-
General ing requirements in the Electrical Characteristics Table.
The ACT88430 is a single-chip integrated power
Table 1: ACT88430 I2C Addresses
management solution designed to power many
processors. It integrates four highly efficient buck 8-Bit Write 8-Bit Read
7-Bit Slave Address
regulators, three LDOs, and an integrated load bypass Address Address
switch. Its high integration and high switching frequency 0x53h 101 0011b 0xA6h 0xA7h
result in an extremely small footprint and lost power 0x55h 101 0101b 0xAAh 0xABh
solution. It contains a master controller that manages 0x5Ah 101 1010b 0xB4h 0xB5h
0x5Bh 101 1011b 0xB6h 0xB7h
startup sequencing, timing, voltages, slew rates, sleep
states, and fault conditions. I2C configurability allows
system level changes without the need for costly PCB I2C Registers
changes. The built-in load bypass switch enables full The ACT88430 has an array of internal registers that
sequencing configurability in 3.3V systems. contain the IC’s basic instructions for setting up the IC
The ACT88430 master controller monitors all outputs configuration, output voltages, switching frequency,
and reports faults via I2C and hardwired status signals. fault thresholds, fault masks, etc. These registers give
Faults can masked and fault levels and responses are the IC its operating flexibility. The two types of registers
configurable via I2C. are described below.
Many of the ACT88430 pins and functions are Basic Volatile – These are R/W (Read and Write)
configurable. The IC’s default functionality is defined by and RO (Read only). After the IC is powered, the user
the default CMI (Code Matrix Index), but much of this can modify the R/W register values to change IC
functionality can be changed via I2C. The first part of the functionality. Changes in functionality include things like
datasheet describes basic IC functionality and default masking certain faults. The RO registers communicate
pin functions. The end of the datasheet provides the IC status such as fault conditions. Any changes to these
configuration and functionality specific to each CMI registers are lost when power is recycled. The default
version. Contact Qorvo for additional information about values are fixed and cannot be changed by the factory
other configurations. or the end user.

I2C Serial Interface Basic Non-Volatile – These are R/W and RO. After
the IC is powered, the user can modify the R/W register
To ensure compatibility with a wide range of systems,
values to change IC functionality. Changes in
the ACT88430 uses standard I2C commands. The
functionality include things like output voltage settings,
ACT88430 always operates as a slave device, and is
startup delay time, and current limit thresholds. Any
addressed using a 7-bit slave address followed by an
changes to these registers are lost when power is
eighth bit, which indicates whether the transaction is a
recycled. The default values can be modified at the
read-operation or a write-operation. As an example, the
factory to optimize IC functionality for specific
7-bit slave address 0x5Ah follows the format 1011010x
applications. Please consult Qorvo for custom options
where “x” is a 0 for write operation and 1 for a read
and minimum order quantities.
operation. This results in 0xB4h for write operations and
0xB5h for read operations. Refer to each specific CMI When modifying only certain bits within a register,
for the IC’s slave address take care to not inadvertently change other bits.
Inadvertently changing register contents can lead to
There is no timeout function in the I2C packet
unexpected device behavior.
processing state machine, however, any time the I2C
state machine receives a start bit command, it State Machine
immediately resets the packet processing, even if it is in The ACT88430 contains an internal state machine with
the middle of a valid packet. five internal states.
The ACT88430 holds the I2C state machine in reset
RESET State
during the RESET, Idle, OVUVFLT, and THERMAL
states to avoid a corruption of registers when the In the RESET, or “cold” state, the ACT88430 is waiting
voltage regulators are out of spec. for the input voltage on VIN to be within a valid range
defined by I2C bits POK_OV_SET and POK_UV_SET.
I2C commands are communicated using the SCL and All regulators are off in RESET. nRESET,
SDA pins. SCL is the I2C serial clock input. SDA is the nRESET_AUX1, and nRESET_AUX2 are asserted low.

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Advanced PMU for Microcontrollers and Solid State Drive Applications

All volatile registers are reset to defaults and Non- enters OVUVFLT state. The OVUVFLT state is timed to
Volatile registers are reset to programmed defaults. The retry after 100ms and enter the ACTIVE state. If the OV
IC transitions from RESET to ACTIVE when the input or UV condition still exists in the ACTIVE state the IC
voltage enters the valid range. The IC transitions from returns back to the OVUVFLT state. The cycle
any other state to RESET if the input voltage drops continues until the OV or UV fault is removed or the
below the UVLO threshold voltage. input power is removed. This state can be disabled by
setting the OV_nMASK or UV_nMASK non-volatile bits
ACTIVE State
low. The IC does not directly enter OVUVFLT in an
The ACTIVE state is the normal operating state when overcurrent condition, but does enter this state due to
the input voltage is within the allowable range, all the resulting UV condition.
outputs are turned on, and no faults are present. When
entering the ACTIVE state from the RESET state, all
regulators are powered on following their programmed
power up sequence. The regulators are not sequenced
when entering ACTIVE from SLEEP.
SLEEP State
The SLEEP state is a low power mode for the operating
system. Each output can be programmed to be on or off
in the SLEEP state. The outputs do not follow any
sequencing when turning on or off as they enter or exit
the SLEEP state. They do turn on with their
programmed softstart time. Buck1/2/3/4 can be
programmed to regulate to their VSET0 voltage, VSET1
voltage, or be turned off in the SLEEP state. LDO1/2/3
can be programmed to regulate to their VSET0 voltage
or can be programmed to be turned off. Note that
LDO1/2/3 do not have a VSET1 voltage.
The IC can enter SLEEP via a hardware input pin or an
I2C command. The hardware input is typically the Figure 4. State Machine
PWREN pin, but this can be reconfigured to other pins.
To enable SLEEP via I2C, program the following: Sequencing
Set register 0x08h bit1 (PWR_DN_MODE) = 1 The ACT88430 provides the end user with extremely
versatile sequencing capability that can be optimized for
Set register 0x00h bit0 (PWR_DN_EN) = 1 many different applications. Each of the seven outputs
To enter SLEEP, program register 0x01h bit1 has four basic sequencing parameters: input trigger,
(SLP_ENTR) = 1. turn-on delay, softstart time, and output voltage. Each
of these parameters is controlled via the ICs internal
I2C is disabled in SLEEP mode, to the only way to exit registers. Contact Qorvo for custom sequencing config-
SLEEP mode is to toggle the PWREN pin. urations. Refer to the Qorvo Application Note describing
THERMAL State the Register Map for full details on I2C functionality and
programming ranges.
In the THERMAL state the chip has exceeded the
thermal shutdown temperature. To protect the device, Input trigger. The input trigger for a regulator is the
all the regulators are shut down and all three nRESETx event that turns that regulator on. Each output can have
pins are asserted low. This state can be disabled by a separate input trigger. The input trigger can be the
setting register 0x0Ah bit4 (TSD_nMASK) = 0. Note that internal power ok (POK) signal from one of the other
thermal shutdown fault flag, TSD_SHUTDWN, still regulators, the internal VIN POK signal, or an external
provides the thermal status even TSD_nMASK = 0. signal applied to an input pin such as EXT_PG or GPIO.
This flexibility allows a wide range of sequencing
OVUVFLT State possibilities, including have some of the outputs be
In the OVUVFLT state one of the regulators has exceed sequenced with another external power supply or a
an OV level at any time or UV level after the soft start control signal from the host. As an example, if the LDO1
ramp has completed. All regulators shutdown and all input trigger is Buck1, LDO1 will not turn on until Buck1
three nRESETx outputs are asserted low when the IC

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 ®
ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

is in regulation. Input triggers are defined at the factory Note that some CMI configurations may not require
and can only be changed with a custom CMI DVS_EN = 1 and may use different input pins.
configuration. The nRESETx, POK, PG, and EXT_EN
Input Voltage Operating Range
outputs can be connected to a power supply’s internal
POK signal and used to trigger external supplies in the The ACT88430 operates from VIN=2.7V to 5.5V. This
overall sequencing scheme. operating range can be tailored for this full range, a 3.3V
input range, or a 5V input range. The full range is
Turn-on Delay. The turn-on delay is the time between suitable for battery inputs like a Li-Ion battery where the
an input trigger going active and the output starting to input voltage has large variations. I2C registers
turn on. Each output’s turn-on delay is configured via its VIN-FULL_RANGE and VIN_LVL set the input voltage
I2C bit ONDLY. Turn-on delays can be changed after UVLO and OV thresholds to be compatible with these
the IC is powered on, but they are volatile and reset to operating ranges. Note that VIN_FULL_RANGE
the factory defaults when power is recycled. register is set at the factory and cannot be changed.
Table 2 shows how to configure the registers to set
Softstart Time. The softstart time is the time it takes an each input voltage range setting. See the EC table for
output to ramp from 0V to its programmed voltage. Each details on
output’s softstart time is configured via its I2C bit
SS_RAMP. Softstart times can be changed after the IC Table 2: ACT88430 Input Voltage Range Settings
is powered on, but they are volatile and reset to the VIN_FULL_RANGE VIN_LVL
factory defaults when power is recycled. 3.3V Input Range 0 0
5V Input Range 0 1
Output Voltage. The output voltage is each regulator’s
Wide Input Range 1 x
desired voltage. Each buck’s output voltage is
programmed via its I2C bits Bx_VSET0 and Bx_VSET1.
The output regulates to Bx_VSET0 in ACTIVE mode. Fault Protection
They can be programmed to regulate to Bx_VSET1 in The ACT88430 contains several levels of fault
DVS mode or SLEEP mode. Each output’s voltage can protection, including the following:
be changed after the IC is powered on, but the new
Input Voltage UVLO
setting is volatile and is reset to the factory defaults
when power is recycled. Output voltages can be Input Voltage OV
changed on the fly. If a large output voltage change is Output Overvoltage
required, it is best to make multiple smaller changes.
This prevents the IC from detecting an instantaneous Output Undervoltage
over or under voltage condition because the fault Output Current Limit
threshold are immediately changed, but the output
takes time to respond. Thermal Warning
Thermal Shutdown
Dynamic Voltage Scaling
On-the-fly dynamic voltage scaling (DVS) for the four There are three types of I2C register bits associated with
buck converters is available via the I2C interface. This each fault condition: fault flag bits, fault bits, and mask
allows systems to save power by quickly adjusting the bits. The fault flag bits display the real-time fault status.
microprocessor performance level when the workload Their status is valid regardless of whether or not that
changes. Note that DVS is not a different operating fault is masked. The mask bits either block or allow the
state. The IC operates in the ACTIVE state, but just fault to affect the fault bit. Each potential fault condition
regulates the outputs to a different voltage. For fault free can be masked via I2C if desired. Any unmasked fault
operation, the user must ensure output load conditions condition results in the fault bit going high, which asserts
plus the current required to charge the output capaci- the IRQ pin. IRQ is typically active low. The IRQ pin only
tance during a DVS rising voltage condition does not de-asserts after the fault condition is no longer
exceed the current limit setting of the regulator. As with present and the corresponding fault bit is read via I2C.
any power supply, changing an output voltage too fast Note that masked faults can still be read in the fault flag
can require a current higher than the current limit setting. bit. Refer to Qorvo Application Note describing the Reg-
The user must ensure that the voltage step, slew rate, ister Map for full details on I2C functionality and
and load current conditions do not result in an instanta- programming ranges
neous loading that results in a current limit condition. Input Voltage UVLO
Enter DVS by programming register 0x00h bit1 The ACT88430 monitors its input voltage at the VIN pin
(DVS_EN) = 1 and then pulling the EXT_PG pin high. for a UVLO condition. When the input voltage is below

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

the UVLO threshold, the IC is turned off and nRESET is limit threshold. This immediately shuts down the
held low. When the input voltage goes above UVLO, the regulator and waits 14ms before restarting.
IC transitions to the ACTIVE state and starts up normally.
The UVLO thresholds are determined by the operating For LDOs, the overcurrent thresholds are set by each
range that is programmed by the VIN_FULL_RANGE LDO’s Output Current Limit setting. When the output
and VIN_LVO registers. See Table 2 for these settings. current reaches the Current Limit threshold, the LDO
limits the output current. This reduces the output
Input Voltage OV voltage, creating an undervoltage condition, causing all
The ACT88430 monitors its input voltage at the VIN pin supplies to turn off for 100ms before restarting.
for an OV condition. When the input voltage is above
the OV threshold, the IC outputs turn off and nRESET The overcurrent fault limits for each output are
asserts low. When the input voltage goes below OV, the adjustable via I2C. Overcurrent fault reporting can be
IC transitions back to the ACTIVE state and starts up masked via I2C, but the overcurrent limits are always
normally. The OV thresholds are determined by the active and will shut down the IC when exceeded.
operating range that is programmed by the
VIN_FULL_RANGE and VIN_LVO registers. See Table Thermal Warning and Thermal Shutdown
2 for these settings. The ACT88430 monitors its internal die temperature
and reports a warning via IRQ when the temperature
Output Under/Over Voltage
rises above the Thermal Interrupt Threshold of typically
The ACT88430 monitors the output voltages for under 135 deg C. It reports a fault when the temperature rises
voltage and over voltage conditions. If one output enters above the Thermal Shutdown Temperature of typically
an UV/OV fault condition, the IC shuts down all outputs 165 deg C. A temperature fault shuts down all outputs
for 100ms and restarts with the programmed power up unless the fault is masked. Both the fault and the
sequence. If an output is in current limit, it is possible warning can be masked via I2C. The temperature
that its voltage can drop below the UV threshold which warning and fault flags still provide real-time status even
also shuts down all outputs. If that behavior is not if the faults are masked. Masking just prevents the faults
desired, mask the appropriate fault bit. Each output still from being reported via the IRQ pin.
provides its real-time UV/OV fault status via its fault
flag, even if the fault is masked. Masking an OV/UV Pin Descriptions
fault just prevents the fault from being reported via the The ACT88430 input and output pins are configurable
IRQ pin. A UV/OV fault condition pulls the nRESETx via CMI configurations. The following descriptions are
pins low. Note that nRESETx pins are configurable via refer to the most common pin functions. Refer to the
CMI settings. CMI Options section in the back of the datasheet for
specific pin functionality for each CMI.
Output Current Limit
The ACT88430 incorporates a three level overcurrent PWREN
protection scheme for the buck converters and a single The PWREN pin controls the IC’s SLEEP state. When
level scheme for the LDOs. For the buck converters, the I2C bit PWREN_MODE = 0, the PWREN pin moves the
overcurrent current threshold refers to the peak switch IC between the SLEEP and ACTIVE states.
current. The first protection level is when a buck
PWREN must be enabled via the PWRDN_EN I2C bit
converter’s peak switch current reaches 80% of the
after power up. PWREN is ignored if the PWRDN_EN
Cycle-by-Cycle current limit threshold for greater than
bit is low. The PWREN polarity is controlled by the
16 switching cycles. Under this condition, the IC reports
PWREN_POL I2C bit. PWREN is active low when
the fault via the appropriate fault flag bit. If the fault is
PWREN_POL is high, and active high when
unmasked, it asserts the IRQ pin. This may or may not
PWREN_POL is low. The host processor can read the
turn off that output or other outputs depending on the
PWREN status via I2C in the PWREN_STAT I2C bit.
specific CMI. The next level is when the current
increases to the Cycle-by-Cycle threshold. The buck PWREN is referenced to the VIO_IN pin, and is 5.5V
converter limits the peak switch current in each tolerant meaning that PWREN can go to 5.5V even if
switching cycle. This reduces the effective duty cycle VIO_IN is less than 5.5V. PWREN has a 10us
and causes the output voltage to drop, potentially bidirectional filter to prevent noise from triggering
creating an undervoltage condition. When the unwanted operation.
overcurrent condition results in an UV condition, and UV
is not masked, the IC turns off all supplies off for 100ms
EXT_PG
and restarts. The third level is when the peak switch The EXT_PG pin is a dual-purpose input. Note that
current reaches 120% of the Cycle-by-Cycle current EXT_PG can only be configured as an input. It functions

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

as either a power good input from an external supply or GPIO pin is referenced to the VIN pin, and is 5.5V
a dynamic voltage scaling control input. Configure tolerant meaning that GPIO can go to 5.5V even if VIN
EXT_PG as a power good input by setting I2C bit is less than 5.5V.
DVS_EN = 0. When configured as a power good input,
EXT_PG can be used as an input to the nRESETx pins.
IRQ
EXT_PG polarity is controlled by the EXT_PG_POL bit. The IRQ pin is an output that issues an interrupt to
EXT_PG is active high when EXT_PG_POL = 0 and the host CPU/Controller when an ACT88430 fault or
active low when EXT_PG_POL = 1. warning condition occurs.

Configure EXT_PG as a dynamic voltage scaling (DVS) IRQ is triggered by:

control input by setting I2C bit DVS_EN = 1. When Die temperature exceeding Thermal Interrupt Threshold
EXT_PG is de-asserted, all buck regulators regulate to of 135C.
their VSET0 voltage. When EXT_PG is asserted, the
buck regulators regulate to their VSET1 voltage. Note Any buck regulator reaching peak current limit, ILIMSET,
that EXT_PG input is only valid for DVS toggling when for 16 cycles after softstart.
the IC is in the ACTIVE state of operation. I2C bit Any LDO regulator reaching current limit, LDOx_ILIM,
EXT_PG_POL has no effect in DVS Mode. for more than 16us after softstart.

EXT_PG is referenced to the VIN pin, and should not BUCK1 PMOS switch exceeding Current Detection
be pulled above VIN. The EXT_PG input has a 10us threshold 75% of ILIMSET when system is configured
bidirectional filter to prevent noise from triggering in bypass mode.
unwanted operation. IRQ is masked by the I2C register 0x00h bit2
(IRQ_nMASK) by default to mask all IRQ conditions. To
VIO_IN
enable IRQ functionality, set IRQ_nMASK = 1. IRQ is
VIO_IN is the input bias supply for the IC. Apply an input an active-low open drain 5.5V compatible output.
voltage between 1.62V and 5.5V. Bypass to AGND with
a high quality, 1uF ceramic capacitor. POK
POK indicates that the voltage on the VIN pin is inside
MODE
the POK UV and OV Interrupt Thresholds. If the VIN
Setting MODE = 0 configures Buck1 as a standard voltage is above or below these values, POK pulls low
integrated buck regulator. Setting MODE = 1 configures to interrupt the host CPU/Controller. POK is masked by
Buck1 as an integrated bypass switch. Buck1 can only the I2C bit POK_nMASK by default. To enable POK
operate as a bypass switch when VIN=3.3V. In bypass functionality, set I2C bit POK_nMASK = 1. I2C bits
mode, the Buck1 P-ch power FET is used to sequence POK_OV and POK_UV provide real-time UV and OV
the 3.3V supply to the downstream load. This provides status, even when POK is masked. The POK UV and
full sequencing flexibility for 3.3V systems by allowing OV threshold are configurable via the I2C bits
the 3.3V input to be used as the input supply for the POK_UV_SET and POK_OV_SET.
other regulators but still be sequenced in any order for
the downstream loads. Bypass mode is only valid for a POK is an open drain output and is 5.5V tolerant
3.3V input voltage. The MODE pin must be tied directly meaning that POK can be pulled up to 5.5V even if
to VIN or AGND. I2C bit MODE_STAT shows the status VIO_IN is less than 5.5V.
of the MODE pin when it was read at startup. nRESET_AUX1 and nRESET_AUX2
GPIO nRESET_AUX1 and nRESET_AUX2 pins can be used
The GPIO pin can be configured as a digital input or an to signal that the IC is in the SLEEP state or that the
open drain output. It has multiple uses, including a input voltage is above or below the UV or OV threshold.
sequencing input, sequencing output, status output, or They can also be tied to one or a combination of the
control input to toggle a supply’s output voltage. Set I2C power supply’s internal POK signals. When asserted by
bit GPIO_OUT = 0 to configure GPIO as an input. When the internal POK signals they immediately assert. They
using GPIO as an output, GPIO_OUT = 0 configures it follow a programmed delay when de-asserted. The
as an open drain output, and GPIO_OUT = 1 configures nRESET_AUX1 delay time is controlled by the I2C bits
it as a logic low output. When used as either an input or RST_AUX1_DLY[2:0], which programs the delay
an output, I2C bit GPIO_STAT always provides the real- between 400us and 2mS in 227us steps. The
time status of the GPIO pin. GPIO_STAT = 0 when nRESET_AUX2 delay time is controlled by the I2C bits
GPIO pin is a logic 0. GPIO_STAT = 1 when GPIO pin RST_AUX2_DLY[2:0], which programs the delay
is a logic 1. between 200us and 1ms in 114us steps. These pins can

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

also be used as inputs to control different power rail Table 3: ACT88430 PG Input Choices
enable signals. They are configurable, so refer to the
Allowable PG Inputs
back of the datasheet for their specific functionality for
Buck1
each CMI. Contact the factory for available options.
Buck2
They are open drain outputs and are 5.5V tolerant Buck3
meaning that they can be pulled up to 5.5V even if Buck4
VIO_IN is less than 5.5V. LDO1
LDO2 AND Buck4
nRESET LDO3
nRESET issues the main reset to the CPU/controller. LDO3 AND Buck4
nRESET is immediately asserted low when either the
VIN voltage is above or below the UV or OV thresholds
or any valid output supply voltage is below its Power PG is configurable, so refer to the back of the datasheet
Good (POK) threshold. After startup, nRESET for its specific functionality for each CMI. PG is an open
de-asserts after a programmable delay time after drain output and is 5V tolerant meaning that PG can be
all outputs are above their respective UVLO thresholds. pulled up to 5.5V even if VIO_IN is less than 5.5V.
The nRESET delay time is controlled by the I2C
bits nRST_DLY[2:0], which programs the delay STEP-DOWN DC/DC CONVERTERS
between 200us and 1ms in 114us steps. nRESET is General Description
configurable, so refer to the CMI Options section in the The ACT88430 contains four fully integrated step-down
back of the datasheet for its specific functionality for converters. Buck1 is a 4A output, while Buck2, Buck3,
each CMI. nRESET is an open drain output and is 5.5V and Buck4 are 2.5A outputs. All buck converters are
tolerant meaning that nRESET can be pulled up to 5.5V fixed frequency, current-mode controlled, synchronous
even if VIO_IN is less than 5.5V. PWM converters that achieve peak efficiencies of up to
EXT_EN 96.5%. The buck converters switch at 2.25MHz and are
internally compensated, requiring only three small
EXT_EN is used to control an external regulator or to
external components (Cin, Cout, and L) for operation.
provide a control signal to other system components.
They ship with default output voltages that can be
When the MODE pin = 0 to configure Buck1 as a
modified via the I2C interface for systems that require
standard power supply, EXT_EN is the output of the
advanced power management functions.
ACT88430’s internal BUCK1 enable signal. When the
MODE pin = 1 to configure Buck1 as a bypass switch, Each buck converter has a dedicated input pin and
EXT_EN is the output of the bypass switch enable power ground pin. Each buck converter should have a
signal. dedicated input capacitor that is optimally placed to
minimize the power routing loops for each buck
The I2C bit EXT_EN_POL controls the EXT_EN polarity.
converter. Note that even though each buck converter
EXT_EN is active high when EXT_EN_POL is low and
has separate inputs, all buck converter inputs must be
EXT_EN is active low when EXT_EN_POL is high.
connected to the same voltage potential.
EXT_EN is a push-pull CMOS output using VIO_IN
supply. Note that the EXT_EN output is enabled and Buck1 is configurable as a bypass switch for systems
valid in all modes of operation. EXT_EN is configurable, with a 3.3V bus voltage. The bypass switch provides full
so refer to the CMI Options section in the back of the sequencing capability by allowing the 3.3V bus to be
datasheet for its specific functionality for each CMI. used as the input to the other supplies and still be
EXT_EN is referenced to the VIO_IN pin. It should not properly sequenced to the downstream load.
be pulled higher than VIO_IN. Tie MODE to AGND to configure Buck1 for a switching
power supply. Tie MODE to VIN to configure Buck1 as
PG
a bypass switch. MODE is only sampled when VIN
The PG pin shows the status of a regulator’s Power reaches its UVLO threshold. Changing the MODE pin
Good / UV comparator. When the regulator is below the after startup has no effect. When Buck1 is configured as
Power Good threshold, the PG pin is pulled low. When a power supply, EXT_EN is a direct output of the
above the threshold, the PG pin is open drain. The PG ACT88430 Buck1 enable signal. When Buck1 is config-
functionality is enabled by default, but can be disabled ured as a bypass switch, EXT_EN is a direct output of
by I2C. PG can be disabled by using the appropriate reg- the bypass switch enable signal.
ulator’s UV_FLTMSK bit. Table 3 shows the possible
regulators that can drive the PG pin.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

The ACT88430 buck regulators are highly configurable each converter can be independently disabled via I2C.
and can be quickly and easily reconfigured via I2C. Each CMI version requires a different set of command
This allows them to support changes in hardware to disable a converter, so contact the factory for specific
requirements without the need for PCB changes. instructions if needed. Each converter contains an
Examples of I2C functionality are given below: optional integrated discharge resistor that actively
discharges the output capacitor when the regulator is
Real-time power good, OV, and current limit status
disabled. The discharge function is enabled via the I2C
Ability to mask individual faults bit Bx_DisPulldown.
Dynamically change output voltage Soft-Start
On/Off control Each buck regulator contains a softstart circuit
that limits the rate of change of the output voltage,
Softstart ramp
minimizing input inrush current and ensuring that the
Slew rate control outputs power up monotonically. This circuitry is
effective any time the regulator is enabled, as well as
Switching delay and phase control
after responding to a short circuit or other fault condition.
Low power mode Buck1/2/3 softstart time is adjustable between 150µs to
485µs via their I2C SS_RAMP registers. Buck4
Overcurrent thresholds
softstart time is adjustable between 25µs to 204µs via
Refer to the Qorvo Application Note describing the Reg- I2C SS_RAMP register. Table 4 summarizes the
ister Map for full details on I2C functionality and pro- softstart settings.
gramming ranges.
Table 4: Buck Softstart Time (0.8V Reference)
Operating Mode
Buck1/2/3 Buck4 Softstart
The buck converters operate in fixed-frequency PWM SS_RAMP
Softstart (µs) (µs)
mode at medium to heavy loads. They transition to a
000 150 25
proprietary power-saving low power mode at light loads
to save power. Power-save mode reduces conduction 001 200 51
losses by preventing the inductor current from going 010 250 76
negative. 011 300 102
To further optimize efficiency and reduce power losses 100 350 127
at extremely light loads, an additional lower power mode, 101 395 153
LPM, is available. LPM minimizes quiescent current in 110 440 178
between switching cycles. This reduces input current by
111 485 204
approximately 200µA in LPM mode. Light load output
voltage ripple increases from approximately 5mV to
Note that when an output’s reference voltage is
10mV when in LPM mode. Light load voltage droop
changed to 0.6V, the softstart time changes to 75% of
when going from light load to heavier loads is only in-
the time in Table 4.
creased by 2-3mV when in LPM mode. LPM allows the
customer to test the IC in their use case and optimize Output Voltage Setting
the balance between power consumption, voltage ripple, Buck1/2/3/4 regulate to the voltage defined by I2C
and transient response in their system. Each buck con- register VSET0 in normal operation and by VSET1 in
verter's LPM is enabled when I2C bits DISLPM = 0 and DVS mode. Buck1/2/3/4 each have two programmable
LP_MODE = 1. output voltage ranges, Output-Low Range and
Synchronous Rectification Output-High Range. Each buck converter’s output
range can be programmed independently of the others.
Buck1/2/3/4 each feature integrated synchronous
Note that the output voltage range can NOT be changed
rectifiers (or LS FETs) to maximize efficiency and
while the output is enabled. Qorvo does not
minimize the total solution size and cost by eliminating
recommend changing the output voltage range from its
the need for external rectifiers.
default setting because its internal voltage reference is
Enable / Disable Control only trimmed to its default setting. The following table
When power is applied to the IC, all converters shows which I2C bits set the output ranges.
automatically turn on according to a pre-programmed
sequence. Once in normal operation (ACTIVE state), Table 5: Buck Output Voltage Programming Ranges

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Register Bit Setting Range to Bx_VSET1 at a rate determined by the output

Output- capacitance and the load current. The outputs transition
0
SEL_REF0P Low between VSET1 and VSET0 by the rate determined by
Buck1 0x74h
8_BUCK1 1
Output-
the I2C bits SLEW.
High
Output-
SEL_REF0P
0
Low
For fault free operation, the user must ensure output
Buck2 0x72h load conditions plus the current required to charge
8_BUCK2 1
Output-
High the output capacitance during a DVS rising voltage
Output- condition does not exceed the current limit setting of the
0
SEL_REF0P Low
Buck3 0x89h
8_BUCK3 Output- regulator. As with any power supply, changing an output
1 voltage too fast can require a current higher than the
High
Output- current limit setting. The user must ensure that the
Buck4 n/a n/a n/a
High voltage step, slew rate, and load current conditions do
The programming range for Output-Low is 0.6V to not result in an instantaneous loading that results in a
3.000V in 9.375mV steps. current limit condition.

VBUCKx = 0.6V + VOUTx * 0.009375V Enter DVS by programming register 0x00h bit1
(DVS_EN) = 1 and then pulling the EXT_EN pin high.
Where VOUTx is the decimal equivalent of the value Note that some CMI configurations may not require
in each regulator’s I2C VOUTx register. The VOUTx DVS_EN = 1 and may use different input pins.
registers contain an unsigned 8-bit binary value. As an
example, if Buck 1’s VOUT0 register contains Bx_VSET0 must be higher than Bx_VSET1.
10000000b (128 decimal), the output voltage is 1.8V. PWR_GOOD, OV, and ILIM are automatically masked
during DVS transitions to avoid asserting nRESET.
The programming range for Output-High is 0.8V to
3.988V in 12.5mV steps. Optimizing Noise
VBUCKx = 0.8V + VOUTx * 0.0125V Each buck converter contains several features available
via I2C to further optimize functionality. The top P-ch
Where VOUTx is the decimal equivalent of the value FET’s turn-on timing can be shifted 100ns from the
in each regulator’s I2C VOUTx register. The VOUTx master clock edge via the PHASE_DELAY I2C bit. It can
registers contain an unsigned 8-bit binary value. As an also be aligned to the rising or falling clock edge via the
example, if Buck 1’s VOUT0 register contains PHASE I2C bit. The internal FET rise and fall times can
01010000b (80 decimal), the output voltage is 1.8V. be optimized to minimize switching noise at the cost of
Qorvo recommends that a buck converter’s output volt- lower efficiency via the DRVADJ I2C bit.
age be kept within +/- 25% of the default output Overcurrent and Short Circuit Protection
voltage to maintain accuracy. Voltage changes larger
Each buck converter provides overcurrent and short
than +/- 25% may require different factory trim settings
circuit protection. Overcurrent protection is achieved
(new CMI) to maintain accuracy.
with cycle-by-cycle current limiting. The peak current
100% Duty Cycle Operation threshold is set by the Bx_ILIM I2C bits. If the peak
The buck regulators are capable of operating at up to current reaches the programmed threshold for 16
100% duty cycle. During 100% duty cycle operation, the consecutive switching cycles, the IC asserts IRQ low. A
high-side power MOSFETs are held on continuously, short circuit condition that results in the peak switch
providing a direct connection from the input to the output current being 122% of Bx_ILIMSET immediately shuts
(through the inductor), ensuring the lowest possible down all supplies, asserts IRQ low and restarts the
dropout voltage in battery powered applications. system in 100ms. If a buck converter reaches
overcurrent or short circuit protection, the status is
Dynamic Voltage Scaling reported in the ILIM_REG[x] I2C registers. The contents
Each buck converter supports Dynamic Voltage Scaling of these registers are latched until read via I2C.
(DVS). DVS allows the user to optimize the processor’s Overcurrent and short circuit conditions can be masked
energy to complete tasks by lowering the processor’s via the I2C bit Bx_ILIM_FLTMSK.
operating frequency and input voltage when lower Compensation
performance is acceptable. In normal operation, each
output regulates to the voltage programmed in the I2C The buck converters utilize current-mode control
register Bx_VSET0. During DVS, each output regulates and a proprietary internal compensation scheme to
to Bx_VSET1. The output transitions from Bx_VSET0 simultaneously simplify external component selection

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

and optimize transient performance over their full the UV_REG I2C bit. Shutdown due to overcurrent can
operating range. No compensation design is required; also be masked via the I2C bit B1_PG_FLTMSK.
simply follow a few simple guide lines described below
B1_OV is disabled. There is no overvoltage detection
when choosing external components.
circuitry on the output of the bypass switch.
Minimum On-Time
Input Capacitor Selection
The ACT88430 minimum on-time is 120ns. If the
Each regulator requires a high quality, low-ESR,
calculated on-time is less than 120ns with 2.25MHz
ceramic input capacitor. Note that even though each
operation, then the user must configure the output to
buck converter has separate input pins, all input pins
switch at 1.125MHz. Setting I2C bits Bx_HalfFreq = 0
must be connected to the same voltage potential. 10uF
sets Fsw = 2.25MHz. Setting Bx_HalfFreq = 1 sets Fsw
capacitors are typically suitable, but this value can
= 1.125MHz. The following equation calculates the on-
be increased without limit. Smaller capacitor values
time.
can be used with lighter output loads. Choose the input
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 capacitor value to keep the input voltage ripple less
𝑇𝑇𝑂𝑂𝑂𝑂 =
𝑉𝑉𝐼𝐼𝐼𝐼 ∗ 𝐹𝐹𝑆𝑆𝑆𝑆 than 50mV.
Where Vout is the output voltage, Vin is the input voltage, 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑢𝑢𝑡𝑡
∗ �1 − �
and FSW is the switching frequency. Vripple = 𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 ∗ 𝑉𝑉𝑉𝑉𝑉𝑉 𝑉𝑉𝑉𝑉𝑉𝑉
𝐹𝐹𝐹𝐹𝐹𝐹 ∗ 𝐶𝐶𝐶𝐶𝐶𝐶
BUCK1 Bypass Switch Be sure to consider the capacitor’s DC bias effects and
The ACT88430 provides a bypass mode for 3.3V maximum ripple current rating when using capacitors
systems. This allows the 3.3V input voltage to power the smaller than 0805.
ACT88430 regulators and also be sequenced to the
downstream loads. In bypass mode, the Buck1 P-ch A capacitor’s actual capacitance is strongly affected by
FET acts as a switch and the N-ch FET is disabled. The its DC bias characteristics. The input capacitor is
bypass switch turns on the 3.3V rail with the typically an X5R, X7R, or similar dielectric. Use of Y5U,
programmed delay and softstart time. Z5U, or similar dielectrics is not recommended. Input
capacitor placement is critical for proper operation.
In bypass mode, the ACT88430 I2C registers are Each buck’s input capacitor must be placed as close to
reconfigured to the following. the IC as possible. The traces from VIN_Bx to the
1. B1_PWR_GOOD register bit reconfigured to capacitor and from the capacitor to PGNDx should as
the output of the Soft Start ramp. When soft short and wide as possible.
start is complete, this bit goes high to allow the Inductor Selection
sequencing of the other regulators to continue.
The Buck converters utilize current-mode control
B1_PWR_GOOD no longer reports the Buck1
and a proprietary internal compensation scheme to
output voltage status. It stays high as long as
simultaneously simplify external component selection
the bypass switch is enabled.
and optimize transient performance over their full
2. B1_ILIM bit is the output of the internal PMOS operating range. The ACT88430 is optimized for opera-
Current Detection circuit. This is set to 3A tion with 1.0-1.5μH inductors. Choose an inductor with
typical. If the bypass current exceeds the a low DC-resistance, and avoid inductor saturation by
Internal PMOS Current Detection current, choosing inductors with DC ratings that exceed the
B1_ILIM triggers an IRQ output and gets maximum output current by at least 30%. The following
latched in the ILIM_REG[0] if configured by the equation calculates the inductor ripple current.
IRQ_nMASK. The B1_ILIM can also be masked 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
with the B1_ILIM_FLTMSK register. �1 − � ∗ 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝐼𝐼𝐼𝐼
∆𝐼𝐼𝐿𝐿 =
B1_UV register bit reconfigured to the output of the 𝐹𝐹𝑆𝑆𝑆𝑆 ∗ 𝐿𝐿
Internal PMOS Current Shutdown circuit. This is set to Where VOUT is the output voltage, VIN is the input voltage,
6A typical. If the bypass switch current exceeds 6A, FSW is the switching frequency, and L is the inductor
limits the current which triggers an under voltage fault value.
condition and moves the IC into the OVUVFLT state.
This immediately shuts down all regulators including the Output Capacitor Selection
bypass switch. The system restarts in 100ms, following The ACT88430 is designed to use small, low ESR,
the programmed startup sequencing. This fault can be ceramic output capacitors. Buck1 typically requires a
masked with I2C bit UV_nMASK. This fault is latched in 44uF output capacitor while Buck2, Buck3, and Buck4

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

require a 22uF output capacitor each. In order to ensure disabled. Each LDO’s discharge function is enabled via
stability, the actual Buck1 capacitance should be its I2C bit DIS_PULLDOWN.
greater than 33uF while Buck2, Buck3, and Buck4
Soft-Start
should be greater than 15uF. The output capacitance
can be increased to reduce output voltage ripple and Each LDO contains a softstart circuit that limits the rate
improve load transients if needed. Design for an output of change of the output voltage, minimizing input inrush
ripple voltage less than 1% of the output voltage. The current and ensuring that the outputs power up in a
following equation calculates the output voltage ripple monotonically. This circuitry is effective any time the
as a function of output capacitance. LDO is enabled, as well as after responding to a short
circuit or other fault condition. Each LDO’s softstart time
∆𝐼𝐼𝐿𝐿
VRIPPLE = is adjustable via its I2C bits SS_RAMP.
8 ∗ 𝐹𝐹𝑆𝑆𝑆𝑆 ∗ 𝐶𝐶𝑂𝑂𝑂𝑂𝑂𝑂
LDO1 is adjustable between 226µs and 570µs,
Where ΔIL is the inductor ripple current, FSW is the depending on output voltage.
switching frequency, and COUT is the output capacitance
after taking DC bias into account. LDO2 is adjustable between 130µs and 220µs,
depending on output voltage
Be sure to consider the capacitor’s DC bias effects and
maximum ripple current rating when using capacitors LDO3 is adjustable between 65µs and 130µs,
smaller than 0805. depending on output voltage

A capacitor’s actual capacitance is strongly affected Table 6 summarizes the LDO softstart programming
by its DC bias characteristics. The output capacitor is ranges.
typically an X5R, X7R, or similar dielectric. Use of Y5U,
Table 6: LDO Softstart Ranges
Z5U, or similar dielectrics are not recommended due to
their wide variation in capacitance over temperature and LDOx LDO1 LDO2 LDO3
Set-
voltage ranges. Softstart softstart softstart softstart
ting
Register (us) (us) (us)
LDO CONVERTERS 00 226 130 36
01 323 133 64
General Description LDOx_SS
10 440 170 96
The ACT88430 contains three fully integrated low 11 570 220 126
dropout linear regulators (LDO). LDO1 is an 800mA
output, while LDO2 and LDO3 are 200mA outputs. The Output Voltage Setting
LDOs are require only two small external components LDO1/2/3 regulate to the voltage defined by I2C
(Cin, Cout) for operation. They ship with default output registers LDO VSET registers. Unlike the buck
voltages that can be modified via the I2C interface converters, the LDOs only have one VSET register.
for systems that require advanced power management LDO2/3 each have two programmable output voltage
functions. ranges, Output-Low Range and Output-High Range.
LDO1 has a dedicated input pin. LDO2 and LDO3 share Each LDO’s output range can be programmed
an input pin. The LDOs can operate from different input independently of the others. Note that the output voltage
voltages than the buck converters. LDO1 and LDO2/3 range can NOT be changed while the output is enabled.
can operate from different input voltage from each other. Qorvo does not recommend changing the output volt-
age range from its default setting because its
LDO1 has the option to be operated as a standard LDO internal voltage reference is only trimmed to its default
or as a load switch. setting. The following table shows which I2C bits set the
Enable / Disable Control output ranges.

When power is applied to the IC, all LDOs automatically Table 7: LDO Output Voltage Programming Ranges
turn on according to a pre-programmed sequence.
Once in normal operation (ACTIVE state), each Register Bit Setting Range
converter can be independently disabled via I2C. Each
Output-
CMI version requires a different set of command to LDO1 n/a n/a n/a
High
disable a converter, so contact the factory for specific Output-
1
instructions if needed. Each converter contains an Low
LDO2 0x81h RANGE_LDO2
optional integrated discharge resistor that actively Output-
0
discharges the output capacitor when the regulator is High

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

1
Output- Output Capacitor Selection
Low
LDO3 0x81h RANGE_LDO3 Each LDO requires a high quality, low-ESR, ceramic
Output-
0 output capacitor. A 1uF is typically suitable, but this
High
value can be increased without limit. The input capacitor
The programming range for Output-Low is 0.8V to is should be a X5R, X7R, or similar dielectric.
2.375V in 25mV steps.
LDO1 Load Switch Mode
VLDOx = 0.8V + LDOxVSET * 0.025V LDO1 has an option to be used as a load switch. This
Where LDOxVSET is the decimal equivalent of the option is only accessible via factory I2C bits and requires
value in each regulator’s I2C LDOxVSET register. The a custom CMI. When in load switch mode, LDO1 still
retains overcurrent protection. Overvoltage and
LDOxVSET registers contain an unsigned 6-bit binary
undervoltage protection are disabled.
value. As an example, if LDO 1’s LDOxVSET register
contains 101000b (40 decimal), the output voltage is The load switch mode softstart times are the same as
1.8V. the LDO mode times.

The programming range for Output-High is 2.0V to The following table shows the load switch Current
3.575V in 25mV steps. limit settings.

VLDOx = 2.0V + LDOxVSET * 0.025V

Table 8: Load Switch Current Limit Settings
Where LDOxVSET is the decimal equivalent of the
value in each regulator’s I2C LDOxVSET register. The ILIM_SET<1:0> ILIM(mA)
LDOxVSET registers contain an unsigned 6-bit binary 0 1415
value. As an example, if LDO 1’s LDOxVSET register 1 1503
contains 01010000b (52 decimal), the output voltage is 2 1626
3.3V.
3 1904
Qorvo recommends that an LDO’s output voltage be
kept within +/- 25% of the default output voltage to main- Both Overvoltage and Undervoltage functionality are
tain accuracy. Voltage changes larger than +/- 25% may disabled.
require different factory trim settings (new CMI) to main- The LDO1 POK is functional in Load Switch mode. The
tain accuracy. POK signal is asserted when the switch is enabled and
Overcurrent and Short Circuit Protection is not in current limit.
Each LDO provides overcurrent and short circuit
protection. The overcurrent threshold is set by the
LDOx_ILIM I2C bits. In both an overload and a short
circuit condition, the LDO limits the output current which
causes the output voltage to drop. This can result in an
undervoltage fault in addition to the current limit fault. If
an LDO reaches current limit protection, the status is
reported in the ILIM_REG[x] I2C registers. The contents
of these registers are latched until read via I2C. When
the current limiting results in a drop in output voltage
that triggers an undervoltage condition, the IC shuts
down all power supplies, asserts IRQ low, and enters
the UVLOFLT state. The IC restarts in 100ms and starts
up with default sequencing. Overcurrent and short
circuit conditions can be masked via the I2C bit
LDOx_ILIM_FLTMSK.
Input Capacitor Selection
Each LDO requires a high quality, low-ESR, ceramic
input capacitor. A 1uF is typically suitable, but this value
can be increased without limit. The input capacitor is
should be a X5R, X7R, or similar dielectric.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

PC BOARD LAYOUT GUIDANCE The AGND ground plane should be routed

separately from the other ground planes and only
Proper parts placement and PCB layout are critical to connect to the main ground plane under the IC at
the operation of switching power supplies. Follow the the AGND pin.
following layout guidelines when designing the
ACT88430 PCB. Refer to the Qorvo ACT88430 6. Connect the VIO_IN input capacitor to the AGND
Evaluation Kits for layout examples ground pin.

1. Place the buck input capacitors as close as possible 7. Connect the VIN input capacitor to the AGND
to the IC. Connect the capacitors directly to the ground pin.
corresponding VIN_Bx input pin and PGNDx power
ground pin. Avoid the use of vias if possible. 8. Remember that all open drain outputs need pullup
resistors.
2. Minimize the switch node trace length between
each SW_Bx pin and the inductor. Avoid routing 9. Connect the exposed pad directly the top layer
sensitive analog signals near these high frequency, ground plane. Connect the top layer ground plane
high dV/dt traces. to both internal ground planes and the PCB back-
side ground plane with thermal vias. Provide ground
3. Place the LDO input capacitors close to their input plane routing on multiple layers that allows the IC’s
pins. Connect their ground pins into the ground heat to flow into the PCB and then spread radially
plane that connects the IC’s exposed pad. from the IC. Avoid cutting the ground planes and
adding vias that restrict the radial flow of
4. The input capacitor and output capacitor grounds heat of operating conditions, and are relatively in-
should be connected as close together as possible, sensitive to layout considerations.
with short, direct, and wide traces.

5. Connect the PGNDx ground pins and the AGND

ground pin directly to the exposed pad under the IC.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

TYPICAL OPERATING CHARACTERISTICS

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Advanced PMU for Microcontrollers and Solid State Drive Applications

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI OPTIONS
This section provides the basic default configuration settings for each available ACT88430 CMI option. IC functionality
in this section supersedes functionality in the main datasheet. Generating the desired functionality for a custom CMI
sometimes requires reassigning internal resources, resulting in removal of base IC functionality. The following sections
attempt to describe any removed functionality from the base IC functionality. The user is required to fully test all required
functionality to ensure the CMI fully meets their requirements.

CMI 101: ACT88430QJ101-T

CMI 101 is optimized for the HiSilicon Hi3519 video processor. It is designed to operate from a 3V to 5V input voltage.

Voltage and Currents

Active Mode
DVS Voltage DVS Voltage Sleep Mode Current Limit
Rail Voltage Fsw (kHz)
VSET1(V) Trigger Voltage (V) (A)
VSET0 (V)
Buck1 0.95 0.95 n/a 0 4 1125

Buck2 0.95 0.95 n/a 0 2.5 1125

Buck3 0.95 0.95 n/a 0 2.5 1125

Buck4 1.2 1.1 GPIO 1.2 2.5 1125

LDO1 1.8 n/a n/a 1.8 0.8 n/a

LDO2 1.8 n/a n/a 1.8 0.2 n/a

LDO3 2.5 n/a n/a 2.5 0.2 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Rail Sequence Order Sequencing Input Trigger StartUp Delay (us) Soft-Start (us)
LDO1 1 PWREN 41 200

Buck4 1 PWREN 41 200

LDO2 1 PWREN 41 200

LDO3 1 PWREN 41 200

Buck1 2 RESET_AUX1 AND PWREN 41 323

Buck2 2 RESET_AUX1 AND PWREN 41 200

Buck3 2 RESET_AUX1 AND PWREN 41 126

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

CMI 101 Startup

VIN

PWREN

Buck4

LDO1

LDO2

LDO3

nRESET_AUX1

BUCK1

BUCK2

BUCK3

SLEEP Mode
Pull PWREN high to operate in ACTIVE mode. Pull PWREN low to operate in SLEEP. Outputs Buck4, LDO1/2/3 are on
in ACTIVE mode and off in SLEEP mode.

DVS Mode
GPIO is the DVS control input. When GPIO = H, the VSET0 register controls the buck converter output voltages. When
GPIO = L the VSET1 register controls the buck converter output voltages. Note that the default VSET0 and VSET1
settings are the same for each buck converter except Buck4. Buck 4 operates at 1.2V in ACTIVE mode and at 1.1V
when DVS is activated.

POK Thresholds
POK_UV = 2.8V
POK_OV = 5.5V

PG
The PG pin is triggered by Buck1.

POK
The POK pin is functional with CMI 101.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

EXT_EN
The EXT_EN pin is functional with CMI 101. Connect to the enable signal of an external power supply.

nRESET
nRESET is not functional with CMI 101. Leave nRESET floating.

nRESET_AUX1
The nRESET_AUX1 pin is programmed as a digital input. The nRESET_AUX1 input should default L when power is
applied to the IC. When nRESET_AUX1 = H, Buck1, Buck2, and Buck3 turn on. When nRESET_AUX1 = L, these
outputs turn off. Note that PWREN must be H before nRESET_AUX1 is pulled high.

nRESET_AUX2
The nRESET_AUX2 pin is not functional with CMI 101. Leave the nRESET_AUX2 pin floating.

EXT_PG
The EXT_PG pin is not functional with CMI 101. Leave the EXT_PG pin floating.

MODE
The MODE pin must be tied to ground.

GPIO
GPIO is the DVS control input. When GPIO = H, the VSET0 register controls the buck converter output voltages. When
GPIO = L the VSET1 register controls the buck converter output voltages. Note that the default VSET0 and VSET1
settings are the same for each buck converter except Buck4. Buck 4 operates at 1.2V in ACTIVE mode and at 1.1V
when DVS is activated.

Buck1/2/3 Voltage Setting

Buck1/2/3 reference voltage is 0.6V. This sets the allowable voltage range between 0.6V to 3.000V in 9.375mV steps.

LDO1/3 Voltage Setting

The LDO1/3 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.

LDO2 Voltage Setting

The LDO2 reference voltage is 0.6V. This sets the allowable voltage range between 0.8V to 2.375V in 25mV steps.

Device ID
The CMI 101 Device ID (register 0x7Dh) = 0x01h

I2C Address
The CMI 101 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 102: ACT88430QJ102-T

CMI 102 is optimized for a custom solid state disk (SSD) drive controller. It is designed to operate from a 3.3V input
voltage.

Voltage and Currents

Active Mode
DVS Voltage DVS Voltage Sleep Mode Current Limit
Rail Voltage Fsw (kHz)
VSET1(V) Trigger Voltage (V) (A)
VSET0 (V)
Buck1 0.7406 0.7406 EXT_PG n/a 5.3 2250

Buck2 0.8813 0.8813 EXT_PG n/a 4 2250

Buck3 1.8 1.8 EXT_PG n/a 3 2250

Buck4 1.2 1.2 EXT_PG n/a 3 2250

LDO1 0.9 n/a n/a n/a 1 n/a

LDO2 1.2 n/a n/a n/a 0.315 n/a

LDO3 2.5 n/a n/a n/a 0.39 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Rail Sequence Order Sequencing Input Trigger StartUp Delay (us) Soft-Start (us)
Buck1 1 GPIO 41 485

Buck2 2 Buck1 41 485

Buck3 3 Buck2 41 485

LDO1 4 Buck3 41 440

LDO2 5 LDO1 41 220

Buck4 6 LDO2 41 204

LDO3 7 Buck4 41 126

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

CMI 102 Startup

VIN

Buck1
41us

Buck2
41us

Buck3
41us

LDO1 41us

LDO2
41us

Buck4
41us

LDO3

1ms
nRESET

SLEEP Mode
CMI 102 does not use SLEEP Mode.

DVS Mode
EXT_PG is the DVS control input. When EXT_PG = L, the VSET0 register controls the buck converter output voltages.
When EXT_PG = H the VSET1 register controls the buck converter output voltages. Note that the default VSET0 and
VSET1 settings are the same for each buck converter.

POK Thresholds
POK_UV = 2.7V
POK_OV = 3.6V

PG
The PG pin is not functional with CMI 102. Leave the PG pin floating.

POK
The POK pin is not functional with CMI 102. Leave the POK pin floating.

EXT_EN
The EXT_EN pin is not functional with CMI 102. Leave the EXT_EN pin floating.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

nRESET
nRESET is triggered from LDO3. It goes high 1ms after LDO3 goes into regulation.

nRESET_AUX1
The nRESET_AUX1 pin is not functional with CMI 102. Leave the nRESET_AUX1 pin floating.

nRESET_AUX2
The nRESET_AUX2 pin is not functional with CMI 102. Leave the nRESET_AUX2 pin floating.

EXT_PG
EXT_PG is the DVS control input for Buck4. When EXT_PG = L, Buck4 = 1.8V. When EXT_PG = H, Buck4 = 1.2V

MODE
The MODE pin must be tied to ground.

GPIO
The GPIO pin is the input trigger for Buck1. When GPIO goes high, Buck1 turns on and starts the turn on sequencing.
When GPIO goes low, all outputs immediately turn off.

Buck1/2/3 Voltage Setting

Buck1/2/3 reference voltage is 0.6V. This sets the allowable voltage range between 0.6V to 3.000V in 9.375mV steps.

LDO1/3 Voltage Setting

The LDO1/3 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.

LDO2 Voltage Setting

The LDO2 reference voltage is 0.6V. This sets the allowable voltage range between 0.8V to 2.375V in 25mV steps.

Device ID
The CMI 102 Device ID (register 0x7Dh) = 0x00h

I2C Address
The CMI 102 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 105: ACT88430QJ105-T

CMI 105 is optimized for the Silicon Motion SM2258H SSD controller. The GPIOs are programmed to allow the
microprocessor to program the ACT88430 for different SM2258H low power operating modes. CMI 105 configured for
a 3.3V or 5V input voltage.

Voltage and Currents

Active
DVS Volt-
Mode Volt- DVS Voltage Sleep Mode Current
Rail age Fsw (kHz)
age Trigger Voltage (V) Limit (A)
VSET1 (V)
VSET0 (V)

Buck1 3.3 3.3 n/a 0 5.3 2250

Buck2 1.5 1.35 EXT_PG 0 3 2250

Buck3 1.8 1.2 GPIO 0 3 2250

Buck4 1.2 1.0 PWREN 1..0 3 1125

LDO1 3.3 n/a n/a 3.3 0.63 n/a

LDO2 1.8 n/a n/a 1.8 0.315 n/a

LDO3 1.8 n/a n/a 1.8 0.315 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Sequence Sequencing StartUp Soft-Start

Rail Order Input Trigger Delay (us) (us)
LDO1 1 UVLO 413 323

LDO2 2 LDO1 413 133

LDO3 2 LDO1 413 133

Buck4 3 LDO2 413 204

Buck1 4 Buck4 413 485

Buck3 5 Buck1 713 485

Buck2 6 Buck3 713 485

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

SLEEP Mode
Pull PWREN high to operate in ACTIVE mode. Pull PWREN low to operate in SLEEP. Outputs Buck1/2/3 are on in
ACTIVE mode and off in SLEEP mode.

DVS Mode
This CMI does not have true DVS functionality. See the different GPIO functions to see which ones control a buck
converter’s output voltage.

POK Thresholds
POK_UV = 2.77V
POK_OV = 5.5V

PG
The PG pin is not used and should be pulled to GND.

POK
The POK pin is not used and should be pulled to GND.

EXT_EN
The EXT_EN pin is not used and should be pulled to GND.

nRESET
The nRESET pin is not used and should be pulled to GND.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

nRESET_AUX1
The nRESET_AUX1 pin is programmed as an open drain output. It goes high 1989us after Buck2 goes into regulation.
Set register 0x01h bit 7 to 1 if nRESET_AUX1 needs to stay high when the IC enters SLEEP Mode.

nRESET_AUX2
The nRESET pin is not used and should be pulled to GND.

EXT_PG
EXT_PG is configured as an input to select the Buck2 output voltage. When EXT_PG is L, VSET0 sets Buck2 to 1.5V.
When EXT_PG is H, VSET1 sets Buck2 to 1.35V.

MODE
The MODE pin configures Buck1 into either bypass or switcher mode. Connect MODE to AGND to configure Buck1
into switcher mode when VIN=5V. Connect MODE to VIN to configure Buck1 into bypass mode when VIN=3.3V.

GPIO
GPIO is configured as an input to select the Buck3 output voltage for different NAND memory voltages. When GPIO3
is H, VSET0 sets Buck3 to 1.8V. When GPIO3 is L, VSET1 sets Buck3 to 1.2V.

PWREN
PWREN is configured as an input. When PWREN = H, the IC operates in Active Mode. When PWREN = L, the IC
operates in SLEEP Mode. Note that Buck4 = 1.2V in Active Mode and 1.0V in SLEEP Mode.

Buck1/3 Voltage Setting

Buck1/3 reference voltage is 0.8V. This sets the programmable voltage range between 0.8V to 3.998V in 12.5mV
steps.

Buck2 Voltage Setting

Buck2 reference voltage is 0.6V. This sets the programmable voltage range between 0.6V to 3.000V in 9.375mV
steps.

LDO1 Voltage Setting

The LDO1 reference voltage is 0.8V. This sets the programmable voltage range between 2.0V to 3.575V in 25mV
steps.

LDO2/3 Voltage Setting

The LDO2/3 reference voltage is 0.6V. This sets the allowable voltage range between 0.8V to 2.375V in 25mV steps.

Device ID
The CMI 105 Device ID (register 0x7Dh) = 0x05h

I2C Address
The CMI 105 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 106: ACT88430VM106-T

CMI 106 is optimized for SMI’s SM2258 solid state disk (SSD) drive controller. It is designed to operate from a 3.3V
input voltage.

Voltage and Currents

Active Mode
DVS Voltage DVS Voltage Sleep Mode Current Limit
Rail Voltage Fsw (kHz)
VSET1(V) Trigger Voltage (V) (A)
VSET0 (V)
Buck1 3.3 n/a n/a OFF 5.3 n/a

Buck2 1.15 1.15 PWREN 1.15 3 2250

Buck3 1.5 1.35 EXT_PG OFF 3 2250

Buck4 1.2 1.8 GPIO OFF 3 2250

LDO1 3.3 n/a n/a 3.3 0.35 n/a

LDO2 1.8 n/a n/a OFF 0.315 n/a

LDO3 OFF n/a n/a OFF n/a n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Rail Sequence Order Sequencing Input Trigger StartUp Delay (us) Soft-Start (us)
LDO1 1 VIN_UVLO 41 500

LDO2 2 LDO1 713 220

Buck2 3 LDO2 713 485

Buck1 4 Buck2 513 n/a

Buck4 5 Buck1 513 204

Buck3 6 Buck4 713 485

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

CMI 106 Startup

VIN

LDO1 713us

LDO2 713us

Buck2 513us

Buck1 513us

Buck4 713us

Buck3
2ms

nRESET_AUX1

SLEEP Mode
Pull PWREN high to operate in ACTIVE mode. Pull PWREN low to operate in SLEEP. Outputs Buck1/3/4 are on in
ACTIVE mode and off in SLEEP mode.

DVS Mode
PWREN is the DVS control input for Buck2. When PWREN = L, the VSET0 register controls the Buck2 converter output
voltage to 1.15V. When PWREN = H the VSET1 register controls the Buck2 converter output voltage to 1.15V. Note
that the default VSET0 and VSET1 settings are the same for Buck2 converter. These can be changed via I2C after
startup.
EXT_PG is the DVS control input for Buck3. When EXT_PG = L, the VSET0 register controls the Buck3 converter
output voltage to 1.5V. When EXT_PG = H the VSET1 register controls the Buck3 converter output voltage to 1.35V.
GPIO is the DVS control input for Buck4. When EXT_PG = L, the VSET1 register controls the Buck4 converter output
voltage to 1.8V. When GPIO = H the VSET0 register controls the Buck4 converter output voltage to 1.2V.

POK Thresholds
POK_UV = 2.7V
POK_OV = 3.6V

PG
The PG pin is not functional with CMI 106. Leave the PG pin floating.

POK

The POK pin is not functional with CMI 106. Leave the POK pin floating.

EXT_EN

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

The EXT_EN pin is not functional with CMI 106. Leave the EXT_EN pin floating.
nRESET
nRESET is not functional with CMI 106. Leave the nRESET pin floating.

nRESET_AUX1
The nRESET_AUX1 is triggered from Buck3. It goes high 2ms after Buck3 goes into regulation.

nRESET_AUX2
The nRESET_AUX2 pin is not functional with CMI 106. Leave the nRESET_AUX2 pin floating.

EXT_PG
EXT_PG is the DVS control input for Buck3. When EXT_PG = L, Buck4 = 1.5V. When EXT_PG = H, Buck4 = 1.35V.

MODE
The MODE pin must be pulled high.

GPIO
The GPIO pin is the DVS control input for Buck4. When GPIO = L, Buck4 = 1.8V. When GPIO = H, Buck4 = 1.2V.

Buck1/2/3 Voltage Setting

Buck1/2/3 reference voltage is 0.8V. This sets the allowable voltage range between 0.8V to 3.988V in 12.5mV steps.

LDO1 Voltage Setting

LDO1 is configured as load switch with CMI106.

LDO2/3 Voltage Setting

The LDO2/3 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.
Note that LDO3 is off by default, but can be enabled via I2C.

Device ID
The CMI 106 Device ID (register 0x7Dh) = 0x06h

I2C Address
The CMI 106 7-bit I2C address is 0x5Ah. This results in 0xB4h for a write address and 0xB5h for a read address.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 109: ACT88430VM109-T

CMI 109 is optimized for general purpose evaluation. It is designed to operate from a 3.3V input voltage.

Voltage and Currents

Active Mode
DVS Voltage DVS Voltage Sleep Mode Current Limit
Rail Voltage Fsw (kHz)
VSET1(V) Trigger Voltage (V) (A)
VSET0 (V)
Buck1 2.5 2.5 n/a OFF 5.3 n/a

Buck2 0.75 0.9 PWREN 0.75 3 2250

Buck3 1.5 1.35 EXT_PG OFF 3 2250

Buck4 1.2 1.8 GPIO OFF 3 2250

LDO1 2.5 n/a n/a 2.5 0.35 n/a

LDO2 1.8 n/a n/a 1.8 0.315 n/a

LDO3 2.5 n/a n/a OFF 0.315 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Rail Sequence Order Sequencing Input Trigger StartUp Delay (us) Soft-Start (us)
LDO1 1 VIN_UVLO 41 226

LDO2 2 LDO1 713 220

Buck2 3 LDO2 713 388

Buck1 4 Buck2 513 485

Buck4 5 Buck1 513 485

Buck3 6 Buck4 713 485

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

CMI 109 Startup

VIN

LDO1 713us

LDO2 713us

Buck2 513us

Buck1 513us

Buck4 713us

Buck3
2ms

nRESET_AUX1

SLEEP Mode
Pull PWREN high to operate in ACTIVE mode. Pull PWREN low to operate in SLEEP. Outputs Buck1/3/4 are on in
ACTIVE mode and off in SLEEP mode.

DVS Mode
PWREN is the DVS control input for Buck2. When PWREN = L, the VSET0 register controls the Buck2 converter output
voltage to 0.75V. When PWREN = H the VSET1 register controls the Buck2 converter output voltage to 0.9V.
EXT_PG is the DVS control input for Buck3. When EXT_PG = L, the VSET0 register controls the Buck3 converter
output voltage to 1.5V. When EXT_PG = H the VSET1 register controls the Buck3 converter output voltage to 1.35V.
GPIO is the DVS control input for Buck4. When DVS = L, the VSET1 register controls the Buck4 converter output
voltage to 1.8V. When GPIO = H the VSET0 register controls the Buck4 converter output voltage to 1.2V.

POK Thresholds
POK_UV = 2.77V
POK_OV = 3.76V

PG
The PG pin is configured as the Buck3 POK output.

POK

The POK pin is configured as the VIN POK functionality.

EXT_EN
The EXT_EN pin is not functional with CMI 109. Leave the EXT_EN pin floating.
nRESET

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

nRESET is triggered from all output’s internal POK signals with a 998us delay.

nRESET_AUX1
The nRESET_AUX1 is triggered all outputs’ internal POK signals with a 1989us delay.

nRESET_AUX2
The nRESET_AUX2 pin is configured to go low when the IC enters SLEEP mode.

EXT_PG
EXT_PG is the DVS control input for Buck3. When EXT_PG = L, the VSET0 register controls the Buck3 converter
output voltage to 1.5V. When EXT_PG = H the VSET1 register controls the Buck3 converter output voltage to 1.35V.

MODE
The MODE pin must be connected to AGND.

GPIO
GPIO is the DVS control input for Buck4. When GPIO = L, the VSET1 register controls the Buck4 converter output
voltage to 1.8V. When GPIO = H the VSET0 register controls the Buck4 converter output voltage to 1.2V.

Buck1/2/3 Voltage Setting

Buck1/3 reference voltage is 0.8V. This sets the allowable voltage range between 0.8V to 3.988V in 12.5mV steps.
Buck2 reference voltage is 0.6V. This sets the allowable voltage range between 0.6V to 3.000V in 9.375mV steps.

LDO1 Voltage Setting

LDO1 is configured as an LDO with CMI109. It can be configured between 2.0V to 3.575V in 25mV steps.

LDO2 Voltage Setting

The LDO2 reference voltage is 0.6V. This sets the allowable voltage range between 0.8V to 2.375V in 25mV steps.

LDO3 Voltage Setting

The LDO2 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.

Device ID
The CMI 109 Device ID (register 0x7Dh) = 0x09h

I2C Address
The CMI 109 7-bit I2C address is 0x5Ah. This results in 0xB4h for a write address and 0xB5h for a read address.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 113: ACT88430QJ113-T

CMI 113 is optimized for the Innogrit Rainier IG5236 SSD controller. Buck3 is set to 1.2V to power DDR4 memory. This
is very similar to the ACT88430QJ114-T which has Buck3 set to 1.1V to power LPDDR4. The GPIOs are programmed
to allow the microprocessor to program the ACT88430 for different IG5236 low power operating modes. CMI 113
configured for a 3.3V input voltage.

Voltage and Currents

Active
DVS Volt-
Mode Volt- DVS Voltage Sleep Mode Current
Rail age Fsw (kHz)
age Trigger Voltage (V) Limit (A)
VSET1 (V)
VSET0 (V)

Buck1 3.0 2.5 n/a 0 5.3 2250

Buck2 0.9 0.8 GPIO 0.8 4 2250

Buck3 1.2 1.2 n/a 0 4 2250

Buck4 1.2 1.2 n/a 0 4 2250

LDO1 1.2 n/a n/a 1.2 0.5 n/a

LDO2 2.5 n/a n/a 0 0.315 n/a

LDO3 1.8 n/a n/a 1.8 0.315 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Sequence Sequencing StartUp Soft-Start

Rail Order Input Trigger Delay (us) (us)
Buck2 1 UVLO 313 485

LDO2 1 UVLO 313 220

LDO3 1 UVLO 313 126

LDO1 2 UVLO 713 570

Buck1 3 Buck2 413 485

Buck3 4 Buck1 313 485

Buck4 5 Buck1 513 204

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

SLEEP Mode
Pull PWREN high to operate in ACTIVE mode. Pull PWREN low to operate in SLEEP. Outputs Buck1/3/4 and LDO2
are on in ACTIVE mode and off in SLEEP mode.

DVS Mode
This CMI does not have true DVS functionality. See the different GPIO functions to see which ones control a buck
converter’s output voltage.

POK Thresholds
POK_UV = 2.77V
POK_OV = 3.76V

PG
The PG pin is not used and can be left open or pulled to GND.

POK
The POK pin configured for standard POK functionality.

EXT_EN
The EXT_EN pin is not used and should be left open.

nRESET
The nRESET pin is not used and should be pulled to GND.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

nRESET_AUX1
The nRESET_AUX1 pin is programmed as an open drain output. It goes high 1989us after LDO1 goes into regulation.

nRESET_AUX2
The nRESET pin is not used and should be pulled to GND.

EXT_PG
EXT_PG is configured as an input to select the Buck1 output voltage. When EXT_PG is L, VSET0 sets Buck1 to 3.0V.
When EXT_PG is H, VSET1 sets Buck1 to 2.5V.

MODE
The MODE pin configures Buck1 into either bypass or switcher mode. MODE must be connected to AGND to
configure Buck1 into switcher mode.

GPIO
GPIO is configured as an input to select the Buck2 output voltage. When GPIO is H, VSET0 sets Buck2 to 0.8V. When
GPIO is L, VSET1 sets Buck2 to 0.9V.

PWREN
PWREN is configured as an input. When PWREN = H, the IC operates in Active Mode. When PWREN = L, the IC
operates in SLEEP Mode.

Buck1/3 Voltage Setting

Buck1/3 reference voltage is 0.8V. This sets the programmable voltage range between 0.8V to 3.998V in 12.5mV
steps.

Buck2 Voltage Setting

Buck2 reference voltage is 0.6V. This sets the programmable voltage range between 0.6V to 3.000V in 9.375mV
steps.

LDO1 Voltage Setting

The LDO1 reference voltage is 0.8V. This sets the programmable voltage range between 2.0V to 3.575V in 25mV
steps.

LDO2/3 Voltage Setting

The LDO2/3 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.

Device ID
The CMI 113 Device ID (register 0x7Dh) = 0x13h

I2C Address
The CMI 113 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 114: ACT88430QJ114-T

CMI 114 is optimized for the Innogrit Rainier IG5236 SSD controller. Buck3 is set to 1.1V to power LPDDR4 memory.
This is very similar to the ACT88430QJ113-T which has Buck3 set to 1.2V to power DDR4. The GPIOs are programmed
to allow the microprocessor to program the ACT88430 for different IG5236 low power operating modes. CMI 114
configured for a 3.3V input voltage.

Voltage and Currents

Active
DVS Volt-
Mode Volt- DVS Voltage Sleep Mode Current
Rail age Fsw (kHz)
age Trigger Voltage (V) Limit (A)
VSET1 (V)
VSET0 (V)

Buck1 3.0 2.5 n/a 0 5.3 2250

Buck2 0.9 0.8 GPIO 0.8 4 2250

Buck3 1.1 1.1 n/a 0 4 2250

Buck4 1.2 1.2 n/a 0 4 2250

LDO1 1.2 n/a n/a 1.2 0.5 n/a

LDO2 1.8 n/a n/a 0 0.315 n/a

LDO3 1.8 n/a n/a 1.8 0.315 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Sequence Sequencing StartUp Soft-Start

Rail Order Input Trigger Delay (us) (us)
Buck2 1 UVLO 313 485

LDO2 1 UVLO 313 220

LDO3 1 UVLO 313 126

LDO1 2 UVLO 713 570

Buck1 3 Buck2 413 485

Buck3 4 Buck1 313 485

Buck4 5 Buck1 513 204

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

SLEEP Mode
Pull PWREN high to operate in ACTIVE mode. Pull PWREN low to operate in SLEEP. Outputs Buck1/3/4 and LDO2
are on in ACTIVE mode and off in SLEEP mode.

DVS Mode
This CMI does not have true DVS functionality. See the different GPIO functions to see which ones control a buck
converter’s output voltage.

POK Thresholds
POK_UV = 2.77V
POK_OV = 3.76V

PG
The PG pin is not used and can be left open or pulled to GND.

POK
The POK pin configured for standard POK functionality.

EXT_EN
The EXT_EN pin is not used and should be left open.

nRESET
The nRESET pin is not used and should be pulled to GND.

nRESET_AUX1

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

The nRESET_AUX1 pin is programmed as an open drain output. It goes high 1989us after LDO1 goes into regulation.

nRESET_AUX2
The nRESET pin is not used and should be pulled to GND.

EXT_PG
EXT_PG is configured as an input to select the Buck1 output voltage. When EXT_PG is L, VSET0 sets Buck1 to 3.0V.
When EXT_PG is H, VSET1 sets Buck1 to 2.5V.

MODE
The MODE pin configures Buck1 into either bypass or switcher mode. MODE must be connected to AGND to
configure Buck1 into switcher mode.

GPIO
GPIO is configured as an input to select the Buck2 output voltage. When GPIO is H, VSET0 sets Buck2 to 0.8V. When
GPIO is L, VSET1 sets Buck2 to 0.9V.

PWREN
PWREN is configured as an input. When PWREN = H, the IC operates in Active Mode. When PWREN = L, the IC
operates in SLEEP Mode.

Buck1/3 Voltage Setting

Buck1/3 reference voltage is 0.8V. This sets the programmable voltage range between 0.8V to 3.998V in 12.5mV
steps.

Buck2 Voltage Setting

Buck2 reference voltage is 0.6V. This sets the programmable voltage range between 0.6V to 3.000V in 9.375mV
steps.

LDO1 Voltage Setting

The LDO1 reference voltage is 0.8V. This sets the programmable voltage range between 2.0V to 3.575V in 25mV
steps.

LDO2/3 Voltage Setting

The LDO2/3 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.

Device ID
The CMI 114 Device ID (register 0x7Dh) = 0x14h

I2C Address
The CMI 114 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 118: ACT88430QJ118-T

CMI 118 is optimized for the Tenafe TF1000 SSD controller. CMI 118 configured for a 3.3V input voltage.

Voltage and Currents

Active
DVS Volt-
Mode Volt- DVS Voltage Sleep Mode Current
Rail age Fsw (kHz)
age Trigger Voltage (V) Limit (A)
VSET1 (V)
VSET0 (V)

Buck1 2.5 2.5 n/a 0 5.3 2250

Buck2 0.8 0.8 n/a 0.8 4 1125

Buck3 0.8 0.8 n/a 0.8 4 125

Buck4 1.8 1.2 POK 0 4 2250

LDO1 1.8 n/a n/a 1.8 1 n/a

LDO2 1.8 n/a n/a 1.8 0.315 n/a

LDO3 1.8 n/a n/a 1.8 0.315 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

EXT_PG n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Sequence Sequencing StartUp Soft-Start

Rail Order Input Trigger Delay (us) (us)
LDO1 1 UVLO 41 323

Buck2 2 LDO1 41 300

LDO2 3 Buck2 713 220

Buck3 4 LDO2 713 150

Buck1 5 Buck3 713 485

Buck4 6 Buck1 713 204

LDO3 7 I2C 41 64

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

SLEEP Mode
Pull PWREN high to operate in ACTIVE mode. Pull PWREN low to operate in SLEEP mode. Buck1/4 turn off in SLEEP
mode. Buck2/3 regulate to VSET1 in SLEEP mode.

DVS Mode
This CMI does not have true DVS functionality. See the different GPIO functions to see which ones control a buck
converter’s output voltage.

POK Thresholds
POK_UV = 2.77V
POK_OV = 3.76V

PG
The PG pin is not used and can be left open or pulled to GND.

POK
POK is configured as an input to select the Buck4 output voltage. When POK is L, VSET1 sets Buck4 to 1.2V. When
POK is H, VSET0 sets Buck1 to 1.8V.

EXT_EN
The EXT_EN pin is not used and should be left open.

nRESET
The nRESET pin is configured as the Buck2 POK open drain output with 0ms delay.

nRESET_AUX1
The nRESET_AUX1 pin is programmed as an open drain output. It goes high 1989us after Buck4 goes into regulation.

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

nRESET_AUX2
The nRESET pin is not used and can be pulled to GND or left floating.

EXT_PG
EXT_PG is configured as an input to enable Buck2. When EXT_PG is L, Buck2 is disabled. When EXT_PG is H, Buck2
is enabled. Note that LDO1 is the input trigger to turn Buck2 on. After Buck2 is in regulation, EXT_PG can then turn it
on and off.

MODE
The MODE pin configures Buck1 into either bypass or switcher mode. MODE must be connected to AGND to
configure Buck1 into switcher mode.

GPIO
GPIO is not used and must be connected to AGND.

PWREN
PWREN is configured as an input. When PWREN = H, the IC operates in Active Mode. When PWREN = L, the IC
operates in SLEEP Mode.

Buck1/4 Voltage Setting

Buck1/4 reference voltage is 0.8V. This sets the programmable voltage range between 0.8V to 3.998V in 12.5mV
steps.

Buck2/3 Voltage Setting

Buck2/3 reference voltage is 0.6V. This sets the programmable voltage range between 0.6V to 3.000V in 9.375mV
steps.

LDO1 Voltage Setting

The LDO1 reference voltage is 0.8V. This sets the programmable voltage range between 2.0V to 3.575V in 25mV
steps.

LDO2/3 Voltage Setting

The LDO2/3 reference voltage is 0.8V. This sets the allowable voltage range between 2.0V to 3.575V in 25mV steps.

Device ID
The CMI 118 Device ID (register 0x7Dh) = 0x18h

I2C Address
The CMI 118 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

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Advanced PMU for Microcontrollers and Solid State Drive Applications

CMI 120: ACT88430QJ120-T

CMI 120 is optimized for the i.MX6 processor. CMI 120 configured for a 5V input voltage.

Voltage and Currents

Active
DVS Volt-
Mode Volt- DVS Voltage Sleep Mode Current
Rail age Fsw (kHz)
age Trigger Voltage (V) Limit (A)
VSET1 (V)
VSET0 (V)

Buck1 3.8 3.8 n/a 0 5.3 2250

Buck2 1.35 1.35 n/a 0 2 2250

Buck3 1.3 1.3 n/a 0 2 2250

Buck4 3.3 3.3 n/a 0 4 2250

LDO1 3.3 n/a n/a 0 0.35 n/a

LDO2 3.3 n/a n/a 3.3 0.315 n/a

LDO3 3.15 n/a n/a 0 0.39 n/a

EXT_EN n/a n/a n/a n/a n/a n/a

Startup and Sequencing

Sequence Sequencing StartUp Soft-Start

Rail Order Input Trigger Delay (us) (us)
LDO2 1 UVLO 313 220

LDO1 2 EXT_PG 213 570

Buck2 3 LDO1 513 485

Buck3 4 Buck2 513 485

Buck4 5 Buck3 513 204

LDO3 6 Buck4 313 126

Buck1 7 GPIO 313 485

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Advanced PMU for Microcontrollers and Solid State Drive Applications

Startup

SLEEP Mode
SLEEP mode is not enabled. Pull PWREN to VCC.

DVS Mode
This CMI does not support DVS functionality.

POK Thresholds
POK_UV = 4.2V
POK_OV = 5.7V

PG
The PG pin is not used and can be left open or pulled to GND.

POK
The POK pin is not used and can be left open or pulled to GND.

EXT_EN
The EXT_EN pin is not used and can be left open or pulled to GND.

nRESET
The nRESET pin is programmed as an open drain output. It goes high 998us after LDO3 goes into regulation.

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Advanced PMU for Microcontrollers and Solid State Drive Applications

nRESET_AUX1
The nRESET_AUX1 pin is programmed as an open drain output. It goes high 1989us after Buck4 goes into regulation.

nRESET_AUX2
The nRESET pin is not used and should be pulled to GND.

EXT_PG
EXT_PG is configured as an input to turn on LDO1 to start the turn on sequence. When EXT_PG is L, LDO1 is disabled.
When EXT_PG is H, LDO1 is enabled.

MODE
The MODE pin configures Buck1 into either bypass or switcher mode. MODE must be connected to AGND to
configure Buck1 into switcher mode.

GPIO
GPIO is configured as an input to turn on Buck1. When GPIO is H, Buck1 is disabled. When GPIO is H, Buck1 is
enabled.

PWREN
PWREN is not used and must be connected to VCC.

Buck1/2/3/4 Voltage Setting

Buck1/2/3/4 reference voltage is 0.8V. This sets the programmable voltage range between 0.8V to 3.998V in 12.5mV
steps.

LDO1/2/3 Voltage Setting

The LDO1/2/3 reference voltage is 0.8V. This sets the programmable voltage range between 2.0V to 3.575V in 25mV
steps.

Device ID
The CMI 120 Device ID (register 0x7Dh) = 0x20h

I2C Address
The CMI 120 7-bit I2C address is 0x53h. This results in 0xA6h for a write address and 0xA7h for a read address.

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Advanced PMU for Microcontrollers and Solid State Drive Applications

PACKAGE OUTLINE AND DIMENSIONS

Top View Bottom View

Side View

Notes

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ACT88430
Advanced PMU for Microcontrollers and Solid State Drive Applications

PACKAGE OUTLINE AND DIMENSIONS

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Advanced PMU for Microcontrollers and Solid State Drive Applications

Product Compliance
This part complies with RoHS directive 2011/65/EU as amended by (EU) 2015/863.

This part also has the following attributes:

• Lead Free
• Halogen Free (Chlorine, Bromine) Pb

Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations:
Web: www.qorvo.com Tel: 1-844-890-8163
Email: [email protected]

For technical questions and application information:

Email: [email protected]

Important Notice
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herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained
herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders
for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any
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SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE,
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medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause
severe personal injury or death.

Copyright 2019 © Qorvo, Inc. | Qorvo®, Active-Semi®, Power Application Controller®, Solutions for Sustainability™, Micro Application
Controller™, Multi-Mode Power Manager™, Configurable Analog Front End™ and Application Specific Power Drivers™ are
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ARM® is a registered trademark and Cortex™ is a trademark of ARM Limited. All referenced brands and trademarks are the property
of their respective owners.

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