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Iotuni 21

The document discusses the 8255A programmable peripheral interface chip which has three 8-bit I/O ports that can be configured in different modes. It describes the features and architecture of the 8255A including the pin diagram and functionality of the pins. The document also briefly introduces the 8253/8254 programmable interval timers.

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Ashwin Benke
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31 views

Iotuni 21

The document discusses the 8255A programmable peripheral interface chip which has three 8-bit I/O ports that can be configured in different modes. It describes the features and architecture of the 8255A including the pin diagram and functionality of the pins. The document also briefly introduces the 8253/8254 programmable interval timers.

Uploaded by

Ashwin Benke
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SEC1312 MICROPROCESSOR AND MICROCONTROLLERBASED SYSTEMS

UNIT 3

8255A - Programmable Peripheral Interface


The 8255A is a general purpose programmable I/O device designed to transfer the data from
I/O to interrupt I/O under certain conditions as required. It can be used with almost any
microprocessor.

It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per
the requirement.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.

 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.

 Port B is similar to PORT A.

 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.

These three ports are further divided into two groups, i.e. Group A includes PORT A and
upper PORT C. Group B includes PORT B and lower PORT C. These two groups can be
programmed in three different modes, i.e. the first mode is named as mode 0, the second
mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes
8255A has three different operating modes −

 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-
bit ports. Each port can be programmed in either input mode or output mode where
outputs are latched and inputs are not latched. Ports do not have interrupt capability.

 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be
configured as either input or output ports. Each port uses three lines from port C as
handshake signals. Inputs and outputs are latched.

 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake
signals for data transfer. The remaining three signals from Port C can be used either
as simple I/O or as handshake for port B.

Features of 8255A
SEC1312 MICROPROCESSOR AND MICROCONTROLLERBASED SYSTEMS

UNIT 3

The prominent features of 8255A are as follows −

 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.

 Address/data bus must be externally demux'd.

 It is TTL compatible.

 It has improved DC driving capability.

8255 Architecture
The following figure shows the architecture of 8255A −

Let us first look at the pin diagram of Intel 8255A −


SEC1312 MICROPROCESSOR AND MICROCONTROLLERBASED SYSTEMS

UNIT 3

Now let us discuss the functional description of the pins in 8255A.

Data Bus Buffer


It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data
bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control
words and status information is also transferred using this bus.

Read/Write Control Logic


This block is responsible for controlling the internal/external transfer of data/control/status
word. It accepts the input from the CPU address and control buses, and in turn issues
command to both the control groups.

CS
It stands for Chip Select. A LOW on this input selects the chip and enables the
communication between the 8255A and the CPU. It is connected to the decoded address,
and A0 & A1 are connected to the microprocessor address lines.

Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B
SEC1312 MICROPROCESSOR AND MICROCONTROLLERBASED SYSTEMS

UNIT 3

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

WR
It stands for write. This control signal enables the write operation. When this signal goes
low, the microprocessor writes into a selected I/O port or control register.

RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.

RD
It stands for Read. This control signal enables the Read operation. When the signal is low,
the microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table
showing their various signals with their result.

A1 A0 RD WR CS Result

0 0 0 1 0 Input Operation

PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B


SEC1312 MICROPROCESSOR AND MICROCONTROLLERBASED SYSTEMS

UNIT 3

1 1 1 0 0 Data Bus → PORT D

Intel 8253/54 - Programmable Interval Timer


The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
microprocessors to perform timing and counting functions using three 16-bit registers. Each
counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a
counter, a 16-bit count is loaded in its register. On command, it begins to decrement the
count until it reaches 0, then it generates a pulse that can be used to interrupt the CPU.

Difference between 8253 and 8254


The following table differentiates the features of 8253 and 8254 −

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

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