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Low Parasitics Planar Transformer For LLC Resonant Battery Chargers

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Low Parasitics Planar Transformer For LLC Resonant Battery Chargers

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This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2602360, IEEE
Transactions on Power Electronics

LLC Converters with Planar Transformers: Issues

and Mitigation
Mohammad Ali Saket, Student Member, IEEE, Navid Shafiei, Student Member, IEEE, Martin
Ordonez, Member, IEEE

Abstract—The use of LLC resonant converters has gained to compact power converters. The main obstacle in high frequency
popularity in multiple applications that require high conversion operation is switching losses that limits the operating frequency
efficiency and galvanic isolation. In particular, many appli- of classical DC-DC PWM hard-switching converters. In order
cations like portable devices, Flat TVs, and electric vehicle to resolve this issue, soft switching techniques have emerged
battery chargers require demanding slim-profile packaging and that minimize the switching loss and allow working in higher
enforce the use of Planar Transformers (PTs) with low-height, frequencies [1–4]. Among different soft-switched converters, the
low leakage inductance, excellent thermal characteristics, and LLC resonant converter offers many advantages including high
manufacturing simplicity. The main challenge in successfully part-load efficiency, no-load voltage regulation, high gain range
designing LLC converters with PT resides in controlling high over narrow frequency variation, inherent short circuit capability,
parasitic capacitances produced by large overlapping layers and good cross regulation [5]. Currently, there are many appli-
in PT windings. When the parasitic capacitances are not cations that require high power density and low profile power
controlled, they severely impair the converters’ performance converters. These applications include and are not limited to
and regulation, and limit the application of PTs in high consumer electronics (portable devices like laptops and cellphones,
frequency LLC converters. This paper characterizes the PT Flat TVs), automotive industry (electric vehicle battery chargers
capacitance issue in detail and proposes mitigation strategies and powering), telecom (servers), space and military applications
to improve the performance of LLC converters with PTs. A (where rugged and compact power supplies are required). In a
systematic analysis is performed, and six PT winding layouts high-frequency LLC converter, magnetic components often are
are introduced and benchmarked with a traditional design. the bulkiest parts, and they determine the overall height of the
As a result of the investigation, an optimized structure is converter [6]. Due to the height of traditional magnetic cores,
obtained, which minimizes both inter-winding capacitance and the form factor of LLC chargers is often plump and bulky. In
AC resistance, while improving the regulation performance of order to implement slim profile converters for the abovementioned
LLC converters. Experimental measurements are presented applications, planar transformers (PTs) can be used featuring low
and show a significant reduction of parasitic capacitance height, reproducibility, lower leakage inductance and low thermal
by up to 21.2 intra- and 16.6 inter-winding capacitances, resistance [7, 8].
without compromising resistance. This substantial capacitance Despite the promising low profile and manufacturing advan-
reduction has a tangible effect on the regulation performance of tages of PTs, their inherent high parasitic capacitances result in
LLC resonant converters. Experimental results of the proposed severe problems for LLC converters. Fig. 1 (a) presents an LLC
PT structure in a 1.2 kW LLC resonant converter show resonant converter schematic and includes the parasitic elements
a reduction in common-mode (CM) noise, extended output of the transformer (leakage inductances, winding resistances, and
voltage regulation, and improved overall efficiency of the parasitic capacitances). In particular, parasitic capacitances in the
converter. transformers can be divided into inter-winding and intra-winding
capacitors, which have a significant detrimental effect in LLC con-
verters as demonstrated in this work. The effect of distributed inter-
Index Terms - LLC resonant converter, voltage regulation,
winding capacitance can be modeled by four capacitors between
planar transformer, parasitic capacitance, common-mode
primary and secondary ports of the transformer which are shown in
noise,Finite element analysis (F EA).
red color in Fig. 1 (a). The high inter-winding capacitance between
primary and secondary provides an undesired low impedance path
for CM noise, contributing to EMI issues. Complying with EMI
I. I NTRODUCTION standards requires significant effort to reduce common mode EMI
Growing interests for higher power density and low profile in noise, especially if the noise level is high. Usually, high EMI
many low and medium power applications has forced designers to noise requires bulkier filter that consequently increase the volume
increase switching frequencies. Increasing the frequency reduces and cost of the system. In isolated power supplies, reducing inter-
the size of passive elements like transformers and inductors, leading winding capacitance decreases CM noise amplitude significantly,
simplifies the filter design and shrink the total filter size. On
This work was supported by the Natural Sciences and Engineering the other hand, the distributed intra-winding capacitance can be
Research Council (NSERC), CANADA. M. A. Saket, N. Shafiei and M. modeled as a lumped capacitor between terminals of the coils.
Ordonez are with the Department of Electrical and Computer Engineering, These capacitors are showed with the purple color in the Fig. 1 (a).
The University of British Columbia, Vancouver, BC, V6T 1Z4, Canada The high intra-winding capacitance gives rise to a high charging
(e-mail: [email protected], [email protected], [email protected]). current at the transformer input, resulting in lower efficiency and

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2602360, IEEE
Transactions on Power Electronics

Transformer
C13
S1 C14

Ls ip Rac1 Llk1 Rac2 Llk2 is D5 D7 vo Llk

+ C
Vfc
C vp + C12 RC Lm C34 vs
- - Cstray Lm
S2 C24
D6 D8

C23
1

(a)

5
iLS
1
VTrans 2

t t
Full-Load
Light-Load

(b) (d)

Copper Traces
...
4
4 FHA Exp
FR4 } Secondary
Capacitance

PCB
...
3 Insulation
iCM iCM iCM iCM
Non-Operating Area

between primary
and secondary PCBs
...
ZCS Region
Voltage Gain

2
3
FR4
...
} Primary
PCB

Insulation
iCM iCM iCM iCM between primary
1 and secondary PCBs
...

0
FR4
...
} Secondary
PCB
fr,oc
fr,sc

0 1 2 3
Normalized Frequency
(c) (e)
Fig. 1: (a) The LLC resonant converter considering parasitic elements of the transformer and one capacitor model of the transformer 1
(b) Transformer distorted no-load voltage due to the stray capacitance 2 , (c) The no-load voltage gain characteristics of the converter
with different transformers: Unfortunate increase of voltage 3 and deviation of experimental characteristics from FHA prediction with
high stray capacitance 4 (d) CM noise problem due to the inter-winding capacitance 5 , (e) A portion of the transformer consisting of
one primary PCB and two secondary PCBs (each PCB is a double layer PCB). The insulation between layers can be FR4, Kapton, or
any other material that can provide insulation. This figure shows CM noise currents that result from distributed parasitic capacitances
between primary and secondary traces.

increased peak voltage stress across secondary rectifying devices light-load current and voltage waveforms of the converter, leading
[14]. In addition to those problems, parasitic capacitances also to an unpredictable behaviour of output voltage which cannot be
bring unwanted regulation issues for LLC resonant converters with seen by First harmonic approxiamation (FHA). A typical waveform
wide output regulation. Voltage regulation is a critical specification of transformer voltage in this condition is presented in Fig. 1 (b).
in power converters to accommodate input voltage fluctuations Since the requirement of applying FHA in resonant converters is
(e.g., line regulation) or output voltage changes (e.g., battery charg- having square shape voltage and sinusoidal current of the same
ers). High parasitic capacitance of transformer severely distorts the frequency, applying FHA under this condition leads to inaccurate

results. Solid and dashed curves in Fig. 1 (c) present the light- problem along high full load efficiency still is missing in the
loading voltage gain characteristics of the LLC resonant converter literature.
with experimental measurements and FHA for different values of This paper characterizes PT capacitance issue in detail and
stray capacitance, respectively. The solid curves clearly show that proposes mitigation strategies to improve the performance of LLC
large parasitic capacitances leads to an unpredictable behavior of converters with PTs. A systematic analysis is performed, and six PT
output voltage and therefore, loss of the regulation. This figure winding layouts are introduced and benchmarked with a traditional
also shows that although FHA can predict an unfortunate increase design. As a result of the investigation, an optimized transformer
in the voltage gain due to the parasitic capacitances which limit the is obtained to minimize PT parasitic capacitance while maintaining
ability of the converter to handles low conversion ratios (e.g., low low AC resistance. For each proposed winding layout, the analyt-
output voltages or high input voltage), it fails to accurately predict ical equations describing the parasitic capacitance are found, and
the output voltage. As it is mentioned before, this discrepancy in the advantages and disadvantages of each layout are presented.
the results are due to parasitic capacitances that distort the voltage In addition to the proposed winding layouts and arrangement, a
and current waveforms and lead to regulation problems for LLC comprehensive procedure to extract all parasitic elements of PTs
resonant converters. It is worthy to mention that the FHA curves are are provided, which can be used to run Finite elements analysis
found by combining the effect of all parasitic capacitance into one (FEA) simulations of the electro- and magneto-static behavior of
parallel stray capacitance that is showed in Fig. 1 (a). The required PTs. Experimental results show that the proposed transformers have
equations for getting the value of this stray capacitance based on up to 21.2 and 16.6 times less intra- and inter-winding capacitance,
the six capacitors model of the transformer will be presented in the without compromising the resistance. This significant parasitic
next sections. Reducing the value of this capacitor can significantly capacitance reduction considerably improves the performance of
improve the situation and resolve the regulation problem. the converter. Experimental results of employing the proposed
During last few years, interesting research has been done to transformers in a 1.2 kW LLC resonant converter show that the
design high efficiency PT for LLC [8–20]. Most of these papers proposed transformers can successfully resolve both CM noise and
have focused on the AC resistance and leakage inductance, so the voltage regulation problem in the LLC resonant converter and
impact of transformer parasitic capacitance on the LLC voltage can regulate the output voltage even in the no-load condition. In
regulation is not covered which is the aim of this paper. Generally addition to these benefits, the converter efficiency increases due to
speaking, there is a trade-off between PT resistance and parasitic elimination of the parasitic capacitance.
capacitance. In order to have a high efficiency LLC converter This paper is organized into six Sections. In Section II, the
with wide output regulation, both parasitic capacitance and AC equivalent circuit of the transformer is studied, and a comprehen-
resistance should be minimized. It is interesting to note that the sive methodology to extract all parasitic elements with FEA is
root cause of LLC regulation problems using PTs has not been proposed. Section III proposes six improved winding layouts to
addressed in detail in the past. The strategies proposed in this paper strongly reduce the parasitic capacitance. Section IV is dedicated
provides a solution for light-loading regulation while ensuring high to finding an optimized structure of transformer concerning AC
efficiency under full load condition. Since the voltage regulation resistance and inter-winding capacitance. Section V provides ex-
problem of LLC resonant converter also can be aroused from perimental results and finally, the conclusion is presented in Section
the rectifier diode junction capacitance, [21–23] have developed VI.
methods to address this problem. The work in [21] developed a
higher order topology that can mitigate the effect of diode junction II. T RANSFORMER PARASITIC CALCULATION
capacitances for different modes of operation. Research in [22]
suggests that adding a dummy load can solve the problem for As describe in the introduction, high parasitic capacitances of the
small values of diode junction capacitance. The work in [23] transformer have severe detrimental effect on the voltage regulation
presents another mitigation strategy by adding a capacitor to and CM noise of the LLC resonant converter. In order to attain
the primary side. Although the prior methods are successful in high conversion efficiency and wider output regulation in LLC
resolving the regulation issue due to the diode junction capacitance, resonant converters, PT stray capacitances should be minimized
their effectivity is limited to the values in the range of diode as much as possible while keeping AC resistance low. To achieve
junction capacitance. Since the parasitic capacitance of PTs are these goals, a complete method is presented in this section to model
much larger, preceding methods cannot be used to resolve the of the electro- and magneto-static behavior of the transformer. A
regulation problem due to PTs parasitic capacitance. For instance, comprehensive study of transformer parasitic elements are pre-
the work in [8] reports stray capacitances in the order of few sented and a full procedure of getting the equivalent circuit using
nanoFarads for conventional PTs which results in serious regulation numerical methods are proposed with the objective of designing
problems in the LLC resonant converters. The work in [24] low parasitic PT to address regulation problems in LCC converters.
develops an interesting comb-shaped Faraday shield that reduces
the CM noise by roughly halving the inter-winding capacitance.
However, in order to mitigate the LLC voltage regulation problem, A. Parasitic Capacitance
the parasitic capacitance should be reduced more. The work in [25] While the transformer is a two-port system from the magne-
developed a minimized overlapping winding layout to reduce the tostatic perspective, the inter-winding capacitance between pri-
inter-winding capacitance. But the impact on the voltage regulation mary and secondary winding provides a path between primary
is not the focus of that work. In addition, no investigation of and secondary, making the transformer a three-port system from
DC and AC resistance of the layout was provided. Indeed, no the electrostatic standpoint [28]. For a three-port system, three
overlapping strategy leads to very high AC resistance which limits independent voltages and six capacitors are needed to model the
its usability in high-efficiency applications. Although many papers electrostatic behaviour of the system. Fig. 2 (a) shows one way of
have discussed different aspects of using PTs in LLC resonant selecting the independent voltages and the six capacitors model of
converter, a paper that resolve the light-loading voltage regulation the transformer.

C14 C13

n:1
V1 C12 C34 V2 V1 V2 Vo

C24
C23
Vo
(a) (b) (c) (d)
Fig. 2: Electrostatic behavior model of the transformer: (a) Six capacitors model with three independent voltages, (b), (c), and (d) the
required numerical analysis to find the six capacitors.

The total energy of the system can be found by summing the The analysis performed in Fig. 2 (d) requires a constant voltage
energies of the lumped capacitors. In this condition, the total energy on all turns of the secondary side and zero voltage on all turns of
of the system is equal to (1). the primary side. Constant Voltage on all turns of the secondary
1 1 1 1 side also is signified by a square beside that winding, which shows
Wt = C12 V12 + C34 V22 + C24 Vo2 + C14 (V1 − Vo )2 that there is no voltage difference between the terminals of the
2 2 2 2 (1) secondary side. Obtaining the value of the first three terms in (4) are
1 1
+ C23 (V2 + Vo ) + C13 (V1 − Vo − V2 )2
2
straightforward. The total electrostatic energy in the fig. 2 (b), (c)
2 2 and (d) are equal to the first, second, and, third terms, respectively.
By rearranging (1) based on voltages, (2) can be obtained. The remaining three components are found using superposition
theorem.
1 1
Wt = (C12 + C14 + C13 )V12 + (C34 + C23 + C13 )V22 Similar to (2), equation (4) indicates that the total energy is
2 2 composed of six components. Equating corresponding terms in (4)
1
+ (C24 + C14 + C23 + C13 )Vo2 + (−C14 − C13 )V1 Vo and (2), the expressions for finding the six capacitors are presented
2 in table I. Among the six capacitances, C13 , C14 , C23 , and C24 are
+ (C23 + C13 )V2 Vo + (−C13 )V1 V2 the inter-winding capacitances and C12 and C24 model the intra-
(2) winding capacitance of the windings. As it is mentioned before,
reducing the inter-winding capacitances can significantly attenuate
The total energy of the system also can be computed using
CM noise and enhance the performance of the converter.
electric fields. Since MAXWELL equations are linear, they satisfy
the superposition principle. In a system with three independent TABLE I: Equations describing parasitic capacitances based on the
voltages, like the one in Fig. 2 (a), the total electric field is equal to
#» #» #» #» #» field analysis
the sum of E1 , E2 , and Eo , corresponding with the voltages V1 , V2 ,
#»
and Vo . Therefore, the total electric field and electric displacement
Capacitor Equation
field in the system can be written as follows:
#» # » # » # » #» # » # » # » −1 #» # » #» # »
H
Et = E1 + E2 + E o Dt = D 1 + D2 + Do (3) C13 2V1 V2(E1 .D2 + E2 .D1 ) dV
V
−1
H #» # » #» # »
The total electrostatic potential energy may be expressed in terms C14 2V1 Vo V (E1 .Do + Eo .D1 ) dV − C13
of these fields in the form of following equation: H #» # » #» # »
1
#» #» #» # » # » # » C23 2V2 Vo V (E2 .Do + Eo .D2 ) dV − C13
I
1
Wt = (E1 + E2 + Eo ).(D1 + D2 + Do ) dV H #» # »
2 V C12 1
(E1 .D1 ) dV − C14 − C13
I
#» # » 1
I
#» # »
I
#» # » V12 V
1 1 H #» # »
= E1 . D 1 + E2 .D2 dV + Eo .Do dV 1
2 V 2 V 2 V C34 V22 V
(E2 .D2 ) dV − C13 − C23
#» # » #» # » #» # » #» # » #» # »
I I
1 1
+ (E1 .D2 + E2 .D1 ) dV + (E1 .Do + Eo .D1 ) dV 1
H
2 V 2 V C24 V 2 V (Eo .Do ) dV − C13 − C23 − C14
o
#» # » #» # »
I
1
+ (E2 .Do + Eo .D2 ) dV In order to evaluate the overal impact of parasitic capacitances
2 V
(4) on the voltage regulation, the six capacitors should be converted
to the one capacitor model of Fig. 3 (b). The expressions for
Numerical methods like FEA can be employed to calculate the calculating this capacitance depends on the connection of primary
energy with (4). Three different analyses are required to find all six and secondary windings and different offset voltages lead to
components which are presented in the Fig. 2 (b), (c) and, (d). The different expressions for this capacitance. For the case that there
cases presented in the Fig. 2 (b) and (c) require a linear voltage is no external connection between the primary and secondary
distribution on the turns of one winding, and zero voltage on all the windings, the offset voltage can be found and the six capacitors
turns of the other winding. The linear distribution of the voltage model can be reduced to the three capacitor model of Fig. 3 (a)
on turns of one side is signified by a triangle beside that winding. [28]. if the leakage inductances are negligible in comparison to the

formula to calculate the AC resistance that is presented in the (6).

Cps
ξ sinh(ξ) + sin(ξ)
1:k Rac = Rdc ×
+ 2 cosh(ξ) − cos(ξ)
Llk1 Llk2 +
sinh(ξ) − sin(ξ)
V1 Cp 2Lm Cs V2 + (2m − 1)2 × (6)
cosh(ξ) + cos(ξ)
- -
h F (h)
(a) ξ= m=
δ F (h) − F (0)
Where h is the thickness of traces, δ is the skin depth at the
Llk operating frequency, and F(h) and F(0) are the magneto-motive
Cstray Lm force (MMF) at the borders of conductor which depend on the
structure of the transformer. The first term in (6) is associated with
the skin effect and only depends on the ratio of tracks thickness
(b) to skin depth ξ. The second term in (6) represents the proximity
Fig. 3: (a) Three Capacitors model of the transformer referred to the effect and depends on two factors; ξ and m. The value of m
primary side and (b) single capacitance model of the transformer. depends on the MMF distribution and is a function of transformers
arrangement. It is very crucial to limit the value of m because
the proximity effect can increase exponentially and dominate AC
resistance. Low m values are achieved in the interleaved structures,
magnetizing inductance, the three capacitor model of Fig. 3 (a) can where large leakage fluxes are avoided. When the windings are
be simplified further to the one capacitor model of Fig. 3 (b) [26]. in series, the currents in the windings are the same, yielding in
Under this condition, the expression for the stray capacitance in the same magnetic fields along each layer. Under this condition,
this circuit has been presented in 5. the MMF distribution changes linearly and is predictable. Due
to the predictability of MMF distribution, equation (6) could be
(C14 C23 − C13 C24 ) used to predict AC resistance. However, When the windings are
Cstray = C12 + k2 C34 + 2k
C13 + C14 + C23 + C24 in parallel, the currents in each winding layer may not be equally

(C14 + C13 )(C23 + C24 ) + k2 (C13 + C23 )(C14 + C24 )
distributed due to the leakage fluxes and the high-frequency eddy
+ current effect. On the other hand, AC resistance of each winding
C13 + C14 + C23 + C24 is a function of current distribution. This mutual dependency
(5) makes it complex to analytically find MMF distribution for parallel
Where k is the transformer turns ratio. (5) shows that both intra- layers. Besides, With the parallel connection of windings, it is also
and inter-winding capacitances contribute to the parallel stray possible that circulating currents exist in the parallel layers, causing
capacitance which leads to regulation problems. Therefore, both additional winding loss. As a result, numerical methods like FEA
types of capacitances should be minimized to reduce the value of should be used in this condition to find the most optimum structure
this capacitance and solve the voltage regulation problem in the with the lowest resistance.
LLC resonant converter. Neglecting the capacitive effects, the transformer is a two port
Equation (5) and table I are useful tools in designing low para- system whose equivalent circuit is shown in the Fig. 4 (a). For a
sitic capacitance PTs for LLC resonant converter. These equations two-port system, the relationship between primary and secondary
can be used along FEA to investigate the parasitic capacitance of voltages and currents can be represented by a 2 × 2 matrix.
any design. Regarding CM noise, these equations split the inter- However, finding the matrix impedance of Fig. 4 (a) is not
winding capacitance to the four capacitors of C13 , C14 , C23 and, straightforward. Thus, a minor circuit transform is required to get
C24 which is a great advantage in CM noise modeling. Regarding the impedance matrix. The parallel core resistance and magnetizing
the voltage regulation problem, (5) can be used to evaluate the inductance can be converted to the series from using (7). Fig 4 (b)
value of parallel stray capacitance and avoid the problem of voltage shows the modified equivalent circuit.
regulation in the LLC resonant converters.
Q2 1 ωLm
Lms = ×Lm , Rcs = 2 ×Rc , Q = (7)
Q2 +1 Q +1 Rc
The matrix representation of this circuit is expressed in 8 and 9.
B. AC Resistance and Leakage Inductance Modeling
R11 + sL11 R12 + sL12

Z= (8)
R21 + sL21 R22 + sL22
In order to design an optimized PT for LLC resonant converter,
not only the parasitic capacitances should be minimized, but Where
also the AC resistance and leakage inductance of the transformer
R11 + sL11 = (Rac1 + Rcs ) + S(Llk1 + Lms )
should be kept low. Therefore, it is also important to define a
procedure for finding the AC resistance and leakage inductance of 1
R12 + sL12 = R21 + sL21 = (Rcs + SLms ) (9)
the transformer. In addition to the analytical equations, a procedure n
of extracting the value of these parasitic elements using numerical 1 1
R22 + sL22 = (Rac2 + 2 Rcs ) + S(Llk2 + 2 Lms )
tools also is presented. n n
AC resistance in high frequencies depends on the skin and Arrays of matrix impedance can be found using field analysis which
proximity effects. These two effects are summarized in the Dowels can be done by aid of FEA. (10) and (11) present the elements of

I 1 Rac1 Llk1 n:1

Llk2 Rac2 I 2 design stage. However, reducing the parasitic capacitance often
leads to increment in resistance. Therefore, both of these para-
+ + sitic elements should be considered at the same time to achieve
Rc Lm high-efficiency and low-parasitic PT. In this section, a systematic
V1 V2 analysis is performed, and six PT winding layouts are introduced
- - and benchmarked with a traditional design. The analysis starts with
(a) the static capacitance between two layers of the traditional spiral
winding layout and then the low parasitic capacitance layouts are
I 1 Rac1 Llk1 Llk2 Rac2 I 2
introduced.
The value of the static capacitance between two conductive
+ n:1 layers with overlapping area of At and separation distance of d
Rcs + is presented in (13).
V1 V2
Lms At
- Cstatic = 0 r
d
(13)
-
(b) Where r is the permittivity of the material between layers. For
a transformer with m intersections of primary and secondary, the
Fig. 4: (a) Transformer equivalent circuit neglecting the capacitive total value of static inter-winding capacitance is presented in (14).
effects and (b) Modified equivalent circuit.
At
Cstatic = m × 0 r (14)
d
each array based on the fields. The total value of the inter-winding capacitance is equal to the
sum of C13 , C14 , C23 and, C24 capacitors. Therefore, reducing
#» # » # » #»
I
1
Rij = (Ji .Jj∗ + Ji∗ .Ji ) dV (10) the total value of inter-winding capacitance means that the overall
2 × Ii(pk) × Ij(pk) V impact of inter-winding capacitance is reduced. Equation (14)
1
I
#» # » # » #» shows that the total value of static inter-winding capacitance can
Lij = (Hi .Hj∗ + Hi∗ .Hi ) dV (11) be reduced by increasing the separation distance, reducing the
2 × Ii(pk) × Ij(pk) V overlapping area, reducing the number of intersections, and using
In the above equations, Ji and Hi are the current density and low permittivity materials between layers. Increasing the separation
magnetic field due to the input current at the port i. Besides, the Rij distance reduces the value of capacitance. However, more distance
and Lij are resistance and inductance associated with the array ij means more space for insulation and less space for copper that
in the impedance matrix. In the case of two windings transformer, leads to higher conduction losses. As a result, this method often
there are two ports and two different analysis are required to get sacrifices resistance to reduce the parasitic capacitance. Reducing
corresponding current densities and magnetic fields. In finding the overlapping area also reduces the PCB utilization and increase
field solution, eddy currents should be considered to investigate the DC resistance. Also, this method suffers from high proximity
the impact of arrangement on the AC resistance and leakage effect that results in very high AC resistance. Therefore, among dif-
inductance. After finding field solution for each case, superposition ferent factors, only number of intersections and the permittivity of
theorem will be used to calculate the (10) and (11). Equating the material can be manipulated to reduce the static inter-winding
the matrix produced with these equations with the transformer capacitance. Reducing the number of intersections should be done
impedance matrix, the values of equivalent circuit can be found by considering the proximity effect. While the non-interleaved (NI)
by (12). structure has only one intersection, it cannot be used due to the
high ratio of AC to DC resistance. The proposed methods and
1 1 procedures in the previous section can be used to find an optimized
Rac1 = R11 − R12 Llk1 = L11 − L12
k k transformer arrangement that minimize both AC resistance and
Rac2 = R22 − kR21 Llk2 = L22 − kL21 (12) inter-winding capacitance. Using low permittivity material is a very
1 1 effective method of reducing the static capacitance with no penalty
Lms = L12 Rcs = R12 on the other parasitics. It should be mentioned that FR4 is the most
k k
widely used material for PCBs due to its electrical and mechanical
Having the required analysis to extract the PT parasitic elements,
properties. This material is flame resistant and provides up to 20
it is possible to design optimized PTs with low parasitic elements
kV/mm electrical insulation. Despite these advantages, FR4 has a
for the LLC resonant converter. These analysis tools are used
relatively high permittivity of 4.7. This high permittivity leads to a
through this paper to investigate different PT structures and design-
considerable parasitic capacitance between top and bottom traces.
ing low parasitic capacitance PTs for the LLC resonant converter
Since commercial PCBs are usually manufactured using FR4, the
with wide output voltage regulation.
parasitic capacitance between top and bottom traces cannot be
reduced by using another material. However, we are still able to
III. R EDUCTION OF THE PARASITIC C APACITANCES use low permittivity materials between separate PCBs to reduce the
As discussed in this paper, the performance of LLC resonant parasitic capacitance between them. This option is only available
converters considerably degrades in the presence of the transformer in the windings realized by modularly stacked double layers PCBs,
parasitic capacitances. The inter-winding capacitance make the CM as the material between PCBs are not necessarily F R4. As a
noise problem and the primary stray capacitance leads to voltage result, the windings made with the double layers PCBs are more
regulation problem under light-loading condition. Therefore, efforts customizable and capable of reducing the parasitic capacitance
should be made to minimize the stray capacitance of PT in the than windings that are manufactured by multi-layers PCBs. In

} Primary
} Secondary
FR4 } Secondary
} Primary
Insulation
} Primary
} Secondary
} Secondary
} Primary

(a) (b)
Fig. 5: (a) The 3D model of a traditional 8 : 4 planar transformer with spiral winding and (b) 2D cross section of the transformer
showing the arrangement of the transformer. Each primary PCB has eight turns (four on each side) and each secondary PCB has four
turns (two on each side). The primary PCBs are connected in parallel and secondary PCBs also are connected in parallel.

order to explain how the material between the PCBs affects the and air used, respectively. These figures show that replacing F R4
distributed parasitic capacitances, a cross section of an 8 : 4 with air reduces the static capacitance between successive PCBs
transformer is showed in the Fig. 5 (a) and (b). The primary has roughly 4.7 times for the same structure. The work in [24] reports
four PCBs in parallel and each PCB has eight turns (four on the that inserting shield can reduce the inter-winding capacitance up to
top and four on the bottom). The secondary also has four PCBs two times. Therefore, inserting air at the intersections is roughly
in parallel and each PCB has four turns. Fig. 5 (b) shows a 2D 2.5 times more effective than inserting the shield. The air separation
cross section of the transformer and explains how the PCBs are can be realized using hollow frames. Fig. 7 shows an example of
arranged. There are four intersections of primary and secondary frame that can be used to provid air separation between layers.
PCBs. The material that is used in these intersections significantly Although air effectively reduces the static capacitance between
affects the interwinding capacitance. In the multi layer PCBs, this successive layers, it cannot provide the required insulation clear-
material is F R4. However, in the winding that are made with ance between overlapping traces. Therefore, the required insulation
double layer PCBs, low permitivity materials like air can be used. clearance between layers can be realized by using one or two layers
Figures 6 (a) and (b) show one of these intersections with F R4 of Kapton tape.
Unlike inter-winding capacitance, finding the self-capacitance
of two overlapping layers of the same winding requires calculating
{ Primary Double the total electrostatic energy in that layer. Fig. 8 shows a double
LayerPCB sided PCB used as a winding in PTs. The analytical expressions
Insulation for calculating the intra-winding energy between overlapping traces
{ Primary Double and adjacent turns are presented in the (15) and (16).
LayerPCB
Z L
1 W × dx Vw 2 1 W ×L 2
3
Eoverlap = 0 r ( x) = 0 r Vw
Energy (J/m ) 0 2 d L 6 d
(15)
1.4e-004

1.2e-004

1.0e-004

(a) 8.6e-005

6.7e-005

4.8e-005

2.8e-005

9.3e-006
(b)
Fig. 6: Inter-winding energy associated with one intersection of
primary and secondary. All of the primary turns have voltage
equal to 1V and all of the secondary turns have 0V. The energy
distribution: (a) with FR4 between PCBs 101pJ and (b) with air
between PCBs 25pJ. Fig. 7: Example of the frame that is used for air separation.

c the thickness of the traces is much smaller than their width and
2 t
the value of the second term is roughly proportional to n12 , the
- + dl
V
( nw )
value of the second term is negligible in comparison to the first
term. For the studied prototypes, the second term is less than three
percents of the first part. Ignoring the second part, the intra-winding
capacitance of Fig. 8 is presented in the (18).
...
1 At 1
+x
... Cintra ≈
0 r = Cstatic (18)
(
-L
) Vw 3 d 3
d
Equation (18) indicates that for the same area, the value of intra-
dl W
winding capacitance of two overlapping layers of Fig. 8 is equal
... to one-third of the static capacitance between two layers. Since
... replacing F R4 with air only is applicable between different PCBs,
1
this method cannot be used to reduce the capacitance between
traces of the same PCB. However, in the case that PCBs of the same
windings are placed next to each other, air can reduce the value of
(a) static capacitance between layers of different PCBs. Figures 9 (a)
and (b) show the intra-winding energy of two successive PCBs of
Vw /2 Vw the same winding with F R4 and air between PCBs, respectively.
These figures confirm that air only can mitigate the intra-winding
X=0 X=L
capacitance between layers of different PCBs. In other words, the
Vw /2 overall impact of this method on the intra-winding capacitance is
0
much lower. Therefore, other methods should be used to reduce
(b) the intra-winding capacitance between traces of the same PCB.
Fig. 8: (a) Traditional spiral winding layout: The distributed ca- In the following subsections, six improved winding layouts
pacitance due to overlapping traces 1 , the distributed capacitance with very low parasitic capacitances are proposed and compared
between adjacent turns at the same side 2 and (b) simplified view regarding the parasitic capacitance and resistance. These winding
of the overlapping traces. layouts are shown in the figures 10 (b), (c), (d), (e), (f), and (g).
For each winding layout, the analytical expressions describing DC
resistance and intra-winding capacitance are proposed and verified
Z 2 )L
(1− n with the aid of FEA. In comparison to the traditional spiral winding
t × dx Vw 2 (n − 2) t × L 2
Eadjacent = ( ) = 0 0 Vw layout, the proposed layouts have up to 21.2 and 16.6 less intra- and
0 c n n3 c inter-winding capacitances which significantly reduce the CM noise
(16)
and solves the regulation problem in the LLC resonant converter,
The parameters of (15) and (16) are presented in the table II. The
which is the objective of this paper.
TABLE II: Parameters definition
Parameter Definition { Primary Double
LayerPCB
L Total lenght of turns in one side
Insulation
W Width of traces { Primary Double
LayerPCB
d Distance between two layers
c Clearance between adjacent traces 3
Energy (J/m )
t Thickness of Copper
7.1e-005
n Total number of turns in PCB
r FR4 permitivity 6.1e-005

At Total area of turns 5.1e-005

(a) 4.2e-005
sum of these energies is equal to the energy stored in the lumped
3.3e-005
intra-winding capacitance. Equating the energy expressions, the
value of lumped capacitor can be found using (17). 2.3e-005

1 At 2(n − 2) t At 1.4e-005
0 r
Cintra = + 0 (17)
3 d n3 W c 9.4e-008
In the equation above, the first term is associated with the (b)
overlapping turns and the second term shows the intra-winding
capacitance due to the adjacent turns of the same side of PCB. In Fig. 9: Intra-winding energy of associated with PCBs of the same
developing the second part, the fringing of electric field is ignored. winding placed next to each other. The PCBs are connected in
In reality, due to the fringing of electric field, part of electric field parallel and 1V is distributed linearly between terminals of each
reaches to the adjacent trace through the PCB. Therefore, the value PCB. Electrostatic energy distribution: (a) with FR4 between PCBs
of the second term is higher than what (17) predicts. However, since 99pJ and (b) with air between PCBs 73pJ.

Primary

Secondary

(a) (b) (c)

Primary

Secondary

(d) (e) (f)

Middle connection for series connection Middle connection for series connection
of two parts of the secondary of two parts of the Primary

PCB4 PCB3 PCB2 PCB1

Insulation between PCBs

top and bottom top and bottom top and bottom top and bottom
are parallel are parallel are parallel are parallel

Secondary part 2 Primary part 2 Secondary part 1 Primary part 1

(last two turns) (Last four turns) (first two turns) (first four turns)

(g)
Fig. 10: The proposed improved winding layouts to reduce the parasitic capacitances in LLC converters: (a) Traditional spiral, (b) and
(c) No overlapping, (d) Optimized overlapping, (e) Alternating, (f) Alternating & no overlapping and, (g) Zero voltage gradient winding
layouts.

3 3
Energy (J/m ) Energy (J/m )
5.5e-005 9.5e-006

2.8e-005 4.8e-006

4.6e-006 2.5e-007

(a) 33 pJ (b) 1.7 pJ

3 3
Energy (J/m ) Energy (J/m )
7.1e-005 1.4e-005

3.7e-005 7.0e-006

4.6e-006 2.5e-007

(c) 10.5 pJ (d) 3.4 pJ

3 3
Energy (J/m ) Energy (J/m )
8.6e-006 3.8e-006

4.3e-006 1.9e-006

9.1e-007 2.5e-007

(e) 2.15 pJ (f) 1.1 pJ

Fig. 11: Intra-winding energy associated with one PCB of the proposed layouts. Each layout consist eight turns and 1V is distributed
linearly between terminals of the layout: (a) Traditional spiral, (b) No overlapping, (c) Optimized overlapping, (d) Alternating, (e)
Alternating & no overlapping, and (f) Zero voltage gradient winding layouts. It is clear that the proposed layouts have significantly less
parasitic capacitance.

A. No overlapping winding layouts means having ( n+1

2
) turns on one side and ( n−1
2
) turns on the other
Minimizing the overlapping area is the first approach to reducing side. This winding layout is called Optimized overlapping winding
the intra-winding capacitance. Fig 10 (b) and (c) show minimized layout in this paper. For even values of n the intra-winding energy
overlapping winding layouts. These winding layouts are called and corresponding capacitance can be found by (19).
no overlapping winding layouts through this paper. The energy n
2
−1
( n )L
Vw ( n−2 ) 2
Z
stored in these winding layouts is proportional to the distributed 2 1
+1 W × dx n
Eintra = 0 r × n −1 x
capacitance between adjacent turns on the same side of PCB. 0 2 d 2
( n +1 )L
The analytical expression for calculating the parasitic capacitance 2 (19)
n
−1 n−2 2

between adjacent turns is equal to the second term in (17). Fig. 11 1 W ×L 2
Cintra = 0 r × (n )( )
(b) shows the intra-winding energy associated with one of these 3 d 2
+1 n
layouts. This figure shows that these layouts strongly reduce the
intra-winding energy as the value of intra-winding energy is re- Following the same procedure for odd values of n, the intra-
duced from 33 pJ in the traditional design to 1.7 pJ. Regarding the winding capacitance associated with this condition is presented in
inter-winding capacitance, these layouts offer double space between the (20).
windings and reduce the value of static inter-winding capacitance. Z ( n−1 )L
Vw ( n−1 ) 2

n+1 1 W × dx n
Although these layouts effectively mitigate the problem of intra- Eintra = 0 r × x dx
winding capacitances, they have higher DC resistance comparing 0 2 d ( n−1
n+1
)L
(20)
to the traditional winding layout. In these layouts, only 50% of
1 W ×L

(n − 1)3

PCBs are used and consequently, the values of DC resistance is Cintra = 0 r × ( 2 )
3 d n (n + 1)
roughly twice of the traditional winding layout. Due to higher
conduction loss, these designs are not suitable for high-efficiency Assuming the total length of winding is equal to the traditional
LLC applications. winding layout, DC resistance for each case is presented in the
(21).
B. Optimized overlapping winding layout n+2
n = Even RDC−Opt = ( )RDC−trad
The second winding layout which attempts to reduce the par- n
(21)
asitic capacitance with less resistance increment is showed in the n(n + 1)
n = Odd RDC−Opt =( 2 )RDC−trad
Fig 10 (d). The stored energy between overlapping traces depends n +1
on the voltage gradient of those traces. Therefore, the energy is In the above equations, RDC−trad is the DC resistance of
not evenly distributed in the area between two layers, and more traditional spiral design. Figures 12 and 13 show the normal-
energy is stored between outer turns that have larger capacitance ized DC resistance and intra-winding capacitance of Optimized
and voltage gradient. This feature is used in this layout to remove overlapping winding layout for different values of n. The base
the overlapping area between the outer turns and effectively reduce values for normalization are the DC resistance and intra-winding
the intra-winding capacitance. Removing the overlapping between capacitance of traditional winding layout. These figures show that
these turns means that putting ( n2 +1) turns on one side and ( n2 −1) the value of intra-winding capacitance can be reduced effectively,
on the other side. For the PCBs with the odd number of turns, it

2 1
One way to reduce the voltage gradient between overlapping
DC Resistance traces is illustrated in the Fig. 14 (a). This winding layout is

Normalized Intra−winding Capacitance

Intra−Winding Cap
called Alternating winding layout in this paper. In this layout,
1.75 the overlapping traces are two successive turns. In other words,
Normalized DC Resistance

after each turn, the next turn is on the other side. These turns are
connected through VIA. For this layout, the intra-winding energy
1.5 0.5
can be calculated by (22).
Z L
1 W × dx Vw
1.25 Eintra = 0 r × n )2 =
0 2 d 2

1 W ×L 2 4
0 r Vw × ( 2 )
1
2 4 6 8 10 12 14 16
0
2 d n
Number of Turns
1 W ×L 6
Cintra = 0 r ×
Fig. 12: Variations of DC resistance and intra-winding capacitance 3 d n2
of Optimized overlapping winding layout for even values of n. (22)
The above equation shows that this winding layout reduces the
value of intra-winding capacitance by the factor of n62 . Fig. 14 (b)
1.4 1 presents the intra-winding capacitance of this layout for different
DC Resistance

Normalized Intra−winding Capacitance

Intra−Winding Cap

1.3
Normalized DC Resistance

1.2 0.5

1.1

1 0
3 5 7 9 11 13 15 17
Number of Turns

Fig. 13: Variations of DC resistance and intra-winding capacitance

of Optimized overlapping winding layout for odd values of n.

without doubling the DC resistance. An eight turns winding lay-

out with this strategy is showed in the Fig. 10 (d). The intra-
winding energy distribution of this layout is showed in the Fig. ....
11 (c). This figure shows that in the case of eight turns PCBs,
removing the overlapping area between first and last turns reduces
the intra-winding capacitance by 69%. This result is in a very (a)
good agreement with (19). The percentage of increase in the DC
resistance can be calculated using (21) which is equal to 25%. In 1
Normalized Intra−winding Capacitance

comparison to the no overlapping winding layouts that have 100%

more DC resistance, the DC resistance increment in this layout is 0.8
just 25%. Although this layout proposes a significant capacitance
reduction by small increment of resistance, the parasitic capacitance
still is considerable and can lead to voltage regulation problems. 0.6
Therefore, more optimized winding layouts should be investigated
to strongly reduce the parasitic capacitance while not letting the 0.4
resistance to increase.
0.2
C. Alternating winding layout
No overlapping and Optimized overlapping winding layouts 0
2 4 6 8 10 12 14 16
are based on the overlapping minimization principle. Although Number of Turns
effective in mitigating the intra-winding capacitance, these winding
layouts sacrifice DC resistance to mitigate the intra-winding capac- (b)
itances. The intra-winding capacitance also can be minimized by
reducing the voltage gradient between overlapping traces. Minimiz- Fig. 14: (a) Alternating winding layout with terminals at the outer
ing voltage gradients between large overlapping traces reduces the edges of PCB and (b) Variations of intra-winding capacitance of
intra-winding energy and consequently the intra-winding capacitor. Alternating winding layout for even values of n.

values of n and shows that the value of intra-winding capacitance E. Zero Voltage gradient winding layout
rapidly decreases by increasing the number of turns. Regarding The final proposed winding layout for solving the parasitic
the DC resistance, this winding layout has no increment as all of capacitance problem is called Zero voltage gradient layout. In order
the available PCB is used for copper traces. Fig. 10 (e) shows an to explain this winding method, a 8 : 4 transformer that is realized
eight turns Alternating winding layout. For the ease of connecting using the double layers PCBs is showed in Fig. 10. (g). There are
to other PCBs, the winding is started from the middle, and the four different PCBs (two double sided PCBs for primary and two
terminals are at the edges of the PCB. The intra-winding energy double sided PCBs for the secondary). This figure shows that the
distribution of this layout also is showed in the Fig. 11 (d). This eight turns of the primary are splitted into two parts. The first four
figure shows that an eight turns Alternating winding layout has turns of the primary are duplicated on both sides of the first PCB
10 times less intra-winding energy than the traditional winding of primary. The top and bottom layers of this PCB are connected
layout which is in a good agreement with (22). In comparison in parallel which means that this PCB has four turns out of eight
to the previous designs, this layout reduces the intra-winding turns of the primary. Since the top and bottom turns of this PCB are
capacitance without sacrificing the DC resistance. Although this identical and connected in parallel, they have the same voltage and
layout is a suitable candidate for wide-range and efficient LLC there is no voltage gradient between the overlapping turns. This
converters, it does not have any superiority in terms of the inter- condition also can be seen from the direction of the turns in this
winding capactitance. Thereofore, other winding layouts should be PCB. The four remaining turns of the primary are duplicated on
investigated to find an optimum layout that minimize both types both sides of second PCB of the primary. Like the first PCB, the
of the parasitic capacitances. top and bottom layers of this PCB also are connected in parallel.
The first four turns that are on the first PCB then are connected
in series to the four turns of second PCB via a middle connection,
D. Alternating & No overlapping winding layout making an eight turns primary winding. The same is true for the
Minimized overlapping strategy also can be used to reduce the secondary winding. Therefore, the key idea here is that the top and
value of inter-winding capacitance. On this basis, a winding layout, bottom layers of each PCB should be identical and connected in
Alternating & no overlapping winding layout, with minimized parallel to achieve zero voltage gradient and minimize the parasitic
overlapping of primary and secondary is showed in the Fig. 10 (f). capacitance. The proposed idea is implemented in the Fig. 10 (7)
This layout uses the alternating layout to reduce the intra-winding (g) by dividing each winding into two portions and duplicating
capacitance and avoids any overlapping between primary and sec- each portion on top and bottom side of a separate PCB. Then
ondary to minimize the inter-winding capacitance. Therefore, this connecting two PCBs with a middle connection. In the general
transformer minimizes both intra and inter-winding capacitances. case, the proposed idea can be extended to dividing winding into
Due to the alternating layout and lower overlapping area between any even number of groups. The following shows the steps that are
the traces of the same winding, the intra-winding capacitance of required to implement this idea:
this layout is very low. Fig. 11 (e) shows the intra-winding energy 1) Each winding should be splitted into two (or any even
of this layout which is roughly 15 times less than traditional layout. number of) groups and each group should be duplicated
Since the overlapping of primary and secondary is avoided in this on both sides of a separate PCB. The minimum number
structure, this layout also has lower inter-winding capacitance. On of required PCBs for each PCB is equal to the number of
the downside, this layout only uses 50% of PCB and therefore has groups.
twice DC resistance. More importantly, this layout has very high 2) The top and bottom layers of each PCB should be connected
AC resistance due to the proximity effect. Therefore, it makes a in parallel.
lot of conduction loss and is not suitable for high efficiency LLC 3) Different PCBs should be placed separately to avoid the
converters. This layout will be discussed more in the next section. voltage gradient between them. All different PCBs should be

P1 S2 S2 P2 P2 S1 S1 P1
Primary part 1 Secondary part 2 Secondary part 2 Primary part 2 Primary part 2 Secondary part 1 Secondary part 1 Primary part 1
(first four turns) (last two turns) (last two turns) (last four turns) (last four turns) (first two turns) (first two turns) (first four turns)

PCB1 PCB2 PCB3 PCB4 PCB5 PCB6 PCB7 PCB8

Air & Kapton Air & Kapton Air & Kapton Air &
Kapton Kapton Kapton Kapton

Connection between Connection between

two parts of the secondary two parts of the primary
Fig. 15: Zero voltage gradient transformer with the P 1S1S1P 2P 2S2S2P 1 structure. It is clear that all overlapping traces of the same
winding have zero voltage gradient.

connected in series to make a complete winding. For some minimize the parasitic capacitance by reducing the voltage gradient
of PCBs, Middle connection should be used to connect two have the benefit of using all the available space and therefore
successive PCB. The number of required middle connections do not compromise DC resistance. The DC resistance and intra-
is equal to half of the number of PCBs. winding capacitance of different winding layouts are compared in
It can be seen that the above rules are applied to the transformer the Fig. 16 (a) and (b). Fig. 16 (a) shows that all of the proposed
of Fig. 10 (g). For this case, each winding is divided into two winding layouts have considerably lower intra-winding capacitance
groups and two PCBs are required for each winding to complete than traditional spiral layout.
the winding (one PCB for each group). The intra-winding energy No overlapping layouts can strongly mitigate the parasitic ca-
distribution of a PCB with this layout is showed in the Fig. 11 pacitance and solve the regulation problem. However, they also
(f). In comparison to the traditional winding, the value of intra- double the DC resistance which leads to higher conduction loss.
winding energy is reduced from 33 pJ to just 1.1 pJ, with the Optimized overlapping layout is the optimized version of No over-
same overlapping area and without any compromise on the DC lapping layouts that reduces a big portion of parasitic capacitance
resistance. This reduction in the parasitic capacitance is even more by a small increase in the resistance. However, it is not as effective
than the minimized overlapping winding layouts that have double of No overlapping layout and since wide output regulation requires
conduction loss. very low parasitic capacitance, it may not solve the regulation
As mentioned before, the minimum number of PCBs that are problem. Alternating layout also strongly reduces the intra-winding
required for each winding in this method is equal to the number capacitance without increasing the DC resistance. Therefore, this
of portions that the winding is divided. If the core windows can layout can be used to resolve the regulation problem without
accommodate more layers, it is desirable to add extra layers in compromising the efficiency. However, in terms of CM noise it
parallel to reduce the resistance. For example in Fig. 15, the does not have any advantage over the traditional layout. In order
windings of the same transformer are realized by using four PCBs to reduce both intra- and inter-winding capacitances, Alternat-
(two PCB in parallel for each portion of windings). The PCBs ing & no overlapping layout is proposed. Although this layout
that are connected in parallel are identical and both have the same effectively reduce the parasitic capacitances, it has significantly
portion of winding. Therefore, they also have the same voltage higher AC resistance in comparison to other layouts which will
distribution. This characteristic can be used to reduce the inter- be discussed more in the next section. Among different layouts,
winding capacitance. Due to zero voltage gradient between these
PCBs, they can be placed very close to each other without being
worry about increasing the intra-winding capacitance or violating 80
the electrical clearance which saves space in the limited height 68
70
of the core windows. This space can be used to increase the
Static Inter-Winding Cap (pF)

number of layers or to increase the separation distance in the 60 31 Times less

primary and secondary intersections to reduce the inter-winding 50 Intra-winding Capacitance
capacitance. This advantage is showed in the Fig 15. This figure with the same DC Resistance
40
clearly shows that similar PCBs are separated just by one Kap-
ton layer, providing more separation distance for intersections of 30
19.8
primary and secondary. Therefore, this winding layout not only 20
gives the minimum intrawindng capacitance, but also provides the 10 6.2
3.8 3.3 2.2
opportunity to reduce the interwinding capacitance. The benefits of
0
this winding layout can be summarized as the following: Traditional Optimized Alternating Alternating & No Overlap Zero Voltage
Overlap No Overlap gradient
1) Having extremely low intra-winding capacitance due to zero
voltage gradient between overlapping traces. Intra-Winding Cap

2) No increment in the value of DC resistance. The same DC

resistance of traditional winding layout. (a)
3) Identical PCBs can be placed with very low separation
90 85
distance without increasing the intra-winding capacitance. 81
Therefore, there is more space to be used in the intersections 80
No sacrifice on
Static Inter-Winding Cap (pF)

of primary and secondary, resulting in a less inter-winding 70

the DC Resistance
capacitance. 60

Due to very low parasitic capacitance, this layout can resolve 50 47.2
42.4
both CM noise and light-load voltage regulation problem in the 40
37.6 37

LLC converter, while at the same time gives low resistance which 30
ensures the high full-load efficiency. Therefore, this layout is very 20
suitable to be employed in the LLC resonant converters.
10

0
F. Comparison of the proposed winding layouts Traditional Optimized
Overlap
Alternating Alternating & No Overlap
No Overlap
Zero Voltage
gradient
In the previous parts, six improved winding layouts are proposed DC Resistance
to minimize the parasitic capacitance of PT and consequently,
solve the problems due to the parasitic capacitance in the LLC (b)
resonant converter. Among the proposed winding layouts, layouts
that reduce the parasitic capacitance by decreasing the overlapping Fig. 16: Parasitic elements comparison of different winding layouts:
have higher DC resistance. On the other hand, the designs that (a) Intra-winding capacitance and (b) DC resistance

Zero voltage gradient layout offers the minimum intra-winding IV. A RRANGEMENT TRADEOFF ANALYSIS
capacitance without any increment in the DC resistance. Reducing
the intra-winding capacitance significantly enhance the converter In the previous section, improved winding layouts are proposed
performance and mitigate the regulation problem. In terms of inter- to significantly reduce the parasitic capacitance and attenuate the
winding capacitance, this layout also provides the lowest inter- CM noise and solve the voltage regulation problem in the LLC
winding capacitance. Minimising the inter-winding capacitance resonant converter. In addition to the winding layout, the structure
not only reduces the CM noise, but also enhance the regulation. of the transformer strongly affect the parasitic elements. It is
Therefore, this layout is the best among the proposed layouts. interesting to note that there is a trade-off between intra-winding
capacitance, AC resistance and leakage inductance against the inter-
winding capacitance. The values of intra-winding capacitances, AC
resistances, and leakage inductances decrease by using interleaved
structures. On the other hand, the inter-winding capacitance is
proportional to the number of intersections between primary and
J (A/m )
2
P1 secondary which increases in the interleaved structure. Most of the
proposed winding layouts in the previous section can effectively
3.7723e+007 P2 solve the intra-winding problem. Besides, the leakage inductances
3.2694e+007
P3 are inherently small in PTs comparing to the wire wound transform-
2.7666e+007
P4 ers and also the primary leakage inductance is capable of being
2.2638e+007
S1 absorbed by the series inductor. For these reasons, the trade-off
1.7609e+007
S2 analysis in finding the optimum arrangement is only made based
1.2581e+007
on AC resistance and inter-winding capacitance. On this basis, the
7.5523e+006 S3 optimum structure is the one that minimizes the AC resistance
9.6864e+003 S4 with the minimum number of intersections between primary and
(a) secondary.
2 Fig. 17 shows the current density in the transformer with four
J (A/m ) S1
1.7947e+007 layers of primary and secondary in different structures. This figure
1.5580e+007
S2 shows that the best current distribution between layers happens in
1.3186e+007 P1 the P SSP P SSP structure. In comparison to the fully interleaved
1.0792e+007 P2 structure, the number of intersections has reduced from seven to
8.3984e+006 P3 four, meaning the value of inter-winding capacitance is reduced
roughly by 43%. This reduction in the parasitic capacitance can
6.0044e+006 P4
3.6104e+006
significantly attenuate the CM noise in LLC converters. The
S3 comparison of different structures regarding parasitic elements are
1.9442e+004
S4 presented in the figures 18 and 20.
(b) It should be noted that both SP P SSP P S and P SSP P SSP
2 have similar results in terms of AC resistance and inter-winding ca-
J (A/m ) P1 pacitance. Sine the number of primary and secondary intersections
9.0282e+006 S1 are equal, they have similar inter-winding parasitic capacitance.
8.0566e+006
P2 The similarity in the result of AC resistance also can be explained
7.0850e+006 by finding the MMF distribution along the wingdings as both of
6.1134e+006
S2
those arrangements have the same MMF distribution. The MMF
P3
5.1418e+006 distribution of these arrangements are showed in Fig. 19 (a). If
4.1702e+006 S3 the core window can accommodate more layers, other portions of
3.1985e+006 P4
1.7411e+006 S4
(d) 1600 The same AC resistance of 120
1414
2 1400 FI structure but with much
Intra-Winding Cap (pF)

J (A/m ) P1 less inter-winding Capacitance 100

AC Resistance (mΩ)

1200
1.0721e+007
S1 1000
80
9.5847e+007 808
8.4484e+007
S2 800
606
60
600
7.3122e+006
P2 40
400 301
202 172
6.1760e+006 P3 200 132
43
20

5.0398e+006 S3 0 0
3.9036e+006
S4
2.1992e+006
P4
(e)
Inter-Winding Capacitance AC Resistance
Fig. 17: Current density in different arrangements: (a) PPPPSSSS
(NI), (b) SSPPPPSS, (c) PSPSPSPS (FI), and (d) PSSPPSSP. It is Fig. 18: The comparison of AC resistance and inter-winding
evident that PSSPPSSP structure leads to an even distribution of capacitance of an eight layers transformer with traditional spiral
the current between layers and provides the best AC resistance. windings in different structures.

800 717 1 the best results. The only exception is the Alternating & No
675 659 0.9 overlapping winding layout which has significantly larger AC

Leakage Inductance (µH)

700 625
Stray Capacitance (pF)

0.8
600
0.7
resistance in all arrangements. Table III shows the ratio of AC to
500
409 389 401 393 0.6 DC resistance of this layout in different structures. This table shows
400 0.5
300 0.4 TABLE III: The ratio of AC resistance to DC resistance of
0.3
200 Alternating & No overlapping winding layout in different structures
0.2
100 0.1
0 0 Arrangement Rac /Rdc
P P P P SSSS 168.6/48.1
P P SSP P SS 184.3/48.1
Stray Capacitance of one Cap model Leakage Inductance P SP SP SP S 212.0/48.1
P SSP P SSP 201.5/48.1
Fig. 20: The comparison of leakage inductance and primary parallel
stray capacitance of an eight layers transformer with traditional that the interleaving does not solve the proximity effect. Since the
spiral windings in different structures. primary and secondary turns do not meet each other, primary and
secondary MMF do not cancel each other and the proximity effect
leads to high ratio of AC to DC resistance. Fig. 21 shows the inter-
interleaving also is viable with the proposed winding layouts and winding energy of Alternating & No overlapping winding layout.
arrangements. For example, Fig. 19 (b) shows the same transformer This figure clearly shows that even with no overlapping between
with the P SSP P SSP P SSP P SSP arrangement. primary and secondary, still there are some capacitive coupling
between windings due to the fringing of electric field. Indeed,
3
even with no overlapping between primary and secondary, the
Energy (J/m )
1.5e-005
value of inter-winding capacitance is half of the traditional winding
layout. Considering the problem of AC resistance and the fact that
6.6e-006 inter-winding capacitance still has large value, the minimization
of overlapping between primary and secondary is not a practical
5.7e-007 way to mitigate the inter-winding capacitance problem. Instead, the
inter-winding capacitance should be minimized through optimizing
Fig. 21: Inter-winding energy of one intersection between windings the structure, increasing the separation distance between windings
in Alternating & No overlapping layouts. and, using the low permeability materials in the intersections.
Having the improved winding layouts and the optimized struc-
The proposed winding layouts also are investigated with dif- ture with low AC resistance and inter-winding capacitance, now
ferent structures and in all cases the proposed arrangement gives we are able to fabricate very low parasitic capacitance PTs for
Insulation

Insulation

Insulation
S

S
P

-NI -NI

0 0

+NI +NI

mmf mmf
(a) (b)
Insulation

Insulation

Insulation
S

S
P

(c)
Fig. 19: (a) Comparison of the MMF distribution along the winding in P SSP P SSP and SP P SSP P S arrangements and (b) Similar
interleaving method with the double number ofr PCBs.

S1-1 P1 S2-2 S1-2 S2-1

Sec1-part 1 Primary part 1 P2
Sec2-part 2 Sec1-part 2 Primary part 2 Sec2-part 1
(First turn) (first four turns) (Second turn) (Second turn) (First turn)
(Second four turns)

PCB2 PCB8 PCB8 PCB8 PCB8 PCB8

Fig. 22: A 8:2:2 centre-tapped planar transformer with zero voltage gradient winding layout and b) the connection of PCBs.

high efficiency LLC resonant converter with wide output voltage. Fig. 24 confirms that the proposed transformers have significantly
These transformers can be used to resolve both CM noise and lower stray capacitance. Fig. 24 (b) shows the stray capacitance of
voltage regulation problem in the LLC resonant converter. different layouts. Among different layouts, zero voltage gradient
winding layout has the lowest primary parallel stray capacitance.
In comparison to the traditional FI transformer, this transformer
A. Application of the Proposed Winding Layouts in the
Centre-Tapped PTs
All of the proposed winding layouts also can be implemented in
the centre-tapped planar transformers. The proposed air separation Trad-FR4
Trad-FR4
Trad-Air No-Overlap
PSSPPSSP
method can be employed between PCBs of different windings to PSPSPSPS PSSPPSSP PSSPPSSP

reduce the inter-winding capacitance. On the other hand, the PCB

layouts that are presented in the paper can be used to minimize
Zero Gradient
the intra-winding capacitance between top and bottom layers of PSSPPSSP
each PCB. winding arrangement of the center-tapped PTs should
be selected by considering the passive losses in the non-conducting
secondary. Finding the optimized arrangement of the center-tapped
PTs falls out of scope of this paper and will be addressed in No-Overlap Opt-Overlap Alternating
PSSPPSSP
Alternate & No
PSSPPSSP
PSSPPSSP PSSPPSSP
the future work. However, In order to show the applicability of
the proposed methods on centre-tapped planar transformers, Fig.
22 (a) shows a 8:2:2 centre-tapped planar transformer that is
realized using the air separation method and zero voltage gradient
layout. As it is clear from this figure, there is no voltage gradient
between top and bottom layers of each PCB which minimizes
the intrawinding capacitance of the windings. The inter-winding
(a)
capacitance between different layers also is attenuated using the
air separation method.

V. E XPERIMENTAL R ESULTS
To verify the theoretical hypothesis, the winding layouts under
investigation were manufactured (total of 6) and employed in a
1.2kW LLC resonant converter. The experimental results show
that the proposed PTs have extremely lower parasitic elements
in comparison to the conventional PTs which mitigates the light-
loading voltage regulation problem and also ensures high full-load Rectifier
efficiency by minimizing AC resistance and inter-winding capaci-
tance. The specification of the converter and PTs are provided in DSP Full-Bridge
table IV.
Fig. 23 (a) and (b) show the prototypes of the special PTs
under study and the LLC resonant converter platform, respectively. Resonant Tank
Transformer
Fig. 24 (a) shows the frequency response of different transformers
with the secondary open. As long as the leakage inductances are (b)
negligible in comparison to the magnetizing inductance, the equiv-
alent capacitor in this condition is equal to Cstray . Considering Fig. 23: Experimental prototypes: (a) Transformers prototypes and
the fact the open circuit inductance is the same in all conditions, (b) LLC resonant converter platform

TABLE IV: Parameters definition

has 21.2 times less stray capacitance. Fig. 24 (c) shows the inter-
winding capacitance of the proposed transformers. This figure Converter Prameters Transformer Prameters
shows that using an optimized structure and replacing F R4 with
Parameters Value Parameters Value
Vin 200 V Np /Ns 2:1 (8:4)
Vout 96 V Core ELP 58/11/38
Pout 1200 W PCB Thickness 0.6mm
Alternating f 200 kHz Copper Thickness 4 Oz
Opt Overlap 2.6 MHz
2.05 MHz Zero Grad
4.2 MHz

air significantly reduces the inter-winding capacitance. Among

different layouts, zero voltage gradient winding layout again has
the best result as its inter-winding capacitance is 16.6 times less
Trad-FI than traditional FI structure. Fig. 25 (a) and (b) show the full-load
950 kHz waveforms of LLC resonant converter with the traditional PT and
the proposed zero voltage gradient transformer. Here, the inverter
voltage is the output voltage of the full-bridge inverter. Com-
paring the waveforms, it is clear that reducing the inter-winding
capacitance reduces the high-frequency currents and considerably

(a)
vinv Effect of large inter-winding
Capacitance
800 21.2 times less intra-winding capacitance,
700
680
618 solving the light-loading regulation problem. ip
600 vs
500
385
400
is
300
200 151
87 56.9
100 49 32
0

(a)
Primary Parallel Stray Cap (pF)
vinv Minimizing the inter-winding capacitance
(b) attenuate the CM noise
1600
1414 ip
1400 16.6 times less inter-winding capacitance,
Significantly Reducing the CM noise.
vs
1200
1000
800
808 is
600
400
172 170 154 124
200 95 85
0

(b)
Fig. 25: Waveforms in the LLC resonant converter under full-
Inter-Winding Capacitance (pF)
loading condition for different transformers: inverter voltage (Ch1),
primary current (Ch2), transformer secondary voltage (Ch3), and
(c)
transformer secondary current (ch4). (a) Traditional-FI and (b)
Fig. 24: Parasitic values of the prototypes: (a) frequency response, zero voltage gradient transformers. It is clear that reducing the
(b) inter-winding capacitance, and (c) equivalent primary stray inter-winding capacitances has attenuated the CM noise problem
capacitance. significantly.

High frequency ocilation on transformer No Load

vinv Unpredictable
voltage due to the high value of stray Cap 3.5 behavior
ip 3 due to the parasitic
capacitances
2.5

Vo/Vin
2
vs 1.5
1
0.5 Regulated voltage
even in no-load!
0
0.75 0.9 1.05 1.2 1.35 1.5 1.65 1.8 1.95
Nrmalized Frequency
Trad-FI-FR4 (680 pF) Trad-Air (389 pF) Zero Gradient (32 pF)

(a) (a)

Very small voltage ocilation due to Very Light-Loading

vinv
reducing the parasitic capacitance 2
ip 1.8
1.6
1.4
1.2

Vo/Vin
1
vs 0.8
0.6
0.4
0.2
0
0.75 0.9 1.05 1.2 1.35 1.5 1.65 1.8 1.95
Normalized Frequency
Trad-FI-FR4 (680 pF) Trad-Air (385 pF) Zero Gradient (32 pF)

(b)
(b)
Fig. 26: Waveforms in the LLC resonant converter under no-
loading condition for different transformers: inverter voltage (Ch1), Light-Loading
primary current (Ch2), and transformer secondary voltage (Ch3). 1.8
(a) Traditional-FI and (b) zero voltage gradient transformers. 1.6
Reducing the stray capacitances has improved the no-load voltage 1.4
waveform and successfully mitigated the light-load voltage regu- 1.2
Vo/Vin

lation problem. 1
0.8
0.6
0.4 Effect of high stray capacitance
improves the current waveforms. Fig. 26 (a) shows the transformer 0.2
voltage in the no-load condition with the traditional PT. This figure 0
0.75 0.9 1.05 1.2 1.35 1.5 1.65 1.8 1.95
shows that high stray capacitance distorts the transformer no-load Normalized Frequency
voltage and it cannot be considered as square-shaped. This distorted Trad-FI-FR4 (680 pF) Trad-Air (389 pF) Zero Gradient (32 pF)
waveform makes serious problems in controlling output voltage in
the no-load and light-load condition which cannot be predicted with
FHA. On the other hand, Fig. 26 (b) shows the no-load voltage of (c)
converter with the proposed zero voltage gradient transformer. This
Fig. 27: Converter voltage gain characteristic with different trans-
figure shows that even under no-load condition, the transformer
formers at a) no load, b) very light load and, c) light load. The
voltage still is square shaped.
conventional PT has serious regulation issues for all cases and
Since large parasitic capacitances distort the transformer no- the proposed Zero voltage gradient layout solves this problem by
load voltage, FHA fails to consider all issues introduced bythese achieving an extremely low capacitance.
parasitic capacitances and accurately predict the output voltage
behavior. Fig. 27 (a), (b), and (c) compare the voltage charac-
teristics of the converter with different transformers in three light-
load conditions. It is clear that large stray capacitance leads to an addition to the unpredictable behavior, the converter cannot regulate
unpredictable voltage behavior under the no-load condition. Fig. for low output voltages as is showed in the Fig. 27 (c). Minimizing
27 (b) and (c) show increasing the load can somehow improve the the parasitic capacitance can avoid these problems and enables
situation. However, the voltage behavior still is unpredictable. In the converter to regulate output voltage. It is clear that for the

96.4 96.3 and resistance at the same time.. This significant parasitic ca-
96.2 96.2
96.1 96.1 pacitance reduction has a tangible effect on the performance of
96 95.9 LLC resonant converter. The experimental results of employing
the proposed transformers in a 1.2 kW LLC resonant converter
Efficiency (Percent)

95.6
shows that not only the proposed transformers have enhanced the
performance and efficiency of the converter by minimizing AC
95.1 resistance and inter-winding capacitance, but also have mitigated
95.2
the voltage regulation problem and enabled the converter to regulate
the output voltage even in the no-load condition.
94.8

94.4 R EFERENCES
[1] M. Ordonez, and J. E. Quaicoe, “Soft-switching techniques for effi-
ciency gains in full bridge fuel cell power conversion,” IEEE Trans.
Power Electron., vol. 26, no. 2, pp. 482-492, Feb. 2011.
[2] F.Z. Peng, G.J. Su and J.S. Lawler, “A new ZVS bidirectional DC-
Fig. 28: Full-load efficiency of the converter at resonant frequency DC converter for fuel cell and battery application,” IEEE Trans. Ind.
with different transformers. Electron., vol. 19, no. 1, pp. 54-65,2004.
[3] I. Lee and G. Moon, “Soft-switching DC/DC converter with a full zvs
range and reduced output filter for high-voltage applications,” IEEE
Trans Pow. Electron, vol. 28, no. 1, pp. 112122, Jan. 2013
same sweeping frequency, the converter with zero voltage gradient [4] J. L. Russi, M. L. S. Martins, and H. L. Hey, “Coupled-filter-inductor
transformer can provide wider ranges of output and regulate the soft-switching techniques: Principles and topologies,” IEEE Trans. Ind
output voltage. Electron., vol. 55, no. 9, pp. 33613373, Sep. 2008.
PTs also are compared regarding the converter efficiency. Fig. 28 [5] BO Yang, Fred C. Lee, Alpha J. Zhang, Guisong Huang “LLC resonant
shows the full-load efficiency of the converter at resonant frequency converter for front end DC/DC conversion,” in Proc. Appl. Power
with different transformers. This figure shows that zero voltage Electron. Conf. Expo, 2002, pp. 1108-1112.
[6] W. T. McLyman,“Designing Magnetic Components for High-
gradient transformer has the highest efficiency between different Frequency DC/DC Converters,” CA, KG Magnetics, Inc. 1993.
transformers. It is mainly due to low resistance and low CM noise. [7] C. Quinn, K. Rinne, T. ODonnell, M. Duffy, and C. O. Mathuna,“A
The efficiency for other transformers that have higher resistance is review of planar magnetic techniques and technologies,” in Proc. Appl.
slightly lower. In the case of Alternating & No overlapping winding Power Electron. Conf. Expo, 2001, vol. 2, pp. 1175-1183.
layout, as it is stated in the previous sections, the interleaving [8] Ouyang, Z., O. C. Thomsen, and M. A. E. Andersen “Optimal design
does not improve the AC resistance, and this transformer has much and tradeoff analysis of planar transformer in high power DC/DC
higher AC resistance. Therefore, the efficiency of this transformer converters,” IEEE Trans. Ind. Electron., vol. 59, no. 7, pp. 2800-2812,
is considerably lower than other transformers. As a result, the non- Jul. 2012.
overlapping strategy is not a suitable layout for high-efficiency [9] S. R. Cove, M. Ordonez, F. Luchino, and J. E. Quaicoe, “Applying
response surface methodology to small planar transformer winding
applications.
design,” IEEE Trans. Ind Electron.,vol. 60, no. 2, pp. 483-493, Feb.
2013.
VI. C ONCLUSION [10] C. Panchal and J.-W. Lu, “High Frequency Planar Transformer
(HFPT) for universal contact-less battery charging platform,” IEEE
This paper presented the problems associated with the parasitic Trans. Magn., vol. 47, no. 10, pp. 2764-2767, Oct. 2011.
capacitance of PTs in LLC resonant converters and proposed a [11] D. Y. Kim, C. E. Kim, and G. W. Moon, “High-efficiency slim adapter
mitigation strategy to reduce the parasitic capacitance and improve with low-profile transformer structure,” IEEE Trans. Ind. Electron., vol.
the converter performance. It was shown that the high inter-winding 59, no. 9, pp. 3445-3449, Sep. 2012.
capacitance makes the CM noise problems while the parallel stray [12] Y. Liang, W. Liu, B. Lu, and J. D. van Wyk “Design of integrated
capacitance leads to voltage regulation problems in the light-load passive component for a 1 MHz 1 kW half-bridge LLC resonant
condition. In order to overcome these problems, a systematic converter,” in Proc. IEEE Ind. Appl. Soc. Annu. Meeting., Hong Kong,
China, Oct. 26, 2005, pp. 2223-2228
analysis was performed, and six PT winding layouts were intro-
[13] D. Huang, S. Ji, and F. C. Lee, “LLC resonant converter with matrix
duced and benchmarked with a traditional design. The proposed transformer,” IEEE Tran. Pow. Electron, vol. 29, no. 8, pp. 4339-4347,
winding layouts were compared regarding parasitic capacitances Aug. 2014.
and resistance with the aid of analytical equations. As a result of the [14] M. Pahlevaninezhad, P. Das, J. Drobnik, P.Jain, A. Bakhshai, G.
investigation, an optimized structure with minimum AC resistance Moschopoulos,“A novel winding layout strategy for planar transformer
and inter-winding capacitance was found and verified by FEA and applicable to high frequency high power DC-DC converters,” in Proc.
experimental results. The proposed winding layouts and structure Energy. Conv. Cong. and Expo (ECCE),, 2011, pp. 3786-3791.
were used to manufacture PTs with very low parasitic capacitance. [15] Jun Zhang, William G. Hurley, Werner H. Wolfle, Maeve C. Duffy,
While all of the proposed transformers significantly reduce the “Optimized Design of LLC Resonant Converters Incorporating Planar
parasitic capacitances, the proposed Zero voltage gradient layout Magnetics” in Proc. Appl. Power Electron. Conf. Expo, pp. 16831688,
Mar. 2013.
has the best results as it has 21.2 times less primary stray capaci-
[16] S. R. Cove, M. Ordonez, F. Luchino, J. E. Quaicoe“Integrated mag-
tance and 16.6 times less inter-winding capacitance. This structure netic design of small planar transformers for LLC resonant converters,”
reduces the stray and inter-winding capacitances from 618pF and in IEEE Energy Conv. Cong. and Expo (ECCE), 2011, pp. 1839-1844.
1414pF to 32pF and 85pF , respectively. Another advantage of [17] J. Zhang, W. G. Hurley, and W. H. Wolfle,“Gapped transformer design
this transformer is that it reduces the parasitic capacitance without methodology and implementation for LLC resonant converters,” in
increasing the resistance and has the lowest parasitic capacitances Proc. Appl. Power Electron. Conf. Expo, 2014, vol. 1, pp. 726-731.

[18] J. Zhang, W. G. Hurley, and W. H. Wolfle, “Design of the planar Navid Shafiei (S11) was born in Isfahan, Iran. He
transformer in LLC resonant converters for micro-grid applications,” received the B.S. degree in electrical engineering
in Proc. IEEE 5th Int. Symp. Power Electron. Distrib. Generation Syst, from Kashan University, Kashan, Iran, in 2005,
2014, pp. 17. and the M.S. degree in electrical engineering from
[19] J. Zhang; Z. Ouyang; M. C. Duffy, M. A. E. Andersen, and W. G. Islamic Azad University, Najafabad, Iran, in 2011.
Hurley, “Leakage inductance calculation for planar transformers with He is currently working toward the Ph.D. degree
a magnetic shunt,” IEEE Trans. Ind. Application., vol. 50, no. 6, pp. at the University of British Columbia, Vancouver,
41074112, Nov.-Dec. 2014. BC, Canada. He was a Technical Designer in the
[20] E. Kim, C. Kang, I. Hwang, Y. Lee, D. Huh, “LLC resonant converter Information and Communication Technology In-
using a planar transformer with new core shape,” IEEE Applied Pow. stitute, Isfahan University of Technology, Isfahan,
Electron. Conf. and Expo, 2014, pp. 3374-3377. Iran, from 2005 to 2013, where he was involved
[21] N. Shafiei and M. Ordonez “Improving the Regulation Range of EV in design and implementation of resonant converters. His current research
Battery Chargers With L3C2 Resonant Converters,” IEEE Trans. Power interests include resonant converters and their application in pure electric
Electron., Vol. 30, no. 6, pp. 31663184, Jun 2015. vehicles.
[22] B. H. Lee, M. Y. Kim, C. E. Kim, K. B. Park, and G. W.
Moon,“Analysis of LLC resonant converter considering effects of
parasitic components,” in Proc. Int. Telecommun. Energy. Conf,, 2009,
pp. 1-6.
[23] J-H. kim, C-E. Kim, J-K. Kim, and G-W. Moon, “Analysis for
LLC Resonant Converter Considering Parasitic Components at Very
Light Load Condition ,” in Proc. Power. Electron. and ECCE Asia
(ICPE&ECCE),, 2011, pp. 1863-1868.
[24] J. Lu and F. Dawson, “Characterizations of high frequency planar
transformer with a novel comb-shaped shield,” IEEE Trans. Magnetics.,
vol. 47, no. 10, pp. 44934496, Oct. 2011.
[25] M. Pahlevaninezhad, D. Hamza, and P. K. Jain, “An improved
layout strategy for common-mode EMI suppression applicable to high
frequency planar transformers in high-power DC/DC converters used
for electric vehicles,” IEEE Trans. Power. Electron., vol. 29, no. 3, pp.
12111228, Mar. 2014. Martin Ordonez (S02M09) was born in
[26] H. Y. Lu, J. G. Zhu, and S. Y. R. Hui, “Experimental determination Neuquen, Argentina. He received the Ing. de-
of stray capacitances in high frequency transformers,” in IEEE Trans. gree in electronics engineering from the National
Power Electron, vol. 18, no. 5, pp. 1105-1112, Sep. 2003. Technological University, Cordoba, Argentina, in
[27] M. A. Saket, N. Shafiei, M. Ordonez, M. Craciun, and C. Botting 2003, and the M.Eng. and Ph.D. degrees in elec-
“Low parasitics planar transformer for LLC resonant battery chargers,” trical engineering from the Memorial University
in Proc. IEEE Applied Power Electronics Conf. and Expo., 2016, vol. of Newfoundland (MUN), St. Johns, NL, Canada,
1, pp. 854-858, Mar 2016. in 2006 and 2009, respectively.
[28] F. Blache, J. P. Keradec and B. Cogitore, “Stray capacitance of two He is currently an Assistant Professor with the
winding transformer: equivalent circuit, measurments, calculation and Department of Electrical and Computer Engineer-
Lowering,” in IEEE Ind. application Society Annual Meeting, Vol. 2, ing, University of British Columbia, Vancouver,
1994, pp l2ll-1217. BC, Canada. He is also a Canada Research Chair in Power Converters
for Renewable Energy Systems, as well as an Adjunct Professor with
Simon Fraser University, Burnaby, BC, Canada, and MUN. His industrial
experience in power conversion includes research and development at
Xantrex Technology Inc./Elgar Electronics Corp. (now AMETEK Pro-
grammable Power in San Diego, California), Deep-Ing Electronica de
Potencia (Rosario, Argentina), and TRV Dispositivos (Cordoba, Argentina).
With the support of industrial funds and the Natural Sciences and Engi-
neering Research Council, he has contributed to more than 60 publications
and R&D reports.
Dr. Ordonez is an Associate Editor of the IEEE TRANSACTIONS
Mohammad Ali Saket (S’15) was born in ON POWER ELECTRONICS, serves on several IEEE committees, and
Tehran, Iran. He received the B.Sc. degree in reviews widely for IEEE/IET journals and international conferences. He
Electrical Engineering from the Amirkabir Uni- was awarded the David Dunsiger Award for Excellence in the Faculty
versity of Technology, Tehran, Iran, in 2009, and of Engineering and Applied Science (2009) and the Chancellors Graduate
the M.Sc. degree in Power Electronics from Sharif Award/Birks Graduate Medal (2006), and became a Fellow of the School
University of Technology, Tehran, Iran, in 2011. of Graduate Studies, MUN.
He is currently a PhD student at the University of
British Columbia (UBC), Vancouver, BC, Canada.
His research interests include planar magnetics,
wireless power transfer, and resonant converters.
He is currently working toward high-efficiency
and low parasitic integrated magnetic structures for resonant DC-DC
converters.

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Low Parasitics Planar Transformer For LLC Resonant Battery Chargers

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Low Parasitics Planar Transformer For LLC Resonant Battery Chargers

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This article has been accepted for publication in a future issue of this journal, but has not been

LLC Converters with Planar Transformers: Issues

Ls ip Rac1 Llk1 Rac2 Llk2 is D5 D7 vo Llk

formula to calculate the AC resistance that is presented in the (6).

I 1 Rac1 Llk1 n:1

At Total area of turns 5.1e-005

(a) (b) (c)

(d) (e) (f)

PCB4 PCB3 PCB2 PCB1

Insulation between PCBs

Insulation between PCBs

Secondary part 2 Primary part 2 Secondary part 1 Primary part 1

(a) 33 pJ (b) 1.7 pJ

(c) 10.5 pJ (d) 3.4 pJ

(e) 2.15 pJ (f) 1.1 pJ

A. No overlapping winding layouts means having ( n+1

Normalized Intra−winding Capacitance

Normalized Intra−winding Capacitance

Fig. 13: Variations of DC resistance and intra-winding capacitance

without doubling the DC resistance. An eight turns winding lay-

comparison to the no overlapping winding layouts that have 100%

PCB1 PCB2 PCB3 PCB4 PCB5 PCB6 PCB7 PCB8

Connection between Connection between

number of layers or to increase the separation distance in the 60 31 Times less

2) No increment in the value of DC resistance. The same DC

of primary and secondary, resulting in a less inter-winding 70

J (A/m ) P1 less inter-winding Capacitance 100

Leakage Inductance (µH)

S1-1 P1 S2-2 S1-2 S2-1

PCB2 PCB8 PCB8 PCB8 PCB8 PCB8

reduce the inter-winding capacitance. On the other hand, the PCB

TABLE IV: Parameters definition

air significantly reduces the inter-winding capacitance. Among

High frequency ocilation on transformer No Load

Very small voltage ocilation due to Very Light-Loading

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