FILL IN THE BLANKS:

1. FIRST MICROPROCESSOR WAS INTRODUCED IN 1971 .

2. PENTIUM WAS INTRODUCED IN 1993.

3. 8086 HAS 6 FLAG REGISTER.

4. 8086 HAS 40 PINS.

5. 8086 HAS 14 16 bits REGISTERS.

6. 8086 HAS 4 (cs, ds, ss and es.) SEGMENT REGISTERS.

7. 8086 HAS 1 MB MEMORY SIZE.

8. 8085 HAS 64 KB MEMORY SPACE.

9. 8086 WAS INTRODUCED IN 1978.

10. 8086 HAS 20 BIT ADDRESS BUS BITS

11 . 8086 HAS 16 BIT DATA BUS BITS.

12. 8085 IS 8-bit microprocessor

BIT MICROPROESSOR.

13. 8085 HAS 8 BIT DATA BUS BITS AND 16 BIT ADDRESS BUS BITS.

14. 8085 HAS 3MHz–6MHz CLOCK FREQUENCY.

15. 8086 HAS 2 POINTER REGISTERS.

16. 8086 HAS 2 (SI (Source Index) and DI (Destination Index)) INDEX REGISTERS.

17. THE FIRST MICROPROCESSOR WAS 4 BIT MICROPROCESSOR.

18. I CORE 5 WAS INTRODUCED IN 2009 YEAR.

19. 80486 IS 32 BIT MICROPROCESSOR.

20. 64 BIT MIROPROCESSOR IS ........

LONG QUESTION ANSWER

Q1. EXPLAIN MICROPROCESSOR AND ITS COMPONENTS.

Ans:- A microprocessor is a computer processor for which the data processing logic and control is
included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the
arithmetic, logic, and control circuitry required to perform the functions of a computer's central
processing unit (CPU).

1. Arithmetic Logic Unit (ALU): The ALU performs arithmetic (addition, subtraction, multiplication,
division) and logical (AND, OR, NOT) operations on data. It's responsible for executing mathematical
and logical operations specified by the instructions.

2.Control Unit (CU): The control unit manages the execution of instructions. It decodes instructions
fetched from memory, directs the flow of data between various functional units, and controls the
operation of other hardware components to execute instructions in the correct sequence.

3.Registers: Registers are small, high-speed storage units within the CPU used to store temporary
data, addresses, and intermediate results during processing. Common types of registers include the
program counter (PC), instruction register (IR), accumulator (ACC), and general-purpose registers
(GPRs).

4.Clock Generator: The clock generator produces clock signals that synchronize the operation of
various components within the microprocessor. The clock signal determines the speed at which
instructions are executed, commonly measured in Hertz (Hz) or megahertz (MHz).

5.Cache Memory: Cache memory is a small, high-speed memory located directly on the CPU chip. It
stores frequently accessed instructions and data to reduce the time required to access them from
slower main memory (RAM). Cache memory helps improve overall system performance by reducing
memory latency.

6.Data Bus: The data bus is a bi-directional pathway that carries data between the CPU, memory,
and other peripheral devices. It consists of multiple parallel lines, each capable of transmitting a
single bit of data at a time.

7.Address Bus: The address bus is a unidirectional pathway used to specify the memory addresses of
data or instructions being read from or written to memory. It determines the range of memory
locations that the CPU can access.

8.Instruction Set Architecture (ISA): The ISA defines the set of instructions that the microprocessor
can execute, including their formats, operation codes, and addressing modes. It serves as the
interface between software programs and the hardware implementation of the microprocessor.
Q2. EXPLAIN ALU, REGISTER ARRAY AND TIMING CONTROL UNIT OF MICROPROCESSOR

Ans:-

1.Arithmetic Logic Unit (ALU):

 The ALU is the part of the microprocessor responsible for performing arithmetic and logical
operations on data.
 Arithmetic operations include addition, subtraction, multiplication, and division. Logical
operations include AND, OR, XOR, and NOT.
 ALU operations are controlled by the control unit based on the instructions fetched from
memory.
 It typically consists of combinational logic circuits that perform the desired operations on
binary data.
 The ALU usually has two inputs (operands) and produces a single output (result). These
inputs and outputs are typically stored in registers.

2.Register Array:

 Registers are small, high-speed storage units within the CPU used to store temporary data,
addresses, and intermediate results during processing.
 The register array typically consists of several types of registers, each serving a specific
purpose:
o Program Counter (PC): Stores the memory address of the next instruction to be fetched.
o Instruction Register (IR): Holds the current instruction being executed.
o Accumulator (ACC): Often used as the primary register for arithmetic and logic operations.
o General-Purpose Registers (GPRs): Used for storing operands, intermediate results, and
other temporary data.
o Special-Purpose Registers: Serve specific functions, such as the stack pointer, index registers,
and status flags.
 Registers are typically implemented using flip-flops or other memory elements and are
directly accessible by the ALU and other CPU components.

3.Timing Control Unit:

 The timing control unit (TCU) manages the timing and sequencing of operations within the
microprocessor.
 It generates clock signals that synchronize the operation of various components, ensuring
that instructions are executed in the correct sequence and at the appropriate times.
 The TCU generates control signals that coordinate the flow of data between the CPU,
memory, and peripheral devices.
 It may include counters, timers, and other circuitry to generate precise timing signals
required for instruction execution and data transfer.
 The TCU ensures that the microprocessor operates reliably and efficiently by coordinating
the timing of internal operations and external interactions.
 The clock speed and timing characteristics of the TCU significantly impact the performance
and reliability of the microprocessor-based system.
Q3. EXPLAIN EVOLUTION OF MICROPROCESSOR.

Ans:-

Q4. DRAW THE ARCHITECTURE OF 8086.

Ans:-

It is internally divided into two separate functional units. These are the Bus Interface Unit (BIU) and
the Execution Unit (EU). These two functional units can work simultaneously to increase system
speed and hence the throughput. Throughput is a measure of number of instructions executed per
unit time.
Q5. EXPLAIN THE FEATURES OF 8086 .

Ans:-

i) It is 1 MB of memory.

ii) It is 20 bit address bus.

iii) It is 16 bit data bus.

iv) It is a 16 bit microprocessor

v) It is support pipelining.

vi) It is high speed than 8085.

vii) It can support up to 64 kb I/O port.

viii) 40 pin dual in line package.

ix) Designed to operate in 2 modes:

 Minimum mode
 Maximum mode

Q6. EXPLAIN THE FEATURES OF 8085.

Ans:-

i) It is 64 kb of memory.

ii) It is 16 bit address bus.

iii) It is 8 bit data bus.

iv) ) It is a 8 bit microprocessor

v) It is does not support pipelining.

vi) It has 6500 transistors.

Q7. EXPLAIN THE FEATURES OF 80286,80386,PENTIUM PROCESSOR.

Ans:- FEATURES OF 80286

i) The Intel 80286 is a high-performance 16-bit microprocessor.

ii) It has been specially designed for multiuser and multitasking systems.

iii) Various versions of 80286 are available that run on 12.5MHz, 10 MHz and 8 MHz clock
frequencies.

iv) The 80286 is the first CPU to incorporate the integrated memory management unit.
 v) It has four-level memory protection and support for virtual memory and operating system.

FEATURES OF 80286

i) 32 bit processor.

ii) The 80386 includes 32-bit extended registers.

iii) It has 32-bit address and data bus.

iv) The 80386 has a physical memory size of 4GB.

v) The 80386 is operated in the pipelined mode.

vi) The concept of paging is included.

vii) 80386 has on chip address translation cache.

viii) 20-33 MHz frequency.

FEATURES OF PENTIUM PROCESSOR

i) 64 bit data bus.

ii) 8 bytes of data information can be transferred to and from memory in a single bus cycle.

iii) Supports burst read and burst write back cycles.

iv) Supports pipelining.

v) Instruction cache.

vi) 8 KB of dedicated instruction cache.

vii) Faster internal operations.

viii) Data Integrity and Error Detection.

Q8. EXPLAIN BIU AND EU OF 8086 MICCROPROCESSO.

Ans:- The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It
performs various machine cycles such as memory read, I/O read, etc. to transfer data between
memory and I/O devices.
BIU performs the following functions are as follows:
 It generates the 20-bit physical address for memory access.
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction queue(supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and
an Address Generation Circuit.

Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers,
the Instruction Register and Instruction Decoder, and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic
operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.(Control
Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.

Q9. EXPLAIN FLAG REGISTER OF 8086.

Ans:- The flag register is a 16-bit register in the Intel 8086 microprocessor that contains
information about the state of the processor after executing an instruction. It is sometimes referred
to as the status register because it contains various status flags that reflect the outcome of the last
operation executed by the processor.
The flag register is an important component of the 8086 microprocessor because it is used to
determine the behavior of many conditional jump and branch instructions. The various flags in the
flag register are set or cleared based on the result of arithmetic, logic, and other instructions
executed by the processor.
The flag register is divided into various bit fields, with each bit representing a specific flag. Some of
the important flags in the flag register include the carry flag (CF), the zero flag (ZF), the sign flag
(SF), the overflow flag (OF), the parity flag (PF), and the auxiliary carry flag (AF). These flags are
used by the processor to determine the outcome of conditional jump instructions and other
branching instructions.
Purpose Register. Depending upon the value of result after any arithmetic and logical operation the
flag bits become set (1) or reset (0).

Q10. EXPLAIN REGISTER ORGANIZATION OF 8086.

Ans:- General 16-bit registers

The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word,
and AH contains the high-order byte. Accumulator can be used for I/O operations, rotate and string
manipulation.

BX Register: This register is mainly used as a base register. It holds the starting base location of a
memory region within a data segment. It is used as offset storage for forming physical address in
case of certain addressing mode.

CX Register: It is used as default counter or count register in case of string and loop instructions.

DX Register: Data register can be used as a port number in I/O operations and implicit operand or
destination in case of few instructions. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.

Q11. EXPLAIN PIPELINING IN 8086 AND ITS ADVANTAGES.

Ans:- In the context of computer architecture, pipelining refers to a technique used to improve the
performance of a processor by allowing multiple instructions to be processed simultaneously. In the
case of the 8086 processor, which is a popular microprocessor architecture developed by Intel,
pipelining is achieved through a series of stages in the instruction execution process.

Here's how pipelining works in the 8086 processor:

Instruction Fetch (IF): The processor fetches the next instruction from memory.

Instruction Decode (ID): The fetched instruction is decoded to determine the operation to be
performed.

Execution (EX): The instruction is executed, which may involve arithmetic or logical operations,
memory accesses, or control flow operations.

Memory Access (MEM): If the instruction requires accessing memory, such as reading or writing
data, this stage handles those operations.

Write Back (WB): The results of the instruction execution are written back to the appropriate
registers or memory locations.

Advantages of pipelining in the 8086 processor include:

Increased throughput: Pipelining allows multiple instructions to be processed simultaneously,

leading to a higher overall instruction execution rate and improved performance.

Better resource utilization: By overlapping the execution of instructions, pipelining helps in utilizing
the processor's resources more efficiently, reducing idle time and maximizing throughput.

Smoother operation: Pipelining helps in reducing the impact of individual instruction latencies by
breaking down the instruction execution process into smaller stages. This results in smoother and
more consistent operation of the processor.
Improved instruction-level parallelism: Pipelining enables the exploitation of instruction-level
parallelism within a program by executing multiple instructions concurrently. This leads to faster
program execution and better overall performance.

Q12. DIFFERENTIATE BETWEEN 8086 AND 8085.

Ans:-

Q13. EXPLAIN THE PIN DIAGRAM OF 8086.

Ans:- The Intel 8086 is 40 pin DIP Microprocessor. Here we will see the actual pin level diagram of
8086 MPU.

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip. Let us
now discuss in detail the pin configuration of a 8086 Microprocessor.
AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with data.
When AD lines are used to transmit memory address the symbol A is used instead of AD, for
example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16-A19: High order address bus. These are multiplexed with status signals. S2, S1, S0: Status pins.
These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or
Tw (when ready is inactive). These are used by the 8288 bus controller for generating all the memory
and I/O operation) access control signals. Any change in S2, S1, S0 during T4 indicates the beginning
of a bus cycle.
S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state
A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding
status signals.
A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant
half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low)
signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.
RD’: This is used for read operation. It is an output signal. It is active when low.
READY : This is the acknowledgement from the memory or slow device that they have completed
the data transfer. The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the microprocessor. The signal is active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each
instruction for determining the availability of the request. If any interrupt request is found pending,
the processor enters the interrupt acknowledge cycle. This can be internally masked after resulting
the interrupt enable flag. This signal is active high(1) and has been synchronized internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A
subroutine is then vectored through an interrupt vector lookup table which is located in the system
memory. NMI is non-maskable internally by software. A transition made from low(0) to high(1)
initiates the interrupt at the end of the current instruction. This input has been synchronized
internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge
cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the
microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of
the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to
gain control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the
completion of the next instruction.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue,
else the processor remains in an idle state. The input is internally synchronized during each of the
clock cycle on leading edge of the clock.
CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control
activity. Its an asymmetric square wave with a 33% duty cycle.
RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal
must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue
according to the table shown below:
QS1 QS0 Status

0 0 No operation
QS1 QS0 Status

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

M/IO’: This signal is used to distinguish between memory and I/O operations. The M Signal is Active
high whereas the IO’ Signal is Active Low. When this Pin is High, the memory operations takes place.
On the other hand, when the Pin is low, the Input/Output operations from the peripheral devices
takes place.
=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286
or 8287 data bus transceiver. The direction of data flow is controlled through the transceiver.
DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system
which uses transceiver. DEN is active low(0) during each memory and input-output access and for
INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an active
high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an
acknowledgement in the middle of a T4 or T1 clock cycle.
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282
or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never
floated, is always integer.

Q14. Explain 20 bit physical address generation of 8086.

Ans:- The 8086 addresses a segmented memory. The complete physical address which is 20-bits
long is generated using segment and offset registers each of the size 16-bit.The content of a segment
register also called as segment address, and content of an offset register also called as offset
address. To get total physical address, put the lower nibble 0H to segment address and add offset
address. The figure shows the formation of 20-bit physical address.