Scribd
Upload
49 views

Class - Analog CMOS Design & Tech - Part-12

The document discusses op-amp bandwidth, unity gain frequency, common mode rejection ratio, offset, noise, and slew rate. It provides equations and explanations for calculating these parameters and improving circuit performance. Matching considerations for fabrication are also covered.

Uploaded by

Mainuddin Mondal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
49 views

Class - Analog CMOS Design & Tech - Part-12

The document discusses op-amp bandwidth, unity gain frequency, common mode rejection ratio, offset, noise, and slew rate. It provides equations and explanations for calculating these parameters and improving circuit performance. Matching considerations for fabrication are also covered.

Uploaded by

Mainuddin Mondal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 15

Course code: ET/PC/B/T/316

Analog CMOS Design &


Technology
Part-12
Sep 2023

Dr. Joydeep Basu, Assistant Professor


Dept. of Electronics & Telecommunication Engg., Jadavpur University
https://jadavpuruniversity.in/faculty-profile/joydeep-basu
Op-amp BW, UGF
pole/zero: freq at
 Frequency response: which denominator
/numerator = 0
 We need to derive the transfer function
 Each node of the circuit generates one pole
(generally true for many circuits)

 Pole frequency - multiply the total equivalent capacitance at that


node (to Gnd) by the total (small-signal) resistance (to Gnd)

 E.g., for the simple case:

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 2


Op-amp BW, UGF
 Transfer function of the single-stage opamp:
 Pole at node-A: 𝜔𝑝𝐴 ≈ 𝑔𝑚3 Τ(𝐶𝐺𝑆3 + 𝐶𝐺𝑆4 + 𝐶𝐷𝐵3 + 𝐶𝐷𝐵1 )

 Pole at node-B: doesn’t affect the differential operation

 Pole at node-C: 𝜔𝑝𝐶 ≈ 1Τ 𝑟𝑜2 ||𝑟𝑜4 𝐶𝐿

 The o/p pole is at a much lower frequency  “dominant pole”

 Thus, the transfer fn:


𝑉𝑜𝑢𝑡 𝐴𝑉0 𝐴𝑉0
≈ ≈
(𝑉𝑖𝑝 − 𝑉𝑖𝑛 ) (1 + 𝑠 )(1 + 𝑠 ) (1 + 𝑠 )
𝜔𝑝𝐴 𝜔𝑝𝐶 𝜔𝑝𝐶

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 3


Op-amp BW, UGF
 Frequency Response: 𝑉𝑜𝑢𝑡 𝐴𝑉0
≈
(𝑉𝑖𝑝 − 𝑉𝑖𝑛 ) (1 + 𝑠 )
𝜔𝑝𝐶

 For one-pole approximation as above: 3dB bandwidth (BW) = 𝜔𝑝𝐶


1
 Thus, gain-bandwidth product (GBW) = 𝐴𝑉0 ∙
𝑟𝑜2 ||𝑟𝑜4 𝐶𝐿
𝑔𝑚1
=
𝐶𝐿

Unity-gain freq (UGF)


𝜔𝑢 = GBW for single-
pole system

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 4


Op-amp BW, UGF
Exercise-1:
Find the values of 3-dB BW and GBW of the 5T OTA. Given VDD= 1.8 V, VTHn= 0.5 V,
VTHp= -0.4 V, μnCox= 100 μA/V2 = 2μpCox, and λn= 0.1 V−1 = 0.5λp. Also, (W/L)1,2 = 40, CL =
10 pF and I0 = 1 mA.

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 5


Op-amp CMRR
 In an opamp/diff-amp, we want to amplify the differential i/p signal (gain say, Adm)
 O/p signal component produced by CM variations (gain say, Acm)  undesirable effect
 It should reject any common signal applied to both the inputs (e.g., coupled noise)

 Common-mode rejection ratio (CMRR) = desired gain divided by the undesired gain
𝐴𝑑𝑚
CMRR = 20 ∙ 𝑙𝑜𝑔 (dB)
𝐴𝑐𝑚

Inferior with
respect to FD amp
– similar for PSRR

1
 Here, 𝐴𝑐𝑚 = −
2𝑔𝑚3 𝑅0

J. Basu Image: R. Baker, CMOS Circuit Design, Layout, and Simulation 6


Op-amp CMRR
1
 As 𝐴𝑐𝑚 = −
2𝑔𝑚3 𝑅0

 Thus, CMRR improved by increasing the o/p resistance of tail current sink

 Further, due to mismatches (during fabrication) between two sides of the ckt, there
is common-mode to differential conversion

J. Basu Image: R. Baker, CMOS Circuit Design, Layout, and Simulation 7


Matching Considerations
 M1 & M2, M3 & M4 are supposed to be identical to each other
 but will have fabrication induced mismatches
 99.9% (999 out of 1000) fabricated values within (μ ± 3σ)

 Layout design techniques to enable better matching


 The i/p pair to be laid out in a common-centroid
configuration
 Allows the two devices to cancel
process gradients in both the x
and y directions
Matched
Large devices lead devices
to better matching

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 8


Op-amp Offset
 Due to mismatches (of VTH, geometries) between M1 & M2, and M3 & M4

 Output offset voltage: vout ≠ 0 even when vip = vin = 0 i.e., differential i/p is zero
 To produce zero output, an input offset voltage can be applied:

𝑣𝑜𝑢𝑡
𝑉𝑂𝑆 =
𝐴𝑑𝑚

 Thus, offset expressed as “input-referred” Contributes


to offset
equivalent voltage source

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 9


Op-amp Offset
 Contribution to total offset voltage due to each of M1 & M2, M3 & M4 (eq. small-
signal sources) can be separately computed and added
𝑔𝑚3
 Thus, 𝑉𝑂𝑆 = ∆𝑉1,2 − ∆𝑉3,4
𝑔𝑚1

 We are not interested in exact value of offset for ΔV


3,4
𝑔𝑚1 ∆𝑉1,2 − 𝑔𝑚3 ∆𝑉3,4
each opamp  instead mean-square/std. deviation
of offset
𝑔𝑚3 2 ΔV
 𝜎𝑉2𝑂𝑆 = 𝜎𝑉21,2 + ∙ 𝜎𝑉23,4 1,2
𝑔𝑚1

o/p is shorted
to incremental
(ac) ground

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 10


Op-amp Noise
 All devices within the opamp generate noise (thermal, 1/f, etc.)
 Net noise current at the o/p:
𝑖𝑛,𝑜𝑢𝑡 = 𝑖𝑛,1 − 𝑖𝑛,2 + 𝑖𝑛,3 − 𝑖𝑛,4
 Uncorrelated from each other

in3 in4
 Thus, o/p current noise spectrum:
16
𝑆𝑖𝑛,𝑂𝑈𝑇 = 𝑆𝑖𝑛,1 + 𝑆𝑖𝑛,2 + 𝑆𝑖𝑛,3 + 𝑆𝑖𝑛,4 = 𝑘𝑇(𝑔𝑚1 +𝑔𝑚3 )
3 in1 in2

in0

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 11


Op-amp Noise
 Can be represented as an input-referred equivalent voltage source (just like offset)
 called “input-referred noise”
 Determines the minimum signal level that can be processed with reasonable quality

16 1 𝑔𝑚3
 I/p referred noise voltage: 𝑆𝑣𝑛,𝐼𝑁 = 3
𝑘𝑇
𝑔𝑚1
+ 2
𝑔𝑚1
in3 in4

in1 in2

in0

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 12


Op-amp Slew-Rate
 Slew-rate (SR) is the max. possible rate of change of the o/p: (𝑑𝑉𝑜𝑢𝑡 Τ𝑑𝑡)max
 Large-signal o/p may be limited by SR due to limited current available to charge and
discharge the dominant capacitor (CL)

 Slewing is a nonlinear phenomenon


 E.g., with step i/p to a unity-gain buffer: response is exponential for small inputs;
whereas a linear ramp (with a constant slope) for large input steps
 creates o/p distortion

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 13


Op-amp Slew-Rate
 For the OTA – with large enough input swing, either M1 or M2 turns off:
𝐼𝑆𝑆
𝑆𝑅+ = = 𝑆𝑅−
𝐶𝐿

J. Basu Image: R. Baker, CMOS Circuit Design, Layout, and Simulation 14


Op-amp Noise
Home Exercise:
I/p-referred-noise voltage of each transistor of the 5T OTA is 1 nV/√Hz.
(a) Find the i/p-referred-noise voltage for this amplifier if (W/L)1,2 = 2 um/1 um, (W/L)3,4
= 1 um/1 um, CL = 10 pF and I0 = 50 uA.
Given μnCox= 100 μA/V2 = 2μpCox.
(b) Find the equivalent output noise current.
(c) What is the slew-rate under these conditions?

J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 15

You might also like