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Mux Demux

The document discusses writing VHDL code for a 4x1 multiplexer and 1x4 demultiplexer. It includes the theory, truth tables and VHDL code using a behavioral modeling approach for both the multiplexer and demultiplexer.

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Vinay Rai
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14 views

Mux Demux

The document discusses writing VHDL code for a 4x1 multiplexer and 1x4 demultiplexer. It includes the theory, truth tables and VHDL code using a behavioral modeling approach for both the multiplexer and demultiplexer.

Uploaded by

Vinay Rai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Expt No:2 MULTIPLEXER AND DEMULTIPLEXER Date:

AIM: To write VHDL codes for Multiplexer and Demultiplexer.

SOFTWARE REQUIRED: Modelsim SE 5.7g/ Modelsim PE student edition

THEORY:
A 4x1 Multiplexer or mux also known as data selector is a device that has many
inputs and a single output. The selected line decides which input is connected
to the output.
A 1x4 demultiplexer or demux is a device, that has one input and multiple
output lines which is used to send a signal to one of the various devices.

TRUTH TABLE:
4x1 Mux: 1x4 Demux:

Select Output
s1 s0 y
0 0 I1 Select Output
s1 s0 Y4 Y3 Y2 Y1
0 1 I2
0 0 0 0 0 In
1 0 I3
0 1 0 0 In 0
1 1 I4
1 0 0 In 0 0
1 1 In 0 0 0
VHDL code for 4x1 MUX

entity multiplexer is
port(I: in bit_vector(3 downto 0) ; S: in bit_vector(1 downto 0) ; O: out bit);
end multiplexer;

architecture testmux of multiplexer is


begin
process(S,I)
begin
case S is
when "00" => O <= I(0);
when "01" => O <= I(1);
when "10" => O <= I(2);
when "11" => O <= I(3);
end case;
end process;
end testmux;

entity testmux is
end testmux;

architecture mux of testmux is


component multiplexer
port(I: in bit_vector(3 downto 0) ; S: in bit_vector(1 downto 0) ; O: out bit);
end component;

signal I: bit_vector(3 downto 0);


signal S: bit_vector(1 downto 0);
signal O: bit;

begin
A: multiplexer port map (I,S,O);

process
begin
I(0) <= '1';
S <= "00";
wait for 5 ns;
I(0) <= '0';
S <= "00";
wait for 5 ns;
I(1) <= '1';
S <= "01";
wait for 5 ns;
I(1) <= '0';
S <= "01";
wait for 5 ns;
I(2) <= '1';
S <= "10";
wait for 5 ns;
I(2) <= '0';
S <= "10";
wait for 5 ns;
I(3) <= '1';
S <= "11";
wait for 5 ns;
I(3) <= '0';
S <= "11";
wait for 5 ns;
end process;
end mux;
VHDL code for Demux

entity demultiplexer is
port(I: in bit ; S: in bit_vector(1 downto 0) ; O: out bit_vector(3 downto 0));
end demultiplexer;

architecture arcdemux of demultiplexer is


begin
process(S,I)
begin
case S is
when "00" => O(0) <= I;
when "01" => O(1) <= I;
when "10" => O(2) <= I;
when "11" => O(3) <= I;
end case;
end process;
end arcdemux;

entity testdemux is
end testdemux;

architecture demux of testdemux is


component demultiplexer
port(I: in bit ; S: in bit_vector(1 downto 0) ; O: out bit_vector(3 downto 0));
end component;

signal I: bit;
signal S: bit_vector(1 downto 0);
signal O: bit_vector(3 downto 0);

begin
A: demultiplexer port map (I,S,O);

process
begin
I <= '1';
S <= "00";
wait for 5 ns;
I <= '0';
S <= "00";
wait for 5 ns;
I <= '1';
S <= "01";
wait for 5 ns;
I <= '0';
S <= "01";
wait for 5 ns;
I <= '1';
S <= "10";
wait for 5 ns;
I <= '0';
S <= "10";
wait for 5 ns;
I <= '1';
S <= "11";
wait for 5 ns;
I <= '0';
S <= "11";
wait for 5 ns;
end process;
end demux;

1) Multiplexer in VHDL using behavioral method

2) Demultiplexer in VHDL using behavioral method

CONCLUSION: The VHDL codes for mux and demux were written and
implemented successfully.

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