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CMPSB/CMPSW
 Used to compare two strings of bytes or words.
 Length of the byte/ word string in CX.
 If both bytes/ words are equal, ZF is set.
 Strings are stored in DS:SI & ES:DI
 REP is used to repeat the comparison operation till CX=0 or
condition specified by REP fails.

CMPSB/CMPSW - Example

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Process Control & Branch Transfer

Instructions

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• Transfers the flow of execution of the program to a new address

specified in the instruction directly or indirectly
• CS and IP registers get loaded with new values of CS and IP
corresponding to the location to be transferred

• Unconditional Branch Instructions

• Conditional Branch Instructions

• Execution control is transferred to the specified location

independent of any status or condition
• The CS and IP unconditionally modified to the new CS and IP

• CALL : Unconditional Call

– Call a Subroutine (Procedure) from a main program
– Address of procedure may be specified directly or indirectly
– NEAR CALL i.e., ±32K displacement
– FAR CALL i.e., anywhere outside the segment
– Stores the incremented IP & CS onto the stack and loads the CS
& IP registers with segment and offset addresses of the
procedure to be called

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• RET: Return from the Procedure

– At the end of the procedure, the RET instruction must be
executed
– Previously stored content of IP and CS along with Flags are
retrieved into the CS, IP and Flag registers from the stack
– Execution of the main program continues further
• INT N: Interrupt Type N
– In the interrupt structure of 8086, 256 interrupts are defined
corresponding to the types from 00H to FFH
– Type byte N is multiplied by 4 and the contents of IP and CS of
the interrupt service routine will be taken from memory block in
0000 segment

• INTO: Interrupt on Overflow

– Executed, when the overflow flag OF is set.
– This is equivalent to a Type 4 Interrupt instruction
• JMP: Unconditional Jump
– Unconditionally transfers the control of execution to the specified
address using an 8-bit or 16-bit displacement
– No Flags are affected by this instruction
• IRET: Return from ISR
– Values of IP, CS and Flags are retrieved from the stack to
continue the execution of the main program.

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• LOOP : LOOP Unconditionally

• This instruction executes the part of the program from the Label or
address specified in the instruction up to the LOOP instruction CX
number of times
• At each iteration, CX is decremented automatically and JUMP IF
NOT ZERO structure.
• MOV CX, 0004H
• MOV BX, 7526H
• Label 1 MOV AX, CODE1
• OR BX, AX
• AND BX, AX
• LOOP Label 1

• Execution control is transferred to the address specified relatively in

the instruction, provided the condition implicit in the Opcode is
satisfied
• Otherwise execution continues sequentially.

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AD0-AD15 (Bidirectional)
• Low order address bus; these are
multiplexed with data.
• When AD lines are used to transmit
memory address the symbol A is used
instead of AD, for example A0-A15.
• When data are transmitted over AD
lines the symbol D is used in place of
AD, for example D0-D7, D8-D15 or D0-
D15.

A16/S3, A17/S4, A18/S5, A19/S6

• High order address bus.
• These are multiplexed with status
signals.

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BHE (Active Low)/S7 (Output)

Bus High Enable/Status
• It is used to enable data onto the
most significant half of data bus, D8 -
D15.
• 8-bit device connected to upper half
of the data bus use BHE (Active Low)
signal.
• It is multiplexed with status signal S7
.

RD (Read) (Active Low)

• The signal is used for read operation.
• It is an output signal.
• It is active when low.

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𝑻𝑬𝑺𝑻 (PIN 23)- Active Low

• 𝑇𝐸𝑆𝑇 input is tested by the ‘WAIT’ instruction.
• 8086 will enter a wait state after execution of the WAIT instruction and
will resume execution only when the 𝑇𝐸𝑆𝑇 is made low by an active
hardware.
• This is used to synchronize an external activity to the processor internal
operation.
READY (PIN 22) – Active High
• This is the acknowledgement from the slow device or memory that
they have completed the data transfer.
• The signal made available by the devices is synchronized by the 8284A
clock generator to provide ready input to the 8086.

RESET (Input)- Active high

• Causes the processor to immediately terminate its present activity.
• The signal must be active HIGH for at least four clock cycles.
CLK
• The clock input provides the basic timing for processor operation and
bus control activity.
• Its an asymmetric square wave with 33% duty cycle.
• This signal is active high and internally synchronized.

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INTR Interrupt Request- Active high

• This is a triggered input. This is sampled during the last clock cycles of
each instruction to determine the availability of the request.
• If any interrupt request is pending, the processor enters the interrupt
acknowledge cycle.
• This signal is active high and internally synchronized.

𝑴𝑵/𝑴𝑿
• The 8086 microprocessor can work in two modes of operations:
Minimum mode and
Maximum mode.
• In the minimum mode of operation the microprocessor do not
associate with any co-processors and cannot be used for
multiprocessor systems.
• In the maximum mode the 8086 can work in multi-processor or
co-processor configuration.
• Minimum or maximum mode operations are decided by the pin
MN/ MX(Active low).
• When this pin is high 8086 operates in minimum mode otherwise
it operates in Maximum mode.

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Minimum mode signals

8086 Microprocessor Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied to VCC (logic

high)

8086 itself generates all the bus control signals

DT/𝐑 (Data Transmit/ Receive) Output signal from the processor to

control the direction of data flow through the data transceivers

𝐃𝐄𝐍 (Data Enable) indicates the availability of valid data over the
address/ data lines. It is used to enable the transceivers to
separate the data from the muliplexed address/data signal. It is
active from the middle of T2 until the middle of T4.

ALE (Address Latch Enable) Indicates the availability of valid address on

the address/data lines

M/𝐈𝐎 Used to differentiate memory access and I/O access. For memory
reference instructions, it is high. For IN and OUT instructions, it is
low.

𝐖𝐑 Write control signal; asserted low Whenever processor writes data

to memory or I/O port

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt request is accepted by

the processor, the output is low on this line.

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Minimum mode signals

8086 Microprocessor

HOLD Indicates to the processor that another master is requesting

the bus access. Processor issues HLDA in the middle of next
clock cycle, after completing the current bus instruction
cycle.

Usually used by the DMA controller to get the control of the

bus.

HLDA (Hold Acknowledge) Acknowledge signal by the processor

to the bus master requesting the control of the bus through
HOLD.

The acknowledge is asserted high, when the processor

accepts HOLD.

RD signal remains tristated

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Maximum mode signals

8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is grounded
(logic low)

Pins 24 -31 are reassigned

𝑺𝟎 , 𝑺 𝟏 , Status signals which indicate the type of
𝑺𝟐 operation being carried out by the processor.
These become active during T4 of the
previous cycle and remain active during T1 &
T2 of the current bus cycle.
Status lines return to passive during T3 so
that they may again become active for the
next bus cycle during T4.

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Maximum mode signals

8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is grounded
(logic low)

Pins 24 -31 are reassigned

𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the

status of queue in these lines.

The queue status can be used by external

device to track the internal status of the
queue in 8086.

The output on QS0 and QS1 can be

interpreted as shown in the table.

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Maximum mode signals

8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is grounded
(logic low)

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are

𝐑𝐐/𝐆𝐓𝟏 used by other local bus masters to force the
processor to release the local bus at the end of
the processor’s current bus cycle.

These pins are bidirectional.

The request on 𝐆𝐓𝟎 will have higher priority

than𝐆𝐓𝟏
𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix
instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.
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• Instructions to the Assembler regarding the program being

executed.
• No machine codes are generated for assembler directives.
• Also called ‘pseudo instructions’.
• Used to:
– › specify the start and end of a program
– › attach value to variables
– › allocate storage locations to input/ output data
– › define start and end of segments, procedures, macros etc..
Example: Org 2000h
Start:
End start
Assume DS: Data

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• PRICES DB 49H, 98H, 29H Declare array of 3 bytes named PRICE

and initialize them with specified values.
• NAMES DB “THOMAS” Declare array of 6 bytes and initialize with
ASCII codes for the letters in THOMAS.
• RESULT DB 100 DUP (?) Set aside 100 bytes of storage in
memory and give it the name RESULT. But leave the 100 bytes
un-initialized.
• PRESSURE DB 20H DUP (0) Set aside 20H bytes of storage in
memory, give it the name PRESSURE and put 0 in all 20H
locations.

• Addition of two 16-bit Numbers

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• Addition of two 16-bit Numbers

With the neat flowchart/algorithm write a program in 8086

assembly to arrange a set of ten 8-bits numbers initialized in data
segment in ascending order.

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Algorithm:
1. Initialize the data segment.
2. Initialize the number of elements counter.
3. Initialize the pointer and number of comparisons
counter.
4. Compare the elements. If first element < second
element go to step VI else go to step V.
5. Swap the elements.
6. Increment the pointer. Decrement the
comparison counter.
7. Is count = 0? If yes, go to step VIII else go to
step IV.

Algorithm:
8. Decrement the number of elements counter.
9. Is count = 0? If yes, go to step X else go to step
III.
10.Stop.

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Label Instruction Comment

.MODEL SMALL
.STACK 100 Initialize stack segment
.DATA Initialize the data segment
NUM DW 0102H, 0154H, Initialize data
0070H, 0005H
COUNT DW 04 Initialize counter
.CODE Initialize code segment
MOV AX, @DATA Initialize data section
MOV DS, AX
MOV DX, COUNT Initialize the number of elements counter
DEC DX Number of comparisons is one less than the
number of elements

Label Instruction Comment

LOOP2: LEA SI, NUM Initialize the pointer
MOV CX, DX CX number of comparisons required
LOOP1: MOV AX, [SI] Load a data
CMP AX, [SI + 2] Compare it with next number
JC NEXT If previous number < = this number go to
next
XCHG [SI + 2], AX Swap if not sorted
MOV [SI], AX Insert in new position
NEXT: INC SI Increment si
INC SI
LOOP LOOP1 Decrement comparison counter and repeat if
not zero

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Label Instruction Comment

DEC DX Decrement number of elements counter

JNZ LOOP2 Repeat if not zero

MOV AH, 4CH Termination of the program

INT 21H
END START

Finding Largest Number: JNC L2

MOV SI, 5000 MOV AL, [SI]

MOV CL, [SI] L2: INC SI

MOV CH, 00 LOOP: L1

INC SI MOV [6000], AL

MOV AL, [SI] HLT

DEC CL

INC SI

L1 : CMP AL,[SI]

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Sorting of Numbers JC L3

(Ascending order) XCHG AL, [SI]

MOV SI, 5000H DEC SI

MOV CL, [SI] XCHG AL, [SI]

DEC CL INC SI

L1: MOV SI, 5000H L3: DEC CH

MOV CH, [SI] JNZ L2

DEC CH DEC CL

INC SI JNZ L1

L2: MOV AL, [SI] HLT

INC SI
CMP AL, [SI]

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