Journal of Information and Optimization Sciences

ISSN: 0252-2667 (Print) 2169-0103 (Online) Journal homepage: https://www.tandfonline.com/loi/tios20

A low power VCO design using composite load

for delay cell with IMOS varactor for wider tuning
range

Manoj Kumar & Vivek Jangra

To cite this article: Manoj Kumar & Vivek Jangra (2019) A low power VCO design using
composite load for delay cell with IMOS varactor for wider tuning range, Journal of Information and
Optimization Sciences, 40:2, 567-585, DOI: 10.1080/02522667.2019.1582877

To link to this article: https://doi.org/10.1080/02522667.2019.1582877

Published online: 08 Mar 2019.

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568 M. KUMAR AND V. JANGRA

1. Introduction
With ever increasing development in wireless communication
for portable devices, the need for low power, low phase noise and less
area consuming systems has increased rapidly [1]. In contemporary
communication systems, high speed digital circuits with clock recovery
has been employed. The clock recovery provides the retiming for
synchronization and clock control which tends to remove the crystal
oscillator at the receiver side [2-3]. So, to design a low power consuming
clock recovery is a challenging task. Phase-locked loop (PLL) system
has been used in modern wireless communication in which voltage-
controlled oscillator (VCO) acts as an essential part. Meanwhile, the VCO
consumes extreme power and therefore low power consumption in VCO
design is an essential requirement. The general equation of an ideal VCO
is a function of output oscillation frequency and control voltage which is
given by Eq. (1)
fout = fo + K vcoVc (1)

f −f
where f0 is the output frequency with zero control voltage and K vco = Vmax − Vmin
max min

is the VCO gain which regulates how much change in control voltage
Vc will modify the output frequency [4]. Two types of structures i.e.
inductor-capacitor (LC) tank-based circuit and complementary metal
oxide semiconductor (CMOS) ring-based circuit can be used to design a
VCO. LC tank-circuit VCO gives higher operation frequency and better
noise performance but the use of spiral inductor and capacitor needs large
chip area which increases the parasitic capacitance resulting in narrower
tuning range [5]. Also, LC tank-circuit VCO fabrication requires additional
processing stages which increase the cost of production. On the other
hand, the CMOS-based ring VCO consumes less area as no need of on-
chip inductors and possesses wider tuning range with the improvement in
packaging density [6]. CMOS ring oscillators are widely needed in recent
years due to the facility of integration and applicability with the CMOS
fabrication process. In a ring VCO, number of delay stages connected in
series form with the output of final delay stage fed back to the initial delay
stage. CMOS ring VCOs are categorized into two main topologies: single
ended VCOs and VCOs based on differential delay cells [7]. A single-
ended ring VCO topology dissipates less power but noise cancellation
problem is more prominent [8]. The differential delay cell VCOs are
much appropriate for high speed circuits in terms of lower phase noise
A LOW POWER VCO DESIGN 569

with less power consumption as it offers more versatility in enhancing

the output oscillation frequency due to even or odd number of stages.
Differential delay cell VCOs provides significant power supply rejection
performance and common mode rejection ratio [9-12]. Various techniques
of VCO design have been reported in literature to control the phase noise
and to alleviate the operating frequency along with the tuning range [12-
14]. VCO based on complementary current control lowers the phase noise
performance at the cost of higher power consumption [15]. The reduction
in output voltage swing and increment in transistor channel thermal noise
degrades the phase noise performance with the advancement in CMOS
technology [16]. So, increasing the output voltage swing and reducing
the extent of noise injected during output voltage transitions enhances
the phase noise of the ring VCO. A ring VCO offers better phase noise
but shows a narrow tuning range because of reduction in supply voltages
due to down scaling of CMOS technology [17]. Another method of coarse
or fine tuning of frequency has been reported for decreasing the noise
sensitivity by controlling the current level, however it results in higher
power consumption [18]. Subsequently, the most important consideration
while designing ring VCO is to achieve lower phase noise with low power
consumption. A single-ended ring VCO tends to decrease the substrate
noise as well as phase noise induced by the power supply. The phase noise
of the VCO is affected by the number of parameters i.e. the number of
delay stages in the closed loop, output frequency and power dissipation.
The general expression of the phase noise for a single-ended ring VCO is
given by Eq. 2 [19].
2
8 kT Vdd fo
L{∆f } = . . . (2)
3η P Vcha ∆f 2

Where h is the constant of proportionality, k is Boltzmann’s constant,

P is power dissipation, Vdd is the power supply voltage, T is absolute
temperature, Vcha is the device characteristic voltage i.e. either short channel
devices or long channel devices, fo is the output frequency of oscillation
and Df is the offset frequency by the carrier.
Various approaches for VCO tuning like output load variations,
dual delay path, multiple feedback loop and varactor tuning have been
reported in the literature [20-22]. In the reported work, a single-ended
ring VCO with composite load using IMOS varactor consists of two PMOS
transistors connected in parallel has been proposed which lowers the
phase noise and power consumption while sustaining adequate frequency
570 M. KUMAR AND V. JANGRA

tuning range. Low-loss varactors are used to overcome the dropping of

power supply voltage which reduces the effective range of control voltage
[23]. A MOS varactor is analogous to a MOS transistor with source (S),
bulk (B) and drain (D) connected to form the first terminal and gate as
second terminal. The voltage Vbg applied between bulk (B) and gate (G)
terminal controls the rate of change of MOS capacitance. A MOS varactor
generally works in three regions: depletion, accumulation and inversion.
Varactors generally operate in accumulation and inversion regions as the
capacitance attained per unit area is maximum [24]. All these modes of
operation differ with the value of Vbg and |Vth| i.e. threshold voltage. The
voltage between the accumulation and depletion region is known as flat-
band voltage (Vfb). For PMOS based MOS transistor, accumulation region
results with mobile holes and the threshold voltage Vth is exceeded by
the bulk voltage which is much higher than the gate voltage i.e. Vbg < Vfb.
For MOS transistor in depletion region, the bulk to gate voltage Vbg keeps
between the flat-band voltage Vfb and threshold voltage |Vth| i.e. Vfb < Vbg
< |Vth| where few mobile charge carriers exist at the gate oxide interface.
An inversion region exists with mobile holes for Vbg > |Vth| i.e. the voltage
across bulk and gate terminal Vbg must be greater than the threshold voltage
|Vth|. The control of the bulk terminal in MOS transistor improves the
power dissipation parameter and the standby leakage in CMOS circuits
has been reduced with reverse body biasing [25]. The inversion-mode
MOS varactor (IMOS) has been utilized to reduce the power dissipation
and to improve the phase noise at large offset frequencies from the carrier.
A 3-stage VCO design is reported in this brief using the proposed
delay stage. Variations in the source/drain control voltage (Vcontrol) of IMOS
varactor helps to achieve fine frequency tuning. The proposed VCO offers
wide frequencyrange, lower power dissipation and better phase noise.
Rest of paper is organized as follows: Section 2 reports a new delay cell
with IMOS varactor. A 3-stage VCO design is also reported in this section.
Section 3 presents results and discussion extracted through simulation of
VCO. Finally, Section 4 describes the concluding remarks.

2. System Description
A ring VCO consists of delay stages and each stage presents input to
the subsequent stage in the ring. The frequency of oscillation for a typical
VCO is given by the total number of delay stages and propagation delay
time of the delay cell as given in Eq. (3).
A LOW POWER VCO DESIGN 571

Figure 1
VCO structure of three stage single-ended VCO

1
fo = (3)
2 Nτ d

where N is the total number of delay stages and td is the propagation delay
time specified by each stage. The basic ring structure of the proposed
single-ended VCO uses odd number of delay stages. The proposed
single-ended ring VCO with composite load topology is schematically
depicted in Figure 1. For the proposed ring VCO structure, a modified
basic CMOS inverter along with composite load has been used with IMOS
varactor employed as a frequency tuning component. A delay stage has
been proposed as shown in Figure 2 with modified CMOS inverter along
with composite load and IMOS varactor based on two PMOS transistors
connected in parallel. In this delay stage, tuning has been attained by
changing power supply voltage (Vdd), back-gate voltage (Vsb) and source/
drain voltage (Vct). The transistor M1 along with M2 creates the common
inverter pair and transistor M3 serves as load to regulate the operating
frequency. Transistor M4 along with transistor M2 works as a composite
load which shows inductive impedance at the drain of transistor M2. The
composite load enables the delay cell to generate oscillations at higher
frequencies and attains wider tuning range.
Assuming the gate source capacitance Cgs appears at the input of
transistor M2, the ratio of output to the input voltage of transistor M2 is
given by
1
Vin sCgs gmM 4
M2
= M2
= (4)
Vout 1 1 gmM 4 + sCgs
M2 + M2

sCgs gmM 4
M2
572 M. KUMAR AND V. JANGRA

Figure 2
Proposed delay cell

And, the current to voltage ratio the output of M2 is given by

I out gmM 2 gmM 4
M2
= (5)
Vout gmM 4 + sCgs
M2 M2

Therefore, the general expression of impedance at the output i.e.

drain of transistor M2 is expressed as
Vout 1 Cgs
Zout = M2
= +s M2
(6)
M2
I out gmM 2 gmM 2 gmM 4
M2

The Eq. (6) shows that the impedance is inductive at the drain of M2.
In the proposed delay cell, the gate length of all MOS transistors have
been taken as 0. 18µm. The sizing of transistors used in delay stage is
shown in Table 1.
The most important parameter which characterizes the MOSFET
operation is the threshold voltage (Vth or Vt). For an inversion mode MOS
transistor, the threshold is given by Eq. (7).
A LOW POWER VCO DESIGN 573

Table 1
MOS transistors sizing for VCO design

Transistors Width/Length

M1, M3, M4 0. 5/0. 18

M2 1. 0/0. 18

M5, M6 2/0. 18

Vth = VFB −
(
2ε si qN A 2 φ f + VC − VB ) −2φ + VC −
Qi
(7)
f
Cox Cox

where Qi = (q × implant dose) is the charge due to ionized donors, VFB is the
flatband voltage, q is the electron charge, NA be the doping concentration
of the p-type substrate, esi be the dielectric constant of silicon, Cox be
the gate oxide capacitance per unit area and ff be the substrate Fermi
potential. In this equation, VC (< 0) is negatively biased for PMOS because
the inversion holes must be negatively biased relating to the n-substrate to
form a reverse biased p-n junction. In PMOS based IMOS varactor, mobile
holes form an inversion channel for Vgs < |Vth|, where VGS is the voltage
between gate and substrate and Vth is the threshold voltage. This condition
enables that a MOS transistor is working in strong inversion mode. The
capacitance in this region is given by
ε .W .L
Cox = = Cmax (8)
tox

where W. L is the area of transistor channel, e is the permittivity of silicon

dioxide and tox is the oxide thickness. This area depends upon the width of
the channel of the IMOS transistor. Channel length and width of the MOS
transistor relates with the threshold voltage is given by Eq. (9) [26].
tox tox
Vth = Vth 0 + γ ( )
Vsb + ϕ o − α l
L
(V sb
+ ϕo ) − α v
L
Vds

tox
+α w
W
(V sb
+ ϕo ) (9)

where Vth 0 is the zero bias threshold voltage, tox is the width of oxide, g is
bulk threshold coefficient, jo is 2ff and ff is Fermi potential, and al, av and
aw are the parameters given by process technology.
574 M. KUMAR AND V. JANGRA

Figure 3
Three stage VCO ring oscillator with delay stage

A 3-stage ring VCO structure as shown in Figure 3 has been designed

with proposed delay stage. Use of inversion mode (IMOS) varactor in the
proposed VCO improves the single ended delay with IMOS varactor as
a variable capacitive load. In IMOS varactor, out of two terminals, body

Figure 4
Equivalent capacitance model for IMOS varactor
A LOW POWER VCO DESIGN 575

terminal is coupled to the back-gate voltage (Vsb) and the source/drain

voltage (Vct) terminal acts as capacitance control voltage.
In an IMOS circuit, increasing the source/drain voltage (Vct) brings
more holes in the channel. Hence, capacitance increases withincrease in
source/drain voltage (Vct) and hence the output frequency decreases.
Moreover, increase in back gate voltage (Vsb) increases the depletion width
of source and drain end results in decrease in depletion capacitance.
Therefore, the overall capacitance of IMOS varactor decreases which
reduces the delay time and hence the output frequency increases. The
general equivalent model of IMOS capacitance [11] is shown in Figure 4.
In Figure 4, Cdep is the channel capacitance, Cox is the oxide capacitance
within gate and substrate, Cgs and Cgd are the parasitic capacitance between
gate to source and gate to drain, Cbs and Cbd are bulk to source and bulk to
drain capacitance. Rdep is the parasitic resistance within gate and source/
drain terminals and Rsub is the resistance offered by the substrate. The
variable capacitance within the gate and the substrate in a MOS varactor
is a successive combination of capacitance due to gate oxide Cox and
depletion region capacitance Cdep is given by Eq. (5).
Ceq = (Cox  Cdep ) ≈ Cmin (10)

As source/drain voltage (Vct) increases, the width of the depletion

region at the source end will decrease which increases source to bulk
capacitance Cdep. As a result, the capacitance between the gate nodes
increases. This increase the time delay of a delay cell which is proportional
to the capacitance and hence, decreases the VCO output oscillation
frequency. As the back-gate voltage (Vsb) increases, large numbers of
electrons are attracted towards the substrate terminal. This results in
positive charge near the surface and increase in the depletion width.
So, increase in depletion width decreases the depletion capacitance as a
result capacitance between bulk and source/drain terminal decreases. As
the load capacitance of the delay stage decreases, the propagation delay
decreases and therefore output oscillation frequency increases.

3. Results and Discussions

The proposed three-stage composite load single-ended VCO has
been designed in TSMC 180nm CMOS technology. Results have been
extracted with different power supply voltage (Vdd), source/drain voltage
(Vct) and back-gate voltage (Vsb) of IMOS transistors. Various analysis like
transient analysis, DC analysis and noise analysis have been executed to
576 M. KUMAR AND V. JANGRA

Table 2
Source/drain Voltage (Vct) tuning of 3-stage VCO with different IMOS widths
at Vdd = 1. 8V and Vsb = 1. 8V

Vct Frequency (GHz) Power

(V) Dissipation(mW)
WI = 2µm WI = 5µm WI = 8µm WI = 10µm
1.0 3.253 2.014 1.457 1.252 0.279
1.2 3.181 1.949 1.405 1.231 0.279
1.4 3.061 1.844 1.309 1.185 0.279
1.6 2.935 1.717 1.213 1.098 0.279
1.8 2.783 1.604 1.129 1.018 0.279
2.0 2.686 1.523 1.063 0.942 0.279
2.2 2.657 1.496 1.042 0.884 0.279
2.4 2.648 1.462 0.990 0.862 0.279

get output oscillation frequency, power dissipation and phase noise along
with figure of merit (FoM) of the VCO with variations in IMOS widths
such as 2μm, 5μm, 8μm and 10μm. Table 2 shows the outcomes of the
proposed three-stage VCO with varying IMOS source/drain voltage (Vct)

Figure 5
Output frequency variations for source/drain voltage with different IMOS
widths (WI)
A LOW POWER VCO DESIGN 577

Table 3
Power supply voltage (Vdd) tuning of 3-stage VCO with different IMOS widths
at Vct = 1. 0V and Vsb = 1. 8V

Vdd Frequency (GHz) Power

(V) Dissipation (mW)
WI = 2 µm WI = 5 µm WI = 8 µm WI = 10 µm
1.0 0.972 0.571 0.407 0.337 0.002
1.2 1.585 0.957 0.687 0.575 0.016
1.4 2.166 1.332 0.968 0.811 0.063
1.6 2.698 1.671 1.224 1.023 0.151
1.8 3.181 1.981 1.469 1.215 0.279
2.0 3.552 2.236 1.674 1.387 0.448
2.2 3.891 2.464 1.848 1.532 0.661
2.4 4.231 2.666 2.004 1.655 0.919

from 1V to 2. 4V. As source/drain voltage (Vct) increases, the capacitance

of IMOS increases which decreases the output oscillation frequency. The
results have been extended with varying IMOS widths (WI).

Figure 6
Output frequency variations for power supply voltage with different IMOS
widths (WI)
578 M. KUMAR AND V. JANGRA

Figure 7
Power dissipation variation with power supply voltage

As the IMOS width (WI) increases, the capacitance of IMOS increases

and therefore output frequency decreases as compared to the smaller
width as presented in Table 2. The proposed ring VCO shows the total
power dissipation of 0. 279 mW. Figure 5 shows the variations in output
frequency for source/drain voltage (Vct) with different IMOS widths
(WI). The variations in output oscillation frequency along with power
dissipation of VCO for the power supply voltage (Vdd) tuning from 1V
to 2. 4V withdifferent IMOS varactor widths (WI) is shown in Table 3. As
the power supply voltage (Vdd) increases, the delay cellbiasing current
increases that increases the output oscillation frequency. This VCO shows
the variations in power dissipation from 0. 002mW to 0. 919mW for power
supply (Vdd) tuning with different IMOS widths (WI). Figure 6 shows the
variations in output frequency for power supply voltage (Vdd) tuning with
different IMOS widths.
The proposed VCO depicts the variations in power dissipation
against variations in power supply voltage in Figure 7. Table 4 displays the
variations in output oscillation frequency along with power dissipation of
the proposed three-stage VCO with change in back-gate voltage (Vsb) from
1V to 2. 4V with differentIMOS varactor widths (WI). When the back-gate
voltage (Vsb) of IMOS increases, the current due to biasing increases in
A LOW POWER VCO DESIGN 579

Table 4
Back-gate voltage (Vsb) tuning of 3-stage VCO with different IMOS widths at
Vdd = 1. 8V, Vct = 1V

Frequency (GHz) Power

Vsb
Dissipation
(V) WI = 2 µm WI = 5 µm WI = 8 µm WI = 10 µm (mW)

1.0 3.114 1.887 1.325 1.140 0.279

1.2 3.155 1.928 1.368 1.171 0.279
1.4 3.195 1.965 1.393 1.196 0.279
1.6 3.226 1.992 1.416 1.221 0.279
1.8 3.251 2.043 1.438 1.238 0.279
2.0 3.262 2.103 1.450 1.249 0.279
2.2 3.272 2.146 1.461 1.263 0.279
2.4 3.282 2.154 1.472 1.267 0.279

the delay cell that decreases the propagation delay and consequently the
output oscillation frequency of the VCO circuit increases.
Phase noise is a significant factor to obtain the noise performance
of the ring oscillator. For the reported VCO, outcomes of phase noise
with an offset of 1MHz from the carrier are shown in Table 5. There is a
compromise between the output frequency range and phase noise of the
ring VCO. The output oscillation frequency increases with the increase
in VCO gain and substantially, the phase noise performance degrades.
The phase noise performance decreases with the increase in number of
delay stages for the defined frequency range and power dissipation. The
phase noise performance of the reported VCO is -107. 77dBc/Hz@1MHz.
Results for dissimilar grouping of power supply voltage, back gate voltage
and source/drain voltage have been reported in Table 5. Figure8 (a) & (b)
demonstrates the phase noise results for different combinations of tuning
voltage.
The phase noise has been normalized in terms of figure of merit
(FoM) used for approximation of VCO performance. The figure of merit is
given by Eq. (11) [27].
 f 
2
1 
FOM = 10 log   o   (11)
  ∆f  L{ ∆f } P ( mW ) 
 DISS

 Table 5
580

Phase Noise outcomes of proposed VCO

Power Control Back-gate Width of

Phase noise of Output Power
Supply Voltage Voltage IMOS Figure of Merit
VCO@1MHz Frequency Dissipation
Voltage (Vcontrol)of (Vsb) of (WI) (FoM)
(dBc/Hz) (GHz) (mW)
(Vdd) IMOS IMOS (µm)

2.0V 0V 1.8V 2 -101.55 3.65 0.448 -162.72

1.8V 1.0V 1.0V 2 -107.12 3.10 0.279 -168.29

1.8V 0.5V 1.8V 2 -107.77 3.28 0.279 -168.94

1.8V 1.0V 0.5V 2 -107.40 2.98 0.298 -168.57

1.8V 1.8V 0.5V 2 -106.12 2.71 0.512 -159.62

1.0V 1.0V 1.0V 2 -109.12 2.79 0.294 -170.23

M. KUMAR AND V. JANGRA
A LOW POWER VCO DESIGN 581

(a)

(b)

Figure 8
Phase noise of the proposed VCO at (a) Vdd = 1. 8V, Vct = 1. 0V & Vsb = 1. 0V
(b) Vdd = 1. 8V, Vct = 0. 5V & Vsb = 1. 8V

where f0 is the carrier frequency, Df is the frequency offset, L{Df }is thephase
noise measured at an offset Df from the carrier and PDISS is the DC power
dissipation in mWconsumed by the VCO. In the reported VCO, the FoM
at 1MHz offset frequency varies from -162. 72 dBc/Hz to -170. 23 dBc/Hz
for different tuning conditions.
The results of proposed VCO has been compared with previously
reported VCOs [3, 7, 10, 13, 15, 20, 22] in terms of output frequency range,
control voltage applied, power dissipation, phase noise and FoM. The
compared result of the proposed VCO has been shown in Table 6. The
proposed work offers wide tuning range along with low power dissipation
and good phase noise.
 Table 6
582

Performance Comparison of the Ring VCO with existing VCO designs

Output Tuning Control Power

Process Supply Phase Noise FoM
References Frequency Range Voltage Dissipation
(µm) (V) (dBc/Hz) (dBc/Hz)
(GHz) (%) (V) (mW)

[3] 0.18 1.8 4.9 - 5.9 18.5 0 - 1.8 8.13 -86.7@1MHz -149.7

[7] 0.18 1.8 5.93 - 5.16 12.9 0.8 - 1.8 80.1 -99.5@1MHz -155.7

[10] 0.18 1.8 6.2 - 7.0 12.0 1.3 - 0.3 72.4 -107.7@1MHz -145.1

[13] 0.18 2.0 4.3 - 6.2 34.6 0.2 - 1.1 81.1 -85@1MHz -140

[15] 0.18 1.8 3.0 - 5.3 43.3 0 - 1.8 100 -107.7@1MHz -161.3

[20] 0.18 1.8 1.77 - 1.92 8.2 0 - 1.8 13.1 -102.2@1MHz -156.3

[22] 0.18 1.8 4.2 - 5.8 13.0 -1.0 - 1.0 58 -99.2@1MHz -156.2

Proposed
0.18 1.8 2.64 - 3.25 21 1.0 - 2.4 0.27 -107.7@1MHz -168.94
VCO
M. KUMAR AND V. JANGRA
A LOW POWER VCO DESIGN 583

4. Conclusion
The three-stage CMOS single-ended ring VCO has been designed
using TSMC 0. 18µm CMOS technology. The ring VCO uses a modified
CMOS inverter along with composite load and IMOS varactor based on
two PMOS transistors connected in parallel. This composite load enables
the delay cell to oscillate at superior frequencies and attains wider tuning
range. Transistor M4 along with transistor M2 serves as composite
load unveiling inductive impedance at the output of transistor M2. The
oscillation frequency range of the proposed ring VCO is 2. 648 GHz to 3.
253 GHz and a very less power dissipation of 0. 279mW with variations
in control voltage from 1. 0V to 2. 4V with IMOS varactor width of 2µm.
Moreover, the proposed VCO achieves output oscillation frequency range
from 0. 972 GHz to 4. 231 GHz and less power dissipation from 0. 002 mW
to 0. 919 mW with a variation of power supply voltage from 1. 0V to 2. 4V.
The proposed ring VCO shows a phase noise of-107. 74 dBc/Hz at 1 MHz
offset and figure-of-merit (FoM) is -168. 94dBc/Hz. Hence, the obtained
performance of the proposed VCO has been found better in terms of wider
tuning range, lower power dissipation, lower phase noise and better FoM.

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