VTU 3rd SEM

DDCO | BCS302

Model Question Paper-1

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• The binary signal at the inputs and outputs of any gate has
one of two values, except during transition.
• One signal value represents logic 1 and the other logic 0.

• Choosing the high‐level H to represent logic 1 defines a

positive logic system.
• Choosing the low‐level L to represent logic 1 defines a
negative logic system.

The conversion from positive logic to negative logic and vice versa is essentially an operation
that changes 1’s to 0’s and 0’s to 1’s in both the inputs and the output of a gate. Since this
operation produces the dual of a function, the change of all terminals from one polarity to the
other results in taking the dual of the function. The upshot is that all AND operations are
converted to OR operations (or graphic symbols) and vice versa
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CD
AB 00 01 11 10

00
Blue: (A + D’) X 0 0
Green: (A + C’) 0 1 3 2
Orange : (C’ + D)
01 0
Brown : (B’ + C + D`) X X
Purple : (A` + B + D) 4 5 7 6

F= (A + D’) (A + C’) (C’ + D) (B’ + C + D’) (A’ + B + D) 11 0 0

12 13 15 14

10 0 8
X 0
9 11 10
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yz
wx 00 01 11 10

00 1
1 1
0 1 3 2

01
1 1 1
4 5 7 6

11 1 1
12 13 15 14

10 1
8 9 11 10
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Binary logic is a system that uses only two digits, 1 and 0, to represent the operation of binary logic gates.
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yz
x 00 01 11 10

0 1 X X
1
0 1 3 2

1
1 1 X 1
4 5 7 6

F=1
 Click here for Explanation
yz
wx 00 01 11 10

00
0 1 3 2

01
1 1 1
4 5 7 6

11 1 X 1 1
12 13 15 14

10 X X
8 9 11 10
• A hardware description language (HDL) is a computer-based language that describes the hardware
of digital systems in a textual form. Click here for Explanation
• It resembles an ordinary computer programming language, such as C, but is specifically oriented to
describing hardware structures and the behavior of logic circuits.
• It can be used to represent logic diagrams, truth tables, Boolean expressions, and complex
abstractions of the behavior of a digital system.
• One way to view an HDL is to observe that it describes a relationship between signals that are the
inputs to a circuit and the signals that are the outputs of the circuit.
• For example, an HDL description of an AND gate describes how the logic value of the gate’s output
is determined by the logic values of its inputs.
• HDLs are used in several major steps in the design flow of an integrated circuit: design entry,
functional simulation or verification, logic synthesis, timing verification, and fault simulation.
 Click here for Explanation
Combinational circuits:
Demultiplexer, Decoder, Full adder
encoder, Half adder, Magnitude
comparator

Sequential Circuits:
Registers, Flip Flops, Counters
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A B C D F
D
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1 D’
4 0 1 0 0 1
5 0 1 0 1
0
0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
1
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
A B C
15 1 1 1 1 1
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module full_adder(input a, b, cin, output S, Cout);

assign S = a ^ b ^ cin;
assign Cout = (a & b) | (b & cin) | (a & cin);
endmodule
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module full_subtractor(input a, b, Bin, output D, Bout);

assign D = a ^ b ^ Bin;
assign Bout = (~a & b) | (~(a ^ b) & Bin);
endmodule
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Here are the characteristic equations

• SR flip flop: Qn+1 = S + QnR'
• D flip flop: Qn+1 = D
• JK flip flop: Qn+1 = Q'nJ + QnK'
• T flip flop: Qn+1 = Q'nT+ QnT'
• Addressing modes are an aspect of the instruction set architecture in most central processing unit
designs.
• The various addressing modes that are defined in a given instruction set architecture define how
the machine language instructions in that architecture identify the operand of each instruction

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Memory Address Register (MAR) is a register in the CPU that stores the memory address from which data is
fetched to the CPU registers. It can also store the address to which data is sent and stored via system bus.

Program Counter (PC) is a register that manages the memory address of the instruction to be executed next.

Instruction Register (IR) is a part of a CPU's control unit that holds the instruction that is being executed or
decoded.

Memory Data Register (MDR) is a register in a computer's CPU that stores data being transferred to and from
immediate access storage. It's also known as the Memory Buffer Register (MBR)

Arithmetic Logic Unit (ALU) performs basic arithmetic and logical operations.
 Click here for Explanation
• The performance of a program depends on the algorithm,
the language, the compiler, the architecture, and the actual
hardware.
• Clock cycle Also called tick, clock tick, clock period, clock, or
cycle.
• The time for one clock period, usually of the processor
clock, which runs at a constant rate.
• Clock period - The length of each clock cycle.

SPEC- System Performance Evaluation Corporation, Its a non profit organization selects and publishes bench marks.
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• Registers R1 and R2 of a computer contain the decimal values 1200 and 4600, we have to find effective address of
associated memory operand in each instruction:
• Load 20(R1),R5 : This means load 20+R1 into R5 .
R1= 1200 , R1 + 20 = 1220 , so R5 have 1220 , Effective address of R5 is 1220.
• Move #3000,R5 : This means move value 3000 into R5
so effective address is part of the instruction whose value is 3000. Now R5 = 3000
• Store R5,30(R1,R2) : This means 30+R1+R2 and store the result into R5 .
so R5 = 30+1200+4600 = 5830 , so now R5 value is 5830 , the effective address is 5830.
• Add -(R2),R5 : This means -1 from R2 value and store the result into R5 . So R5= 4600 - 1 = 4599 , effective
address of R5 is 4599 . It is pre decrement addressing.
• Subtract (R1)+,R5 : This means effective address is contents of R1 so EA = 1200 .
It is post increment addressing .
Effective addresses are:
• 1220
• 3000 [ it is not the effective address , it is the address of the instruction part where 3000 is stored ]
• 5830 Click here for Explanation
• 4599
• 1200
 Click here for Explanation

• A single bus structure is a computer architecture that uses a common bus to communicate between the
processor, memory, and I/O devices.
• one common bus is used to communicate between peripherals and microprocessors
• Only one transfer at a time: The bus can only be used for one transfer at a time, so only two units can actively
use the bus at any given time.
• A single bus structure is primarily found in mini and microcomputers.

• One significant advantage of using a one bus data path is its simplicity.
• Single bus structure has disadvantages of limited speed since usually only two units can participate in a data
transfer at any one time. This means that an arbitration system is required and that units will be forced to wait.
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Daisy chaining is a method of interrupt handling that involves connecting devices that can request an interrupt
in a serial manner. The devices are connected in a serial form, with the device with the highest priority placed
first, followed by lower-priority devices. Click here for Explanation
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