DIGITAL SYSTEMS III

Chapter 4
AVR Interrupts

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CONTENTS

1. AVR Interrupts Concept

2. AVR Interrupts Sources
3. AVR Interrupts Execution Steps
4. AVR Interrupts Response Time
5. AVR Interrupts Vector Table
6 AVR Interrupts Registers

The contents of this presentation is confidential. ©VUT

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AVR Interrupts Concepts

▪ AVR devices provide several different interrupt sources including internal and external interrupts.
▪ Interrupts can stop the main program from executing to perform a separate interrupt service routine (ISR).
▪ When the ISR is completed, program control is returned to the main program at the instruction that was interrupted.
▪ With AVR Micro-controllers, you can configure interrupts on various sources such as:

Port Pins: INT0, INT1 and INT2 ADC

Timers EEPROM
UART Analog Comparator
SPI TWI or I2C

▪ All interrupts are assigned individual enable bits which must be written in one logic together with the Global Interrupt Enable bit in the
Status Register to enable the interrupt.
▪ The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
▪ They have determined priority levels, the lower the address the higher the priority level. RESET has the highest priority, and next is the
External Interrupt Request 0 (INT0).

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AVR Interrupts - Interrupt Sources

▪ External Interrupts
▪ External interrupts are triggered by the INT pin or any of the PCINT pins.
▪ If enabled, the interrupts trigger even if the INT or PCINT pins are configured as outputs.
▪ This feature provides a way of generating a software interrupt.
▪ The external interrupts can be triggered by a falling or rising edge or a low level.
▪ This is set up by the External Interrupt Control Register A EICRA.
▪ When the external interrupts are enabled and are configured as level-triggered, the interrupts trigger if the pin is held low.

▪ Timer Interrupts
▪ Status flags in the TIMSK register show if an event has occurred or the timer is at overflow state.
▪ A timer overflow means that the counter has counted to its maximum value and is reset to zero in the next timer clock cycle.
▪ The resolution of the timer determines the maximum value of that timer. There are two timers with 8-bit resolution and third timer with 16-bit
resolution on the ATmega32.
▪ Depending on the Timer selected, TIMISK register can be used to enable the interrupt for the selected Timer while TIFR can be used to monitor
the status of all Timer enabled interrupts.
▪ For Timer interrupts to function, I-Global bit of SREG must be configured to high state.

▪ SPI
▪ The SPI interrupt gets triggered when the serial transfer is complete, the SPIF Flag in the SPSR register is set.
▪ An interrupt is generated if SPIE bit in SPCR is set, and global interrupts are enabled. 4
▪ SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
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AVR Interrupts - Interrupt Sources

▪ USART
▪ USART interrupts can be used to transmit and receive data. This increases the efficiency of the code and keeps the processor free for other tasks.
▪ The UCSRB register has RXCIE (Reception Complete Interrupt Enable) bit, which is used to enable the serial reception interrupt.
▪ The I-bit of SREG register must be set to enable global interrupt of ATmega32.
▪ Every time one byte of the data is received serially, a serial receive interrupt is generated and the control transfers to the corresponding ISR.
▪ The RXC flag will go high to indicate the serial receive interrupt.

▪ WDT
▪ In Interrupt mode, the WDT forces an interrupt when the timer expires.
▪ This interrupt can be used to wake the device from any of the sleep-modes, and as a general system timer.
▪ One example is to limit the maximum time allowed for certain operations, forcing an interrupt when the operation has run longer than expected.
▪ This is enabled by setting the Interrupt mode bit (WDIE) in the Watchdog Timer Control Register (WDTCSR).
▪ Interrupt and System Reset mode combines the other two modes by first forcing an interrupt and then switching to the System Reset mode.
▪ This mode will offer a safe shutdown by allowing time to save critical parameters before a system reset. This is enabled when both the WDTIE
and WDTE are set.
▪ The Watchdog System Reset Flag (WDRF) bit in the MCU Status Register (MCUSR) is set if a Watchdog System Reset occurs.
▪ The WDRF bit is cleared by a Power-on Reset or by writing '0' to it. To identify a reset condition, the user should read and then reset the WDRF
as early as possible in the program.
▪ If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.
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AVR Interrupts - Interrupt Sources

▪ ADC
▪ in-built ADC of AVR consists of ADIE (ADC interrupt Enable) bit in ADCSRA register.
▪ In addition, the I-bit of SREG is also activated to activate interrupts
▪ ADC system consists of ADIE bit in ADCSRA register.
▪ ADIE bit is enabled to use ADC interrupts
▪ In A/D conversion ADSC bit remains high till the conversion is not completed. As soon as the conversion gets completed, ADSC automatically
gets cleared by hardware.
▪ Before starting the next conversion, ADSC must be set high again. Alternatively, auto triggering can be used to enable the ADSC bit after each
conversion.
▪ The ADATE (ADC Auto Triggering Enable) bit in ADCSRA register is used to activate auto-triggering mode.

▪ Analog Comparators
▪ The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function.
▪ In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on
comparator output rise, fall or toggle.
▪ Analog Comparator interrupt can be enabled by ACIE bit in the Analog Comparator and Status Register (ACSR) and configuring I-Global bit of
SREG bit to high.
▪ Once the Interrupt has triggered, the ACI bit in the ACSR register will be set and this bit can be cleared by software.

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AVR Interrupts - Interrupt Sources

▪ TWI/I2C
▪ I2C (Inter-Integrated Circuit) is a serial bus interface connection protocol. It is also called TWI (two-wire
interface) since it uses only two wires for communication, that two wires called SDA (serial data) and SCL
(serial clock).
▪ This bit gets set whenever TWI completes its current event (like start, stop, transmit, receive, etc).
▪ While I-bit in SREG and TWIE bit in TWCR is enabled then TWI interrupt vector called whenever TWI
interrupt occurs.
▪ TWI interrupt flag must be cleared by software by writing a logical one to it. This bit is not automatically cleared
by hardware.

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AVR Interrupts - How do we handle Interrupts

▪ The method of handling interrupts differs in different languages. For an Interrupt to fire ISR three
conditions must be true. When all three conditions are met, the AVR will fire our ISR each time the
interrupt event occurs.
1. The AVR’s global Interrupts Enable bit must be set to one in the microcontroller control register SREG.
▪ This allows the AVR’s core to process interrupts via ISRs when set and prevents them from running when
set to zero.
▪ It is like a global ON/OFF switch for the interrupts. By default, this bit is zero.
2. The individual interrupt source’s enable bit must be set.
▪ Each interrupt source has a separate interrupt enable bit in the related peripherals control registers, which
turns on the ISR for that interrupt.
▪ This must also be set, so that when the interrupt event occurs the processor runs the associated
ISR.
3. The condition of the interrupt must be meet
▪ for example, when the ADC conversion is complete then only it will fire ADC conversion interrupt.

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AVR Interrupts - Interrupt Execution Steps Sources

1. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
2. The interrupt vector directs program control to the proper ISR or execution.
▪ That ISR can write logic one to the I-bit to enable nested interrupts.
3. All enabled interrupts can then interrupt the current interrupt routine.
4. When the ISR is completed and the return (RETI) command is executed from the ISR, the Global I-bit
is automatically set to 'ON' and the program execution returns to the main program at the instruction
that was interrupted.

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AVR Interrupts - Interrupt Response Time

▪ The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
▪ After four clock cycles, the program vector address for the actual interrupt handling routine is executed.
▪ During this four-clock cycle period, the Program Counter is pushed onto the stack.
▪ The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
▪ If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt
is served.
▪ If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four
clock cycles.
▪ This increase comes in addition to the start-up time from the selected sleep mode.
▪ A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program
Counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is
set.

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AVR Interrupts - Interrupt Vector Table

▪ These interrupts each have a separate program vector in the program memory space.
▪ The vector name is the identifier that should be used at the start of the interrupt service routine (ISR).
▪ The names of the vectors are not always the same for the same interrupt in different processors

▪ In the ATmega32 processor, an Interrupt Vector is the address used to access the ISR when an enabled interrupt is triggered.
▪ A instruction that causes the processor to jump to the actual ISR code used to handle the interrupt must be placed at the vector address.
▪ Vectors with lower numbers have higher priority. In ATmega32 processors, priority determines which of several simultaneously
occurring interrupts will be handled and executed first.
▪ The section of memory (addresses 0x0000 to 0x0032) that holds the vectors (ISR jump instructions) can be referred to as a “vector
table”
▪ The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
MCUCR.
▪ The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse.

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AVR Interrupts
- Interrupt
Vector Table

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AVR Interrupts - Interrupt Registers

▪ Status Register (SREG)

▪ Bit 7 – I: Global Interrupt Enable
▪ The Global Interrupt Enable bit must be set for the interrupts to be enabled.
▪ The individual interrupt enable control is then performed in separate control registers.
▪ If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the
individual interrupt enable settings.
▪ The I-bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable
subsequent interrupts.
▪ The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in
the instruction set reference.

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AVR Interrupts - Interrupt Registers

▪ General Interrupt Control Register (GICR)

▪ The General Interrupt Control Register controls the placement of the Interrupt Vector table.
▪ Bit 7 – INT1 - External Interrupt Request 1 Enable
▪ When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled.
▪ The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU General Control Register (MCUCR) define
whether the External Interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.
▪ Activity on the pin will cause an interrupt request even if INT1 is configured as an output.
▪ The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt Vector.
▪ Bit 6 – INT0: External Interrupt Request 0 Enable
▪ When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled.
▪ The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU General Control Register (MCUCR) define
whether the External Interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.
▪ Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
▪ The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector.

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AVR Interrupts - Interrupt Registers

▪ General Interrupt Control Register (GICR)

▪ The General Interrupt Control Register controls the placement of the Interrupt Vector table.
▪ Bit 5 – INT2: External Interrupt Request 2 Enable
▪ When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
▪ The Interrupt Sense Control2 bit (ISC2) in the MCU Control and Status Register (MCUCSR) defines whether the External Interrupt is activated
on rising or falling edge of the INT2 pin.
▪ Activity on the pin will cause an interrupt request even if INT2 is configured as an output.
▪ The corresponding interrupt of External Interrupt Request 2 is executed from the INT2 Interrupt Vector.
▪ Bit 1 – IVSEL - Interrupt Vector Select
▪ When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
▪ When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the Flash.
▪ The actual address of the start of the Boot Flash section is determined by the BOOTSZ fuses
▪ Bit 0 – IVCE - Interrupt Vector Change Enable
▪ The IVCE bit must be written to logic one to enable change of the IVSEL bit.
▪ IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.
▪ Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above.

7 6 5 4 3 2 1 0
INT1 INT0 INT2 - - - IVSEL IVCE
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AVR Interrupts - Interrupt Registers

▪ MCU Control Register (MCUCR)

▪ To define a level trigger or edge trigger on external INT0 and INT1 pins MCUCR register is used.
▪ Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
▪ The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR
are set.
▪ The level and edges on the external INT1 pin that activate the interrupt are defined in Table 34.
▪ The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt.
▪ Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the
completion of the currently executing instruction to generate an interrupt.

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AVR Interrupts - Interrupt Registers

▪ MCU Control Register (MCUCR)

▪ To define a level trigger or edge trigger on external INT0 and INT1 pins MCUCR register is used.
▪ Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
▪ The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.
▪ The level and edges on the external INT0 pin that activate the interrupt are defined in Table 35.
▪ The value on the INT0 pin is sampled before detecting edges.
▪ If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
▪ Shorter pulses are not guaranteed to generate an interrupt.
▪ If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate
an interrupt.

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AVR Interrupts - Interrupt Registers

▪ MCU Control and Status Register (MCUCSR)

▪ Bit 6 –Interrupt Sense Control 2 (ISC2)
▪ The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding
interrupt mask in GICR are set.
▪ If ISC2 is written to zero, a falling edge on INT2 activates the interrupt.
▪ If ISC2 is written to one, a rising edge on INT2 activates the interrupt. Edges on INT2 are registered asynchronously.
▪ Pulses on INT2 wider than the minimum pulse width given in Table 36 will generate an interrupt.
▪ Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an interrupt can occur.
▪ Therefore, it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register.
▪ Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical one to its
Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.

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AVR Interrupts - Interrupt Registers

▪ General Interrupt Flag Register (GIFR)

▪ Bit 7 – INTF1: External Interrupt Flag 1

▪ When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).
▪ If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
▪ The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
▪ This flag is always cleared when INT1 is configured as a level interrupt.
▪ Bit 6 – INTF0: External Interrupt Flag 0
▪ When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes see (one).
▪ If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding interrupt vector.
▪ The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
▪ This flag is always cleared when INT0 is configured as a level interrupt.
▪ Bit 5 – INTF2: External Interrupt Flag 2
▪ When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).
▪ If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
▪ The flag is cleared when the interrupt routine is executed.
▪ Alternatively, the flag can be cleared by writing a logical one to it.
▪ Note that when entering some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will be disabled.
▪ This may cause a logic change in internal signals which will set the INTF2 Flag
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AVR Interrupts - Interrupt Registers

▪ Timer/Counter Interrupt Mask Register (TIMISK)

▪ Bit 7 – Timer/Counter2 Output Compare Match Interrupt Enable (OCIE2)
▪ When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match
interrupt is enabled.
▪ The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, that is, when the OCF2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
▪ Bit 6 – Timer/Counter2 Overflow Interrupt Enable (TOIE2)
▪ When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is
enabled.
▪ The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR
▪ Bit 5 – Timer/Counter1, Input Capture Interrupt Enable (TICIE1)
▪ When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter(n)
Input Capture Interrupt is enabled.
▪ Bit 4 – Timer/Counter1, Output Compare A Match Interrupt Enable (OCIE1A)
▪ When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1
Output Compare A match interrupt is enabled.
▪ The corresponding Interrupt Vector is executed when the OCF1A Flag, located in TIFR, is set.
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AVR Interrupts - Interrupt Registers

▪ Timer/Counter Interrupt Mask Register (TIMISK)

▪ Bit 3 – Timer/Counter1, Output Compare B Match Interrupt Enable (OCIE1B)
▪ When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1
Output Compare B match interrupt is enabled.
▪ The corresponding Interrupt Vector is executed when the OCF1B Flag, located in TIFR, is set.
▪ Bit 2 – Timer/Counter1, Overflow Interrupt Enable (TOIE1)
▪ When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1
Overflow Interrupt is enabled.
▪ The corresponding Interrupt Vector is executed when the TOV1 Flag, located in TIFR, is set.
▪ Bit 1 – Timer/Counter0 Output Compare Match Interrupt Enable (OCIE0)
▪ When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match
interrupt is enabled.
▪ The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, that is, when the OCF0 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
▪ Bit 0 – Timer/Counter0 Overflow Interrupt Enable (TOIE0)
▪ When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt
is enabled.
▪ The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the
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Timer/Counter Interrupt Flag Register – TIFR.
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AVR Interrupts - Interrupt Registers

▪ Timer/Counter Interrupt Flag Register (TIFR)

▪ Bit 7 – Output Compare Flag 2 The OCF2 (OCF2)
▪ bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2.
▪ OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.
▪ Alternatively, OCF2 is cleared by writing a logic one to the flag.
▪ Bit 6 – Timer/Counter2 Overflow Flag (TOV2)
▪ The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2.
▪ TOV2 is cleared by hardware when executing the corresponding interrupt handling vector.
▪ Alternatively, TOV2 is cleared by writing a logic one to the flag.
▪ In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
▪ Bit 5 – Timer/Counter1, Input Capture Flag (ICF1)
▪ This flag is set when a capture event occurs on the ICP1 pin.
▪ When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP
value.
▪ ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed.
▪ Alternatively, ICF1 can be cleared by writing a logic one to its bit location.
▪ Bit 4 – Timer/Counter1, Output Compare A Match Flag (OCF1A)
▪ This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A).
▪ Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
▪ OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. 22
▪ Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
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AVR Interrupts - Interrupt Registers

▪ Timer/Counter Interrupt Flag Register (TIFR)

▪ Bit 3 – Timer/Counter1, Output Compare B Match Flag (OCF1B)
▪ This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B).
▪ Note that a forced output compare (FOC1B) strobe will not set the OCF1B Flag.
▪ OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
▪ Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
▪ Bit 2 – Timer/Counter1, Overflow Flag (TOV1)
▪ The setting of this flag is dependent of the WGM13:0 bits setting.
▪ In normal and CTC modes, the TOV1 Flag is set when the timer overflows.
▪ TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed.
▪ Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
▪ Bit 1 –Output Compare Flag (OCF0)
▪ The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 – Output Compare Register0.
▪ OCF0 is cleared by hardware when executing the corresponding interrupt handling vector.
▪ Alternatively, OCF0 is cleared by writing a logic one to the flag.
▪ Bit 0 – Timer/Counter0 Overflow Flag (TOV0)
▪ The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0.
▪ TOV0 is cleared by hardware when executing the corresponding interrupt handling vector.
▪ Alternatively, TOV0 is cleared by writing a logic one to the flag.
▪ When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
▪ In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00 23
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AVR Interrupts - Interrupt Registers

▪ SPI Control Register (SPCR)

▪ Bit 7 – SPIE: SPI Interrupt Enable

▪ This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit
in SREG is set.
▪ SPI Status Register (SPSR)
▪ Bit 7 – SPIF: SPI Interrupt Flag
▪ When a serial transfer is complete, the SPIF Flag is set.
▪ An interrupt is generated if SPIE bit in SPCR is set and global interrupts are enabled.
▪ If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
▪ SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
▪ Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data
Register (SPDR).

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