PSIT, Kanpur

Computer Organization and Architecture (BCS302)

Unit - 3 (Part – II)
 Design of Basic Computer
 Program Control
 Hardwired and Microprogrammed Control
 Reduced Instruction Set Computer

Design of Basic Computer

As discussed in complete computer description, the basic computer consists of the following hardware components:
1. A memory unit with 4096 words of 16 bits each.
2. Nine registers:AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC.
3. Seven flip-flops: I, S, E, R, IEN, FGI, and FGO.
4. Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder.
5. A 16-bit common bus.
6. Control logic gates.
7. Adder and logic circuit connected to the input of AC.

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Program Control
 Program control instructions specify conditions for altering the content of the program counter PC.
 The change in value of the PC causes a break in the sequence of instruction execution to provide control over the flow of
program execution and capability for branching to different program segments.
Some typical program control instructions are listed in the following table (*MM Table 8-10).
TABLE 8-10: Typical Program Control Instructions

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANDing) TST

 Branch and jump instructions may be conditional or unconditional.

o An unconditional branch instruction causes a branch to the specified address without any conditions.
o The conditional branch instruction specifies a condition such as branch if positive or branch if zero.
 If the condition is met, the PC is loaded with the branch address and the next instruction is taken from this
address.
 If the condition is not met, the PC is not changed and the next instruction is taken from the next location in
sequence.
 The skip instruction does not need an address field and is therefore a zero-address instruction.
 The call and return instructions are used in conjunction with subroutines.
Status Bit Conditions
 Status bits supplement the ALU circuit with a status register where status bit conditions can be stored for further analysis.
 Status bits are also called condition-code bits or flag bits. Following figure (*MM Fig. 8-8) shows the block diagram of an
8-bit ALU with a 4-bit status register symbolized by C. S, Z, and V.

Figure 8-8 Status register bits

i) Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.

ii) Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if the bit is 0.
iii) Bit Z (zero) is set to 1 if the output of the ALU contains all 0's. It is cleared to 0, otherwise.
In other words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
iv) Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1, and cleared to 0 otherwise.
This is the condition for an overflow when negative numbers are in 2's complement (see *MM Sec. 3-3).

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Conditional Branch Instructions

Following table (*MM Table 8-11) gives a list of the most common branch instructions. Each mnemonic is constructed with the
letter B (for branch) and an abbreviation of the condition name. When the opposite condition state is used, the letter N (for no)
is inserted to define the 0 state.

NOTE: The conditional instructions can be associated also with the jump, skip, call, or return type of program control instructions.
Numerical Example
Consider an 8-bit ALU as shown in the above figure (*MM Fig. 8-8).
Let A = 11110000 and B = 00010100. To perform A - B, the ALU takes the 2's complement of B and adds it to A.

A: 11110000
B + 1: + 11101100
A - B: 111011100 C=1 S=1 V=0 Z=0

If we assume unsigned numbers, the decimal equivalent of A is 240 and that of B is 20.
The subtraction in decimal is 240 - 20 = 220 i.e. binary result 11011100.
Since 240 > 20, we have that A > B and A ≠ B. The instructions that will cause a branch after this comparison are BHI (branch if
higher), BHE (branch if higher or equal), and BNE (branch if not equal).

If we assume signed numbers, the above subtraction in decimal is (-16) - (+20) = -36.
Since (-16) < (+20) we have that A < B and A ≠ B.
These two relations can also be derived from the fact that status bits S = 1 (negative), V = 0 (no overflow), and Z = 0 (not zero).
The instructions that will cause a branch after this comparison are BLT (branch if less than), BLE (branch if less or equal), and
BNE (branch if not equal).

Subroutine Call and Return

A subroutine is a self-contained sequence of instructions that performs a given computational task when called in the main
program.
A subroutine call is implemented with the following microoperations:
SP ← SP - 1 Decrement stack pointer
M [SP] ← PC Push content of PC onto the stack
PC ← effective address Transfer control to the subroutine
The instruction that returns from the last subroutine is implemented by the microoperations:
PC ← M [SP] Pop stack and transfer to PC
SP ← SP + 1 Increment stack pointer
NOTE: A recursive subroutine is a subroutine that calls itself.

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Control Unit Organization (Types)
There are two major types of control organization: hardwired control and microprogrammed control.

1. Hardwired Control Unit

 In the hardwired organization, the control logic is implemented with gates, flip-flops, decoders, and other digital circuits. It
has the advantage that it can be optimized to produce a fast mode of operation.

 A hardwired control, as the name implies, requires changes in the wiring among the various components if the design has
to be modified or changed.

 The block diagram of the control unit is shown in the above figure. It consists of two decoders, a sequence counter, and a
number of control logic gates.
 An instruction read from memory is placed in the instruction register (IR) which is divided into three parts: the I bit, the
operation code, and bits 0 through 11.
 The 4-bit sequence counter can count in binary from 0 through 15. The outputs of the counter are decoded into 16 timing
signals T0 through T15 using the 4 x 16 decoder.
 Once in awhile, the counter is cleared to 0, causing the next active timing signal to be T0.
As an example, consider the case where SC is incremented to provide timing signals T0, T1 T2, T3, and T4 in sequence.
At time T4, SC is cleared to 0 if decoder output D3 is active.
This is expressed symbolically by the statement D3 T4: SC ← 0

2. Microprogrammed Control Unit

 A control unit whose binary control variables are stored in memory is called a microprogrammed control unit.
 Each word in control memory contains within it a microinstruction that specifies one or more microoperations for the
system.
 A sequence of microinstructions constitutes a microprogram.
 In the microprogrammed control, any required changes or modifications can be done by updating the microprogram in
control memory.
 There are two separate memories: a main memory and a control memory.
o In the main memory, the user can store programs which may be altered when the data are manipulated and the
program is changed.
o In contrast, the control memory holds a fixed microprogram that cannot be altered by the occasional user.

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Address Sequencing
The next address generator is sometimes called a microprogram sequencer, as it determines the address sequence that is read
from control memory. The address of the next microinstruction can be specified according to the sequencer inputs.
Typical functions of a microprogram sequencer are:
 Incrementing of the control address register
 Unconditional or conditional branch, depending on status bit conditions
 A mapping process from the bits of the instruction to an address for control memory
 A facility for subroutine call and return

Mapping of Instruction
A mapping from instruction code to microinstruction address is needed to map opcode (4-bits) with address of control memory (7-
bits).
Figure 7-3 Mapping from instruction code to microinstruction address

One simple mapping process that converts the 4-bit opcode to a 7-bit address for control memory is shown in above figure
(*MM Fig. 7-3).
This mapping consists of placing a 0 in the MSB of the address, transferring the four opcode bits, and clearing the two least
significant bits of the control address register.

Microinstruction Format
The computer instruction format is depicted in the following figure (*MM Figure 7-5). It consists of three fields as shown below.

The microinstruction format for the control memory is shown in the following figure (*MM Fig. 7-6).
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The 20 bits of the microinstruction are divided into four functional parts:

1. The three fields F1, F2, and F3 specify microoperations for the computer.
2. The CD field selects status bit conditions.
3. The BR field specifies the type of branch to be used.
4. The AD field contains a branch address. The address field is seven bits wide, since the control memory has 128 = 27
words.

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Figure 7-7 Decoding of microoperation fields

Figure 7-8 Microprogram Sequencer for a Control Memory

Hardwired Vs Microprogrammed Control

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Complex Instruction Set Computer (CISC)
As digital hardware became cheaper with the advent of integrated circuits, computer instructions tended to increase both
in number and complexity. A computer with a large number of instructions is classified as a complex instruction set computer,
abbreviated CISC.

CISC Characteristics
 A large number of instructions-typically from 100 to 250 instructions
 A large variety of addressing modes- typically from 5 to 20 different modes
 Variable-length instruction formats
 Instructions that manipulate operands in memory

Reduced Instruction Set Computer (RISC)

In the early 1980s, a number of computer designers recommended that computers use fewer instructions with simple constructs
so they can be executed much faster within the CPU without having to use memory as often. This type of computer is classified
as a reduced instruction set computer or RISC.

RISC Characteristics
 Relatively few instructions
 Relatively few addressing modes
 Memory access limited to load and store instructions
 All operations done within the registers of the CPU
 Fixed-length, easily decoded instruction format
 Single-cycle instruction execution
 Hardwired rather than microprogrammed control
 Efficient instruction pipeline
CISC Vs RISC Architecture

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