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ETM10

Revision: r0p0

Technical Reference Manual

Copyright © 2001, 2003 ARM Limited. All rights reserved.

ARM DDI 0206B
ETM10
Technical Reference Manual

Copyright © 2001, 2003 ARM Limited. All rights reserved.

Release Information

Change history

Date Issue Change

25 July 2001 A ETM10 (Rev 0) release.

28 Nov 2003 B Second release r0p0. Updated to include errata fixes.

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.

The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

ii Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Contents
ETM10 Technical Reference Manual

Preface
About this manual .......................................................................................... x
Feedback ...................................................................................................... xv

Chapter 1 Introduction
1.1 About the ETM10 ........................................................................................ 1-2
1.2 Supported standard configurations ............................................................. 1-3

Chapter 2 Accessing the ETM10 Registers

2.1 The JTAG interface ..................................................................................... 2-2
2.2 ETM10 registers .......................................................................................... 2-3

Chapter 3 Integrating the ETM10

3.1 About integrating the ETM10 ...................................................................... 3-2
3.2 ARM1020E trace interface .......................................................................... 3-4
3.3 System control signals ................................................................................ 3-8
3.4 Clocks and resets ..................................................................................... 3-12
3.5 TAP interface wiring .................................................................................. 3-14
3.6 Trace port interfacing ................................................................................ 3-17
3.7 Modes of operation of the trace port ......................................................... 3-21

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. iii
Contents

Chapter 4 Design for Test

4.1 About DFT .................................................................................................. 4-2
4.2 Scan chain configurations .......................................................................... 4-4
4.3 ETM10 test wrapper ................................................................................... 4-6
4.4 Test modes and ports ............................................................................... 4-10
4.5 Clocks and gating ..................................................................................... 4-15

Chapter 5 Implementation-defined Behavior

5.1 ETM architecture version ............................................................................ 5-2
5.2 Precise TraceEnable events ....................................................................... 5-3
5.3 Parallel instruction execution ...................................................................... 5-4
5.4 Independent load/store unit ........................................................................ 5-5
5.5 The FIFOFULL level register ...................................................................... 5-7
5.6 Context ID tracing ....................................................................................... 5-8

Chapter 6 Tracing Dynamically-loaded Images

6.1 About tracing dynamically-loaded code ...................................................... 6-2
6.2 Software support for context ID .................................................................. 6-3
6.3 Hardware support for context ID ................................................................. 6-4

Chapter 7 Physical Trace Port Signal Guidelines

7.1 About trace port signal quality .................................................................... 7-2
7.2 ASIC pad selection, placement, and package type .................................... 7-3
7.3 PCB design guidelines ............................................................................... 7-4
7.4 EMI compliance .......................................................................................... 7-8
7.5 Further references ...................................................................................... 7-9

Appendix A Signal Descriptions

A.1 Functional signals ....................................................................................... A-2
A.2 DFT signals ................................................................................................ A-5

Glossary

iv Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
List of Tables
ETM10 Technical Reference Manual

Change history .............................................................................................................. ii

Table 1-1 ETM10 configurations ............................................................................................... 1-3
Table 3-1 ETM10 to ARM1020E signal connections ................................................................. 3-2
Table 3-2 ETM10 datapath input signals ................................................................................... 3-4
Table 3-3 Signals on the ETMCORECTL[23:0] bus .................................................................. 3-6
Table 3-4 SYSOPT bus settings ............................................................................................. 3-10
Table 3-5 Single-processor configurations .............................................................................. 3-19
Table 3-6 Dual-processor trace port configurations for a single 20-pin trace port ................... 3-19
Table 4-1 Internal scan chain concatenations ........................................................................... 4-4
Table 4-2 Scan chain configurations ......................................................................................... 4-5
Table 4-3 ETM10 boundary-scan test signals ......................................................................... 4-10
Table 4-4 Test mode selection ................................................................................................ 4-11
Table 4-5 Test signals in serial core test mode ....................................................................... 4-12
Table 4-6 Test signals in external test mode ........................................................................... 4-12
Table 4-7 Test signals in functional mode ............................................................................... 4-14
Table 5-1 ETM ID register fields for ETM10 (Rev 0) ................................................................. 5-2
Table 5-2 Conditions for observing address comparator sticky bits .......................................... 5-5
Table A-1 ETM10 functional signals .......................................................................................... A-2
Table A-2 ETM10 boundary-scan test signals ........................................................................... A-5

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. v
List of Tables

vi Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
List of Figures
ETM10 Technical Reference Manual

Key to timing diagram conventions ............................................................................. xii

Figure 1-1 Block diagram of the ETM10 ..................................................................................... 1-2
Figure 2-1 ETM10 TAP structure ................................................................................................ 2-2
Figure 3-1 ETM10 signals .......................................................................................................... 3-3
Figure 3-2 Combining DBGRQ inputs ........................................................................................ 3-8
Figure 3-3 Recommended TAP interface structure .................................................................. 3-14
Figure 3-4 Using ETM10 and ARM10 with an external scan chain .......................................... 3-15
Figure 3-5 Multiprocessor TAP structure .................................................................................. 3-16
Figure 3-6 Reusing TRACEPKT pins ....................................................................................... 3-18
Figure 3-7 Normal signal timing with normal clocking .............................................................. 3-22
Figure 3-8 Normal signal timing with half-speed clocking ......................................................... 3-22
Figure 3-9 Demultiplexed signal timing with normal clocking ................................................... 3-23
Figure 3-10 Demultiplexed signal timing with half-rate clocking ................................................. 3-23
Figure 4-1 Dedicated input wrapper cell ..................................................................................... 4-7
Figure 4-2 Dedicated output wrapper cell ................................................................................... 4-8
Figure 4-3 Reset-dedicated wrapper cell .................................................................................... 4-9
Figure 4-4 ETM10 production-scan mode clocking requirements ............................................ 4-15
Figure 4-5 ETM10 serial core test clocking requirements ........................................................ 4-16

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. vii
List of Figures

viii Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Preface

This preface introduces the ARM10™ Embedded Trace Macrocell (ETM10) Revision
r0p0 Technical Reference Manual. It contains the following sections:
• About this manual on page x
• Feedback on page xv.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. ix
Preface

About this manual

This is the technical reference manual for the ARM10 Embedded Trace Macrocell
(ETM10) Revision r0p0. This product is referred to as ETM10 throughout this manual.

Product revision status

The rnpn identifier indicates the revision status of the product described in this
document, where:

rn Identifies the major revision of the product.

pn Identifies the minor revision or modification status of the product.

Intended audience

This manual is written for hardware and software engineers who want to integrate the
ETM10 into an ASIC that includes and ARM1020E processor.

Using this manual

This manual is organized into the following chapters:

Chapter 1 Introduction
Read this chapter for an introduction to the ETM10.

Chapter 2 Accessing the ETM10 Registers

Read this chapter for information about programming the registers that
control the ETM10.

Chapter 3 Integrating the ETM10

Read this chapter for information about integrating the ETM10 with an
ARM1020E processor.

Chapter 4 Design for Test

Read this chapter for details of the Design for Test (DFT) features of the
ETM10, including how to configure the scan chains and select a test
mode.

Chapter 5 Implementation-defined Behavior

Read this chapter for additional implementation-specific information
relating to ETM10.

x Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Preface

Chapter 6 Tracing Dynamically-loaded Images

Read this chapter for a discussion of the software issues that relate to the
ETM10.

Chapter 7 Physical Trace Port Signal Guidelines

Read this chapter for guidance about output pad selection and PCB
design.

Appendix A Signal Descriptions

Read this appendix for a description of the ETM10 functional and DFT
signals.

Conventions

Conventions that this manual can use are described in:

• Typographical
• Timing diagrams on page xii
• Signals on page xii
• Numbering on page xiii.

Typographical

The typographical conventions are:

italic Highlights important notes, introduces special terminology,

denotes internal cross-references, and citations.

bold Highlights interface elements, such as menu names. Denotes

ARM processor signal names. Also used for terms in descriptive
lists, where appropriate.

monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.

monospace Denotes a permitted abbreviation for a command or option. You

can enter the underlined text instead of the full command or option
name.

monospace italic Denotes arguments to monospace text where the argument is to be

replaced by a specific value.

monospace bold Denotes language keywords when used outside example code.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. xi
Preface

< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
• MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
• The Opcode_2 value selects which register is accessed.

Timing diagrams

The figure named Key to timing diagram conventions explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.

Clock

HIGH to LOW

Transient

HIGH/LOW to HIGH

Bus stable

Bus to high impedance

Bus change

High impedance to stable bus

Key to timing diagram conventions

Signals

The signal conventions are:

Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means HIGH for
active-HIGH signals and LOW for active-LOW signals.

Prefix A Denotes Advanced eXtensible Interface (AXI) global and address

channel signals.

Prefix B Denotes AXI write response channel signals.

Prefix C Denotes AXI low-power interface signals.

Prefix H Denotes Advanced High-performance Bus (AHB) signals.

xii Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Preface

Prefix n Denotes active-LOW signals except in the case of AHB or

Advanced Peripheral Bus (APB) reset signals. These are named
HRESETn and PRESETn respectively.

Prefix P Denotes APB signals.

Prefix R Denotes AXI read channel signals.

Prefix W Denotes AXI write channel signals.

Numbering

The numbering convention is:

<size in bits>’<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
• ‘h7B4 is an unsized hexadecimal value.
• ‘o7654 is an unsized octal value.
• 8’d9 is an eight-bit wide decimal value of 9.
• 8’h3F is an eight-bit wide hexadecimal value of 0x3F. This is
equivalent to b00111111.
• 8’b1111 is an eight-bit wide binary value of b00001111.

This section lists publications by ARM Limited, and by third parties.

ARM Limited periodically provides updates and corrections to its documentation. See
http://www.arm.com for current errata sheets, addenda, and the ARM Limited
Frequently Asked Questions list.

ARM publications

This manual contains information that is specific to the ETM10. Read the following
manuals for additional information:
• Embedded Trace Macrocell Specification (ARM IHI 0014)
• ARM1020E Technical Reference Manual (ARM DDI 0177)
• Multi-ICE User Guide (ARM DUI 0048).

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. xiii
Preface

Other publications

This section lists relevant documents published by third parties.

• Trace Port Analysis for ARM ETM Users Guide, Agilent Publications,
publication number E5903-97002.

xiv Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Preface

Feedback
ARM Limited welcomes feedback on the ETM10 and its documentation.

Feedback on the product

If you have any comments or suggestions about this product, contact your supplier
giving:
• the product name
• a concise explanation of your comments.

Feedback on this manual

If you have any comments on this manual, send email to [email protected] giving:
• the document title
• the document number
• the page number(s) to which your comments refer
• a concise explanation of your comments.

ARM Limited also welcomes general suggestions for additions and improvements.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. xv
Preface

xvi Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Chapter 1
Introduction

This chapter gives an overview of the ARM10 Embedded Trace Macrocell (ETM10)
r0p0. It contains the following section:
• About the ETM10 on page 1-2.
• Supported standard configurations on page 1-3.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 1-1
Introduction

1.1 About the ETM10

The ETM10 provides instruction and data trace for the ARM1020E microprocessor.
The block diagram of the ETM10 is shown in Figure 1-1.

TRACEPKT
Trace FIFO
control
ETM interface signals ARM1020E PIPESTAT
from ARM1020E interface logic
processor
TraceEnable, ViewData

Trigger, sequencer,
counters
System control
TAP signals
controller
Scan chain 6

ETM10

JTAG signals

Figure 1-1 Block diagram of the ETM10

For information about the trace protocol, and about controlling tracing using triggering
and filtering resources, see the Embedded Trace Macrocell Specification.

For information about ETM10 input and output signals, see Appendix A Signal
Descriptions.

1-2 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Introduction

1.2 Supported standard configurations

The three standard configurations for ETM10 are shown in Table 1-1.

Table 1-1 ETM10 configurations

Resource description Small Medium Large

Pairs of address comparators 1 4 8

Data comparators 0 2 4

Memory map decoders 0 0 0

CONTEXT ID comparators 0 1 3

Counters 1 2 4

Sequencer present No Yes Yes

External inputs 2 4 4

External outputs 0 1 4

FIFOFULL present Yes Yes Yes

FIFO depth 30 45 60

Port sizea 4/8/16 4/8/16 4/8/16

a. Software-selectable using the ETM control register.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 1-3
Introduction

1-4 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Chapter 2
Accessing the ETM10 Registers

This chapter describes how to program the registers that control the trace and triggering
facilities of the ETM10. It contains the following sections:
• The JTAG interface on page 2-2
• ETM10 registers on page 2-3.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 2-1
Accessing the ETM10 Registers

2.1 The JTAG interface

All registers in the ETM10 are programmed through a JTAG interface. The interface is
an extension of the ARM Test Access Port (TAP) controller, and is assigned scan chain
6.

The ETM10 TAP is logically part of the ARM processor to which it is connected. This
means that Multi-ICE detects only one TAP in a single ARM10-ETM system.

The general arrangement of the ETM10 JTAG registers is shown in Figure 2-1.

R/W Update
6 Address
Address decoder
0
31

Data

ETM registers

TDI TDO

Figure 2-1 ETM10 TAP structure

The scan chain consists of a 40-bit shift register comprising:

• a 32-bit data field
• a 7-bit address field
• a read/write bit.

The data to be written is scanned into the 32-bit data field, the address of the register
into the 7-bit address field, and a 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the
read/write bit. The 32-bit data field is ignored.

A read or a write takes place when the TAP controller enters the UPDATE-DR state.

2-2 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Accessing the ETM10 Registers

2.2 ETM10 registers

When modifying ETM10 registers, you must set the programming bit in the ETM
control register (0x00) before making any further modifications. When all register
updates are complete, you must clear the programming bit. While the programming bit
is set, all ETM operations are disabled.

The setting and clearing of the programming bit is necessary for proper synchronization
between the CLK and TCK clock domains. You do not have to set the programing bit
to read ETM registers.

The ETM control register and all the other ETM registers are described in the
Embedded Trace Macrocell Specification.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 2-3
Accessing the ETM10 Registers

2-4 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Chapter 3
Integrating the ETM10

This chapter describes how to integrate the ETM10 with an ARM10 processor. It
contains the following sections:
• About integrating the ETM10 on page 3-2
• ARM1020E trace interface on page 3-4
• System control signals on page 3-8
• Clocks and resets on page 3-12
• TAP interface wiring on page 3-14
• Trace port interfacing on page 3-17
• Modes of operation of the trace port on page 3-21.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-1
Integrating the ETM10

3.1 About integrating the ETM10

The interface comprises 267 signals as follows:

232 inputs All input signals are registered immediately inside the ETM10.

35 outputs all outputs are driven directly from the output of a register, with the single
exception of TDO.

3.1.1 ETM10 to ARM10 connection guide

Table 3-1 shows how the ETM10 must be connected to the ARM1020E.

Table 3-1 ETM10 to ARM1020E signal connections

ETM10 signal name ARM1020E signal name

DBGRQ EDBGRQ

TDO SDOUTBS

PWRDOWN ETMPWRDOWN

FIFOFULL FIFOFULL

DBGACK DBGACK

ETMCORECTL[23:0] ETMCORECTL[23:0]

ETMDATAVALID[1:0] ETMDATAVALID[1:0]

ETMIA[31:1] ETMIA[31:1]

ETMDA[31:0] ETMDA[31:0]

ETMR15EX[31:1] ETMR15EX[31:1]

ETMR15BP[31:1] ETMR15BP[31:1]

ETMDATA[63:0] ETMDATA[63:0]

The functional diagram of the ETM10 is shown in Figure 3-1 on page 3-3.

3-2 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

GCLK ETM10DFTGCKEN
Clock
NRESET ETM10DFTWCKEN
Reset
TRIGGER ETM10RSTSAFE

FIFOFULL SCORETEST

PORTSIZE[2:0] SCANMUX12

PWRDOWN SCANMUX6
Miscellaneous
output signals ETMEN ETM10WCLK

CLKDIVTWOEN ETM10WSCANEN

EXTOUT[3:0] ETM10SCANMODE

PORTMODE[1:0] ETM10SCANEN

ETMDA[31:0] ETM10SAFE Design for Test

Load Data bus[63:0] (DFT) interface
ETMDATA[63:0] ETM10WMUXINSEL
Store Data bus[63:0]
ETMIA[31:1] ETM10WMUXOUTSEL
MCR Data bus[63:0]

ETM10
ETMR15EX[31:1] ETM10DFTRESET
MRC Data bus[63:0]
ETMR15BP[31:1] ETM10SCANIN[23:0]

TCK ETM10SCANOUT[23:0]

TMS ETM10WSCANIN[1:0]

TDI ETM10WSCANOUT[1:0]
TAP interface NTRST WMUX2

ARMTDO PIPESTATA[3:0]
TDO
PIPESTATB[3:0]
ETMDATAVALID[1:0]
TRACEPKTA[15:0] Trace port
Control inputs
ETMCORECTL[23:0]
TRACEPKTB[15:0]

EXTIN[3:0] TRACECLK
Miscellaneous
input signals SYSOPT[8:0]

DBGRQ
Debug DBGACK

Figure 3-1 ETM10 signals

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-3
Integrating the ETM10

3.2 ARM1020E trace interface

ARM10 interfacing is described in the following sections:
• ETM10 datapath inputs
• ETM10 control inputs on page 3-5.

3.2.1 ETM10 datapath inputs

The ETM data input buses are described in Table 3-2.

Table 3-2 ETM10 datapath input signals

Signal name Description

ETMDATA[63:0] Contains the data value for a Load, Store, MRC, or MCR
instruction.

ETMDA[31:0] Data address bus. Gives the address for every load or store
transaction.

ETMIA[31:1] Instruction address bus. Gives the address for every instruction
fetch.

ETMR15BP[31:1] Address for the branch phantom currently in the Execute stage
of the processor pipeline.

ETMR15EX[31:1] Address for the instruction currently in the Execute stage of

the processor pipeline.

The ETMDATA bus

Four data buses are used for ETM data tracing:

• load data bus
• store data bus
• MCR data bus
• MRC data bus.

Each data bus is 64 bits wide. Only one data bus can contain valid data in any cycle, so
all four buses are multiplexed within the ARM1020E processor to a single 64-bit data
bus, ETMDATA. ETMDATA is registered within the ARM1020E processor before it
is driven to the ETM. ETMDATA is valid in the Write (WR) stage of the ARM1020E
pipeline.

3-4 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

Address buses

Four address buses are driven from the ARM1020E processor to ETM10:

ETMDA[31:0] Valid in the Memory (ME) stage of the ARM1020E pipeline.

ETMIA[31:1] Valid in the Decode (DE) stage of the ARM1020E pipeline.

ETMR15BP[31:1] Valid in the Execute (EX) stage of the ARM1020E pipeline.

ETMR15EX[31:1] Valid in the Execute (EX) stage of the ARM1020E pipeline.

As shown in Table 3-2 on page 3-4, ETMDA[31:0] is for data addresses and the other
address buses are for instruction addresses.

3.2.2 ETM10 control inputs

The ETM10 control inputs are described in the following sections:

• ETMDATAVALID[1:0]
• ETMCORECTL[23:0].

ETMDATAVALID[1:0]

This signal qualifies the data on the ETMDATA[63:0] bus as follows:

ETMDATAVALID1 Qualifies ETMDATA[63:32].

ETMDATAVALID0 Qualifies ETMDATA[31:0].

ETMCORECTL[23:0]

The control signals from the ARM10 core comprise ETMCORECTL[23:0]. The
control signals present on this bus are described in Table 3-3 on page 3-6.

Note
All the signals described in Table 3-3 on page 3-6 are valid in the Write (WR) stage of
the ARM1020E pipeline, unless specified otherwise.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-5
Integrating the ETM10

Table 3-3 Signals on the ETMCORECTL[23:0] bus

Signal name Bit number Description Qualified by

ITBit 0 Asserted when ARM1020E is in InMREQ/ForcePF

Thumb state (valid in ME).

InMREQ 1 Current address on the IA bus is for a None

valid instruction fetch.

ForcePF 2 Current address on the IA bus is a None

target for an indirect branch.

InstValid 5 Asserted once per executed None

instruction. Not asserted for
mispredicted branches, because these
are fetched but not executed.

BpValid 3 Asserted once per executed branch None

phantom. When asserted, a branch
phantom is present in the Execute
stage of the processor pipeline.

CCFail 6 Current instruction failed its InstValid

condition codes.

BpCCFail 4 Branch phantom failed its condition BpValid

codes.

Tbit 7 Asserted when ARM1020E is in InstValid

Thumb state (valid in ME).

ETMBranch 8 Last instruction executed is an Asserted before or

indirect branch. coincident with
ForcePF

R15HoldMe 9 Stall signal for the address given on None

R15EX.

UpdatesContextID 10 Current instruction is updating the DATAVALID

CONTEXT ID.

DnMREQ 11 Qualifies the Data Address bus, DA. None

DMAS[1:0] [13:12] Load or store data size. DnMREQ

ETMSwap 14 Indicates a 64-bit store to a DnMREQ

big-endian memory device.

DnRW 15 Data request read/write signal (LOW DnRW

for read cycle).

3-6 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

Table 3-3 Signals on the ETMCORECTL[23:0] bus (continued)

Signal name Bit number Description Qualified by

HUMACK 16 Valid load miss data is present on the None

data bus this cycle.

LSCMInit 17 Current instruction is an LSM InstValid

instruction.

LSCM 18 LSM is in progress in the Load/Store DnMREQ

Unit.

MISSCNT[1:0] [20:19] The number of load misses that are None. Transitions
outstanding. indicate new miss.

Exception 21 Current instruction is an exception InstValid

(interrupt, reset, or abort).

DAbort 22 Data request aborted. DnMREQ

PreLoad 23 Current instruction is a preload and InstValid

must not be traced.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-7
Integrating the ETM10

3.3 System control signals

The ETM10 outputs that are input to the ARM1020E are described in the following
sections:
• Debug
• Using the PWRDOWN signal on page 3-9
• The FIFOFULL stall signal on page 3-10
• The SYSOPT bus on page 3-10.

3.3.1 Debug

When the trigger condition occurs, you can set bit 9 in the ETM control register to assert
DBGRQ until DBGACK is observed.

It is recommended that you connect the DBGRQ output of the ETM10 to the
EDBGRQ input of the ARM processor. If this input is already in use, when for example
a DBGRQ input is present on the device, you can logically OR the DBGRQ signals
together as shown in Figure 3-2.

ARM ETM10

EDBGRQ DBGRQ

ASIC

DBGRQ

Figure 3-2 Combining DBGRQ inputs

Note
ARM10 processors take at least one cycle to respond to EDBGRQ. This means that the
ARM processor can execute a few instructions after the trigger condition is detected but
before the system has stopped. Some debug tools can report an unrecognized breakpoint
as a result.

3-8 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

The core only recognizes EDGBRQ if the ARM10 core is currently in hardware debug
mode.

For more information about ARM10 debug modes, see the ARM1020E Technical
Reference Manual.

3.3.2 Using the PWRDOWN signal

PWRDOWN is asserted when the ETM is not enabled. When a TAP reset (NTRST)
occurs, PWRDOWN is forced HIGH until bit 0 of the ETM10 control register has been
deasserted (the ETM10 registers are programmed by the ARM debug tools through
JTAG). The ARM1020E processor uses the assertion of PWRDOWN to indicate that
ETM10 bus inputs must be held stable. Within the ETM, PWRDOWN assertion is also
used to gate the clock, for more power savings.

Note
For PWRDOWN to function correctly, the TAP reset must be asserted every time the
system is powered on (see NTRST on page 3-12).

The PWRDOWN output is controlled by the ARM debug tools, and is automatically
cleared at the start of a debug session.

The PWRDOWN signal is changed synchronously to TCK. PWRDOWN changes

many cycles before trace is enabled, so using PWRDOWN to gate the ETM10 clock
does not cause any metastability problems.

Context ID values

ETM10 supports the tracing of dynamically loaded memory and overlay systems by
maintaining the current context ID value in an internal register. To guarantee that
context ID values are updated while the ETM is in powerdown state, the ETM10 clock
gating logic allows a one cycle clock pulse on context ID updates. This logic is part of
the ETM10 internal clock control logic, and is controlled by ETMCORECTL10 (an
input from the ARM1020E core).

Note
Context ID was previously known as process ID. This has been changed to avoid
confusion with the Fast Context Switch Extensions (FCSE) field, sometimes referred to
as the FCSE process ID.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-9
Integrating the ETM10

3.3.3 The FIFOFULL stall signal

FIFOFULL changes on the rising edge of GCLK and is active HIGH. When asserted,
it indicates that the trace tools user has enabled the ETM FIFO full detection mechanism
and that one of the following is true:
• bytes are currently present in the FIFO
• bytes are being inserted this cycle.

You can use FIFOFULL to stall the ARM core, so that more trace data is not generated
until the FIFO has drained. It is recommended that you implement this by connecting
the FIFOFULL ETM10 output directly to the FIFOFULL input on the ARM1020E
processor. Within the ETM you can specify the address regions in which FIFOFULL
can be asserted. This enables you to slow down non real-time areas of code, while
critical regions remain unaffected.

The logic does not directly affect the behavior of the ETM, so it is not significant if the
FIFOFULL logic inside the ETM is programmed and enabled when the system
designer cannot support the use of this signal. However, if FIFOFULL is not used,
there is a risk of some trace data being lost while the FIFO drains.

Note
To maintain interrupt response time in the system, you might have to override
FIFOFULL assertion when nIRQ and/or nFIQ are asserted.

3.3.4 The SYSOPT bus

System control signals are broadcast on the system options bus, SYSOPT[8:0]. You
can use the SYSOPT bus to specify whether certain trace features, such as half-rate
clocking, are implemented on the ASIC. You must tie each of the bits of the bus LOW
or HIGH, depending on the features supported. The trace debug tools read the state of
the SYSOPT bus using the JTAG interface, and adapt the user options offered
accordingly. The signals on the SYSOPT bus are described in Table 3-4.

Table 3-4 SYSOPT bus settings

Bit number Description

[8] If HIGH, FIFOFULL is supported.

[7] If HIGH, demultiplexed trace data format is supported.

[6] If HIGH, multiplexed trace data format is supported.

[5] If HIGH, normal trace data format is supported.

3-10 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

Table 3-4 SYSOPT bus settings (continued)

Bit number Description

[4] If HIGH, full-rate clocking is supported.

[3] If HIGH, half-rate clocking is supported.

[2:0] Maximum port width supported:000 = 4-bit only001 = 4 or 8-bit 010 =

4, 8, or 16-bit.
The behavior is undefined if you use other bit settings.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-11
Integrating the ETM10

3.4 Clocks and resets

The ETM10 has two sets of clock and reset inputs. These are described in the following
sections:
• GCLK
• TCK
• NRESET
• NTRST.

3.4.1 GCLK

GCLK is the clock domain used for ETM trace generation logic. GCLK is the same
clock that is used by the ARM1020E core. To save power, GCLK is gated internal to
ETM10 whenever the ETM10 output PWRDOWN is asserted. The PWRDOWN
signal is described in Using the PWRDOWN signal on page 3-9.

3.4.2 TCK

TCK is the clock domain of the JTAG interface. This is the clock domain in which the
ETM registers are programmed.

ETM10 is designed to function with fully asynchronous GCLK and TCK inputs.
Synchronizing logic is included in the design to prevent metastability problems
between the two clock domains when running with asynchronous clocks.

3.4.3 NRESET

NRESET is the system power-on reset. NRESET is used only to reset the ContextID
shadow register in ETM10. NRESET is synchronized to GCLK for deassertion
internal to ETM10 to avoid timing problems. Assertion of NRESET is asynchronous.

3.4.4 NTRST

NTRST is the TAP controller reset. It is used within the ETM10 as the main reset signal
for both TCK and GCLK domain logic. ETM10 uses NTRST rather than the core reset
signal so that you can trace the core through reset. Deassertion of the main NTRST
input can be asynchronous to both TCK and GCLK, and TCK and GCLK are
asynchronous clock domains, so NTRST is synchronized internally for deassertion for
both the TCK and GCLK domains. Assertion of NTRST is asynchronous.

3-12 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

Note
NTRST must be asserted for at least eight cycles when the system is initially powered
on, otherwise the behavior of the ETM and of the whole system is unpredictable.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-13
Integrating the ETM10

3.5 TAP interface wiring

Both the ARM1020E microprocessor and the ETM10 provide scan chain expansion
inputs. These are:
• SDOUTBS on the ARM1020E processor
• ARMTDO on ETM10.

In each case, this input is routed through to TDO when a non-ARM1020E or

non-ETM10 scan chain is selected. This enables the ARM1020E and ETM10 TAP
controllers to run in parallel, with a single TDO output.

ETM10 uses the same TAP interface wiring as previous ETM versions. The TDO pin
is connected to the ARM1020E scan expansion input SDOUTBS. ETM10 registers are
accessed using scan chain 6 and are programmed in a manner identical to previous ETM
implementations.

The recommended connectivity is shown in Figure 3-3. For information about the
JTAG interface, see The JTAG interface on page 2-2.

TDO

ARM TDO ETM10 TDO

SCREG SCREG

ARMTDO
TAP Scan SDOUTBS TAP Scan
controller chains controller chain

TCK TDI TMS TCK TDI TMS

Figure 3-3 Recommended TAP interface structure

Note
For clarity, NTRST is omitted from figures relating to the TAP interface. You must
connect NTRST to all TAPs on the chip. See the Multi-ICE User Guide for details.

If your ASIC includes a further scan chain controlled by the ARM1020E TAP
controller, then the TDO of this scan chain can be connected into the otherwise unused
ARMTDO input on the ETM10. This is shown in Figure 3-4.

3-14 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

TDO

TDO TDO
ARM10 ETM10

SDOUTBS ARMTDO
External scan
chain
TCK TDI TMS TCK TDI TMS

TCK TDI TMS

Figure 3-4 Using ETM10 and ARM10 with an external scan chain

3.5.1 Multiprocessor TAP structure

If you want your multiprocessor-compatible run control products, such as Multi-ICE,

to work correctly when used with more than one ARM processor on a chip, ARM
Limited recommends that you connect the processors as a serial TAP structure. The
presence of an ETM10 on any or all of the ARM processors does not affect this. The
TAP structure for a dual-processor ARM processor system is shown in Figure 3-5 on
page 3-16.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-15
Integrating the ETM10

TDO TDO
ARM10 ETM10

SDOUTBS
ARMTDO

TCK TDI TMS TCK TDI TMS

TDO TDO
ARM10 ETM10
SDDOUTBS
ARMTDO

TCK TDI TMS TCK TDI TMS

TDO TCK TDI TMS

Figure 3-5 Multiprocessor TAP structure

Note
For clarity, NTRST is omitted from figures relating to the TAP interface. You must
connect NTRST to all TAPs on the chip. See the Multi-ICE User Guide for details.

3-16 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

3.6 Trace port interfacing

Trace port interfacing is described in the following sections:
• Trace port logic
• Single-processor tracing
• Dual-processor tracing on page 3-18
• PCB design guidelines on page 3-20.

See Modes of operation of the trace port on page 3-21 for details of trace port operation.

3.6.1 Trace port logic

Trace information from the ETM10 is broadcast on the following signals:

• TRACECLK
• PIPESTATA[3:0]
• TRACEPKTA[15:0]
• PIPESTATB[3:0]
• TRACEPKTB[15:0].

PIPESTATB and TRACEPKTB are used only in demultiplexed mode.

Three configuration signals are also provided:

• ETMEN
• PORTSIZE[2:0]
• PORTMODE[1:0].

You can use these to configure the external logic connected to the trace port, under the
control of the debugger.

3.6.2 Single-processor tracing

Some chips might not dedicate 16 pins to the TRACEPKTA bus. Under some
circumstances you might be able to re-use miscellaneous output signals from the chip
as trace port pins. To allow this, the ETM10 has the following outputs:
• ETMEN
• PORTSIZE[2:0].

Figure 3-6 on page 3-18 shows one way in which the TRACEPKTA pins can be shared
with the ASIC pins.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-17
Integrating the ETM10

ASIC
logic ASIC output
0 TRACEPKTA[15:4]
ETM10 TRACEPKTA[15:0]
1
ASIC output
TRACEPKTA[3:0]
PORTSIZE, ETMEN
Logic

Figure 3-6 Reusing TRACEPKT pins

You can use the PORTSIZE and ETMEN signals to control on-chip logic to select
between the normal ASIC output signals and the ETM10 trace port signals. This enables
you to control the port width of the trace, and the number of pins used, from the
debugger.

At reset the ETM10 is disabled (ETMEN LOW) and a 4-bit port is selected
(PORTSIZE = 000). This ensures that normal operation of the ASIC is unaffected.

Once the debug session starts, the debug tools can control ETMEN and PORTSIZE
by programming the ETM control register.

3.6.3 Dual-processor tracing

Where there are multiple ARM processors on a single chip, it is recommended that each
ARM processor has its own dedicated ETM.

The principle of controlling the port width, described in Single-processor tracing on

page 3-17, can be extended to support dual-processor systems without dedicating a
large number of pins to the trace signals.

The recommended dual-trace configuration uses 21 pins on the ASIC, because this
matches the 20 data pins and one clock pin defined in the trace connector specification.
These pins are configured as 20 data pins and a single clock pin (assuming that both
processors are controlled by a single clock).

3-18 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

Possible trace port configurations for a single processor are shown in Table 3-5.

Table 3-5 Single-processor configurations

TRACEPKT PIPESTAT Total

16 trace packet pins 4 status pins 20 data pins

8 trace packet pins 4 status pins 12 data pins

4 trace packet pins 4 status pins 8 data pins

You can, therefore, use a single 20-pin trace port to allow the configurations shown in
Table 3-6 for dual-processor systems.

Table 3-6 Dual-processor trace port configurations for a single 20-pin trace port

Processor 1 Processor 2

20 data pins No trace

12 data pins 8 data pins

8 data pins 12 data pins

No trace 20 data pins

Pseudo-HDL to implement this is as follows:

if (PORTSIZE_2 = 21)
TRACE_DATA <= {PIPESTATA_2, TRACEPKTA_2[15:0]}
else if (PORTSIZE_1 = 13) and (PORTSIZE_2 = 9)
TRACE_DATA <= {PIPESTATA_2, TRACEPKTA_2[3:0],
PIPESTATA_1, TRACEPKTA_1[7:0]}
else if (PORTSIZE_1 = 9) and (PORTSIZE_2 = 13)
TRACE_DATA <= {PIPESTATA_1, TRACEPKTA_1[3:0],
PIPESTATA_2, TRACEPKTA_2[7:0]}
else
-- select 1 as the "master" for all other combinations.
TRACE_DATA <= {PIPESTATA_1, TRACEPKTA_1[15:0]}
end if

Note
If you want to trace multiple cores in demultiplexed mode, you must use two separate
target system connectors. See Demultiplexed trace port signals on page 3-22 for more
details.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-19
Integrating the ETM10

The Embedded Trace Macrocell Specification documents the target system connector
pin allocations for single and dual-processor configurations. Support for the
dual-processor pinouts is dependent on the debug tools and the TPA.

It is not recommended that you connect a single ETM10 to multiple ARM10 processors.
This is because there is no general mechanism available to control the logic that selects
which processor is connected to the single ETM.

3.6.4 PCB design guidelines

See Chapter 7 Physical Trace Port Signal Guidelines, for information about output pad
selection and PCB design, including:
• trace signal termination
• PCB track lengths
• pad drive strength.

3-20 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

3.7 Modes of operation of the trace port

The PORTMODE output bus provides a copy of the contents of bits [17:16] of the
ETM control register. PORTMODE enables the trace debug tools to configure how the
trace port signals from the ETM (PIPESTATA, PIPESTATB, TRACEPKTA, and
TRACEPKTB) are mapped onto the trace port pins of the ASIC. The following modes
of operation are supported:

Normal mode See Normal trace port signals.

Demultiplexed mode
See Demultiplexed trace port signals on page 3-22.

In each mode, both normal and half-rate clocking are supported. The clocking mode is
controlled by CLKDIVTWOEN (this is a copy of ETM control register bit 13).

Normal and demultiplexed modes are supported directly on ETM10. Multiplexed mode
is not supported directly by ETM10, because it is unlikely that the system speed will be
slow enough for it to be used. You can implement multiplexed mode with logic external
to ETM10 in the same way as for ETM9 (see the ETM9 Technical Reference Manual
for details).

3.7.1 Normal trace port signals

In normal mode tracing, the trace port signals PIPESTATA and TRACEPKTA are
mapped directly onto the trace port pins of the ASIC. PIPESTATB and TRACEPKTB
are not used. Both normal and half-rate clocking are supported in this mode, but
half-rate clocking is recommended to allow for higher frequency tracing. To use
half-rate clocking, the TPA device must be capable of capturing data on both edges of
TRACECLK.

Figure 3-7 on page 3-22 shows the timing for the normal trace port with normal
clocking.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-21
Integrating the ETM10

T1 T2 T3 T4 T5

GCLK

TRACECLK

Trace port A Data 1 Data 2 Data 3 Data 4

Figure 3-7 Normal signal timing with normal clocking

Figure 3-8 shows the timing for the normal trace port with half-rate clocking.

T1 T2 T3 T4 T5

GCLK

TRACECLK

Trace port A Data 1 Data 2 Data 3 Data 4

Figure 3-8 Normal signal timing with half-speed clocking

3.7.2 Demultiplexed trace port signals

This scheme is recommended for high-speed systems where the switching frequency of
the off-chip trace signals is unacceptable.

Figure 3-9 on page 3-23 shows the timing for the demultiplexed trace port with normal
clocking.

3-22 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Integrating the ETM10

T1 T2 T3 T4 T5

GCLK

TRACECLK

Trace port A Data 1 Data 3

Trace port B Data 2 Data 4

Figure 3-9 Demultiplexed signal timing with normal clocking

Figure 3-10 displays the timing for the demultiplexed trace port with half-rate clocking.

T1 T2 T3 T4 T5

GCLK

TRACECLK

Trace port A Data 1 Data 3

Trace port B Data 2 Data 4

Figure 3-10 Demultiplexed signal timing with half-rate clocking

In demultiplexed mode, the TPA must examine the trace port A and trace port B in
parallel to determine whether a trigger has occurred. It must also check for the TD
(Trace Disabled) pipeline status in trace port A and trace port B.

3.7.3 Operation with asynchronous TCK

You can use the ETM10 in systems that have a fully asynchronous TCK and GCLK.
All synchronization issues are handled in the ETM10. All groups of signals are
synchronous to the relevant clock:
• ARM10 interface GCLK

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 3-23
Integrating the ETM10

• Trace port GCLK

• JTAG port TCK
• ETM register programming TCK.

Slow system clock speeds

The ETM10 contains synchronizing D-types to synchronize between the TCK timing
domain and the GCLK timing domain. When GCLK is much slower than TCK, it
might take several TCK cycles before you can disable tracing (by setting the
programming bit). It is possible to read back the programming bit value to guarantee
that synchronization has occurred. For more information, see the Embedded Trace
Macrocell Specification.

3-24 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Chapter 4
Design for Test

This chapter describes the Design for Test (DFT) features of ETM10. It contains the
following sections:
• About DFT on page 4-2
• Scan chain configurations on page 4-4
• ETM10 test wrapper on page 4-6
• Test modes and ports on page 4-10
• Clocks and gating on page 4-15.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 4-1
Design for Test

4.1 About DFT

For the purposes of boundary-scan testing, ETM10 comprises a functional core
surrounded by a test wrapper. The wrapper provides a single serial scan ring around the
entire periphery, and enables:
• test control and observation of the functional core from the ports
• control and observation of the external logic surrounding the functional core.

The test wrapper enables a tester to apply vectors, or control stimulus, that can achieve
a high quality measurement with a minimal amount of external pin control. This is
extremely important if the design unit is to be embedded or buried within other design
units or chip logic. See ETM10 test wrapper on page 4-6 for more details.

4.1.1 DFT modes

In addition to the normal ETM10 functional mode, there are three DFT modes, as
follows:

Internal test mode In this mode, you have control over the inputs to the functional
core during test, and you can observe the core outputs (see
Internal test mode on page 4-12).

External test mode In this mode, you can observe the logic in the wrapper cell itself,
while signals are propagated between the peripheral logic to the
functional core (see External test mode example on page 4-12).

Serial core test mode

In this mode, all scan chains (from both the functional core and the
test wrapper) are concatenated, effectively combining the internal
and external test modes (see Serial core test mode on page 4-13).

4.1.2 Scan chains

ETM10 comprises 24 individual scan chains. You can combine them in different
configurations, as follows:

Functional core Three internal scan chain configurations are possible:

• 24 scan chains
• 12 scan chains
• 6 scan chains.

Test wrapper Two wrapper scan chain configurations are possible:

• one scan chain
• two scan chains.

4-2 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Design for Test

The scan chains are shorter if there are more parallel scan chains in a design. The total
vector count becomes smaller as the scan chains become shorter, saving tester memory.
However, you must choose the 12 or 6-chain configuration if your final package or test
environment does not have the pin bandwidth to handle the maximum 24 chains. There
are no memories on the core.

See Scan chain configurations on page 4-4 for more details.

4.1.3 Clock signals

The test wrapper contains only dedicated test wrapper cells, and these are clocked by
ETM10WCLK, a dedicated test wrapper clock. Gating of ETM10WCLK is enabled
by ETM10DFTWCKEN.

Gating of the internal clock domain, GCLK, is enabled by ETM10DFTGCKEN.

See Clocks and gating on page 4-15 for more details.

4.1.4 Asynchronous signals

Asynchronous signals must be directly controlled by the Automatic Test Pattern

Generator (ATPG) tool. The asynchronous reset signals on the ETM10 are directly
controlled during testing by the ETM10DFTRESET signal. See Reset-dedicated
wrapper cell on page 4-8 for more details.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 4-3
Design for Test

4.2 Scan chain configurations

ETM10 is a full-scan design comprising the following configuration options:

6, 12, or 24 internal scan chains

Controlled by SCANMUX6 and SCANMUX12.

One or two wrapper scan chains

Controlled by WMUX2.

The ETM10 internal scan chain concatenations are shown in Table 4-1.

Table 4-1 Internal scan chain concatenations

Scan chains
Mode ScanIn ScanOut
concatenated

SCANMUX12 23, 11 SCANIN[11] ETM10SCANOUT[11]

SCANMUX12 22, 10 SCANIN[10] ETM10SCANOUT[10]

SCANMUX12 21, 9 SCANIN[9] ETM10SCANOUT[9]

SCANMUX12 20, 8 SCANIN[8] ETM10SCANOUT[8]

SCANMUX12 19, 7 SCANIN[7] ETM10SCANOUT[7]

SCANMUX12 18, 6 SCANIN[6] ETM10SCANOUT[6]

SCANMUX12 17, 5 SCANIN[5] ETM10SCANOUT[5]

SCANMUX12 16, 4 SCANIN[4] ETM10SCANOUT[4]

SCANMUX12 15, 3 SCANIN[3] ETM10SCANOUT[3]

SCANMUX12 14, 2 SCANIN[2] ETM10SCANOUT[2]

SCANMUX12 13, 1 SCANIN[1] ETM10SCANOUT[1]

SCANMUX12 12, 0 SCANIN[0] ETM10SCANOUT[0]

SCANMUX6 23, 11, 17, 5 SCANIN[5] ETM10SCANOUT[5]

SCANMUX6 22, 10, 16, 4 SCANIN[4] ETM10SCANOUT[4]

SCANMUX6 21, 9, 15, 3 SCANIN[3] ETM10SCANOUT[3]

4-4 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Design for Test

Table 4-1 Internal scan chain concatenations (continued)

Scan chains
Mode ScanIn ScanOut
concatenated

SCANMUX6 20, 8, 14, 2 SCANIN[2] ETM10SCANOUT[2]

SCANMUX6 19, 7, 13, 1 SCANIN[1] ETM10SCANOUT[1]

SCANMUX6 18, 6, 12, 0 SCANIN[0] ETM10SCANOUT[0]

Note
The internal scan chains do not cross clock domains during 6, 12, or 24 scan chain
modes.

For scan testing of the core, you must tie the SCANMUX12, SCANMUX6, and
WMUX2 signals in one of the configurations listed in Table 4-2.

Table 4-2 Scan chain configurations

Maximum
Configuration Pins
chain length

24 internal scan chains SCANMUX12 237

LOWSCANMUX6 LOW

12 internal scan chains SCANMUX12 465

HIGHSCANMUX6 LOW

6 internal scan chains SCANMUX12 921

LOWSCANMUX6 HIGH

Restricted SCANMUX12 -
HIGHSCANMUX6 HIGH

2 wrapper scan chains WMUX2 HIGH 155

1 wrapper scan chain WMUX2 LOW 292

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 4-5
Design for Test

4.3 ETM10 test wrapper

You use the test wrapper for control and observation of the ports during testing of the
ETM core and the logic external to the core.

The longest scan chain must not be a wrapper chain, otherwise it controls the ultimate
length of each scan pattern. If you are implementing 24 internal scan chains, you must
implement two test wrapper scan chains, so that the wrapper chain does not gate the
scan pattern length.

The wrapper scan chain comprises only dedicated test wrapper cells. There is a wrapper
cell connected to every functional input and output port with the exception of the clock
ports.

There are three types of wrapper cell, described in the following sections:
• Dedicated input wrapper cells
• Dedicated output wrapper cells on page 4-7
• Reset-dedicated wrapper cell on page 4-8.

4.3.1 Dedicated input wrapper cells

The input wrapper cells are controlled by ETM10WMUXINSEL. When

ETM10WMUXINSEL is HIGH, all the input wrapper cells are in inward-facing mode
to enable you to control the ETM core inputs during test. When ETM10WMUXINSEL
is LOW, the wrapper input cells observe signal propagation from the peripheral logic to
the functional ports of the ETM.

Figure 4-1 on page 4-7 shows a dedicated input wrapper cell.

4-6 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Design for Test

Scan input Scan output

Functional path
OUT 0 IN
D 1
SI Q
SE
CK
Peripheral Functional
logic Wrapper cell core of ETM

ETM10WMUXINSEL
ETM10WCLK
ETM10WSCANEN

Figure 4-1 Dedicated input wrapper cell

4.3.2 Dedicated output wrapper cells

The output wrapper cells are controlled by ETM10WMUXOUTSEL. When

ETM10WMUXOUTSEL is HIGH, the output wrapper cells control the signals to the
peripheral logic attached to the core. When ETM10WMUXOUTSEL is LOW, the
cells observe the logic in the functional core.

Note
Dedicated output cells have safe gates.

Figure 4-2 on page 4-8 shows a dedicated output wrapper cell.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 4-7
Design for Test

Scan input Scan output ETM10SAFE

Functional path
OUT 0 Safe IN
D 1 gate

SI Q
SE
CK
Functional Peripheral
Wrapper cell
core of ETM logic

ETM10WMUXOUTSEL
ETM10WCLK
ETM10WSCANEN

Figure 4-2 Dedicated output wrapper cell

4.3.3 Reset-dedicated wrapper cell

The reset-dedicated wrapper cell is used during asynchronous reset input. During
external test mode, the safe gate on the reset wrapper cells can enable the reset of the
core to reduce power and to keep the core safe. In addition, both asynchronous resets
(NRESET and NTRST) are directly-controllable during scan mode. The
ETM10DFTRESET port is a separate port that must be directly connected to a pin to
have direct control of reset during ATPG testing.

Note
Reset-dedicated wrapper cells have safe gates.

Figure 4-3 on page 4-9 shows a reset-dedicated wrapper cell.

4-8 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Design for Test

Scan input Scan output ETM10RSTSAFE

Functional path
OUT 0 Safe IN
1 gate

D
SI Q
SE

Functional CK Peripheral
core of ETM Wrapper cell logic

ETM10DFTRESET ETM10WMUXINSEL
ETM10WCLK
ETM10WSCANEN

Figure 4-3 Reset-dedicated wrapper cell

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 4-9
Design for Test

4.4 Test modes and ports

Some of the ETM10 test signals are static and some are dynamic. In the case of the
ETM10 scan patterns, a dynamic signal must propagate from the pin of the chip to the
first flip-flop in the core (the head flip-flop of a scan chain), within a cycle of the test
pattern. The timing of the test patterns is such that:
• at time zero, the inputs change
• mid-point through the cycle, the clock becomes active (except in the case of
ETM10WCLK, as shown in Figure 4-4 on page 4-15).

The ETM10 boundary-scan test ports are described in Table 4-3.

Table 4-3 ETM10 boundary-scan test signals

Signal name Direction Type Description

ETM10WCLK Input Dynamic Wrapper clock for dedicated wrapper cells.

ETM10SCANMODE Input Static Puts the device into scan mode.

ETM10SCANEN Input Dynamic Scan enable for all internal clock domains. HIGH = shift.

ETM10SAFE Input Static Forces safe values onto the outputs of the core. Use during
core test and during the shift sequence of any other mode
that uses the ETM10 wrapper.

ETM10WMUXINSEL Input Static Configures the wrapper cells into internal test mode.

ETM10WMUXOUTSEL Input Static Configures the wrapper cells in external test mode.

ETM10DFTRESET Input Dynamic Direct control over asynchronous reset during scan mode.

ETM10SCANIN[23:0] Input Dynamic Scan input ports.

ETM10DFTGCKEN Input Static Enables gating of the internal core clocks.

ETM10DFTWCKEN Input Static Enables gating of the wrapper clock to the dedicated test
cells.

ETM10RSTSAFE Input Static Enables the reset to the core.

ETM10WSCANEN Input Dynamic Scan enable for all dedicated test cells in the wrapper.
HIGH = shift.

SCORETEST Input Static Serialize all of the scan chains (internal and wrapper).

SCANMUX12 Input Static Enables accessibility to 12 separate internal scan chains.

SCANMUX6 Input Static Enables accessibility to 6 separate internal scan chains.

4-10 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Design for Test

Table 4-3 ETM10 boundary-scan test signals (continued)

Signal name Direction Type Description

ETM10WSCANIN[1:0] Input Dynamic Input ports for the wrapper scan chains.

WMUX2 Input Static Enables accessibility to 2 separate wrapper scan chains.

ETM10SCANOUT[23:0] Output Dynamic Scan output ports.

ETM10WSCANOUT[1:0] Output Dynamic Output ports for the wrapper scan chains.

4.4.1 Selecting a test mode

You use the wrapper control signals to select the wrapper mode, as shown in Table 4-4.

Table 4-4 Test mode selection

Mode ETM10WMUXINSEL ETM10WMUXSELOUT

Internal test mode HIGH LOW

External test Mode LOW HIGH

Functional Mode LOW LOW

Safe mode

There is safe state logic on:

• all dedicated output wrapper cells
• all reset-dedicated wrapper cells.

During the internal test, ETM10SAFE can be asserted so that the values at the output
of the core are held in a steady state.

To enable the reset of the ETM10 during external test mode, the ETM10RSTSAFE
signal must be asserted. If the state of the core is to be frozen (for example, for IDDQ
testing), this signal must be disabled along with the clock enable signals after set up of
the core, to hold the state.

ARM DDI 0206B Copyright © 2001, 2003 ARM Limited. All rights reserved. 4-11
Design for Test

4.4.2 Internal test mode

The ETM10 test signals for internal test mode are shown in Table 4-5. You can create
a test control module to control the states of these signals.

Table 4-5 Test signals in serial core test mode

ETM10 Test Pins Connection

ETM10SCANMODE 1

ETM10DFTGCKEN 1

ETM10DFTWCKEN 1

ETM10SCANEN Connect to an external pin

ETM10WSCANEN Connect to an external pin

ETM10DFTRESET Connect to an external pin

ETM10WMUXINSEL 1

ETM10WMUXOUTSEL 0

ETM10SAFE 1 (recommended)

ETM10RSTSAFE 0

SCANIN Connect to external pins

ETM10SCANOUT Connect to external pins

4.4.3 External test mode example

The ETM10 test signals for external test mode are shown in Table 4-6.

Table 4-6 Test signals in external test mode

ETM10 Test Pins Connection

ETM10SCANMODE 1

ETM10DFTGCKEN 0 (recommended)

ETM10DFTWCKEN 1

ETM10SCANEN 0 (recommended)

ETM10WSCANEN Connected to a pin

4-12 Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Design for Test

Table 4-6 Test signals in external test mode (continued)

ETM10 Test Pins Connection

ETM10DFTRESET Connected to a pin if

ETM10RSTSAFE disabled

ETM10MUXINSEL 0

ETM10MUXOUTSEL 1

ETM10SAFE 0 (1 recommended during shift)

ETM10RSTSAFE 1 (recommended except for IDDQ

setup)

SCANIN 0

ETM10SCANOUT Not needed

ETM10WSCANOUT Connected to a pin or another scan

chain

WSCANIN Connected to a pin

4.4.4 Serial core test mode

The serial core test (SCORETEST) mode is enabled by the SCORETEST signal. In
this mode, all the scan chains are connected serially, with the wrapper chain attached
last in the ETM10 module. The last cell in the wrapper chain is a lock-up latch, enabling
this output to be connected to another clock domain and retain safe shift properties. This
means that values can be shifted from one scan cell to the next with no risk of error due
to clock skew. You must ensure that the chain shifts safely. ETM10WCLK must be in
the same phase as GCLK during serial core test mode. Capture cycles cannot occur
safely if there are delay differences between the clock domains.

The ETM10 serial scan chain does cross clock domains in serial core test mode.
Lock-up latches are placed wherever the serial scan chain crosses clock domains to
allow safe shift.

4.4.5 Functional mode

The states of the ETM10 test signals when the ETM is in functional mode are shown in
Table 4-7.

Table 4-7 Test signals in functional mode

ETM10 Test Pins Connection

ETM10SCANMODE 0

ETM10DFTGCKEN 1

ETM10DFTWCKEN 0 (recommended)

ETM10SCANEN 0

ETM10WSCANEN 0

ETM10DFTRESET 0 (recommended)

ETM10MUXINSEL 0

ETM10MUXOUTSEL 0

ETM10SAFE 0

ETM10RSTSAFE 0

SCANIN 0 (recommended)

ETM10SCANOUT Gated 0 (recommended)

4.5 Clocks and gating

The clock gating signals are ETM10DFTGCKEN and ETM10DFTWCKEN. These
signals enable the gating of:
• the ETM10 core clock (GCLK)
• the ETM10 wrapper clock(ETM10WCLK)
• both.

While the clock gating signals are enabled, GCLK and ETM10WCLK are enabled.

Note
During functional mode, ETM10DFTGCKEN must be enabled. You are advised to
disable ETM10DFTWCKEN.

If gating of the TCK signal is necessary, this must be done external to the ETM10 core.

The ETM10 patterns are created with GCLK and TCK driven separately. These two
clock domains are not delay-matched, and the ETM10 scan patterns do not allow these
clocks to toggle simultaneously during a capture cycle. The ETM10 wrapper clock
(ETM10WCLK) is 180 degrees out of phase with GCLK during production scan
mode, as shown in Figure 4-4. This prevents hold-timing issues, because GCLK and
ETM10WCLK are not perfectly delay matched within the ETM10.

ETM10WCLK can be created by inverting GCLK, but the timing from the package
pins to the ports of these two signals on the ETM10 must be closely delay-matched.

T1 T2 T3 T4 T5

GCLK

TCLK

ETM10WCLK

Figure 4-4 ETM10 production-scan mode clocking requirements

4.5.1 Clocking in serial core test mode

In SCORETEST mode, all scan enables must remain enabled. All clocks are coincident
(see Figure 4-5). For more information about SCORETEST mode, see Serial core test
mode on page 4-13.

T1 T2 T3 T4 T5

GCLK

TCLK

ETM10WCLK

Figure 4-5 ETM10 serial core test clocking requirements

This chapter contains implementation-specific information relating to the ETM10. It

contains the following sections:
• ETM architecture version on page 5-2
• Precise TraceEnable events on page 5-3
• Parallel instruction execution on page 5-4
• Independent load/store unit on page 5-5
• The FIFOFULL level register on page 5-7
• Context ID tracing on page 5-8.

5.1 ETM architecture version

ETM10 (Rev 0) implements version 2.0 of the ETM architecture (ETMv2.0).

5.1.1 ETM ID register

Table 5-1 shows the value of the fields when reading the ETM ID register (0x79).

Table 5-1 ETM ID register fields for ETM10 (Rev 0)

Bit
Value Meaning
numbers

[31:24] 0x41 Implementor = A (ARM Limited)

[23:16] 0000 Reserved

[15:12] b0010 ARM core = ARM10

[11:8] b0001 Major ETM architecture version number = 2

[7:4] 0000 Minor ETM architecture version number = 0

[3:1] 0000 Implementation-defined

5.2 Precise TraceEnable events

The Embedded Trace Macrocell Specification states that TraceEnable is imprecise
under certain conditions, with some implementation-defined exceptions. Selection of
the following resources by the enabling event does not cause TraceEnable to be
imprecise, provided that those resources are themselves precise:
• single address comparators
• address range comparators
• context ID comparators.

5.3 Parallel instruction execution

ARM10 supports branch folding, where correctly predicted branches are executed in
parallel with the following instruction. The ETM is therefore capable of tracing two
instructions per cycle, although only the second can have data associated with it.

While the trace start/stop block is calculated for each instruction as required, the ETM
is not capable of tracing one instruction without the other. In particular, if a folded
branch is traced, the instruction it is paired with is also traced, along with any data
associated with it if ViewData is active.

5.4 Independent load/store unit

ARM10 has an independent load/store unit. This means that it is capable of continuing
to transfer data values for an earlier instruction after later instructions have been
executed. In these circumstances, the later instructions are said to have executed
underneath the data instruction. Once a data instruction has been traced, all instructions
executed underneath it are also traced.

Note
This does not create any extra data, because the instructions executed underneath
cannot be data instructions or indirect branches.

All address comparators have a sticky bit that is observed when the comparator is used
as shown in Table 5-2.

Table 5-2 Conditions for observing address comparator sticky bits

Single address Address range

Comparator usage
comparator comparator

Selected as an event Sticky bit ignored Sticky bit observed

Selected by Sticky bit ignored Sticky bit ignored

TraceEnable

Selected by start/stop Sticky bit ignored Sticky bit ignored

block

Selected by ViewData Sticky bit observed Sticky bit observed

Where it is observed, the sticky bit behaves as follows:

Sticky bit set When the comparator matches the instruction address of a data
instruction.

Sticky bit cleared When the data instruction completes.

The sticky bit is never set for address comparators configured for data addresses.

Where observed, the comparator continues to match while the sticky bit is set.

Single address comparators cannot observe the sticky bit when selected as an event,
because they are defined to be active for only one cycle for the benefit of the counters
and sequencer. If an event of the kind instruction address = X AND data address = Y
is required, the instruction address comparator must be an address range comparator to
guarantee that it will still match when the data address comparator matches.

ViewData always observes the sticky bits so that if an instruction address comparator
is selected, all the data corresponding to that instruction will match. In normal
circumstances, you must not use single instruction address comparators as the enabling
event, because they do not observe the sticky bit.

There is no need for TraceEnable or the start/stop block to observe the sticky bit,
because when a data instruction has been traced, tracing cannot be disabled until all data
transfers corresponding to that instruction have occurred.

Note
Using data values to create an event, such as a sequencer transition, might result in
out-of-order events occurring because the load data might be returned out of order. If
you are concerned that the ARM10 nonblocking cache might affect programmed
events, you can disable it in the core by writing to bit 21 of the cp15 configuration
register (r1). See the appropriate ARM10 Technical Reference Manual for more
information.

5.5 The FIFOFULL level register

The FIFOFULL level register is read-only for ETM10 and is not used for FIFOFULL
assertion. It is used only to specify the FIFO size on ETM10. FIFOFULL assertion for
ETM10 is described in The FIFOFULL stall signal on page 3-10.

5.6 Context ID tracing

The ETM detects the MCR instruction that changes the context ID and traces the
appropriate number of bytes as a context ID packet instead of a normal data packet. As
a result, if context ID tracing is enabled, an MCR instruction that changes the context ID
does not have its data traced separately.

This chapter describes software issues relating to the ETM10. It contains the following
sections:
• About tracing dynamically-loaded code on page 6-2
• Software support for context ID on page 6-3
• Hardware support for context ID on page 6-4.

6.1 About tracing dynamically-loaded code

When a debugger is debugging a system, it communicates mainly in terms of accesses
to addresses in memory or virtual memory. It must translate between these addresses
and the locations in the code images loaded on the system. This enables the debugger
to present a symbolic or source-level view of the code running on the system to the user.

In a simple statically-linked and loaded system, a single image is run that describes the
mapping between target addresses as image locations. To perform the debugging, the
debugger requires only the name of the code image. However, many systems, including
operating systems such as Windows CE, Linux, or EPOC32, load part or all of their
software dynamically. This can have a number of effects:

• the address at which an image is loaded might not be known until it is loaded

• at different times different images might be loaded at the same address

• in a complex system the debugger might not know what images are candidates to
be loaded until they are loaded.

To debug systems like these, the debugger must be able to interrogate the target, to
determine what images are loaded and where they are loaded from.

The problem is more complex when using trace, because trace data is historical
information. Any embedded trace solution requires an image of the code that was
executed to be available to the trace decompression software of the debugger, otherwise
the debugger cannot decode the trace.

The compression algorithm used for trace conserves data bandwidth by broadcasting
only the minimum of address information. This means that, given a (compressed)
address issued by the trace port, the tools must be able to know what instructions are at
and around that point. This enables the target address of direct branches (B and BL
instructions in the case of code in ARM state) to be inferred. This is difficult with, for
example, virtual memory and software paging, because the debugger is unlikely to
know where the code is executed from.

To resolve this problem, ETM10 uses context IDs. These require both software and
hardware support, as described in:
• Software support for context ID on page 6-3
• Hardware support for context ID on page 6-4.

6.2 Software support for context ID

When the operating system switches between binary images, or virtual memory spaces,
it must update the value in the context ID register, which is part of coprocessor 15. The
debugger must have access to a mapping file specifying the context ID that correlates
to each binary image. With this information, the debugger can then associate each
binary image with the correct part of the trace.

6.3 Hardware support for context ID

ETM10 outputs the variable-length context ID value whenever trace is enabled, and as
part of the periodic synchronization packet. This enables the current context ID value
to be passed to the debugger. You can also filter out unwanted trace based on the current
context ID using programmable trigger resources (see the Embedded Trace Macrocell
Specification).

To support tracing when only a partial binary image is available, the ETM10
compression protocol maintains synchronization even as the ETM branches into
unknown code regions. Trace is decompressable again immediately after jumping back
into a region for which the code image is available.

This chapter contains some signal guidelines that can ensure correct operation of the
ETM and trace tools. It contains the following sections:
• About trace port signal quality on page 7-2
• ASIC pad selection, placement, and package type on page 7-3
• PCB design guidelines on page 7-4
• EMI compliance on page 7-8
• Further references on page 7-9.

7.1 About trace port signal quality

Guaranteed operation of the TPA depends on correct design of the ASIC and of the
target PCB.

When integrating an ETM into an ASIC, the quality and timing of the trace port signals
to the TPA are critical for reliable operation. Some of the issues to consider are:
• output pad selection
• PCB track lengths
• PCB track termination
• setup and hold times for the trace data signals with respect to TRACECLK.

The importance of these issues is directly proportional to the operating frequency. At

trace port frequencies greater than 100MHz, careful SPICE analysis of the system
including the characteristics of the package and the chosen Trace Port Analyzer is
recommended.

7.2 ASIC pad selection, placement, and package type

The position and type of ASIC pad that you select depends on the following factors:
• the ability to minimize the noise and coupling between trace and other signals
• the ability to drive the external load.

The quality of the TRACECLK signal, as observed by the TPA, has the greatest effect
on the reliability of the system. It is vital that TRACECLK transitions move cleanly
through the threshold region of the input circuitry of the TPA, without glitches or
ringing.

With certain types of package and pin placement (for example, pads on the corner or the
edge of a package), the signal coupling between the trace data signals and the trace
clock can be significant. If this problem is encountered during simulations, place GND
or static I/O signals on both sides of the TRACECLK signal.

The quality of the package, and specifically the presence or absence of a ground plane
in the package, can significantly affect the quality of the output signal. In general, ASIC
pads are specified in terms of current drive and signal slew rate. For calculating the PCB
signal quality you are likely to also have to determine:
• the signal rise and fall times
• the pad output impedance.
Note
Matched impedance output pads give a significantly improved performance.

You must also consider the pad placement, to ensure that the PCB tracking to the trace
port connector is possible. You are recommended to place the pads so that they are:
• on the outside of the package
• grouped together
• in the same order as the connector.

7.3 PCB design guidelines

Two implementations are possible:

A dedicated trace port

The TPA is the only load on the trace port signals. See Dedicated
trace port.

A shared trace port

The trace pins are shared with other functions, and therefore there
are stubs on the PCB tracks of the development board and an
increased load on the output driver. See Shared trace port on
page 7-6.

7.3.1 Dedicated trace port

This is the preferred implementation for connecting a TPA to a trace port. The TPA is
the only load on the nodes connected to target ASIC pins, so the only factor affecting
operation is signal integrity at the TPA connector.

If you know the characteristics of your PCB tracks, use the actual trace impedance and
propagation delay. If you do not have access to this information, use the following
guidelines for microstrip (track on outer layer over a ground plane) on FR4 PCB:

• Propagation speed is typically 160ps/inch (approximately 63ps/cm).

• The impedance of a 0.005-inch (0.013 cm) wide track as a microstrip is between

70Ω to 75Ω on a typical six-layer foil construction board. The impedance of a
track reduces as the width of the track increases.

To design the target system effectively, you must know:

• the characteristic impedance and signal edge rates of the ETM output drivers

• the actual setup and hold provided by the ASIC ETM outputs with reference to
the ETM TRACECLK.

If you do not know the characteristics of the signals from your ASIC, consult your ASIC
vendor. It is difficult to provide any general rule because ETM output drivers and
timings vary between ASIC vendors.

PCB track length

You must match all TRACECLK, PIPESTATA[3:0], and TRACEPKTA[15:0]

track lengths between the ASIC and the trace port connector within 100ps. If you are
implementing a demultiplexed port, PIPESTATB and TRACEPKTB must match as
well. Overall differences in track lengths directly impact setup and hold requirements
as follows:

• if the clock is delayed compared to the data, you must increase the setup
specification by the additional clock delay

• if any data is delayed compared to the clock, you must add the delay to the setup
requirement

• if data paths are such that data has both greater than and less than delays compared
with the clock, you must add the difference to both the setup and hold
specification.

Signal quality

The primary variable that characterizes signal quality is the rise time of a signal
compared to its propagation time. It is this relationship that affects the track length, and
this is where the minimum signal rise and fall time becomes important.

To ensure accurate data acquisition, you must minimize all reflections, overshoot, and
undershoot. Aim to keep the one-way propagation time for all tracks at less than one
third of the signal rise time.

As the fabrication process for your ASIC improves, your output driver is likely to
improve and your rise and fall times are likely to decrease. If you cannot keep the
propagation time for all tracks below one third of the signal rise time, some form of
signal termination is required. This can be either of the following:

Series termination Place the series resistor as close as possible to the ASIC pin,
ideally within half an inch (1.27 cm). The value of this series
resistor plus the output impedance of the signal driver must
closely match the impedance of the PCB track. This is the
recommended method.

Parallel or matched AC termination

If you cannot use series termination, add parallel or matched AC
termination on each signal track at the TPA target header. This
requires significantly more power from the ASIC, and the AC
termination must closely match the frequency and rise time of the
terminated signal. In practice therefore, parallel termination is
rarely possible.

If the total track length is equivalent to one rise time propagation delay or greater,
follow standard high-speed design practices to minimize cross talk between the clock
and the data signals. (The total track length is the target PCB track length plus any PCB
track on the TPA buffer board.)

Note
ASIC output pads with an output impedance that is matched to the PCB track might be
available from your ASIC vendor. If these are used, the signal quality of the trace port
signals is significantly improved.

7.3.2 Shared trace port

Some applications might not have enough pins available for trace, so you might have to
multiplex trace signals with other functions. This has the effect of increasing the load
on the trace signals, unless a specific trace-only development board is built.

When an ETM output pin is multiplexed with other functions, the addition of the TPA
target header can add a stub to the PCB track on the target system. It is important to
minimize the effect of the TPA target header on non TPA-based signal usage and
maintain the integrity of the trace measurements. The following constraints apply:

Signal does not require termination in normal operation or is parallel-terminated

This means that a full voltage swing signal travels down the track.
Ensure that the propagation delay of the stub added for the TPA
target header is 20 per cent or less of the overall rise and fall time
of the signal.

Signal is series terminated for normal operation

This means that a one-half voltage swing signal begins each
transition on the track and propagates down the track until it is
terminated at the target node. This case is potentially very
problematic. The one-half voltage swing signal can maintain the
TPA input at its threshold voltage for longer than the required rise
and fall time. To prevent this, you must move the TPA target
header to within one fifth of the rise time of the target end of the
track. If this is not possible, you must slow down the rise and fall
times until this requirement can be met.
Sometimes, board layout constraints make it impossible to keep
the stubs to the trace target header to less than 20 per cent of the
rise and fall time. If length and speed requirements do not allow
the rise and fall times to be increased to meet the design

requirements in this case, you can adjust the thresholds used by

the TPA or LA, if supported. The target system must be able to
provide:
• sufficient noise margin around an altered threshold
• sufficient setup and hold times because these will now be
reduced.
Note
It is unlikely that any TPA supplier will guarantee support for this
mode of operation.

7.4 EMI compliance

The trace port does not affect your EMI compliance testing because the trace port pins
are active only when the Trace Debug Tools are connected to the target. It might be
useful to carry out some testing with the trace port enabled, to determine the effect of
trace port switching on overall system noise.

7.5 Further references

Many TPA vendors provide models for download from the internet. These models
enable you to use SPICE-like tools to analyze the signal integrity at the point that it is
sampled by the TPA or Logic Analyzer:

Agilent The Agilent web site enables you to download data on their TPA and LA
products. You can use the search engine on the web site to look for pages
and documents that refer to ETM. For example, the document Trace Port
Analysis for ARM ETM (Agilent document number E5903-97002)
contains equivalent models for Agilent TPA and Logic Analyzer
products.

Tektronix The Tektronix web site has a number of documents relating to the use of
their Logic Analyzers for acquiring trace. For example, the document
P6434 Mass Termination Probe (Tektronix document number
070-9793-02) provides models for the equivalent load of the Logic
Analyzer probe.

Other vendors
Details about TPA vendors are added to this document as they become
known to ARM. You can also contact your chosen vendor directly for the
latest information.

This appendix describes the signals used in ETM10. It contains the following sections:
• Functional signals on page A-2
• DFT signals on page A-5.

A.1 Functional signals

Table A-1 describes the functional ETM10 signals.

Table A-1 ETM10 functional signals

Signal name Type Description

ARMTDO Input The TDO output signal from an external scan chain.

CLKDIVTWOEN Output If HIGH, indicates that the ETM10 is in half-rate clocking

mode.

DBGACK Input The debug acknowledge signal driven by the ARM

macrocell. When HIGH this signal indicates that the ARM
is in debug state.

DBGRQ Output Debug request. You can use this signal to stop the ARM
processor.

ETMCORECTL[23:0] Input Miscellaneous control signal inputs from the ARM1020E

core (see Table 3-3 on page 3-6).

ETMDA[31:0] Input The ARM1020E data address bus.

ETMDATA[63:0] Input The load, store, and coprocessor data from the ARM1020E
core.

ETMDATAVALID[1:0]] Input Valid signal for ETMDATA bus (one bit for each for high
and low word).

ETMEN Output This output is HIGH when the debugger has enabled the
ETM.

ETMIA[31:1] Input The ARM1020E instruction fetch address bus.

ETMR15BP[31:1] Input The instruction address for branch phantom instructions.

ETMR15EX[31:1] Input The instruction address for all non branch phantom
instructions.

EXTIN[3:0] Input General-purpose external inputs to the ETM, controlling

tracing and other resources.

EXTOUT[3:0] Output External outputs from the ETM. Can be used to trigger
hardware inside the ASIC, or external equipment such as a
logic analyzer.

Table A-1 ETM10 functional signals (continued)

Signal name Type Description

FIFOFULL Output Can be used to stall the ARM1020E core and prevent the
ETM FIFO from overflowing in most circumstances. See
The FIFOFULL stall signal on page 3-10 for more
information.

GCLK Input The same clock that is used by the ARM1020E core. Used
to time most of the operations in the ETM10. GCLK is
gated internal to ETM10 to be disabled whenever
PWRDOWN is asserted.

NRESET Input Power-on reset signal. Resets the ETM10 context ID

shadow register.

NTRST Input Active LOW JTAG reset. Used to reset everything in

ETM10 except the context ID shadow register.

PIPESTATA[3:0] Output Indicates the pipeline status of the ARM1020E core. Used
in both normal and demultiplexed ports.

PIPESTATB[3:0] Output Indicates the pipeline status of the ARM1020E core. Used
in demultiplexed ports only.

PORTMODE[1:0] Output Indicates whether the trace port has been configured in the
normal or demultiplexed configuration.

PORTSIZE[1:0] Output Indicates the currently selected port size in use on the
TRACEPKTA and TRACEPKTB buses.

PWRDOWN Output When HIGH, indicates that the ETM10 is powered down.

SYSOPT[8:0] Input Indicates to the debug tools the system options that have
been implemented. Bits are tied HIGH or LOW, as
appropriate, as part of the integration process.

TCK Input Test clock.

TDI Input Test data input.

TDO Output Test data output.

TMS Input Test mode select.

TRACECLK Output Trace port clock used by TPA device to sample trace port
outputs.

Table A-1 ETM10 functional signals (continued)

Signal name Type Description

TRACEPKTA[15:0] Output Trace packet port used in both normal and demultiplexed
ports.

TRACEPKTB[15:0] Output Trace packet port used in demultiplexed ports only.

TRIGGER Output Single bit indication that a trigger has occurred in the ETM.
TPA devices do not require this signal because triggers are
usually indicated by the TR PIPESTAT value on the trace
port. However, ASIC logic can make use of this signal for
a glueless indication that a trigger has occurred.

A.2 DFT signals

Table A-2 describes the ETM10 DFT signals.

Table A-2 ETM10 boundary-scan test signals

Signal name Direction Type Description

ETM10WCLK Input Dynamic Wrapper clock for dedicated wrapper cells.

ETM10SCANMODE Input Static Puts the device into scan mode.

ETM10SCANEN Input Dynamic Scan enable for all internal clock domains. HIGH = shift.

ETM10SAFE Input Static Forces safe values onto the outputs of the core. Use during
core test and during the shift sequence of any other mode that
uses the ETM10 wrapper.

ETM10WMUXINSEL Input Static Configures the wrapper cells into core test mode.

ETM10WMUXOUTSEL Input Static Configures the wrapper cells in external test mode.

ETM10DFTRESET Input Dynamic Direct control over asynchronous reset during scan mode.

ETM10SCANIN[23:0] Input Dynamic Scan input ports.

ETM10DFTGCKEN Input Static Enables gating of the internal core clocks.

ETM10DFTWCKEN Input Static Enables gating of the wrapper clock to the dedicated test cells.

ETM10RSTSAFE Input Static Enables the Reset to the core.

ETM10WSCANEN Input Dynamic Scan enable for all dedicated test cells in the wrapper. HIGH
= shift.

SCORETEST Input Static Serialize all of the scan chains (internal and wrapper).

SCANMUX12 Input Static Enables accessibility to 12 separate internal scan chains.

SCANMUX6 Input Static Enables accessibility to 6 separate internal scan chains.

ETM10WSCANIN[1:0] Input Dynamic Input ports for the wrapper scan chains.

WMUX2 Input Static Enables accessibility to 2 separate wrapper scan chains.

ETM10SCANOUT[23:0] Output Dynamic Scan output ports.

ETM10WSCANOUT[1:0] Output Dynamic Output ports for the wrapper scan chains.

This glossary describes some of the terms used in this manual. Where terms can have
several meanings, the meaning presented here is intended.

Abort A mechanism that indicates to a core that it must halt execution of an attempted illegal
memory access. An abort can be caused by the external or internal memory system as a
result of attempting to access invalid instruction or data memory. An abort is classified
as either a Prefetch Abort, a Data Abort, or an External Abort.
Application Specific Integrated Circuit (ASIC)
An integrated circuit that is designed to perform a specific application function. It can
be custom-built or mass-produced.
ASIC See Application Specific Integrated Circuit.
ATPG See Automatic Test Pattern Generation.
Automatic Test Pattern Generation (ATPG)
The process of automatically generating manufacturing test vectors for an ASIC design,
using a specialized software tool.
Branch folding Branch folding is a technique where, on the prediction of most branches, the branch
instruction is completely removed from the instruction stream presented to the
execution pipeline. Branch folding can significantly improve the performance of
branches, taking the CPI for branches below one.

Branch phantom The condition codes of a predicted taken branch.

Clock gating Gating a clock signal for a macrocell with a control signal such as PWRDOWN and
using the modified clock that results to control the operating state of the macrocell.
Context The environment that each process operates in for a multitasking operating system. In
ARM processors, this is limited to mean the Physical Address range that it can access
in memory and the associated memory access permissions.

2 (Complex) A boolean combination of simple events that is used by an ETM to control

aspects of a trace.
Fast context switch In a multitasking system, the point at which the time-slice allocated to one process stops
and the one for the next process starts. If processes are switched often enough, they can
appear to a user to be running in parallel, as well as being able to respond quicker to
external events that might affect them.

In ARM processors, a fast context switch is caused by the selection of a non-zero PID
value to switch the context to that of the next process. A fast context switch causes each
Virtual Address for a memory access, generated by the ARM processor, to produce a
Modified Virtual Address which is sent to the rest of the memory system to be used in

place of a normal Virtual Address. For some cache control operations Virtual Addresses
are passed to the memory system as data. In these cases no address modification takes
place.

Trace Port Analyzer (TPA)

A hardware device that captures trace information output on a trace port. This can be a
low-cost product designed specifically for trace acquisition, or a logic analyzer.

A ETM internal 3-12 Design for Test. see DFT

Configuration, ETM 1-3 DFT 4-1
Address Connection guide 3-2 clocks and gating 4-3
buses 3-5 Context ID modes 4-2
comparators 5-5 tracing 5-8 ports 4-10
ARMTDO A-2 values 3-9 scan chains 4-2, 4-4
ARM10 processor Control inputs 3-5 test modes 4-10
connecting to 3-2 Control signals (SYSOPT bus) 3-10 test wrapper 4-6
interfacing to 3-4 Conventions Dual-processor, tracing 3-18
Asynchronous TCK 3-24 numerical xiii Dynamically-loaded code, tracing 6-2
signal naming xii
timing diagram xii
B typographical xi E
Block diagram, ETM10 1-2 EMI compliance 7-8
Branch folding 5-4, Glossary-1 D ETMCORECTL 3-5, A-2
ETMDA 3-5, A-2
Datapath inputs 3-4 ETMDATA 3-4, A-2
C DBGACK 3-8, A-2 ETMDATAVALID 3-5, A-2
DBGRQ 3-8, A-2 ETMEN 3-18, A-2
CLKDIVTWOEN 3-21, A-2 DBGRQ inputs, combining 3-8 ETMIA 3-5, A-2
Clocks Dedicated trace port 7-4 ETMR15BP 3-5, A-2
DFT 4-3 Demultiplexed trace port 3-22 ETMR15EX 3-5

ETM10 Multiprocessor TAP structure 3-15 DBGACK 3-8, A-2

configuration 1-3 DBGRQ 3-8, A-2
connecting to ARM10 3-2 DFT 4-10
functional signals A-2–A-4 N ETMCORECTL 3-5, A-2
ID register 5-2 ETMDA 3-5, A-2
programming 2-2 Normal trace port 3-21 ETMDATA 3-4, A-2
registers 2-3 NRESET 3-12, A-3 ETMDATAVALID 3-5, A-2
External scan chain 3-14 NTRST 3-12, A-3 ETMEN 3-18, A-2
External test mode 4-12 Numerical conventions xiii ETMIA 3-5, A-2
EXTIN A-2 ETMR15BP 3-5, A-2
EXTOUT A-2 ETMR15EX 3-5
O EXTIN A-2
EXTOUT A-2
F Operating modes FIFOFULL 3-10, A-3
demultiplexed 3-22 GCLK 3-12, A-3
FIFOFULL 3-10, A-3 normal 3-21 NRESET 3-12, A-3
Functional diagram, ETM10 3-3 NTRST 3-12, A-3
Functional mode 4-14 PIPESTATA 3-17, 7-5, A-3
Functional signals, ETM10 A-2–A-4 P PIPESTATB 3-17, 7-5, A-3
PORTMODE A-3
Package type 7-3 PORTSIZE 3-18, A-3
G Pad placement 7-3 PWRDOWN 3-9, A-3
Parallel AC termination 7-5 SYSOPT A-3
GCLK 3-12, A-3 PCB design 7-4 system control 3-10
PCB track length 7-5 TCK A-3
PIPESTATA 3-17, 7-5, A-3 TDI A-3
I PIPESTATB 3-17, 7-5, A-3 TDO A-3
PORTMODE 3-21, A-3 TMS A-3
ID register, ETM10 5-2 PORTSIZE 3-18, A-3 TRACECLK 3-17, 7-5, A-3
Interface PWRDOWN 3-9, A-3 TRACEPKTA 3-17, 7-5, A-4
ARM10 3-4 TRACEPKTB 3-17, 7-5, A-4
DFT 3-3, 4-10 TRIGGER A-4
JTAG 2-2 R Single-processor, tracing 3-17
TAP 3-14 Slow clock speed 3-24
trace port 3-17 Resets 3-12 SYSOPT bus 3-10, A-3
Internal test mode 4-12

S T
J
Scan chains 4-2 TAP
JTAG interface 2-2 concatenations 4-4 interface 3-14
Scan chain, external 3-14 reset 3-12
Serial core test mode 4-13 TCK 3-12, 3-24, A-3
M Shared trace port 7-6 TDI A-3
Signal naming conventions xii TDO A-3
Matched AC termination 7-5 Signal quality 7-1 Test
Modes of operation Signals modes 4-10
demultiplexed 3-22 ARMTDO A-2 ports 4-10
normal 3-21 CLKDIVTWOEN 3-21, A-2 wrapper 4-6

Timing diagram conventions xii

TMS A-3
Trace port
dedicated 7-4
demultiplexed 3-22
logic 3-17
normal 3-21
shared 7-6
TRACECLK 3-17, 7-5, A-3
TRACEPKT pins, reusing 3-18
TRACEPKTA 3-17, 7-5, A-4
TRACEPKTB 3-17, 7-5, A-4
Tracing
dual-processor 3-18
dynamically-loaded images 6-2
single-processor 3-17
TRIGGER A-4
Typographical conventions xi

W
Wrapper cells
input 4-6
output 4-7
reset 4-8

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