Computer Architecture

Nguyễn Trí Thành

Information Systems Department
Faculty of Technology
College of Technology
[email protected]

9/12/2010 1
 Fundamentals

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 Boolean
Boolean Algebra
Algebra

9/12/2010 3
Digital Representation

Digital is an abstraction of analog voltage

Voltage is a continuous, physical unit

Typically ranging from 0 to 5 volts on PCs

Digital logic abstracts it to 2 distinct levels
 “1” or positive (typically 2.5 V or greater)
 “0” or negative (typically less than 1 volt)

Eases design and manufacturing

5V 5V 1 1

0V 0V 0 0
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Analog Voltage Waveform Digital Voltage Waveform
Digital Processing

Combine “1”s and “0”s in different ways

To generate more “1”s and “0”s

This is finally what a computer really does

Need a well defined mechanism

Ease design & development of circuits

Boolean Algebra

Mathematical framework for processing “1”s & “0”s

Based on simple, scalable primitive operations
 Easy to realize using basic hardware components

Scales to reason about complex operations

Leads to information processing
 When combined with suitable interpretations
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Axioms of Boolean Algebra

Two Boolean constants

“1” or “true”

“0” or “false”

Boolean variables

An unknown Boolean value

Can be “1” or “0” (but not both at the same time)

Represented using symbols (or alphabets)

Examples: “X”, “A”, “B”, “α”, “β”

3 primary Operators

NOT (unary operator)

AND (Binary operator)


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Truth Table

Tabulates results of operators

Involves n variables

Consists of 2n rows

Each row has a unique combination of “1” and “0” for
the n variables

Used to define result of primary operators

NOT, AND, & OR

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NOT Operator

NOT operator inverts the value of a variable

Given a Boolean variable A

NOT operation is represented as A

NOT is described by the following truth table:

A A
0 1
1 0

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AND Operator

AND operator

Binary operator: Uses 2 operands

Result is a “1” only if both operands are “1”

AND operation is represented as AB or A•B

Where A and B are two Boolean variables

AND is described by the following truth table:

A B A••B
0 0 0
0 1 0
1 0 0
1 1 1
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OR Operator

OR operator

Binary operator: Uses 2 operands

Result is a “1” if any one of the operand is a “1”

OR operation is represented as A+B

Where A and B are two Boolean variables

OR is described by the following truth table:

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
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Exercises

If A=1 and B=0, What is

A+B =

AB =

AA =

B+B =

A=

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Exercises

If A=1001 and B=0111, What is

A+B =

AB =

AA =

B+B =

A=

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Boolean Expression

Combination of operands & operators

Examples

A+A

(A+B)•1

(A•0)+(B•0)

A+B+C+D

A•1+B•1

What is the results of the above expressions if A=1, B=0

Operator precedence

Inner most parentheses

NOT

AND

OR

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Boolean Equations & Truth
Tables

Illustrate Truth Table for A+B•C
A B C B•C A+B•C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
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Laws of Boolean Algebra

For a Boolean variable A

Identity law

A+0=A

A•1=A

Zero and One laws

A+1=1

A•0=0

Inverse laws

A+A=1

A•A=0
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 Laws of Boolean Algebra
(Contd.)

Given Boolean variables A, B, & C

Commutative laws

A+B=B+A

A•B=B•A

Associative laws

A + (B + C) = (A + B) + C

A • (B • C) = (A • B) • C

Distributive laws

A • (B + C) = (A • B) + (A • C)

A+(B • C) = (A+B) • (A+C)

DeMorgan’s laws

(A • B) = A + B

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(A+B) = A • B 16
Verification of Laws (1)

Using Truth Tables

Identity Law

A+0=A

A A+0
0 0
1 1

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Verification of Laws (2)

Distributive law

A • (B + C) = (A • B) + (B • C)

A B C A•(B+C) (A•B)+(B•C)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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More Boolean Operators

Other commonly used Boolean Operators

Convenient when implementing logic operations using
electronic components

NAND

(A•B)

NOR

(A+B)

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English to Logic Conversion

Straightforward strategy

Use common sense

Identify independent clauses

Look for “and” & “or” clauses in sentences

Identify primary inputs

Work logic out for each independent clause

Connect them back together

Optimize the final equation

We will not deal with optimizations in this course

Verify using Truth Table
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Example 1

Output is 1 only if the two primary inputs are
zero

Let the primary inputs be A and B

Output is 1 in the following cases

A=0 & B=0 => A • B

The above equation can be rewritten as:

(A+B)

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Example 2

Output is 1 only if the two primary inputs are
different

Let the inputs be A and B

Output is 1 in the following cases

A=0, B=1 => A•B

A=1, B=0 => A•B

Combining the above two cases gives:

(A•B)+(A•B)

This operation is called Exclusive-OR or XOR
 It is frequently used
 Represented as A + B
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Truth Table for XOR

XOR is a frequently used operation

It is important to remember its operation

A B A+B
0 0 0
0 1 1
1 0 1
1 1 0

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 Digital
Digital Logic
Logic Circuits
Circuits

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 Electronics for Boolean
Algebra

Interconnected set of Transistors called Circuits

Transistors are Electronic Switches

Turn “On” or “Off”
 Depending on input voltages

Used to implement Boolean expressions Transistor

A (A•B)+C

B
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Logic Gates

Developing large circuits is complex

Drawing many transistors is cumbersome

Makes the circuit diagram unwieldy

Hard to illustrate and comprehend

Solution: Logic Gates

Abstract notation for common logic circuits

Functionally similar to set of transistors

Simpler to develop and use

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 Basic Gates

Corresponding to basic operations in Boolean
Algebra

NOT Gate Output
A A

AND Gate Input

Data always flows
A A•B in a unidirectional
B manner from

OR Gate inputs to outputs
A A+B
of the logic gates!
B
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Commonly used Gates

Other commonly used gates

NAND
A (A•B)

NOR The circle (or bubble) indicates inversion

or NOT operation. You may add this
A (A+B) circle (or bubble) at the output or input of
any gate!
B

XOR
A A⊕
⊕B
B
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Equations to Circuits

Convert Boolean equations to Logic Circuits

Logic circuits drawn on paper are often also called
Schematics

Straightforward process

Convert each operator to a Logic Gate

Suitably connect inputs and output

Pay attention to crossing lines versus connected lines

A A A
B B A

No relationship No relationship These two lines/wires

Label all inputs and outputs
between A & B. between A & B. This are the same!
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is preferred!
Example 1
There are a few aspects to consider when using
the shortcut version:

A•B•C•D 1. All gates must be the same

(A•B)•(C•D) 2. Input to output transformation must be
straightforward

A A•B
A
B A•B•C•D B A•B•C•D
C
C
D
D C•D

Standard Version (With 2-input Gates) Shortcut Version (n-Input Gates)

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Example 2

Convert English to logic circuit

Output O is

A, if C=1

B, if C=0

Solution

O = (A•C)+(B•C)

A A•C
O=(A•C)+(B•C)
C
B
B•C

Shortcut for NOT

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General Selection Logic

Develop a circuit to select
1 of the given 5 inputs

Let the inputs be A, B, C, D, S1 S2 S3 O
&E 0 0 0 A

Assign unique combinations 0 0 1 B
of 1s and 0s to identify each
Input 0 1 0 C

Given n inputs you need k 0 1 1 D
bits such that 2k>=n
1 0 0 E

In this case n=5 and
therefore k=3

Let selection variables be
s1, s2, and s3
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General Selection (Cont.)

Boolean equation for the example:

O=(A•S1•S2•S3)+(B•S1•S2•S3)+(C•S1•S2•S3)+(D•S1•S2•S3)+
(E•S1•S2•S3)

S1 S2 S3 O
0 0 0 A
Draw
0 0 1 B the
0 1 0 C circuit?
0 1 1 D
1 0 0 E

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Logic Circuit for Selector
A

C O

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S1 S2 S3 34
Multiplexer (Mux)

Select 1 given N circuits are

called Multiplexers

Have N inputs

K selection lines NxK
N inputs

•••
Multiplexer

Such that 2k >= N

1 output line •••

K select
lines

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De-Multiplexer (DeMux)

Move 1 input bit to selected output line

1 Input

N Output lines

K selection lines K select
lines

Such that 2K>=N

•••

NxK
1 Input N Outputs

•••
De-Multiplexer

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De-Multiplexer Logic Circuit

1 X 4 De-Multiplexer
A•S1•S2

A•S1•S2

A•S1•S2

A•S1•S2

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Timing

Gates take time to work

Outputs don’t stabilize for some time

Stabilization time is usually in nanoseconds

Gate delays compound in circuits

Final output is not ready until all gates are stable

Propagation delay
 Time taken for changes at the input to propagate to
output

Typically, the longest path from input to output

This is often called the “critical path” in a circuit

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Example

A A•B
2ns
B A•B•C•D
2ns
C
2ns
D C•D

Total delay = 4ns

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Timing Diagrams

Illustrate change in inputs & outputs in a

circuit with respect to time

In the form of a graph

Time on X-axis

Selected inputs / outputs on the Y-axis

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Timing Diagram Example
A A•B
2ns
B A•B•C
2ns
C

A.B

A.B.C

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Clocks

Delays require careful timing

Otherwise results will be incorrect or garbled

Particularly when multiple inputs are to be processed

I/O is synchronized using a Clock

Clock is a alternating sequence of 1 and 0

With a given periodicity or frequency
 Frequency = 1/Period

Frequency is determined by the gate delays and circuit
complexity
1

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Clock Example

Clocked I/O

Minimum clock period = 4ns

Maximum Frequency = 1/4ns = 250 MHz
A
2ns A•B•C
Clock 2ns
2ns
B

4 ns

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Triggering

Clocks transitions are used in different ways

Level triggering

When clock is in a given state

Edge triggering

Raising edge triggered
 When the clock is in transition from 0 → 1

Falling edge triggered
 When the clock is in transition from 1 → 0

Rising Falling
edge Clock edge

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Latches

Latches maintain state

Can be set to a specific value

Output of latches does not change even after
Inputs change to 0!

Fundamental units for storage

Building blocks for memory

Latches always store data when the clock is
at a fixed level

Hence they are also called as level triggered
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Set-Reset (SR) Latch
S
Q

Q
R

S R Q
0 0 No change
1 0 1
0 1 0
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Clocked S-R Latch
S Q

Clock /
Enable
Q
R

Latch stores (or changes) value only when clock is

high

Clock must be at logic level 1 to store data in the latch.

Data can be read at any time

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 D-Latch
D Q

Clock /
Enable
Q

Advantages over S-R Latch

Single input to store 1 or 0

Avoid spurious input of S=1 and R=1

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 D-Flip Flop

An edge triggered D-Latch is a D-Flip Flop
D Q
Clock

• Stores data only on raising edge

– Changes at input at other times is ignored
• Suitable clock frequency permits data to be stored only
after inputs have settled
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• Data can be read at any time!
 Abstract Representations
D Q D Q

CK CK

D-Latch D-Flip Flop

(Positive Level Triggered) (Rising Edge Triggered)

D Q D Q

CK CK

D-Latch D-Flip Flop

(Negative Level Triggered) (Falling Edge Triggered)
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Asserted: Terminology

Flip Flops use positive or negative logic

Same concept applies to other devices

In order to ease discussion the term “asserted” is
used

Positive logic
 A “1” triggers the working of the device

Negative logic
 A “0” triggers the working of the device

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Sequential Logic Circuits

Involve one or more memory elements

Output depends on value in memory
element

Typically based on earlier computations or
history

Opposite of combinatory logic circuits
 Also known as Combinatorial logic circuits
 Circuits we have been dealing with so far

Does not include a memory element

Outputs depend purely on primary inputs
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Typical Sequential Circuits

Clocks control timings

Ensure values are not stored when they are
transient

Have to wait for the signals to stabilize

State elements store values between
computations
Memory Combinational Memory Combinational
Elements Logic Elements Logic

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Circuit to read a Bit

Given 4 Flip Flops, develop a logic circuit to

select and read a given Flip Flop.
D Q D Q D Q D Q
CK CK CK CK

4 X 1 Multiplexer

Select Lines Output

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Circuit to write a Bit

Given 4 Flip Flops, develop a logic circuit to
select and change data in a given Flip Flop.
Input D Q
1X4 CK

Clock to trigger one of the D Q

De-
D FFs to store the input bit CK
Mux
D Q
CK
D Q
CK
Select Lines
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Word

A fixed number of D-Flip Flops

Usually powers of 2 (2, 4, 8, 16, 32, 64)

Operate as a single unit

Store/Read n-bits at a time
D0 D1 D2 D3

D Q D Q D Q D Q

CK CK CK CK

Q0 Q1 Q2 Q3
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Reading & Writing Words

A fixed number of D-Flip Flops
I1 I2 I3

DeMux DFF DFF DFF DFF DFF DFF

S0

Mux #1 Mux #2 Mux #3

O1 O2 O3
CLK
9/12/2010 RD 57
(1=Read, 0=Write)
 Random Access Memory
(RAM)

RAM is the common form of main memory that is
used to store data and programs in modern
computers.

It is typically designed as a collection of flip flops
as shown in the previous slide

However fabrication technology is different to
reduce cost and improve transistor densities

Terminology:

Lines that carry input or output data are referred to
as data lines or data bus

The select lines associated with the Mux and
DeMux are called the address bus
 The selection data is called address
 In programming terminology it is called a pointer or a
9/12/2010 58
reference.
 Number
Number Representation
Representation

9/12/2010 59
Its all 1s and 0s!

Computers operate using bits

Everything is ultimately a “1” or a “0”

Mind Bender

If everything is a “1” or a “0” then how does the
computer:

Show and edit video?

Compose and play music?

Display and modify pictures?

Learn and recognize speech?

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Magic of Interpretation

The key is interpretation

Different sequence of 1s and 0s are assumed to
convey different meanings to different devices

Example: What does bits 1011 imply

Letter “A” on the keyboard

A number (11) to the CPU

Color red to the video card

Music note F# to the sound card

Sector number 11 to the hard disk drive

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Standards

Interpretations can be problematic

Different interpretations can lead to confusion

Problems with portability & interoperability

Solution: Standards

Standard ways to represent data

Different data types need different standards
 Integers have different representation versus floating point
numbers
 Numbers have different representation than characters and
strings

Depending on needs
9/12/2010

Efficiency of hardware implementation 62
Integer representation

Several standards are available

Mirrors standard mathematical representation of
numbers for most part

Subdivided into 2 main categories

Unsigned integer representation

Standard binary number representation

Signed integer representation

Sign-bit Magnitude representation

1’s Complement representation

2’s Complement representation
9/12/2010 63
Background on number representation

Number representation are based on

mathematical representation of decimal
numbers

Uses 10 symbols (0 through 9) to represent 10
different values

Uses powers of 10 and a sequence of above
symbols to represent larger values

103 102 101 100

0 3 8 6
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 Think Time
• Standard number conversions
Break 345 into Units, tens, Combine the digits shown
& hundredths place below into a number

10 345 Remainder 102 101 100

10 34  5 3 4 5
3  4
Value=(3*102)+(4*101)+
102 101 100
(5*100) = 300+40+5 =
3 4 5
345
9/12/2010 65
Binary number representation

In Binary system there are only 2 symbols

“1” and “0”

Yields base-2 representation

This enables representation of 2 unique values

Namely 02 = 010 and 12=110 d
 Notice the use of base values for numbers!

Analogous to the decimal system, larger numbers are
represented using sequence of “1”s and “0s”

Each position indicates a specific power of 2

Example binary
22 21 20
number: 1 0 1
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Unsigned Decimal to Unsigned
Binary Conversion

Performed through successive division by 2

Until quotient becomes 1

Writing remainders in reverse order

Example convert 510 to binary
Remainder
2 5
2 2 1

1 0

510 = 1012
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Example 2

Convert 12 to binary
2 12
2 6 0
2 3 0
1 1

1210 = 11002

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Fixed Size Representation

Numbers are represented using a fixed

number of bits

Typically a word is used

A word can be 8, 16, 32, or 64 bits depending on how
a given machine is designed.

Representation mechanism

Convert decimal to binary

Pad binary with leading 0s to fit given word size

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Example

Represent 1210 as a 8-bit binary number

Solution:

Convert 1210 to binary which is 11002

Now 11002 as 8-bit number = 000011002
 Padding 4 leading 0s to make it 8-bits wide

Represent 39 as a 5-bit binary number

Solution:

Convert 3910 to binary which is 1001112
 Cannot fit 6-bits into 5-bits position!

Drop left-most digits as necessary
 Result = 001112
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Binary to Decimal Conversion

Multiply by powers of 2 and add

Powers of 2 increase from left to right!

Example: Convert 1102 to decimal
22 21 20
1 1 0
Decimal = (1*22) + (1*21) + (0*20)
= 4 + 2 + 0 =6
1102 = 610
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Binary to Decimal Conversion
(Example 2)

Example: Convert 110102 to decimal

Value = (1*24)+(1*23)+(0*22)+(1*21)+(0*21)
= 16 + 8 + 0 + 2 + 0
= 26

110102 = 2610

Tip for verification

Even valued binary numbers have 0 at the end

Odd valued binary numbers have 1 at the end
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Table of Values

Decimal (Base-10) Binary (Base-2)

010 02
110 12
210 102
310 112
410 1002
510 1012
610 1102
710 1112
810 10002
910 10012

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Range of numbers

Given a unsigned binary number with K

positions

Minimum number = 0

Maximum number = 2K-1

Example if K = 8

With 8 bits, maximum number = 28-1 = 255

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Octal representation

Octal representation is to the base-8

Uses symbols “0” through “7” to represent 8
different values

Uses sequence of symbols for larger numbers.

Convenient for representation of larger

numbers

Easy to convert between Octal & binary

Requires fewer display places on hardware
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devices 75
Decimal to Octal Conversion

Performed through successive division by 8

Similar in philosophy to other conversions

Until quotient becomes less than 8

Writing remainders in reverse order

Example: Convert 8310 to Octal
8 83
8 10 3

1 2

8310 = 1238
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Octal to Decimal Conversion

Example: Convert 5678 to decimal

Value = (5*82)+(6*81)+(7*80)
= 320 + 48 + 7
= 375

5678 = 37510

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Octal to Binary Conversion

Simply write 3-bit binary representation for

each digit as if it was a decimal digit

3-bits are needed to represent 8 different values (0 to
7) for each digit in the octal representation

In a left to right manner

Example: Convert 1238 to binary

18 = 0012

28 = 0102

38 = 0112


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1238 = 0010100112 78
Binary to Octal Conversion

Organize bits in binary number in sets of 3

From right to left manner

Write decimal value for each set of 3 bits

Range of values will be from 0 to 7

Example: Convert 101100002 to Octal

10 110 000

2 6 0

2608

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Hexadecimal Representation

Hexadecimal (or Hex)

uses Base-16 Dec Hex Dec Hex

Requires 16 symbols for 010 016 810 816
values 0 to 15 110 116 910 916

Uses standard
210 216 1010 A16
numerals for 0 to 9 310 316 1110 B16

Uses A through F for 410 416 1210 C16
values 10 to 15 510 516 1310 D16
610 616 1410 E16
710 716 1510 F16

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Motivation for Hex

Primarily for display purposes

Originally intended for 7-segment displays

Still used in conventional computers for display of

binary information

Such as memory addresses etc.

9/12/2010 81
Decimal to Hex Conversion

Performed through successive division by 16

Similar in philosophy to other conversions

Until quotient becomes less than 16

Writing remainders in reverse order

Example: Convert 73410 to Hex
16 734
16 35 E (1410)

2 D (1310)

73410 = 2DE16
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Hex to Decimal Conversion

Example: Convert A8F16 to decimal

Value = (A*162)+(8*161)+(F*160)
= (10*162)+(8*161)+(15*160)
= 2560 + 128 + 15
= 2703

A8F16 = 270310

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Hexal to Binary Conversion

Simply write 4-bit binary representation for

each digit as if it was a decimal digit

4-bits are needed to represent 16 different values (0 to
F) for each digit in the hexal representation

In a left to right manner

Example: Convert 1C316 to binary

116 = 00012

C16 = 11002

316 = 00112


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1C316 = 0001110000112 84
Binary to Hexal Conversion

Organize bits in binary number in sets of 4

From right to left manner

Write decimal value for each set of 4 bits

Range of values will be from 0 to F

Example: Convert 1001100002 to Hexal

1 0011 0000

1 3 0

13016

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Table of Equivalent Values

Dec. Binary Octal Hexal Dec. Binary Octal Hexal

010 02 08 016 810 10002 108 816
110 12 18 116 910 10012 118 916
210 102 28 216 1010 10102 128 A16
310 112 38 316 1110 10112 138 B16
410 1002 48 416 1210 11002 148 C16
510 1012 58 516 1310 11012 158 D16
610 1102 68 616 1410 11102 168 E16
710 1112 78 716 1510 11112 178 F16
9/12/2010 86
 Binary
Binary Addition
Addition

Computer Architecture

9/12/2010 87
Review of Addition

Addition of decimal numbers

Proceeds from lowest to highest powers

That is from left to right

Each digit is added

If result is below 10, the digit is written as is

If the result is above 9, it is broken into two parts
 Sum: Digit which results from adding the numbers
 Carry: Digit for use in the next higher power column.

9/12/2010 88
Example

Add 7810 with 9910

1 1
0 7 8
+
0 9 9

1 7 7

9/12/2010 89
Binary Addition

Proceeds in a similar A B Cin Sum Cout

fashion as conventional 0 0 0 0 0
addition
0 0 1 1 0

Bits are added from right
to left 0 1 0 1 0

Sum is 1 or 0 0 1 1 0 1

Carry is 1 or 0
1 0 0 1 0

Results from addition of
bits is illustrated in the 1 0 1 0 1
adjacent truth table. 1 1 0 0 1
1 1 1 1 1
9/12/2010 90
Binary Addition: Example 1

Add 10112 to 11012

1 1 1 1
0 1 0 1 1
+
0 1 1 0 1

1 1 0 0 0

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Logic Circuit to add 2 Bits: Half
Adder

Truth table for sum &
carry bits are as A B Sum Cout
follows. 0 0 0 0

Given the truth table 1 0 1 0

Sum = A + B 0 1 1 0

Cout = A • B 1 1 0 1

B
Half Sum = A + B

Adder Carry = A • B

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Logic Circuit to add 3 bits: Full
Adder

Refer to truth table shown earlier

Sum = A + B + C

Carry = (A•B) + (B•C) + (C•A)

A A⊕ B
B Sum
C
FullAB
BC Carry
Adder
CA

9/12/2010 93
Ripple Carry Adder

Several full adder’s can be cascaded to add

multiple-bits!

Circuit reflects the way binary numbers are added

The following circuit adds 2 3-bit binary numbers namely
A2A1A0 and B2B1B0 to yield result C3C2C1C0
A2 A1 A0
FA2 B2 FA1 B1 FA0 B0
0

This bit is typically

called the Overflow bit!
C3 C2 C1 C0
9/12/2010 94
Ripple Carry Adder

To add 2 n-bit numbers you need n Full Adders

First carry to the circuit is 0

A half adder could be used here instead

Each carry-out (except the last) is fed to the carry-in of the

next stage

Note that inputs are organized from lowest to highest power
of 2

Circuit generates n+1 bits as result of addition

Last carry (highest power) is called an overflow bit
 Because it does not fit in n-bits (which is typically what is expected to
happen in these circuits).

If a carry is present in the n+1th bit it is called an overflow
condition!

Microprocessors typically provide a mechanism to detect
9/12/2010 95
overflows!
Unsigned Representations

Unsigned number representations

Binary (base-2)

Octal (base-8)

Hexadecimal (base-16)

Given n bits

Range: 0 to 2n-1 decimal numbers

9/12/2010 96
Need for Signed
Representations

Unsigned representations cannot represent
negative numbers

Such as: -2, -51 etc.

However negative numbers are frequently
used

Need a representation for positive & negative
numbers – that is, signed numbers

9/12/2010 97
Standard Signed
Representations

Signed numbers are represented using 3
different standards

Sign-bit Magnitude (SBM) representation

1’s Complement Representation

2’s Complement Representation

This is the representation that is used by computers
today!

9/12/2010 98
Strategy for Signed
Representation

General strategy is as follows:

All representations assume fixed size

8, 16, 32, or 64 bits operated on as a single unit-word

Given n bits (unsigned range: 0 to 2n-1)

Break the range into two halves

One half represents positive numbers

0 to 2n-1-1 corresponds to positive numbers
 Decimal value: 0 to 2n-1-1

Another half represents negative numbers

2n-1 to 2n-1 corresponds to negative numbers
9/12/2010
 Decimal range: -2n-1 to -1 99
Sign-Bit Magnitude (SBM)
Representation

Uses left-most bit called sign bit to indicate

sign

Sign bit = 0 implies positive number

Sign bit = 1 implies negative number

Example:
27 26 25 24 23 22 21 20
1 0 0 0 1 0 0 1
Sign-bit
Decimal value = -910
9/12/2010 100
SBM Examples (1)

Represent 1010 using 8-bit SBM

Converting to binary: 1010 = 10102

8-bit SBM representation: 000010102

Sign bit is 0 to indicate positive value.

Represent -1510 using 8-bit SBM

Converting to binary: 1510 = 11112

8-bit SBM representation: 100011112

Sign bit is 1 to indicate negative value
9/12/2010 101
SBM Examples (2)

Convert 8-bit SBM 000001012 to Decimal

The sign bit (left most bit) is 0 indicating positive
value

Converting 00001012 to decimal we get 510

000001012 in SBM = 510

Convert 8-bit SBM 100011012 to Decimal

The sign bit (left most bit) is 1 indicating negative
value!

Converting 00011012 to decimal we get 1310


9/12/2010
Result: 100011012 = -1310 102
1’s Complement
Representation

There are a few drawbacks with SBM

There are 2 different representations for zero

+0 (00000000) and -0 (10000000)

Logic circuits for addition and subtraction of binary numbers

are complicated as they have to handle sign bit separately.

1’s Complement Representation

Fixed size representation

Most significant bit is reserved as sign-bit

Positive numbers are represented using standard binary
notation

Negative numbers are represented by inverting all bits in
9/12/2010
the standard binary notation 103
Example of 1’s Complement

Represent 1210 using 8-bit 1’s Complement

Converting to binary: 1210 = 11002

8-bit 1’s complement representation: 000011002

Sign bit is 0 to indicate positive value.

Represent -1310 using 8-bit SBM

Converting to binary: 1310 = 11012

8-bit representation: 000011012

Since original decimal number was negative each
bit in 8-bit representation is inverted!

1s Complement representation = 11110010


9/12/2010 Note: Sign bit becomes 1 to indicate negative value 104
Example of 1’s Complement

Convert 1’s complement 000011112 to decimal

Sign bit is 0 to indicating positive value.

Converting 000011112 to decimal we get 1510

Final result: +1510

Convert 1’s complement 111101012 to decimal

Sign bit is 1 indicating negative value.

First invert all the bits to get: 000010102

Convert above binary to decimal to get 1010

Final result: -1010

9/12/2010 105
1’s Complement

Still has 2 different representations for 0

+0 (00000000) and -0 (11111111)

However, A – A operations can be easily
represented

A – A = A + (-A) = 11111111 (which is effectively
0 in 1’s complement)

9/12/2010 106
2’s Complement

Overcomes the limitations of SBM and 1’s

complement representation!

Fixed size representation

Enables subtraction of numbers via addition!

Also reserves a special sign bit (left most bit)

0 (sign bit) indicates positive numbers

1 (sign bit) indicates negative numbers

Conversion to and from 2’s complement requires
similar steps

Several of them are identical to 1’s complement
9/12/2010 107
Convert Decimal to 2’s
Complement
Signed Decimal
Number
Positive Negative

Invert all the Decimal to

Decimal to n bits n-bit Binary
n-bit Binary

Add 12

9/12/2010 108
2’s Complement Example

Represent +2010 using 8-bit 2’s Complement

Since number is positive simply represent +2010 as a
8-bit binary number!

+2010 = 000101002

Represent -1810 using 8-bit 2’s complement

Since number is negative we need to do 1’s
complement and add 12

Step 1: Convert 1810 to 8-bit binary = 000100102

Step 2: Invert bits = 111011012

Step 3: Add 12 = 111011102

Final result: -1810 = 111011102 in 8-bit 2’s
9/12/2010
complement 109
2’s Complement to Decimal
Binary number in n-bit 2’s complement

Value of Sign-bit (Left most bit)

Sign Bit=0 Sign Bit=1

Binary to decimal
Invert all bits
(positive number)
Add 1

Binary to decimal
(Negative number)
9/12/2010 110
Example

Convert 8-bit 2’s complement to decimal

Case 1: 000010102

Sign bit is 0 indicating positive number

Simply convert binary to decimal to get 1010

Case 2: 111110102

Sign bit is 1 indicating negative number

Step 1: Invert all bits to get 000001012

Step 2: Add 12 to get 000001102

Convert binary to decimal to get -610

9/12/2010
 Note the negative sign on decimal number! 111
Subtraction using 2’s
Complement

Perform 510 – 310 using 4-bit 2’s complement
510 – 310 = 510 + (-310)
510 = 01012 INV
-310 = (00112 →11002 + 12) = 11012
510 + (-310) = 01012 + 11012 = 00102
00102 = 210

9/12/2010 112
Subtraction using 2’s
Complement

Perform 210 – 410 using 4-bit 2’s complement
210 – 410 = 210 + (-410)
210 = 00102 INV
-410 = (01002 →10112 + 12) = 11002
210 + (-410) = 00102 + 11002 = 11102
11102 is 2’s complement result and because
it is negative (sign bit is 1) it needs to be
converted
INV
11102 → 00012 + 12 = 00102 = -210
9/12/2010 113
Subtraction Circuit

Circuit to subtract two 3-bit 2’s complement

numbers

Recollect that subtraction is performed via
addition in 2’s complement representation.

Addition is performed using Full Adder modules

Cascaded together in the form of Ripple Carry Adder

One of the numbers have to be converted to 2’s
complement representation

Invert all the bits

Add 12
9/12/2010 114
Logic Circuit to add 3 bits: Full
Adder

Refer to truth table shown earlier

Sum = A + B + C

Carry = (A•B) + (B•C) + (C•A)

A A+B
B Sum
C
FullAB
BC Carry
Adder
CA

9/12/2010 115
Ripple Carry Adder

Several full adder’s can be cascaded to add

multiple-bits!

Circuit reflects the way binary numbers are added

The following circuit adds 2 3-bit binary numbers namely
A2A1A0 and B2B1B0 to yield result C3C2C1C0
A2 A1 A0
FA2 B2 FA1 B1 FA0 B0
0

What happens this bit is

set to 1 instead of 0?
C3 C2 C1 C0
9/12/2010 116
Subtraction Circuit

A2 A1 A0
FA2 B2 FA1 B1 FA0 B0
1

C2 C1 C0

Each bit is inverted (Step

1 of Converting to 2’s Add 1 to inverted Bn bits
Complement) to generate 2’s
complement!

9/12/2010 117
 Add/Subtract Circuit

Circuit to Add or Subtract two 3-bit 2’s complement
number
The XOR gate inverts the bits
only when control input is 1
B2 B1
B0

A2 A1 A0
FA2 FA1 FA0

C3 C2 C1 C0 Control Input
0 = Add
9/12/2010 118
1 = Subtract
 ALU
ALU &
& CPU
CPU

9/12/2010 119
Introducing ALU

ALU: Arithmetic & Logic Unit

Performs arithmetic operations

Addition

Subtraction

Performs logic operations

AND: A•B

OR: A+B

NOT: A

Desired operation/result is chosen based on a
selection logic.
9/12/2010 120
Exercise

Develop a circuit that S0 S1 S2 Out Cout

accepts 3 inputs (say A, 0 0 0 A•B X
B, and Cin) and
0 0 1 A+B X
generates 2 outputs
(say Out and Cout) 0 1 0 A X
depending on 3 control 0 1 1 B X
inputs S1,S2, and S3 as 1 0 0 A⊕B AB+
shown in the truth table: ⊕ Cin BCin
+
ACin
X = Don’t care (can be 1 or 0)
9/12/2010 121
Solution: 1-bit ALU
S0S1S2
A A•B
B 000
A+B
001

Multiplexer
A Out
010

B
011

Sum
Cin Full Adder 100

S0
This approach can be
S1 extended to include other
S2 operations such as
subtraction.
9/12/2010
Cout 122
n-bit ALU

n-bit ALU

Repeat 1-bit ALU n times

All 1-bit ALUs get the same selection lines

Carry out (Cout)from one stage is wired to carry-in
of next state

Similar to how a ripple carry adder (or subtraction
circuit) is wired

Performs operation on n-bits simultaneously

9/12/2010 123
Example 4-bit ALU
Selection lines simply renamed to
operation code (OPCode) lines

A3 B3 A2 B2 A1 B1 A0 B0

OP0
OP1
OP2

ALU3 ALU2 ALU1 ALU0

Cin Cin Cin Cin

O4 O3 O2 O1 O0 Add/Sub
9/12/2010 124
 ALU Notation

An ALU is denoted using the following graphical
notation.

Operand1 Operand2
(A) (B)
Indicates number of 8 8
bits on each line.
The size of each
operand is typically OP Code Result
the same and 010 A•B
ALU
corresponds to the 110 A+B
word size. 9 210 A
4
310 B
… …
Operation Result
Selection
9/12/2010 (OP Code) 125
Thought Experiment

Where do the inputs to the ALU come from?

The two operands

The operation the ALU needs to perform

Similarly where do the outputs from the ALU
go?

Solution: Registers!

The fundamental storage units.

9/12/2010 126
Registers Revisited

Fixed number of D-Flip Flops to form a Word

Corresponding to size of ALU operands!

Operate as a single unit

Store/Read n-bits at a time
D0 D1 D2 D3

D Q D Q D Q D Q

CK CK CK CK

Q0 Q1 Q2 Q3
9/12/2010 127
 Selecting a Register

Given n Registers how to read data from

This is not aasingle
Mux but a set of 8
specific register? 8 Mux’s all having
Register 1 00
the same selection
8 logic!
Register 2 01 M
U
8
Register 3 10 X

8 8
Register 4 11

2
Set of registers is
called a Register File Register
9/12/2010
Select 128
 Selecting 2 Registers

ALU needs 2 operands to work!

How to select 2 registers from a Register File?

8 8
00 M 00 M
Register 8 U 8
01 01 U
8 X 8 X
File 10 10
8 1 8 2
11 11
2 8 2 8
Register Register
Select 1 Select 2

9/12/2010
Operand1 Operand2
129
ALU with Inputs

Mux2
Register
8
File

Mux1
(4)
8 8

What do we do with
ALU results or output
from
2 the ALU?2
4 8

Results

Operation Operand1 Operand2

9/12/2010 130
ALU Output

Solution: Put it into a register!

OK, so do we do that?

That is, Given 1 input how to route it on n different
paths? 8
Register 1 00

DeMux
8
Register 2 8
01
8 Result from ALU
Register 3 10
8
Register 4 11

2
9/12/2010
Select Inputs 131
Handling ALU Output
A

Mux2
8
Each device has its own Clock
Register 8

DeMux
slection logic typically 8
8
specified using a truth File
B

Mux1
table! 8
8 8 (4)
Flags

ALU
2
2 2
4 8 Operation Result
010 A•B
110 A+B
210 A
Operation Operand1 Operand2 Destination
9/12/2010 132
Data path

The ALU and associated components

constitute the Data Path

Includes Registers, Multiplexers and any other
device associated with ALU operations

All operands are typically the same size

Register sizes match with size of operand

Size of operands are associated with CPU

32-bit processor (ALU uses 32-bit operands)

64-bit processor (ALU uses 64-bit operands)

9/12/2010 133
 ALU Notation

An ALU is denoted using the following graphical
notation.

Operand1 Operand2
(A) (B)
8 8

Indicates number of
bits on each line
ALU
Operation Result
9
010 A•B
4
110 A+B
210 A
Operation Result

9/12/2010 134
 Selecting 2 Registers

ALU needs 2 operands to work!

How to select 2 registers from a Register File?

8 8
00 M 00 M
Register 8 U 8
01 01 U
8 X 8 X
File 10 10
8 1 8 2
11 11
2 8 2 8
Register Register
Select 1 Select 2

9/12/2010
Operand1 Operand2
135
ALU with Inputs

Mux2
Register
8
File

Mux1
(4)
8 8

What do we do with
ALU results or output
from
2 the ALU?2
4 8

Results

Operation Operand1 Operand2

9/12/2010 136
ALU Output

Solution: Put it into a register!

OK, so do we do that?

That is, Given 1 input how to route it on n different
paths? 8
Register 1 00

DeMux
8
Register 2 8
01
8 Result from ALU
Register 3 10
8
Register 4 11

2
9/12/2010
Select Inputs 137
 Handling ALU Output
A

Mux2
Each device has its own
selection logic typically Clock
32 Register

DeMux
specified using a truth table!
(Note that this is not a single
Mux but 8, 4x1 Muxs) File
B

Mux1
8 8 (4)
Flags

ALU
2
2 2
4 8
Operation Result
010 A•B
110 A+B
Operation Operand1 Operand2 Destination
9/12/2010 210 A 138
Data path

The ALU and associated components
constitute the Data Path

Includes Registers, Multiplexers and any other
device associated with ALU operations

All operands are typically the same size

Register sizes match with size of operand

Size of operands are associated with CPU

32-bit processor (ALU uses 32-bit operands)

64-bit processor (ALU uses 64-bit operands)

9/12/2010 139
Handling Constant Values

Earlier data path did not permit initialization of

registers with constant values

Limited constant values could be achieved using
operations supported by ALU.

Even that was pretty convoluted!

Solution: Add instruction to initialize register

With a constant value

Typically, the constant value is embedded as a
part of the instruction.

By reusing as many bits as possible for this task
9/12/2010 140
Implementation Strategy

Fix code for constant value initialization

Have to use a code that is not already used by
ALU

In our case, let’s set it to 1111 for our ALU

If initialization is detected, use constant bits in
instruction to initialize a register.

Need 8-bits to hold constant value for 8-bit CPU
 For this we can reuse register selection input bits to double
up as constant bits in this instruction as we are not using
registers for any operation.

Need 2-bits to select 1 of 4 destination registers
9/12/2010 141
 Handling Constants
AThis Mux chooses between data from registers or

Mux2
the 8 bits from the instruction depending on the
operation. If the operation is to store a constant
Register

DeMux
8 then the ALU8 simply passes the constant bits as
8
its output. The constant bits are then pushed to
File
Bthe DeMux and are finally stored in the register

Mux1
0
Mux 1
8 indicated by destination
(4)
8
Flags
This is not a
ALU special device
4 but just a 4 Where do4 these
8 notation to show bits actually
the lines are
4
4 being combined
come from?

4
9/12/2010 142
Operation Operand1 Operand2 Destination
Where do instructions come from?

The data path uses a set of bits that

constitute an instruction

Where do these instruction bits come from?

Solution: Memory

A large collection of words

Each word consists of 1 or more bytes (8-bits)

Similar in philosophy as a Register File

Manufactured using different technology

Makes it slower
9/12/2010

But a whole lot cheaper! 143
Memory Organization Revisited

Bi-directional Memory Slot 0 D 16

Data lines M E
Memory Slot 1
16 U M
•••
X U
X
Memory Slot n
Read (RD)Note that any memory slot can be read or
written to by providing suitable bit patterns
(or Lines
Selection Addresses) for the selection lines to the
Mux and De-Mux. In other words, memory
slots 8can be Randomly accessed.
Consequently, such memory organizations
Tri-state Buffer: Special device that
are called Random Access Memory (RAM)
disables the line so that the same
wire can be used for reading or
9/12/2010 writing (bi-directional)! 144
Memory-ALU Interconnection

Typically memory is large in size

Gigabytes in size these days

Cannot be packed into the CPU

Cost prohibitive

Memory is manufactured separately

Interconnected with the CPU using Buses

Buses are long wires interconnecting devices
 Particularly ALU Data Path & Memory

Buses for memory
 Address Bus: Selection lines for Mux and De-Mux
9/12/2010  Data Bus: Bits to be written into memory locations. 145
Abstract Notation for Memory
Address Bus carries bits
for Selection lines (Mux &
De-Mux). These bits are
Uni-directional called Addresses!
Address Bus
8 Memory Note the relationship
(RAM) between the Memory
configuration and the
Enable (EN) Size of each Slot
number of lines in the
X Address and Data
Read/Write (RD) Logic Number of Slots Buses.

16
(16 x 256)
Bi-directional
Data Bus

9/12/2010 146
Using Memory

Memory has 3 primary inputs

Address Bus carrying address of memory slot
 Indicates which memory slot to read or write

Data Bus (The actual data bits to be stored or read)

Control signals (Read/Write & Enable)

How to wire these inputs & outputs
We needto
go the ALU
provide Addresses
data path? to the Memory unit in order to
do these operations!

Design requirements
 Need to store output from ALU
 Need to load data from memory into ALU
 Need to load instructions from memory into ALU
9/12/2010 147
Tackling Addresses

Address is used to select a memory slot

For fetching instructions

In an repetitive manner

Typically from consecutive locations
 Think of it as an Array in Java!

Need to somehow generate
// Assume the addresses
each instruction is 16-bits long
 Typically doneshort
usingmemory[256];
some register in the ALU to store
for (int address = 0; (address < 256); address++) {
intermediate results instruction = memory[address];

For reading/writing data at random addresses
process(instruction);
}

Address depends on the instruction at hand
 The instruction typically needs to identify the address to
9/12/2010
read or write. 148
Address Generation Logic Circuit

Issues to consider & solutions

Address needs to be generated by adding 1

Use a ripple carry adder to add

Addresses need to be stored before/after add

Use a register

Need alternate between address for instructions
and address for storing/reading data

Use a multiplexer for choosing

Use a Clock to drive the selection lines of this
multiplexer
9/12/2010  Select address for instruction first (Clock = 0). 149

 Select address for reading/writing data next (Clock = 1).

Catch!

Our data path is not symmetric

Instructions are 16-bits wide

Data or Registers are 8-bits wide

How do we design a memory module that can

Provide 16-bits first

Provide 8-bits next

It is going to take some work

Use the lowest denominator memory module

One than can provide 1 byte at a time
9/12/2010

Assemble bytes together to make instructions 150
 Working with Bytes…
Instruction Address Bus
Data Chip
Enable RD
Byte 1 Byte 2 Byte 3
8

00 01 1X 8 Memory
De-Mux (8 x 256)
Data Bus
S1 S0 1
Instruction Byte Least significant address bit changes between
/ Data Select 0 and 1 for each consecutive address.

When the clock is low (S1=0) the De-Mux places the bytes read from Memory into Byte1
and Byte2 depending on S0 (so S0, the least significant bit from the address bus) which
switches between 0 and 1 when clock is low to fetch two bytes from memory.. When the
clock is high (S1=1), the De-Mux ignores s0 and places the data read from memory into 151
9/12/2010
Byte 3.
Design Considerations

Address needs to be generated to fetch
instructions from memory

Typically one of the registers hardwired to the data path
is reused for this purpose

This register is typically called
 Program Counter
 Instruction Pointer

In the sample data path Reg3 is being used as the
instruction pointer

Using a register eases handling conditional and
unconditional branching in programs

These are used to achieve if and looping constructs in
high level languages

Also used for managing
subprograms/methods/functions in a high level
9/12/2010
languages 152
 Adding Memory to Data path
Register
Latch
8 File (3) *

Mux1
Mux2
Reg3 + R W
8 Flags 8
8
32 110 Address EN RD

0 1 DeMux Bus Memory

Mux

8 A B 8 (8 X 256)
Delay to generate 2 clock
0 1
Mux
pulses from 1. This causes
8 R
Mux
ALU 2 2 0 1 * 110 to be added to Reg3 two
times for each clock pulse.
6 8
8
2 8 Data
4
* W
Bus
OP Code Operand1 Operand2 Destination Data Latch
*
00
DeMux
01 8
9/12/2010 11 153
Branching

Branching is achieved by simply resetting

value in Register R3 with a suitable address

Note that R3 ultimately determines address from
where next instruction is fetched for processing.

Can be achieved in two ways

Load a constant in to R3

Add a different constant (other than 1) in the
address generation circuit.

Assign a new OPCode for this operation, say: 110000

9/12/2010 154
Branching Circuit
8

Temp 8-bit Address Bus

Reg3
8 Reg 8 Adder
8
8
0 110
Clock Mux7 8-bit Constant from
1 8
Multiplier Instruction
2
Sel.
OpCode (1100)
2
Clock Input
Select to add
constant address This circuit adds 110 to the address of next instruction
only when clock is 1 stored in Reg3 normally. However, in a branch instruction,
because until such rather than adding 110 this logic circuits adds a constant
time, the constant value specified in the instruction causing the address for
value is not yet the next instruction to change. The constant can be
sable! positive or negative (2’s comp). Similar approach is used
9/12/2010 155
for conditional branching as well!
Conditional Branching

Branching based on conditions

Used to implement if..then constructs

Constant branch address is added only if some
condition is true

In our case let’s do a simple example involving the
carry flag generated by the ALU

Introduce new OPCode (say 1110)

Change address (in Reg3) only if Carry Flag is 12.

9/12/2010 156
 Conditional Branching Circuit
8

Temp 8-bit Address Bus

Reg3
8 Reg 8 Adder
8
8
0 110
Clock Mux7 8-bit Constant from
1 8
Multiplier Sel.
Instruction
+ Carry Flag (1 bit)
3 OpCode (1110)
1
2
Generates a 1 when OpCode (1100)
2
OPCode=1110 and
CarryFlag = 1 Clock Input
Only when Clock is 1

9/12/2010 157