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Sequence Generator

The document discusses the fundamental structure of a sequence generator which generates a sequence of binary bits using a shift register with combinational logic. An example is provided to design a sequence generator that produces the specific sequence '100010011010111' using 4 flip flops. The sequence generator is also known as a pseudo noise generator and can be used in the transmitter and receiver circuits of a communication system.

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17 views

Sequence Generator

The document discusses the fundamental structure of a sequence generator which generates a sequence of binary bits using a shift register with combinational logic. An example is provided to design a sequence generator that produces the specific sequence '100010011010111' using 4 flip flops. The sequence generator is also known as a pseudo noise generator and can be used in the transmitter and receiver circuits of a communication system.

Uploaded by

smvks2512
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Second Year Digital System Design

Sequence Generator
The fundamental structure of a sequence generator is shown in the figure below:

The sequence generator is a shift register of FIFO (first input first output) with input (I), where
(I) is a combinational logic function of the outputs (N) produced from the flip-flops of the shift
register. The sequence generator generates a sequence of binary bits (information). Thus, the
length of the sequence is related to the number of flip-flops that are required to produce a sequence
generator. The general equation is:
𝑆 ≤ 2% − 1
Where:
S = the length of the repeated sequence.
M = number of the sequence generator’s flip-flops
Note:
If S = 2% − 1, then we have a maximum length of sequence generator.
Example: Design a sequence generator that generates the sequence “100010011010111”
Solution:
Since there is no repeated in the sequence, then;
𝑆 = 15 𝑏𝑖𝑡
𝑆𝑖𝑛𝑐𝑒 𝑆 ≤ 2% − 1
𝑡ℎ𝑒𝑛 15 ≤ 2% − 1
2% ≥ 16

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Second Year Digital System Design

So, (n) is at least = 4, (i.e. four flip-flops are required to design the sequence generator; A, B, C
& D).
Now we write a table to specify the operation of the sequence generator, also to design the logic
circuit that generates the output (I).
Note, if a row in the table is repeated, then we must add another flip-flop to the sequence generator
to remove the repetition case from the table.
D C B A I = f(A, B, C, D) B
1 1 1 1 0 DC A 00 01 11 10
1 1 1 0 0 00 X 0 0 0
1 1 0 0 0 01 1 1 1 1
1 0 0 0 1 11 0 0 0 0
0 0 0 1 0 10 1 1 1 1
0 0 1 0 0
0 1 0 0 1
1 0 0 1 1 I = 𝐶̅ 𝐷 + 𝐶𝐷
7
0 0 1 1 0 =𝐶 ⊕𝐷
0 1 1 0 1
1 1 0 1 0
1 0 1 0 1
0 1 0 1 1
1 0 1 1 1
0 1 1 1 1
1 1 1 1 0 Repeated
1 1 1 0 0
1 1 0 0 0
The sequence generator logic circuit must be protected from the reset state (0000) by adding two
logic gates to the circuit, are connected as follows: the AND-gate is anding 𝐴̅, 𝐵< , 𝐶̅ & 𝐷
7 , while the
OR-gate is oring I and the output of AND-gate as shown in the figure below.

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Second Year Digital System Design

Data
Tx Rx Data

PN
PN

Note:
The sequence generator is also called pseudo noise (PN) generator.

H.W., discuss how we can use the PN generator in the transmitter (Tx) and receiver (Rx) circuits
with a simple example?

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