0

15
ic-
t
sta
Total No. of Questions—8
8] [Total No. of Printed Pages—3
3

g-
ns
S
eat
e at
[5352] - 562

:24
1
No .

44
:23
10
09
S .E . ( C om . E n g g . ) ( I- S e m . ) E XA M I NA T I O N , 2 0 1 8

18
0
D IG I T A L E L E C T R O N IC S A ND L O C I C D E S IG N
GP
/20
( 2 0 15 P A T T E R N )
05

0
CE
5/

5
Time : T wo Hours M ax i m u m M a r k s : 5 0

-1
00

c
ati
.15

N .B . : — (i ) Attempt Q.1
1 or Q.2
2, Q.3
3 or Q.4
4, Q.5
5 or Q.6
6, Q,7
7 or

-st
48

Q.8
8.

sg
5.2

4n
(ii ) Neat diagram must be draw wherever necessary.
2.7

41
3:2
18

(iii ) Assume suitable data, if necessary.

9:2
04
80
01
01

1. (a) Design two bit comparator using gates (consider A1 MSB and
GP
5/2

A0 LSB) [4]
5/0

50
CE

-1
00

(b) Minimize the following logic function using K-map and realize

tic
.15

sta
using logic gates : [4]
48

g-
F(A,B,C,D) = M(1, 5, 7, 13, 15) + d (0, 6, 12, 14).
5.2

ns
2.7

:24
(c ) Design 3-bit synchronous counter using T filp-flop. [4]
1
01 44
18

:23

Or
10
09

2. (a) Design a sequence generator for the sequence 1010 using shift
8
P0

register. [6]
5/2
G
5/0

(b) Simplify the following function using Qunie-McCluskey mini-

CE
00

mization technique : [6]

.15

Y(A, B, C, D) = m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14).

48
5.2

P.T.O.
2.7
18
 0
15
ic-
t
sta
3. (a) State and explain basic components of ASM chart. Draw ASM

g-
chart for MOD 3 UP counter. [6]

ns
:24
(b) Implement 3 bit binary to gray code converter using PLA.[6]

1
44
:23
Or

10
09
4. (a) Write VHDL code for full adder using data flow modeling style.[4]

18
0
GP
/20
(b) Explain entity declaration for 4 : 1 multiplexer having enable

line. 05 [2]

0
CE
5/

5
-1
00

(c ) Design BCD to Excess-3 code converter using PLA. [6]

c
ati
.15

-st
48

sg
5.2

5. (a) Explain with neat diagram CMOS inverter. [4]

4n
2.7

41
3:2
(b) State the following characteristics of digital IC logic family
18

9:2
04
TTL and CMOS : 80 [4]
01

(i ) FAN out
01
GP
5/2

(ii ) Noise Margin

5/0

50
CE

(c ) Explain TTL open collector logic. [5]

-1
00

tic
Or
.15

sta
48

6. (a) Give the classification of logic family. [4]

g-
5.2

(b) Draw three imput standard TTL NAND gate and explain its ns
2.7

:24
1
01 44

operation. [5]
18

:23
10
09

(c ) Explain wired logic in CMOS. [4]

8
P0
5/2
G

7. (a) Give the significance of the following pins of mirocontroller

5/0
CE

8051 : [7]
00
.15

(i ) ALE
48
5.2

[5352]-562 2
2.7
18
 0
15
ic-
t
sta
(ii ) INT1

g-
(iii ) TXD

ns
:24
1
(vi) PSEN

44
:23
(v) EA

10
09
(vi) WR

18
0
GP
/20
(vii) RXD.
05

0
CE

(b) Explain addressing modes of 8051 with example (any 3).[6]

5/

5
-1
00

c
Or

ati
.15

-st
8. (a) Which pins of 8051 are used for interrupt. Draw and explain
48

sg
5.2

4n
IF register. [5]
2.7

41
3:2
(b) Compare microprocessor and microcontroller. [2]
18

9:2
04
(c ) Explain the following instructions with respective to microcontroller
80
01

8051 and give example of each : [6]

01
GP
5/2

(i ) DIV
5/0

50
CE

(ii ) L JUMP

-1
00

tic
(iii )
.15

PUSH.

sta
48

g-
5.2

ns
2.7

:24
1
01 44
18

:23
10
8 09
P0
5/2
G
5/0
CE
00
.15
48

[5352]-562 3 P.T.O.
5.2
2.7
18