unit IV Algorithmic State Machine, -— Finite State Machines (FSM) ang . |AsM, ASM Charts and Notations 1 hat SM a | 2(SPPU : Dec-08.10.15, May-1.13,49, ny, sacha that has been developed specifically ims is called an Algorithmic State Maa ans: A special digial hardvare algo ASM) chart a2 How dos ASM chart differ from conventional flowehart 2 SS {SPPU : May-09,12, Doe43, May Ans: The ASM chan_resembles @ conventional flow chan, bu imerreted somewhat difeenly, A conventional flow chart describes y: sequence of procedural steps and decision paths for an algorithm wits conver for their time relationship. An ASM chart describes the sequen cf events as well as the timing relationship between the states of + sequemial conrlle and the events that occur while going from one sat wo the aext 3 State and explain basic components of ASM chart. FFISPPU : Dec.-11,13, May-13,15,16,18, June-22, Marks 6] Ans. An ASM chart consists of three basic elements : The state bi. ‘Be decision box and the conditional box. State box: A sate in he 5 shown inthe Fig Q3.1 As shown inthe Fig, Q3.1 (AL the left = contol sequence is indicated by a state bx . eclangle shape is used to represent sate bt the night hand top ot the name of the state, such as A, B, Qy Qr i Sef that sate ee OF the box isa Tst of the flip-flop vale i the conesponding ie gctgus that can occur whenever the cis tox.) Finally, a ing pea Tegardless of input values are listed withia Path othe nent sig, 2"2 ftom state box, known as exit, indicates sand Logic Design — ont a ee Aoi rh 5, ‘e Envy Cosing oy wt Macins ° ea valu for YY thes Register operation ‘or Output jen ’ rit () rma ger) et ay Fig. 0.3.1 State box pox: The decision box describes te fs is subsystem. It has a diamond shape ao = mgs sown inthe Fi. O32. The ipa emia 252s Ween iside the diamond box. Each vale ete poy 8 “Seedy a input OF EXTON non ny ye ep fom that diamond. These paths lead tothe bios = ye comespondng tp erent states of the cicuit following the nex clock puse : ' ' zntpatht Ent path2 Ext pat eupanz (2) General description (b) Specie example Fig, 0.3.2 Decision box Conditional box : The state and decision boxes are familiar from use in ‘sventional flowcharts. The third basic element the condional bu. usque to the ASM chart. It is an oval "er extranct ses ® box. Its rounded comers ‘Sfferentiate it from the state box. The "Mt path for the conditional box. always usd fen ftom one of the exit paths of @ wc" box. The outputs that occur 7 ‘et the path to a conditional output box ' ' Stisfied are listed within the box. ‘a.3.3 Conditional box condional ovoulsoy fsted in ether the state Box or g active wi COndi recs 3 rt ae ay INE We the gel 4 re pte AS ae ste 1 ASM chart fenaes of gga st the fete ISTSPPU: May-126, cides the sequence of events’ Mita ‘ean ASM chart desribes eS as yg 4 ans: en the sles of & sequential cong a ship bene ler ming enone le going fom one state to the next, ay coms at our ‘very book i rome Gi aaa ansspcted within the sate and conditional Pee pefomed inthe datapath subsystem Th ht fe oF HE OE Fr gg : ‘gy shen «an ASM cha consists of one or mre interconnected blocks ‘ ne any number of sian ASM Mock has one enance_ an a ‘rset bythe rast of the decision boxes. my an ASM chat specifis the operations thy, ‘one common clock pulse a bons «Each Mook in the ASM chart desribes the state of the sy one clock-pulse interval 5 Menton application of ASM chart ? SE[SPPU : May-12,19, Doc.t8, Mara Aas: ASM chart is used to represent state machine/sequental cing with the description of sequence of events and timing relation beter te te day 8.2: Construction of ASM Chart and Realization for Sequential Circuits| 6 Develop an ASM chart for a controllable waveform geneitr ‘that will output any one of the four waveforms given in Fig. Q6i, ‘9 determined by the values ofits two inputs x, and x,. The peri Of the first two waveforms is four clock ‘cycles, the period of third is three, and the Period of the fourth waveform is two cht Svcs, respectively. When an is the ae * 2 an input change does occur t! "form may begin at any poat in its period. Of ge Sie iodo at states, {suo Qj: In the Gre sate, Q, ie ia te fax dk le snthens ae a lope |. There, te cup, 2= ase gee sate box for the fist state, Q, 2. State Q, : In the second state, Q., ie inthe seend cack ee, he aut is 1 except for the waveform coresponing opus x, © 11 This condition can be tested by expression x, » x, inthe decion bot ‘When the result of expression is 0, the inputs ae other than x,x, = | tod hence output Z = 1, This is represented by decision bow and ‘ondtional box in state Q, 4). State Q, : During the third state Qy i. inthe thd clock pus, he oat wil be 1, if x2 = L The condition of is cece and acces aut is made 1 by decision box and condom tor in sate Q, 8 at Fig, Q62 we cam rele that te cup of i ain ":Q, and state Q, is same, i. logic I. In oler words sae ye aveform stats new cycle, There, wien," 10 6 "eis not used and line goes back to first state t0 sta he ne A Guide for Enginecig SO way 1 Gor Eire etcarones and Logle Design he ys a ie Mean oa came AS a gy oy ee (htm Tsin a k P Q B a ein tee with 80 iPops, A and. Bane MUX | and yt be eae | Bp eee me out. The cup of te ny, Sabine 2 ere | ssemmif the multiplexers, In this way, presen ME Wed tg CUCU tp ee [BP eetissone of te inns fm ea et cist es 19 coh mali ale of the net se? ona Paps ota be op inary val eX sate ng tip ca tas inputs of he multiplexers ae determine he repeated se mestions given inthe ASM chars (Refer po Sion boa aa es, next states and conditions for transition sar 263) The eset ea Soe given in Fig. Q.6.3, a8 shown in the Table 7 Med for asyy _— No. | Present state Next state the state tables | we lit the eee ae [QT oT fale wih the oe [2 feo yp sa ote 3 TQ] To Te) =— Qt ‘ach combination 4 Went Ta Tere of input valves, Table 7.1 wits for Mutipeners | MUX1 | Muxz Fig. @.6.2 ASM chart for waveform generator 050 Jonr 7 Explain the MUX controler method with the suitable exa ple el jize SSISPPU : Dec.-08,15 May-14,19, Marks § 2Ahey [245% : 18 May-11,18, i Rat Whey os ae 26 sight forward method for reaisie 330 Boo onal circuit for any conraller, m SS 7. Oita we pee, Jn this method, the gates ut ‘method there are respectively. In ths liplxers te {8 9 Somponens. The fst level cos # Contain a register that hol the next state of the register. The secon le! the decoder tat pone PRESER! binary state. The tid kee INES combinational ere ae PUL for each contl sa ee: A Guide for Engnerng 8 oO Table a72 for ‘flipslop A and MUX ? genres ig fr ta om Be dared bln ein Logi 1 psn hp ste Cn Tite fom Qs to Op. For fipop A te nat ane BG hice He fee ane input of mulplexer I is 0. For fipfopB te net ste Ait Corresponding input of mulipleer 1 8 he gn conn of 1 Beer: gots spe $00 8. The mulipierer Sesion corresponding to te = 1 Ge for Engieing Soeition from Q3 1° is 0 for Qa nding © sition OTT x inten ein state Qy. Z Qj oF Qs. Im this case, ye hs and 1 for Qy. Therefore, the Ne Gy ken aS coresponig et ‘an be directly derived from Agyy FAST 4SM chant and find the cong’ therefore Q, wit Yh “Z. After collecting all the conditions where a « ong ft te tay AR Fapinccnn So an ASM chart for a 244 5 © = 1 counig ean hg rf ER TSPPU : Dae a ze uel PEE the cua ee MAME ag r tt % ‘ure 10 o atu uraw | Fig, 81 ASM Chat 7 8 Draw an ASM chart and state table for a 20 UPDON ‘unter having mode control input : M = 1: Up cous ae DOWN counting \ circuit should generate 4 ouput 5 ‘inimum oF maximum. g@{spPU : May0st4 Ove 2 MAM EE “de po Ein nS, — -A Guide for Engineering Soe costa Deen by Y ASM ¢ the followin ee op 5 0, counter changes the sate ay ugg, 1 be dy H9~ Gould remain I present ane, pon lOH Hp coi suitable MUXs. in ri ESISPPU : May-06,07,14, Marks nf ASM chart = 7.04 wee YO rah aa = a Beat Fig. 1041 ASM char => — Gu forEnincering Sates‘The Table 10.1 shows the mul sample Nett state | Input Pris | Seca ea a) Bo Ae i oa Ore cc eae of of oe 1 x tr pepe of{iftifo] x TPepr ye] x ee eno) tit x a Tt | oe|e s Table Q.10.1 Logie Diagram ox Fig. 102 fenerator cireuit to genera 7 Crea 2H conta input C = 0, the sequence genet the same state. i) If control input C= 1, the sequeat fecerator cc goes into next stat. garegppy : Dec-13, Mths 7 O14 Design & sequence ‘A Gul for Engineering 0 + fo C= 1,B=1.Az1 1 i Fig, 41.5 ater eemux? wax Sos S5) Fig. .14.2 END.W# “A Guide for Engnesing Sul ne PLD. Mention differen yey ot pip ot vel 5 [rey ‘a pLD stands for Programmable Loge Denes Mt sy configuarable BY the individual in get Sg m > i spec ve ae reprogrammed in few sex fess 5, experiment wih desis PE ey seat. achileCKNe, COMPA and Dewi Apease classified as —— PROMS : Programmable Read Only Nemures {plas + Prosrammble Loc ars: PAL. : Programmable Amy Loe: * FPGAs : Feld Propannsbe Gae aay feos | Coulee te aw and explain the structare of ROM! PROM wi 94 Potmatrix and OR mats MT FRO wth he ep ere The ROM / PROM is a to lee impleneutise i en of Stes form ire Ge - Fig. 0.2.4 42 PROM with AND-OR Ga¥6 oD ii\ joa Laie DO en yroduct a tris asd fo fom : ve the logical sy AND ed 1 re Mm OF th, The OR mB PST a r erm opus of al circuit using ROM. The etregi, ey 3 Design # com enertes an-owpat DINGY numbey hy, ner a0 i sum terms, si ‘Way cof input number: im square a a Binary | Square of gy —~ input on | “on daty ser audeess 8 ag | lines | Fig. 0.41 Block diagram inserted between all ninpus an 1 CAND aa. d re also provided between the AS oF he a 1708 F the OR ates. SUIS oF the ayy 5 dy oe thee ae set of fe inthe up inne gh a ated either inthe Alles nS VERT form AND-OR "mn fain ao vided in the PLA j oe Bele OS FA it ae yy, Bane pe ain EY Of FLA ne ya ‘ 8 bles abe xt i 5 Acombinational circuit is dened by ie anipy p25, 2G 5: Ds Fy =D m4, §,7) Implement te creat wit fiabsvag 3 inputs, 3 product terms and to naryne FEISPPU yt, e814 as fac: Stop 4 : Simplify the given Boolean finion ‘te Bolan functions are simplified, as shown 9.2: Programmable Logic Array (PLA), Programmable Array Logic (PAL), in te Fi 051. The Designing Combinational Circuits using PLDs sled hestons in sm of poss we ofan fone i ory ory (G4 Explain the block diagram of a PLA. No on Men an EE[SPPU : May-t4, Juno-22, Marks 6 ololiyo ofo]oyolo Ans. «PLA stands for Programmable Logic Array : ‘ln PLA, both AND and OR gates have fuses at the inputs, therefore a PLA both AND and OR gates are programmable. Fig. Q41 shows the lock diagram of PLA. “consists of ninputs, ouput buffer with m outputs, m produst tem ' sum terms input and output buffers, TTD oduct tems consute a group of m AND gates and tke si ‘ems constute group ta at of m OR gates, called OR matrix. A Guide for Engincering Se FL= AC+BC, F,=AB ate te dst ter: Write PLA program table : Therefore, tere are te tems : AC, BC and AB, and two sum terms. Tam ‘Sl shown in Table Q.4.1 consists of three columns specifying POU = “efor niin Soe —ast col RIVES THE Hity sys The o vs ss ese the crcl TM, So The AD ee, sO he OR es Under yn 2 Mahe ent VEEN iN tof pp are be complemen Mam sted of the TN OF Fit gape . mn we iy ae cle fr efernge pete pat of PLATE Product | apes | Ontpats term fajate| Alf oes viata] - of 3 J toley tt T(t] te ‘Table Q.5.1 PLA program table pe akeeCcT || Fig. 5.2 Fig. 062 S “A Gude forEngineing St® I afr Egrcrn Hecron od Lap De® att Paso o (07 Design using PLD ® 3:8 dec Marks 8; Dec.-13, May, Ma Fy decoder wing PLD, vg san TEE OTE Fig. a7 4 Implement 5b binary to gray cade converter using PLA, 5 (SPU :Dec16, May, June-2, Has As: Step 1: From the truth table Binary code | Gray code & (8 [ale Tala i Chali ol el 4 o ‘ho 0 eS 1 flilitolil 5 1 oro 1 1 0 1 as 1 : L 1 ‘yo = 0 L ‘ 1 1 1 o a et A Guide for Engineering Smien® ier, MLL yyy $8 Dsign 4 input and 6 output combiaatinsl cic wig PLA. Teiaput variables are A, B, C and D : ‘ism, 3, 5,6, 9 10, 12, 15) {22m 1,2, 3, 1, 12, 14 15) Tstm 0, 4,8, 12) {TEMG 23,5, 7,812, 13) : 272, 1,3, 4,5, 6,11, 13, 14 1 i Vane 2 ce - sayispPU: May at«a Yor RBC + RBCB + ABTD Ki Afr snplicaton for ouput fanetons we ave realized that there ae 23 Hod tems which ae greater than possible 16 mintems. To Get minima combina tional circuit it is better to implement all 16 Fessible mintems as pro fet terms as shown in the Fig, Q9.2. ‘A Guide for Engineering Soe? Rosi Een oe?code converter using PLA, to Excess . ama SGTSPPU : May. | 7 | Step 2: Simplify the Boolean functions for Excess-3 code For Ey 1 1 9 te) elofo x|x|x PPR +85 5, +88, + 8,8, For Ey orn 10 oj ola ofols x| x |x o| xfly) BB, +8.8, A Gul for Engnering Sse “tar gg StDig eons and Lope Dosen G11 Implement the following Boolean functions ABCD) = Ym (02,6, 7,895 12,13) 2 (A,B,C D)= Fm 0,26, 7.89, 12,13, 14) Y1A,B, C.D) = F m2,3,8,9, 10, 12,13) 21,8, C.D) = & m(,3, 46,9, 12, 14) ERISPPU : May. Ans. Stop: Simplify the four functions O14 Mata Note that finction has four product tems. Thee of W, Therefore we can write n= w+ BCD. montis ee ven oT «Ll | a 1 Th} ol ea ula ale] 4 wolf a) voll |] 5 + Rac +0 ** BC +AT + ACD ‘Step 2: Implementation In the last section we have 0, asQoo_ or tt ao VRB B53 Fors seen the PLA program table. of Gy The program table for PAL of] > is similar to PLA. program table. Table QUILT shows oO Te PAL program table with wl alt Product terms, AND inputs wi | and outputs 22750 +300 +85 Fig. Q11.1 K-map simplification Product term | __AND Inputs a]sle] |e lel 2 oe l= | 3 ri-jo}-|- Fig. 0.11.2 Logic diagram “A Guido Engng So “yor Eine So ————Digital Elcronkrand Logie Deion 9 mt 12 linplement 4: 1 multiplexer using PAL, Oy, one ine FEISPPU : Doe. 4 ee eee s we ‘ miler is Y = F8iS0Dp +ESiS9D) +E5,390, | in ®Sisyp, 1 Fo kyRE Es Rag, iil Fig, 0134 Logi dagan stion using PAL following uns ra A446 ‘glenn ml, 3, 4 6 9 name Fig, 3124 a ee) al circuit is defined by the function FAA, B,C, D) FV(A.B.C)= 5m (01,34) Implement this circuit with PAL, FSISPPU : Dec.-13, Marks 4) ‘Ans, : Kemap implication oon = FL = BC+Ac 2.43 A combination of, fa) 4 Guide for Enginerng Seswat = ot implity the: two functions. s! ; 1 ee Lo Dien gn on sep 1 Remap smifintion Fig. 0.1641 (a) F's plement the folowing Boolean function using PAL Fi=E0,23,4 56,78, 10,11, 15) F-20281, 13) SS[SPPU : Dec.-16, Marks 6) le 1 Gui for Ev — A Guidefor Engineering ace | SSin te i ta {sprU : Dae 08,06 07, May-06.07,0, 16,16, PROM AND am is hos ~ pwc PROM, PLA ad Pa uteence beeneen PLA. PAL and PROM PLA 7: classification of Logie Families unipolar and Bipolar Logie Famiies Both AND and OR meee! | ieee pnw ami? Gv th hse ge ant FS emape and simple 19 | Costes and complex “o ES [SPPU : May-10,16.12, Des.08,16, arg Sees in PAL an PROM gt le family 8.4 BONG of comp vs ape immemsa | ANDanay an be > pe levels and supply votes According wo components ued ig esate propanmed 10 ge oe iy, digital Topic families ae clusied as showy an yh | desired mierms. OO + Onl Boolean focins sand_|nSOP frm can | in SOP fn ——+ gut | Any Bowen futons] Any Book * ean fat omtetont ann ‘SOP form can be | implemented using emented cre inpeneted wing | FLA ane Font | END... | set | mem nt Coe age a trata Setar oe Ex erage ras. ‘Risepmaecninge In rom orto Fig. Q.1.1 Classification of logic families Seas Gu fr Egneing Ss ao-0)Dige:Fxronis and gh Deen 183 [10.2 Characteristics of Digital ICs: speea, Power Soy | isspation, Figure of Meets, Fano ¢ rn |e Fara Nae minty, ag Yemperatere Rage, Power Spy ee az te and explain any fo harass of dat oy FRTSPPU : Dec.on, Ma OF Pee ng Wm a8 men dey TT ogi amity A 1 Voltage ad core parameter 2) Power dstipation 2) Nowe Margin watson . fv frepgiton Deny: The epgnton delay ota at 0 Se me eral feren the aplication of an ape ete Sica Pulse SE of ron cue pe The ous sopra cher of loge ett cae heel ‘bh they can operate, The shone the propagation delay the niga speed ofthe ect and viee-vema here Terer Dispaion : The anoint of pover tht a IC gy cerined by he serge suply caret Ice hat it dans eos sxpply eas the product of Ice and Ve Current and Voltage Parameter musi High-Level Input Voltage : It is the minimum yo ture fr 8 lope 1 at an input Any voliage below thi ons wll be accepted as a HIGH by the logic cireuit, = Vit easy Low-Level input Voltage : required for @ logic 0 at an input. Any be accepted as @ LOW by the logie cireu tis the maximum voltage above this le it olage lvl vel il pa "ou iin High-Level Output Voltage : level at a logic circuit 0 conditions, © is the minimum votage put in the logical 1 state under defined led Not ina Low-Level Output Voltage : level at @ logic cireuit conditions. It isthe maximum volage Surput in the logical 0 state under defined lo A Guide for Engineering Svs ot currents and voltages in the two logie sates oat 7 srmput Curt : It is the curest that Nous ino an apart ped ig-level voltage is applied to that input ae f Current : It is the cunent that fons iano an yn ined low-level voltage is applied to that inpur ns we use! Output Current : ICs the cureat that flows fom an Ham Me agial 1 state under specified load conditions. | Output Current : It is the current that lows from an erie logical 0 state under specified load conditions. + The noise immunity of at a logic circuit refers to the ey to tolerate the noise without causing spurious changes in supt volage. To avoid this problem due 10 noise, voltage level, lou Ket at a few fraction of volts below Voy ng) and voltage jy i Hep aDOVE Vou gan ak the desig tin, ‘ute difeence between the lowest posible HIGH ouput, Vojinn te isimum voltage, Vjyiny required for a HIGH int, Ths nie fence, Vy is called high-state noise margin. Similarly, = Eile noise margin. It is the voltage difference between pose low output, Votimas) and the maximum voltage, Vi (nx) dar LOW input Ss “A Gude fr Enginering Stabegm: Piers ond nc een . om andy Fann and Fanaut | The MINIM MIMeY of inp. the utr of & topic pa it Of Int fancut In general. the fang cu mame of inputs ofthe SAME TC fatty a titans cup evel within the specified Tyna Te fant +S! HE FEE 0 mae fy Speed Power Product (Figure of Merit) ™ tn gover foram ct 1. desirable to hang dela (higher seed! and loner salves of power he ually # bade between switching speed ang eg ba a eed gan sncreased power disipation, Therefore, a common means 4, se sod compurng the oven perfrtance fone of aN IC fan SpecdPove Prec (SPP) Ts abo eed Figur eri," & Operating Temperature Range siti the temperature range specified by the logic fa deve gure 1 Mod ely. yw Power Supply Requirements, “Power supply fequements differ fom logic family yy ample. 8 SV for TTL family and 3-15 vol fy CMos fat? Furr more, power supply tolerance also depends on ‘ogi oS ‘ample for 74 series TTL family it is 0.25 and oe, fe family iis 208V seins 10.3 : Transistor-Transistor Logic : |) Operation of TTL NAND Gate, TTL with Active Pull up, TTL with Open Collector Output, Wired AND Connection, Tri-state TTL Devices, TTL Characteristics | 3 With neat circuit dia i : cuit diagram explain the operation of two TTL NAND gates, . re SSP ISPPU : May-06,10,12,13,8, Dec.-07,12, Marks 8, June-22, Marks eons “A Gude for Enginern Sse? og ONL (8) MO the cre iy og oem ca ecemiter transistor Q. a5 ah —_ set toi Den : vcture consists of multiple-emi ra eof YteM-POle MPU. Here 6 an Ney nite, 008 fF ACN Rp 1 the ge ign eR ce. ne ca” SY 8 ay by ange nmieepresent the $9 EB junctin pase (C-B) junction lg. 2.1 (a) Two Input TT NANO gua The ipa vohages Aw % Bae eiber LOW ely gonded) ot HIGH (eal $0) er Aer B or toh a lo, the conespondng dk: couducs and te bie of Qy pul dove dpposimae 07 VTA Teor the be ole of ‘on ainon Tact, Gy ew Ta Os a a to ston te te rt SH Six Qs AL HIGH voltage 8 BEtate y >t HI ee dy the of Tis HES the ollecon FQ, ba a as foes Q2 Base to go ype val ss en oe in #1 $e ace tiga nd 00 ‘able. Truth table for 24nput NAN e io de Die eit Qs wl conduct tighty ye the ‘vow Teese this he dds inset is voltage eM ogy trent die of Qs vee I is vay, eM ber be ouput is cue (26 Expl open collector output. ERTS PU sus, Wie eles nile wae et Ma 2 all sr ages ald open ea 2 Mg St ety fom eon cles eget Oa Gna i a ptr wa ope oa sien wiser boomers : ssa, “ot work Proper Veg Ener oe teaser Cupar Open cotect ote el vansior oe seantages and disadvantages of totempole output nn BISPPU : May-05, Dec.07, Marks 4) oe sa he advantages of open collector output geo Tar[SPPU : Dac.06,15, May-08, Marka 4) snparison between totem-pole and open clletor outputs, ive on Gt ws Pelee sae Open collector [ouput stage cont of pllup | Oupu sage cosine of cay | wanstor(Qs), diode resistor and pulldown tanastor | pulldown mansistor (Qs) ‘tema pull-up resistor is not | required ‘External pullup resistor is required for popet operon of gate 3. | Output of two gates cannot be ted | roger (Ouppur of two gates canbe ied Vogetber sing wired AND technique [ Operating speed is high Operating speed is low Table Q.5.1 Comparison of totem-pole and opan collector output 6 What is wired AND connection ? ES{SPPU : Dec.-18, Marks 5) ‘Ass. : The open collector ouputs of two or mote gates can be connected teeter, as shown in the Fig. Q6.1 (a) The conection is called a WHeGAND and represented schematically by the special AND pate Symbol as shown in Fig. Q61(). (Refer Fig. Q6.1 on next page) (O7 Draw and explain the circuit dlagram of tristate TTL NAND fate, [SPPU : May 05,19, Dc.08, 07, tune-22, Mark 6) Ams: The iste confguation is a thd pe of TTL. euput Senfiguation, Mt lizes the highspeed operation of the totem pole mangement while pemiting oupus to be witedANDed (commeed ‘ogether, I is called state TTL because it allows three possible out Sages : HIGH, LOW and high-impedance, Fig. Q7.1 shows the simplified circuit for tristate inverter, It has two inputs A and E. ———a lene jo enna Tie MHL HST sg ie M6 HUGH the cite wks ae "pt. When ANE NGH, he sae of the tase gen sie sie 1B MPLA. ad the ain cnmey as cabo Lge HIGH. She Pua So cg of te st FTE PU A, he seem en LOM egy Ry 20) from Oy making it OFF. ASO. 4 OFF, gent ve fOr Oy 0 conduct and hence Q, tans OFF “The tow SRABLE input also forvardsbases diode O;, which shut we earch rey om the base of , making i OF. nhs ny, ate arace Mout is LOW, both Wanistors are OFF and opus a high ine oe (8 Explain the following characteristic 4) Power dissipation i) Noise margin oat 20a We of TTL loge families (0) WedsAND oetp t, i) Propagation delay i) Fan Conese tpt ‘AND gate symbol "Pal Fig. 06.4 on Explain standard TTL characteristics in detail, 3v EB TSPPU : Dec.18,10,12, May-10.13,15, Marks 8) OR Define the following terms related to logic families. Mention typical values for standard TTL family i) Power disipation {i Fan-in ii) Vy, Vou iv) Noise margin. [EESPPU : May-12, Marks 8, June-22, Marks 2] Fe iy pti obpiing ‘TTL family : i) Voltage parameters ii) ‘Power dissipation iii) Fan out EH|SPPU : May-16, 18, Maks 6, ‘June-22, Marks 4), oe eee ta Say eo vs aga 8 oe x Oh ee oA ee oe shown in the Table Q&1 are for worst case consis a — Fig. Q7.4 Tristate TTL inverter ome acoa) got Een on Las De lott Typleal Voniages Minimum \ wn M a4 oR Mw Table Q.81 Voltage lovels fo: TTL Low state nie margin, Vand igh Sate nog tech are ogual and 4 V Rin, Power dispation and propagntion delay : A standard Typ average power dissipation of about 10 mW. Beta, Fancout : A standard TTL output can typically drive 19 pus Thee andard TTL has fou! 10. a 1, 28 Discus the advantages and disadvantages of TTL Logie i Ans: Advantages of TTL aly High speed operation, Fastest among the saturated loge roozton del tie is about 10s ik Moderate power dissipation Available in commercial and military versions, Available for wide range of functions. Low cost 6, Moderate packaging density Disadvantages of TTL |, Higher power dissipation than CMOS. 2. Lower noise immunity than CMOS, 3. Less fan-out than CMOS, 10.4 : CMOS : CMOS Inverter, CMOS Characteristics, CMos Configurations - Wired Logic, Open Drain Outputs 2.10 Draw the structure of CMOS inverter gate, Explain i Working. ES{SPPU : Dec.-07, Marks 3; May-12,18, Marks 4, June-22, Marks 6) ‘Ams. : Fig. Q.10.1 shows the basie CMOS inverter circuit. It consists of {wo MOSFETs in series in such a way that the P-channel device has is A Guide for Engineering Sates rot omens te a M00 i Ds mesand toni Deen Let Fmt ced 10 * Yoo (® positive voltage) and they, neh connected 0 ound. The gates of he ourtever 38 the COMMON input and the dea ‘ommon out chancel devise 0 devices are IS a competed Fi. 0101 The CHOS near ven ins HIG, be of 0 Phan) 0 V ane 1 Mae tg, de Woy OT 0, OF. Ort ob we peo Eames gine 8 rm Vpp: Ths, Q; is ON, Ths wil price to Tmo 8 ie Very 4. When input is LOW, the gate of Q, (Pct potential relive tits sauce wile Qs BS Vs DN and Q) is OFF. This produces oupst © ce M ND gate. J c08 SAND oan yh et diagram tC a. [aPISPPU : Dec.-12,14, May-4, ee ang qu ows 80S 2a NAND cu Mciet wosre 0) ml Os cam 2 anne! NOSE a SF rs are negative with respect 10 oe 2 of both P-channel Caen eel cs és %s es ar Goameorce voages of 3 and Os a ay, i rs are OFF. The w 5 See oats a OF sce be a oh OX. Si rel MOSFETS) ae P00? Vici dough Q a 0 fd B00: 8 their sOures, et ‘pp Ns onmecte 0 “800 ‘ xis therefore ieee Sorenee on pine dee cnn on ‘9 inpat CMOS NOR gate, - C[SPPU : Dec.10, 18, May. 11 0) soos 2inpt CMOS NOR eae Hee, pene Oe cael ly a og chanel MOSFET, 0 Opec sp 0 ssnmaraes the operation of Ding NOR gue Table 121 Trath abe fr NOR gate —) 2, sehenate Fig, 42:1 GMOS NOR gst Ee Table Q114 Truth table of NAND gate ee A Gade for Eninering Sennont Dosen tote ig! Berni ed co Site mevits and demerits of CMOS logic fami ery Ans. Advantages 1 consumes less power 2 can Ne operated at bith woages, resulting i rami - 5 Fan-out is more : 4 ener nose margin. Disadvantages: 1) Sussepible to static charge. 2 Sostching sped low Greater propagation delay Q.1¢ Why wired logic i not possible in CMOS operation, Ans . together, ie QI4I shows mo CMOS vere with ou Ml ‘Sonn, wg ee 0; y enorme) Fit 014.1 CMOS inverter with outputs connected 1 When A= B= y (0): Q, and gy vinearga® Q; are cutoff and Y 3. When A= Vi) and are OFF, an eas Lier aod Gh ae ON, very age cue tty a ake vlvae a Y Yee eh en Fa. 6 (2 ein HE ANE Of Lge Theta et ey 2 opty. The same thing wi happen ye CH Wl et eth Ove 10 lage eat anise may get ng,” IO) and 8. age must wot be used for CMOS logic cragy, tee Thee, ve ge #08 ends ngo + CMOS gates ae available with open da In OU, a8 shown in Fig, 181 ‘In open drain outputs, PMOS transistor is replaced by aide D, wed provides protection ffom eecrosati dchree ‘Open drain gates canbe used with extemal pullup reser to perfom wited-AND operation, as discussed in TTL loge 46 Differentiate between standard TTL and CMOS logic czeit ‘wars. i) Propagation delay i) FANOUT i) Figure of merit List the Aifferences between CMOS and TTL. [5 {SPPU ; May-15,18,9, Jne22, Mats 6} Aas. pe a 7 = VU) = Veg \sr. Ni Parameter -cmtos Tm | a8 a ON ad ¥ = VY 1 fmt |e tet MO): Qi and G5 are ON whereas Qf and —— — ae [env — “A Gide for Empincering Sudents A Guide for Engineering Sides sua Eero and Lai eset 10-16 Dia Eero and ae OE —— ]49sv igh level ove mui | Vyqg* 148 V Saat | fe = /\\ Introduction to | [_ 7 _| tow tee ons margin Vag" UAY__| \ \ | Noe inmiy | Bene than TTL 0 Switching seed | Less than TTL w ower dsipation er | 01 mW | ee | Sped power product | 07 pb avi is microprocessor > Write a short note on ideal pales [» a 1 (9PPU :Juno-22, Marks 6 14 | Power supply v 10 x mieroroeessor jg an important part of a computer architecture mee [SY IN not be abl ig pare Find 3 es aie 7 ot be able to pero anything on You sinwion | nce ase wit «| sug | Tee “ptt aviation Pont A wih fe got ogrammable device Mt kes. in input, performs some | Porabe instrument | i iss | eG ml a : cae nee a | DRY fn va an oes! peso Nt it and produces desied ost = _ Fe singl words 8 sTOMOCST isa digital device ona hip which tah instructions fF" HE, decode and execute them a ve rel there is noting Uke ai To don of he copocetr we DHE deve fig, QU shows a ideal microprocessor seth inputs and utp input signals a applied fom input devices, The iu devices may. inslude eyboard, OWE, a a ieroproeeot gals of Toes gals a pa Tse Ng ad a ami ane inp ae a? Table 0.16.1 Comparison between TTL and CMOS f families dal microprocessor. Howeret, 0 understand ed this hypotelca END. A Guide for Engineering Stade