Full Adder :

Structural Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder_Structural is
port(
A, B, Cin : in std_logic;
Sum, Cout : out std_logic
);
end Full_Adder_Structural;

architecture Structural of Full_Adder_Structural is

component XOR_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;

component AND_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;

signal X1, X2, X3 : std_logic;

begin
XOR1: XOR_Gate port map(A, B, X1);
XOR2: XOR_Gate port map(X1, Cin, X2);
AND1: AND_Gate port map(A, B, X3);
 AND2: AND_Gate port map(X1, Cin, Cout);
OR1: OR_Gate port map(X3, X2, Sum);
end Structural;

Data Flow method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder_Dataflow is
port(
A, B, Cin : in std_logic;
Sum, Cout : out std_logic
);
end Full_Adder_Dataflow;

architecture Dataflow of Full_Adder_Dataflow is

begin
Sum <= (A xor B) xor Cin;
Cout <= (A and B) or ((A xor B) and Cin);
end Dataflow;

Behavioral Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder_Behavioral is
port(
A, B, Cin : in std_logic;
Sum, Cout : out std_logic
);
end Full_Adder_Behavioral;

architecture Behavioral of Full_Adder_Behavioral is

begin
Sum_Process: process(A, B, Cin)
begin
Sum <= (A xor B) xor Cin;
Cout <= (A and B) or ((A xor B) and Cin);
end process Sum_Process;
end Behavioral;
Full Subtractor :

Structural Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Subtractor_Structural is
port(
A, B, Bin : in std_logic;
Diff, Bout : out std_logic
);
end Full_Subtractor_Structural;

architecture Structural of Full_Subtractor_Structural is

component XOR_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;

component AND_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;

component NOT_Gate
port(
A : in std_logic;
Y : out std_logic
);
 end component;

signal X1, X2, X3 : std_logic;

begin
XOR1: XOR_Gate port map(A, B, X1);
XOR2: XOR_Gate port map(X1, Bin, X2);
AND1: AND_Gate port map(A, NOT B, X3);
AND2: AND_Gate port map(X1, NOT Bin, Bout);
OR1: OR_Gate port map(X3, X2, Diff);
end Structural;

Data Flow method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Subtractor_Dataflow is
port(
A, B, Bin : in std_logic;
Diff, Bout : out std_logic
);
end Full_Subtractor_Dataflow;

architecture Dataflow of Full_Subtractor_Dataflow is

begin
Diff <= (A xor B) xor Bin;
Bout <= (A and (not B)) or ((not A) and Bin);
end Dataflow;

Behavioral Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Subtractor_Behavioral is
port(
A, B, Bin : in std_logic;
Diff, Bout : out std_logic
);
end Full_Subtractor_Behavioral;

architecture Behavioral of Full_Subtractor_Behavioral is

begin
Diff_Process: process(A, B, Bin)
begin
Diff <= (A xor B) xor Bin;
Bout <= (A and (not B)) or ((not A) and Bin);
end process Diff_Process;
end Behavioral;
Decoder :

Structural Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Decoder_Structural is
port(
A, B : in std_logic;
Y0, Y1, Y2, Y3 : out std_logic
);
end Decoder_Structural;

architecture Structural of Decoder_Structural is

component AND_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;
signal X0, X1, X2, X3 : std_logic;
begin
AND0: AND_Gate port map(A, B, X0);
AND1: AND_Gate port map(A, NOT B, X1);
AND2: AND_Gate port map(NOT A, B, X2);
AND3: AND_Gate port map(NOT A, NOT B, X3);
Y0 <= X0;
Y1 <= X1;
Y2 <= X2;
Y3 <= X3;
end Structural;
Data Flow Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Decoder_Dataflow is
port(
A, B : in std_logic;
Y0, Y1, Y2, Y3 : out std_logic
);
end Decoder_Dataflow;

architecture Dataflow of Decoder_Dataflow is

begin
Y0 <= A and B;
Y1 <= A and (not B);
Y2 <= (not A) and B;
Y3 <= (not A) and (not B);
end Dataflow;

Behavioral Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Decoder_Behavioral is
port(
A, B : in std_logic;
Y0, Y1, Y2, Y3 : out std_logic
);
end Decoder_Behavioral;

architecture Behavioral of Decoder_Behavioral is

begin
Decoder_Process: process(A, B)
begin
Y0 <= A and B;
Y1 <= A and (not B);
Y2 <= (not A) and B;
Y3 <= (not A) and (not B);
end process Decoder_Process;
end Behavioral;
Priority Encoder :

Structural Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Priority_Encoder_Structural is
port(
I0, I1, I2, I3 : in std_logic;
Y0, Y1 : out std_logic
);
end Priority_Encoder_Structural;

architecture Structural of Priority_Encoder_Structural is

component OR_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;
signal P0, P1, P2, P3 : std_logic;
begin
P0 <= I0 or I1 or I2 or I3;
P1 <= (I1 and I2) or (I0 and I2) or (I0 and I1);

OR0: OR_Gate port map(I0, P1, Y0);

OR1: OR_Gate port map(I3, P1, Y1);
end Structural;

Data Flow Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Priority_Encoder_Dataflow is
port(
I0, I1, I2, I3 : in std_logic;
Y0, Y1 : out std_logic
);
end Priority_Encoder_Dataflow;

architecture Dataflow of Priority_Encoder_Dataflow is

begin
Y0 <= I0 or I1 or I2 or I3;
Y1 <= (I3 and (not I2) and (not I1) and (not I0));
end Dataflow;

Behavioral Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Priority_Encoder_Behavioral is
port(
I0, I1, I2, I3 : in std_logic;
Y0, Y1 : out std_logic
);
end Priority_Encoder_Behavioral;

architecture Behavioral of Priority_Encoder_Behavioral is

begin
Priority_Encoder_Process: process(I0, I1, I2, I3)
begin
Y0 <= I0 or I1 or I2 or I3;
Y1 <= (I3 and (not I2) and (not I1) and (not I0));
end process Priority_Encoder_Process;
end Behavioral;

Multiplexer :
Structural Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_Structural is
port(
A, B : in std_logic;
S : in std_logic;
Y : out std_logic
);
end Multiplexer_Structural;

architecture Structural of Multiplexer_Structural is

component AND_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;

component OR_Gate
port(
A, B : in std_logic;
Y : out std_logic
);
end component;

signal S_Not, A_And, B_And, Y_And, Y_Or : std_logic;

begin
S_Not <= not S;
AND0: AND_Gate port map(A, S_Not, A_And);
AND1: AND_Gate port map(B, S, B_And);
OR0: OR_Gate port map(A_And, B_And, Y);
end Structural;

Data Flow Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_Dataflow is
port(
A, B : in std_logic;
S : in std_logic;
Y : out std_logic
);
end Multiplexer_Dataflow;

architecture Dataflow of Multiplexer_Dataflow is

begin
Y <= (A and (not S)) or (B and S);
end Dataflow;

Behavioral Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexer_Behavioral is
port(
A, B : in std_logic;
S : in std_logic;
Y : out std_logic
);
end Multiplexer_Behavioral;

architecture Behavioral of Multiplexer_Behavioral is

begin
Multiplexer_Process: process(A, B, S)
begin
if S = '0' then
Y <= A;
else
Y <= B;
end if;
end process Multiplexer_Process;
end Behavioral;

Barrel Shifter using Data flow method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Barrel_Shifter_Dataflow is
port (
A : in std_logic_vector(7 downto 0);
shift_amount : in std_logic_vector(2 downto 0);
direction : in std_logic; -- '0' for right shift, '1' for left shift
Y : out std_logic_vector(7 downto 0)
);
end Barrel_Shifter_Dataflow;

architecture Dataflow of Barrel_Shifter_Dataflow is

begin
 process(A, shift_amount, direction)
begin
if direction = '0' then -- Right Shift
Y <= A(shift_amount(2) & "00") & A(7 downto shift_amount(2) + 1);
else -- Left Shift
Y <= A(shift_amount(2) downto 0) & A(7 downto shift_amount(2) + 1);
end if;
end process;
end Dataflow;

4*4 Keyboard encoder using Data flow method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Keyboard_Encoder_Dataflow is
port (
Row : in std_logic_vector(3 downto 0);
Col : in std_logic_vector(3 downto 0);
Key : out std_logic_vector(3 downto 0)
);
end Keyboard_Encoder_Dataflow;

architecture Dataflow of Keyboard_Encoder_Dataflow is

begin
process(Row, Col)
begin
case Row & Col is
when "0001" =>
Key <= "0001";
when "0010" =>
Key <= "0010";
when "0100" =>
Key <= "0011";
when "1000" =>
Key <= "0100";
when "0011" =>
Key <= "0101";
when "0101" =>
Key <= "0110";
when "1001" =>
Key <= "0111";
when "0110" =>
Key <= "1000";
when "1010" =>
Key <= "1001";
when "1100" =>
Key <= "1010";
when "0111" =>
 Key <= "1011";
when "1011" =>
Key <= "1100";
when "1101" =>
Key <= "1101";
when "1110" =>
Key <= "1110";
when "1111" =>
Key <= "1111";
when others =>
Key <= "0000"; -- No key pressed
end case;
end process;
end Dataflow;

Multiplier using Data Flow Method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Multiplier_Dataflow is
port (
A, B : in std_logic_vector(3 downto 0);
P : out std_logic_vector(7 downto 0)
);
end Multiplier_Dataflow;

architecture Dataflow of Multiplier_Dataflow is

begin
process(A, B)
begin
for i in 0 to 7 loop
P(i) <= '0';
for j in 0 to 3 loop
if (i - j) >= 0 then
P(i) <= P(i) + (unsigned(A(j)) * unsigned(B(i - j)));
end if;
end loop;
end loop;
end process;
end Dataflow;

Divider using data flow method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Divider_Dataflow is
port (
A, B : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
R : out std_logic_vector(3 downto 0)
);
end Divider_Dataflow;

architecture Dataflow of Divider_Dataflow is

begin
process(A, B)
begin
if (to_integer(unsigned(B)) = 0) then
Q <= (others => '0');
R <= A;
else
Q <= std_logic_vector(unsigned(A) / unsigned(B));
R <= std_logic_vector(unsigned(A) rem unsigned(B));
end if;
end process;
end Dataflow;

Hamming code encoder and correction using data flow method :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Hamming_Code is
port (
Data_In : in std_logic_vector(4 downto 1);
Encoded_Out : out std_logic_vector(7 downto 1);
Corrected_Out : out std_logic_vector(4 downto 1)
);
end Hamming_Code;

architecture Dataflow of Hamming_Code is

signal P1, P2, P4, P8, Syndrome : std_logic;
begin
-- Parity bit calculations
P1 <= Data_In(1) xor Data_In(2) xor Data_In(4);
P2 <= Data_In(1) xor Data_In(3) xor Data_In(4);
P4 <= Data_In(2) xor Data_In(3) xor Data_In(4);
P8 <= P1 xor P2 xor P4;

-- Encoded output
Encoded_Out <= Data_In(4) & Data_In(3) & Data_In(2) & P8 & Data_In(1) & P4 &
P2 & P1;
 -- Error correction
Syndrome <= P1 xor P2 xor P4 xor Data_In(1) xor Data_In(2) xor Data_In(3) xor
Data_In(4);
Corrected_Out <= Data_In;
if Syndrome /= '0' then
case Syndrome is
when "0001" =>
Corrected_Out(1) <= not Corrected_Out(1);
when "0010" =>
Corrected_Out(2) <= not Corrected_Out(2);
when "0100" =>
Corrected_Out(3) <= not Corrected_Out(3);
when "1000" =>
Corrected_Out(4) <= not Corrected_Out(4);
when others =>
null;
end case;
end if;
end Dataflow;

NOTES :

● Functions and Procedures:

○ Functions: Functions in VHDL are similar to functions in other
programming languages. They can take input parameters, perform
some computation, and return a value.
○ Procedures: Procedures are similar to functions but do not return a
value. They are used for performing actions or operations that don't
necessarily need to return a result.
● Attributes:
○ Attributes provide additional information about signals, types, or other
constructs in VHDL. For example, the 'length attribute returns the
length of a signal or array.
● Generics:
○ Generics are used to make VHDL entities and components more
flexible and reusable. They allow parameters to be passed to entities or
components, which can be used to configure their behaviour or
characteristics.
● Generate:
○ The generate statement is used to create multiple instances of a VHDL
construct (such as entities, components, or processes) based on some
condition or iteration. It allows for the creation of hierarchical structures
in VHDL.
● Package:
○ A package is a reusable collection of declarations, constants, types,
functions, procedures, and other constructs that can be shared across
multiple VHDL files. Packages are typically defined in a separate file
and then imported into other VHDL files using the use statement.
● IEEE Standard Logic Library:
○ The IEEE standard logic library is a predefined library in VHDL that
provides commonly used types and subprograms for working with
digital logic signals. It includes types like std_logic and
std_logic_vector, as well as functions and procedures for working with
these types.
● File I/O:
○ File I/O in VHDL allows you to read from and write to files on the host
system. This can be useful for tasks such as reading test vectors from
a file or logging simulation results to a file. VHDL provides file handling
procedures and functions in the std.textio package for this purpose.
● Test Bench:
○ A test bench in VHDL is a separate VHDL file used to simulate and
verify the functionality of your design. It contains stimulus generation,
which drives inputs to your design, and assertions or checks to verify
the correctness of the outputs. Below is a basic example of a test
bench for a simple VHDL entity.