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DLD Final Term Exam

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84 views

DLD Final Term Exam

Uploaded by

Muhammad Akhtar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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The Islamia University of Bahawalpur

Department of Computer Science & IT

FINAL-TERM
MCS(Computer Science)
Subject: Digital Logic Design Time: 1:20 Hrs
Type: Subjective Total Marks: 30

Q. 2– Implement the following SOP function using NAND gate only: F = XZ + Y′Z + X′YZ (5.0)
Q. 3– Implement the following Boolean functions using the PAL device as shown above (8.0)
W(A, B, C, D) = ∑m(2, 12, 13) , X(A, B, C, D) = ∑m(7, 8, 9, 10, 11, 12, 13, 14, 15)
Q. 4- Simplify these functions F1 and F2, by using karnaugh map. (6.0)
F1= ∑m(1,3,4,5,10,12,13), F2= ∑m(0,2,3,5,6,7,8,10,11,14,15)
Q. 5- Determine the Q and its invert, Q dash output state of this D-type gated latch, given (6.0)
the following input conditions:

Q. 6- Draw a circuit for adding three single bit numbers. (7.0)


Q. 7- Design a Rom for the given functions
F(a,b,c) = ab+ a’bc+ c , X(x,y,z) = xy+zy+x’y’ (5.0)
The Islamia University of Bahawalpur
Department of Computer Science & IT
MID-TERM
MCS(Computer Science)
Subject: Digital Logic Design Time: 0:20 Hrs
Type: Objective (B) Total Marks: 13

NOTE: Answer all the questions. Draw diagrams and use set theory where necessary.
1- Two cross coupled NAND gates make
A. SR Latch C. flip-flop
B. master slave flip-flop D. RS flip-flop
2- The logic circuits whose outputs at any instant of time depends only on the present input but also on the
past outputs are called
A. Combinational circuits C. Latches
B. Sequential circuits D. Flip-flops
3- The output of latches will remain in set/reset untill ___________
A. The trigger pulse is given to change the state C. They don’t get any pulse more
B. Any pulse given to go into previous state D. The pulse is edge-triggered
4- What is an ambiguous condition in a NAND based S’-R’ latch?
A. S’=0, R’=1 C. S’=1, R’=1
B. S’=1, R’=0 D. S’=0, R’=0
5- A multiplexer is also called as a
A. Coder C. Data selector
B. parallel adder D. NOR gate
6- The characteristic equation of S-R latch is ____________
A. Q(n+1) = (S + Q(n))R’ C. Q(n+1) = S’R + Q(n)R
B. Q(n+1) = SR + Q(n)R D. Q(n+1) = S’R + Q'(n)R
7- 4 to 1 mux would have
A. 1 output C. 3 outputs
B. 2 outputs D. 4 outputs
8- A device which converts an input device state into a binary representation of ones or zeros is termed as
A. Decoder C. multiplexer
B. Encoder D. data selector
9- One input NOR and NAND gate behaves like a
A. Converter C. inverter
B. Reflector D. differentiator
10- How many inputs a full adder have
A. Two inputs, two outputs C. two output, three inputs
B. Three inputs , 1 output D. one output, two inputs
11- An OR gate has 4 inputs. One input is high and the other three are low. The output is …….
A. Low B. alternately high and low
B. High C. may be high or low
12- Both OR and AND gates can have only two inputs.
A. True
B. False

13- For the gate in the given figure the output will be

A. 0 C. A
B. 1 D. A '

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