SKDAV GOVT.

POLYTECHNIC
ROURKELA

DEPARTMENT OF ELECTRONICS
AND TELECOMMUNICATION
ENGINEERING
LECTURE NOTES

Year & Semester: 3RD Year, V Semester

Subject Code/Name: TH-2, VLSI & EMBEDDED SYSTEM

Prepared by Smt. Smaranika Sundar Ray, Lect. (E&TC)

VISION -

To be a center of excellence in the field of E&TC Engg by providing quality

technical education as well as inculcating entrepreneurial skill, self-learning attitude
and human values.

MISSION -

1) To create an excellent infrastructure and teaching-learning environment for

making the student acquire the knowledge needed.
2) To inculcate self-learning attitude, entrepreneurial skill and human values.
3) To impart knowledge required for recent & advanced Engg.

PROGRAM EDUCATIONAL OBJECTIVE-

1) To apply knowledge of E&TC Engg. and principles of basic science & mathematics
for analyzing the circuit of different electronics devices.
2) To compete for employment both in public and private sector.
3) To pursue higher study in E&TC as well as any other related branch for carrier
enhancement.
4) To establish own assembly or service section with innovative, entrepreneurial
ideas.
5) To work with team spirit and social ethics.

PROGRAM SPECIFIC OUTCOME-

1) Use techniques and skills to design, analyze, synthesize and simulate electronics
components and systems.
2) Architect, partition and select appropriate technology for implementation of a
specified communication system.
PROGRAM OUTCOME (PO)-

PO1: Basic and Discipline specific knowledge- Apply knowledge of basic mathematics, science
and engineering fundamentals and engineering specialization to solve the engineering problems.

PO2: Problem Analysis- Identify and analyze well defined engineering problems using codified
standard methods.

PO3: Design/ development of solutions- Design solutions for well-defined technical problems
and assist with the design of systems components or processes to meet specified needs.

PO4: Engineering Tools, Experimentation and Testing- Apply modern engineering tools and
appropriate technique to conduct standard tests and measurements.

PO5: Engineering Practices for society, sustainability and environment- Apply appropriate
technology in context of society, sustainability, environment and ethical practices.

PO6: Project Management- Use engineering management principles individually, as a team

member or a leader to manage projects and effectively communicate about well-defined
engineering activities.

PO7: Life-long learning- Ability to analyze individual needs and engage in updating in the context
of technological changes.

COURSE OUTCOME
After the completion of the course the students will be able to

CO1-Analyze the MOSFET circuit and characteristics curve and understand the basic concept
of VLSI.

CO2-Organize the different layers of MOSFET for fabrication process.

CO3-Examine the performance of MOS inverters using different loads.

CO4-Design combinational, sequential & memories circuits using CMOS logic technique.

CO5-Compare different types of VLSI system design method and analyze the different
technologies of embedded system.
 UNIT-1
INTRODUCTION TO VLSI & MOS TRANSISTOR
HISTORICAL PERSPECTIVE- INDRODUCTION-
The electronics industry has achieved a phenomenal growth over the last two decades,
mainly due to the rapid advances in integration technologies, large-scale systems design - in short,
due to the advent of VLSI. The number of applications of integrated circuits in high-performance
computing, telecommunications, and consumer electronics has been rising steadily, and at a very fast
pace.
The current leading-edge technologies (such as low bit-rate video and cellular
communications) already provide the end-users a certain amount of processing power and
portability. This trend is expected to continue, with very important implications on VLSI and systems
design.
One of the most important characteristics of information services is their increasing need for very
high processing power and bandwidth (in order to handle real-time video, for example).
The other important characteristic is that the information services tend to become more and
more personalized (as opposed to collective services such as broadcasting), which means that the
devices must be more intelligent to answer individual demands, and at the same time they must be
portable to allow more flexibility/mobility.

As more and more complex functions are required in various data processing and
telecommunications devices, the need to integrate these functions in a small system/package is also
increasing. The level of integration as measured by the number of logic gates in a monolithic chip has
been steadily rising for almost three decades, mainly due to the rapid progress in processing
technology and interconnect technology.
 YEAR COMPLEXITY
(number of logic blocks per chip)

Single transistor 1959 less than 1

Unit logic (one gate) 1960 1
Multi-function 1962 2-4
Complex function 1964 5 - 20
Medium Scale Integration (MSI) 1967 20 - 200
Large Scale Integration (LSI) 1972 200 - 2000
Very Large Scale Integration (VLSI) 1978 2000 - 20000
Ultra Large Scale Integration (ULSI) 1989 20000 - ?

The logic complexity per chip has been (and still is) increasing exponentially. The
monolithic integration of a large number of functions on a single chip usually provides:

 Less area/volume and therefore, compactness

 Less power consumption
 Less testing requirements at system level
 Higher reliability, mainly due to improve on-chip interconnects
 Higher speed, due to significantly reduced interconnection length
 Significant cost savings

INTRODUCTION TO MOS TRANSISTOR & BASIC OPERATION OF MOSFET-

 The MOSFET transistor is a semiconductor device is used for switching and amplifying signals in the
electronic devices.
 The full form of MOSFET is Metal Oxide Semiconductor Field Effect Transistor. The MOSFET is a four
terminal device with Source (S), Gate (G), Drain (D) and Body (B) terminals.
 The body of the MOSFET is frequently connected to the source terminal. So, making it a three terminal
device.
 The MOSFET works by applying voltage at gate terminal, which is used to control the flow of current
within the device.
 Types of MOSFET-

 Enhancement type MOSFET- When there is no channel present at zero gate bias is known as
enhancement type MOSFET.
 Depletion type MOSFET- When there is a channel present in a MOSFET at zero gate bias is known as
depletion type MOSFET.

 We generally prefer enhancement type MOSFET. Depletion type MOSFET conducts at 0V and it has
positive cut off gate voltage so less preferred.
NMOS-
 First take a P-type substrate. After this two n-type wells are created on the p-type substrate. Out of
two n wells one act as source and the other act as drain.
 The gate terminal formed between source and drain. A SiO2 layer is exist between gate terminal and
substrate.
 Initially VGS is kept 0V. Whenever we apply +ve voltage at the gate terminal, then the holes which are
near this oxide layer will be pushed away and at the same time, the electrons will get attracted
towards the gate terminal.
 As we keep increasing this voltage VGS means gate voltage, then the holes will be pushed more and
more deep in the substrate. The electrons will start accumulating near this oxide layer.
 The inversion layer of free electrons will get created near this oxide. This inversion layer will act as
a channel between this drain and the source.
 If we apply the voltage between this drain and the source terminal, then the current can flow through
this channel.

PMOS-
 First take a n-type substrate. After this two p-type wells are created on the n-type substrate. Out of
two p wells one act as source and the other act as drain.
 The gate terminal formed between source and drain. An oxide layer will be formed between gate
terminal and substrate.
 In PMOS we apply –ve voltage at the gate terminal, because of that the electrons which are near this
oxide layer will be pushed away and at the same time the holes will get attracted towards the gate
terminal.
 As we keep increasing this voltageVGS, then the electrons will be pushed more and more deep in the
substrate. The holes will start accumulating near this oxide layer.
 The inversion layer of holes will get created near this oxide. This inversion layer will act as a channel
between this drain and source.
 If we apply the voltage between the drain and the source terminal, then current can flow through this
channel.

STRUCTURE AND OPERATION OF MOSFET (NMOS ENHANCEMENT TYPE)-

Structure-

 First take a P-type substrate. After this two n-type wells are created on the P-type substrate. Hence
here two junctions formed between P and N type semiconductor. So, depletion layer formed at
these junctions.
 Out of two n wells, one act as source and the other act as drain. The gate terminal formed between
source and drain. A silicon oxide layer is present between gate terminal and substrate. So, there is
no direct contact between gate and substrate.
 SiO2 layer is very thin. This is known as gate oxide. Gate controls the movement of charge carrier
near the surface of substrate. So, that the oxide layer is made very thin.
 There is no channel initially. The majority charge carrier in P-type substrate is holes and the
majority is electrons.

Operation-
 Initially VGS is kept 0V. The substrate and the source terminals are connected together and
they are connected to the ground terminal.
Assume that Vds= 0.

 Whenever we apply the +ve voltage at this gate terminal, then the holes which are near this oxide
layer will be pushed away from this gate and at the same time, the electrons get attracted towards
this gate terminal.
 As we keep on increasing this voltage Vgs , then the holes will be pushed more and more deeper in
the substrate and the electrons will be accumulated near the substrate surface of gate terminal.
 The inversion layer of free electrons will get created near the oxide. This inversion layer will act as
a channel between this drain and source.
 If we apply the voltage between this drain and source terminal, then the current can flow through
this channel.
 The value of the Vgs at which this inversion layer is created is known as the threshold voltage. Below
this threshold voltage, there will not be any flow of current through the MOSFET.
 Whenever the Vgs is greater than this threshold voltage, then the width of the channel is increases.
Along with this channel, there will also be a depletion layer around this channel. When we apply
the voltage Vds, then through the channel electrons get attracted towards this positive terminal and
in this way, the current will establish in this way, the current will establish in this circuit.
 As we keep on increasingVds, then at one particular voltage, the pinch off condition will occur. At
that particular voltage, the drain current which is flowing through the circuit will get saturated.
 The voltage Vds , at which this pinch off condition occurs is known as the saturation voltage and this
saturation voltage can be expressed as Vgs − Vt .
 For the fixed value of Vgs , if we further increase the value of Vds the voltage difference between the
gate and drain terminal will be even lesser than this threshold voltage and due to that, the channel
will not get formed towards the drain terminal. So, it appears that the current through the channel
should become zero.
 But actually still the current will flow through this channel and this current Id will get saturated.
Because the electrons which are passing through this channel can still be able to cross this
depletion layer due to the electric force.
 Even if we increase the drain voltage, the current through this circuit will remain almost constant.
 a) Operating in the linear region, b) operating at the edge of saturation and c)
operating beyond saturation
CMOS-

 CMOS stands for Complementary Metal Oxide Semiconductor. CMOS transistor consists of PMOS
and NMOS. NMOS consists of N-type source and drain on a P type substrate. When a high voltage
is applied to the gate, the NMOS will conduct and when a low voltage is applied to the gate, NMOS
will not conduct.
  PMOS consists of P-type source and drain on an N-type substrate. When a high voltage is applied
to the gate, the PMOS will not conduct. When a low voltage is applied to the gate, the PMOS will
conduct.
 CMOS use same signal which turns on a transistor of one type and turn off a transistor of the other
type.
 Lets see a simple CMOS inverter.

 In CMOS inverter PMOS is connected to 𝑉𝐷𝐷 and the NMOS is connected to ground. The gate
terminals of both NMOS and PMOS are connected together and act as the input terminal.
 The drains of both are connected together and act as the output terminal. The inverter has only
two states. For a high input, the output is low and for a low input, the output is high.
 There is never a short circuit between 𝑉𝐷𝐷 and ground because in either state only one MOS
transistor is conducting while the other is off.
MOSFET V-I CHARACTERISTICS-
Gradual Channel Approximation-
 We use the gradual channel approximation for establishing the MOSFET current voltage
relationship.
 Using this method we find out the drain current ID in linear region and saturation region.
 When gradually VDS increases than VDSATthe channel length in MOSFET starts to decease. So
another method named channel length modulation is used to find out the drain current with this
new channel length.
 Consider the cross sectional view of the n-channel MOSFET operating in linear mode.

 VS = VB = 0
 VGS > VTO
 Assume the coordinate system such that x –direction is perpendicular to the surface and the y-
direction is parallel to the surface.
 Assume that electric field component in y-direction is dominant compared to x direction.
 The channel voltage is denoted by VC (y).
 At y=0, the VC (y = 0) = VS = 0.
 At y=L, the VC (y = L) = VDS .
 Let Q(y) is the mobile electron charge in channel-

Q(y)= −COX [VGS − VC (y) − VTO ]

 Net voltage is

Y=0, V= VGS − VTO

Y=L, V= VGS − VDS − VTO

 Calculate the incremental resistance dR
dY
dR = − Wµ
n Q(y)

The above equation derived from a Basic resistance formula is-

L 1 dy dy dy dy dy
R=ρ A = 𝛔 wt = 𝛔w = w[q(nµ +pµ = Wqnµ = Wµ Q(y)
n p )] n n
Calculate the drain current by using the ohm’s law
I
dVC = ID dR = − W µ DQ(y) dy
n

=> ID dy = −Wµn q(y)dVc

Then integrate the both side
L V
=> ∫0 ID dy = − ∫0 DS Wµn Q(y) dVC
VDS
=> ID [L − 0] = −Wµn ∫ Q(y)dVC
0
VDS
=> ID L = −Wµn ∫ −COX (VGS − VC (y) − VTO )dVC
0
 VDS
=> ID L = Wµn COX ∫ (VGS − VC (y) − VTO )dVC
0

W µn COX
=> ID = L 2
[2(VGS − VTO )VDS − VDS 2 ]

If we take µn COX = K ′
K′ W
ThenID = [2(VGS − VTO )VDS − VDS 2 ]
2 L
W
 Again if we take K’ L = K

K
ThenID = 2 [2(VGS − VTO)VDS − VDS 2 ]
 But when VDS = VDSAT,

VDS = VGS − VTO

After substituting the value of VDS in drain current equation, we get

W µn COX
ID = L 2
[2(VGS − VTO)(VGS − VTO ) − (VGS − VTO )2]

W µn COX
= L 2
[2(VGS − VTO )2 − (VGS − VTO )2 ]

W µn COX
= (VGS − VTO )2
L 2

Channel Length Modulation-

 Channel Length Modulation happens in saturation region.
 Channel length will change with respect to drain voltage of MOSFET.
 Charge density in channel is given by

Q(y)= − COX (VGS − VC (y) − VTO )

 Inversion layer charge at source y=0 end is given by-
Q(y=0)= − COX (VGS − VTO )
 Inversion layer charge at drain end y=L is given by-

Q(y)= − COX (VGS − VDS − VTO )

 At the edge of saturation VDS = VDSAT

VDS = VDSAT = VGS − VTO
 Inversion layer charge at drain end (y=L) in saturation region is given by-
Q(y=L)=0
 If we further increase drain voltage beyond this saturation voltage then length of channel will
decrease to L′ .
 Effective channel length in saturation region will become
L′ = L − ΔL
 At pinch off point of channel, channel voltage will beVDSAT.
 The drain current equation in saturation region with change in channel length is given by-
 µn COX W
ID(sat) = 2 L′
(VGS − VTO )2
µn COX W
=> ID(sat) = (VGS − VTO )2
2 (L−ΔL)

1 µn COX W
=> ID(sat) = ΔL 2 L
(VGS − VTO )2
(1− )
L

Here ΔL α √VDS − VDSAT

 To simplify this drain current equation we will take-

ΔL
1− = 1 − λVDS
L
λ= Channel length modulation coefficient
 So, drain current is given by
1 µn COX W
ID(sat) = (VGS − VTO )2
(1−λVDS ) 2 L

1 µn COX W (1 + λVDS )
=> ID(sat) = (VGS − VTO )2
(1 − λVDS ) 2 L (1 + λVDS )
1 µn COX W
=> ID(sat) = [12 −(λV 2 (VGS − VTO )2 (1 + λVDS )
DS ) ] 2 L

 Assuming that λVDS ≪ 1

 Hence the equation is –
µn COX W
ID(sat) = (VGS − VTO )2 (1 + λVDS )
2 L

MOSFET CAPACITANCES-
The on chip capacitances found in MOS circuits are known as parasitic capacitance. These are
unavoidable and unwanted capacitances exists in MOSFET due to its layout geometries and the
manufacturing processes.
Most of these capacitances are distributed. Let’s take the cross sectional and top view of MOSFET.

The overlap areas in both source and drain side denoted as LD , they are symmetrical. Both source
and drain diffusion regions have a width of W. the diffusion region length is denoted by ‘y’.
The both source and drain diffusion region are surrounded by a P doped region, also called the
channel stop implant. This channel stop implant. This channel stop implant region provides the
electrical isolation from neighboring devices.
The total length of gate means the mask length is indicated by LM and the actual length of the channel
is denoted by L.
L= LM − 2. LD
Based on their physical origins, the parasitic device capacitances can be classified into two types-
2) Oxide related capacitance
3) Junction related capacitance
Oxide related capacitance-
A MOS transistor consists of a gate conductor and a semiconductor (substrate) separated by a gate
dielectric.
So, it act as a parallel plate capacitance. Hence the gate oxide capacitance per unit area is given by-
ϵox
Cox =
tox

Where ϵox = ϵo ϵr
 ϵo ϵr
Hence Cox = tox

ϵo = 8.85x10−12Fm−1
ϵr = 3.9
The two overlap capacitances that arise as a result of this structural arrangement are called
CGS(overlap) andCGD(overlap) .

CGS(overlap) = Cox W LD
CGD(overlap) = Cox W LD

The channel region is connected to the source, drain and substrate. Depending on biasing condition
the MOSFET operates in 3 regions i.e, cut off, linear and saturation.
Cut-off Mode-
In this mode there is no channel formed because of that there is no connection present between
source and drain. Therefore gate to source and gate to drain capacitances are both equal to zero.

𝐶𝑔𝑠 = 𝐶𝑔𝑑 = 0

So, the total capacitance is-

𝐶𝑔𝑠(𝑡𝑜𝑡𝑎𝑙) = 𝐶𝑔𝑠 + 𝐶𝐺𝑆(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 0 + 𝐶𝑜𝑥 . 𝑊. 𝐿𝐷 = 𝐶𝑜𝑥 . 𝑊. 𝐿𝐷

𝐶𝑔𝑑(𝑡𝑜𝑡𝑎𝑙) = 𝐶𝑔𝑑 + 𝐶𝐺𝐷(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 0 + 𝐶𝑜𝑥 . 𝑊. 𝐿𝐷 = 𝐶𝑜𝑥 . 𝑊. 𝐿𝐷

Due to absence of channel there is a direct contact between gate and body.
So, 𝐶𝑔𝑏 = 𝐶𝑜𝑥 . 𝑊. 𝐿

Linear Mode-
In this mode there is channel present between source and drain. This inversion layer on the surface
cover the substrate and there is no connection between substrate and gate. Thus 𝐶𝑔𝑏 = 0.
 𝐶𝑔𝑏 = 𝐶𝑔𝑏(𝑡𝑜𝑡𝑎𝑙) = 0

𝐶𝑔𝑠 𝑎𝑛𝑑 𝐶𝑔𝑏 both are gate to channel capacitance between the source and drain. Hence 𝐶𝑔𝑠 ≅ 𝐶𝑔𝑑 ≅
1
𝐶 . 𝑊. 𝐿
2 𝑜𝑥
1
So, 𝐶𝑔𝑠(𝑡𝑜𝑡𝑎𝑙) = 𝐶𝑔𝑠 + 𝐶𝐺𝑆(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 2 𝐶𝑜𝑥 𝑊𝐿 + 𝐶𝑜𝑥 𝑊𝐿𝐷

1
𝐶𝑔𝑑(𝑡𝑜𝑡𝑎𝑙) = 𝐶𝑔𝑑 + 𝐶𝐺𝐷(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 𝐶𝑜𝑥 𝑊𝐿 + 𝐶𝑜𝑥 𝑊𝐿𝐷
2
Saturation Mode-
In this mode the inversion layer on the surface does not extend to the drain means it is pinched off.

So, 𝐶𝑔𝑑 = 0

𝐶𝑔𝑑(𝑡𝑜𝑡𝑎𝑙) = 𝐶𝑔𝑑 + 𝐶𝐺𝐷(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 𝐶𝑜𝑥 . 𝑊. 𝐿𝐷

Since the source is still connected to the conducting channel. So, the 𝐶𝑔𝑏 = 0.

𝐶𝑔𝑏 = 𝐶𝑔𝑏(𝑡𝑜𝑡𝑎𝑙) = 0

As the channel is present near the source only. So, this part approximated as two-third part of the
channel.
2
So, 𝐶𝑔𝑠 ≅ 𝐶𝑜𝑥 . 𝑊. 𝐿
3

2
𝐶𝑔𝑠(𝑡𝑜𝑡𝑎𝑙) = 𝐶𝑔𝑠 + 𝐶𝐺𝑆(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 𝐶𝑜𝑥 . 𝑊. 𝐿 + 𝐶𝑜𝑥 . 𝑊. 𝐿𝐷
3
JUNCTION CAPACITANCE-
 Whenever we have a PN junction whether or not we apply any voltage across the junction, we always
get a depletion region across the junction.
Because of that the n region and P region act as two plates and the depletion region act as dielectric.
So, this is the capacitance of the PN junction.
𝐶𝑠𝑏 𝑎𝑛𝑑 𝐶𝑑𝑏 are function of 𝑉𝑠𝑏 𝑎𝑛𝑑 𝑉𝑑𝑏 because it modulating the depth of the junction.
Capacitance depends on the depth of the junction, as junction depth increases further and further, as
we give reverse bias.

All of these surfaces contribute to the source to body capacitance. The height of the region is ‘h’, the
area of the source is ‘𝐴𝑠 ‘, area of the drain is ‘𝐴𝐷 ’, the perimeter of the drain is ′𝑃𝐷 ’ and the perimeter
of the source is ‘𝑃𝑠 ’.
The area of the junction for the source side is- 𝐴𝑠 + 𝑃𝑠 ℎ
The area of the junction for the drain side is- 𝐴𝐷 + 𝑃𝐷 ℎ
(𝐴𝑠 +𝑃𝑠 ℎ)
Junction capacitance of source is 𝐶𝑗𝑠 = 𝜖𝑠𝑖
𝑑𝑗

(𝐴𝐷 +𝑃𝐷 ℎ)
Junction capacitance of drain is 𝐶𝑗𝑠 = 𝜖𝑠𝑖
𝑑𝑗

Where 𝑑𝑗 = depth of the junction

𝜖𝑠𝑖 = Permitivity of the junction

MODELLING OF MOS TRANSISTORS INCLUDING BASIC CONCEPT OF THE SPICE LEVEL MODEL-

 Modeling of MOS device consist of writing a set of equations that link voltages and
currents, in order to simulate and predict the behavior of a single device and hence the
complete circuit.
 Main aim of the model is to evaluate the current Ip which flows between drain and source,
depending on the supply voltages VD, VG, VS &VB.
 The most popular circuit simulator is SPICE (simulation program with IC emphasis).
 SPICE describes the device with a set of equations that represent the equivalent circuit.
 The basic drain current models are level-1,level-2 & level-3.

Level-1 model equations:-

 1. it is the simplest I-V description of MOS which is basically the GCA based model
originally concerned by Sah in early 1960s and later developed by shichman and
Hodges.
2. The equation used in level1 n-channel MOS model in SPICE are –
ID (Linear)µnCox w/L[2(VGS –Vih)VDS –V2DS][1+λ VDS]
For VGS≥VTH& VDS<VGS –VTH.
ID (saturation)=µCoxw/2L(VGS-Vth)2(1+λVDS)
For VGS≥Vth & VDS ≥Vgs-Vtn
Where, L is the effective length i.e., L=LM-2LD
Where Lm=total length of gate oxide
LD= length of source & drain extended bel oxide & (1+λVDS) is the empirical
channel length modulation which is sorting of the length of the inverted channel region
with increase in drain voltage. It increases the drain current.
& λ= channel length modulation parameter.
 Thus, level-1 model offers a useful estimate of the circuit performance without using a
large no. of device model parameter.

Level-2 model equations:-

 To obtain a more accurate model for drain current, it is necessary to eliminate some of
the simplifying assumption in GCA analysis.
 Considering depletion charge and its dependence on channel voltage, the drain current-
µCoxW
ID=(1−λVDS)L{(VGS-VFB-(2ØF)-VDS/2) VDS -2/3Y[VDS – VBS+│2ɸF│3/2}

Where, VFB=Flat band voltage (ie; flat energy band in the semiconductor when a voltage
is applied at gate).
ɸF=Fermi potential describes the carrier concentration in the semiconductor.
VBS=Substrate to Source Voltage .
Y=Substrate bias coefficient.
 The saturation is reached when the channel charge at the drain end is Zero.
 The saturation voltage:-
VDSAT=VGS-VFB -│2ɸF│+Y2[1 -√1 − 2/𝑌2(𝑉GS –VFB)]
& saturation mode current is :-
ID=IDSAT 1/1-λVDS
Where IDSAT is saturated using VDS=VDSAT.

 Level 2 model generates more accurate results than Level 1,but its accuracy is still not
sufficient to achieve good experimental data for short & narrow channel MOS.
Level 3 model equations:-
  Level 3 has been developed. for simulation of short channel MOS.
 It can represent the characteristics of MOS for channel length 2mm.
 The I-V equation are calculated same as Lavel2.
 However the Current equation in linear region has been simplified using Taylor Series
expansion which is more approx then level 2 model.
 Lavel 3 model equation are mainly empirical bios it imprones the accuracy of model &
limit the complexity of calculation and also the amount of required simulation time.
 The drain current in linear region is:-

ID=µS CO X W/L(VGS –VTH – 1+FB/2 VDS )VDS , Where, FB=YFS/4√│2ɸf│ + VSB+Fn

Where FB express the dependence of depletion charge on the 3-D geometry of MOS.
Fs =specifies short channel effect; Fn=Specifics narrow width effect
Ms=Surface mobility = µ/1+θ(𝑉𝐺𝑆 − 𝑉𝑡ℎ )

VLSI DESIGN FLOW-

The VLSI design flow starts with a formal specification of a VLSI chip, follows a series of steps
and eventually produced a packaged chip.
1) System specification-
It is a high level representation of the system. The factors to be considered in this
process include: performance, functionality, size, speed and power. The specification of a
system is a compromise between market requirements, technology and economic viability.
2) Functional design-
With the help of specification, design engineers decide the architecture. This includes
decisions like type of processor, no. of ALUs, floating point units, number and structure of
pipelines etc.
In this step these functional units of the system are identified and also identifies the
interconnect requirements between the units. It is a Resistor Transfer Level(RTL) description
is done using Hardware Description Language (HDL) such as VHDL or Verilog.
3) Functional verification-
In this step the functional design is tested to verify its correctness.
4) Logic design-
The functional design can be refined into logic level design using gates, flip-flop etc.
The RTL design is decomposed into gate level netlist.
5) Logic verification-
In this step the logic design of the system is simulated and tested to verify its
correctness.
6) Circuit design-
The purpose of circuit design is to develop a circuit representation based on the logic
design. This is the transistor level design. The every logic design realized into typical CMOS
transistors. Then define the interconnection between the transistors.
7) Circuit verification-
Circuit verification is used to verify the correctness of each components.
8) Physical design-
In this step the circuit representation is converted into a geometric representation.
The geometric representation of a circuit is called a layout.
9) Layout verification-
In this step various verification and validation checks are performed on the layout.
10) Fabrication and testing-
After layout verification, the design is ready for fabrication. Then the entire layout is
fabricated on wafer. Each chip is then packaged and tested to ensure that it meets all the
design specification and function properly.
Y CHART-

The Y-chart consists of three major domains, namely:

 behavioral domain
 structural domain
 Geometrical layout domain

 The design flow starts from the algorithm that describes the behavior of the target chip. The
corresponding architecture of the processor is first defined.
 It is mapped onto the chip surface by floor planning.
 The next design evolution in the behavioral domain defines finite state machines (FSMs)
which are structurally implemented with functional modules such as registers and arithmetic
logic units (ALUs).
 These modules are then geometrically placed onto the chip surface using CAD tools for
automatic module placement followed by routing, with a goal of minimizing the interconnects
area and signal delays.
 The third evolution starts with a behavioral module description. Individual modules are then
implemented with leaf cells.
 At this stage the chip is described in terms of logic gates (leaf cells), which can be placed and
interconnected by using a cell placement & routing program.
 The last evolution involves a detailed Boolean description of leaf cells followed by a transistor
level implementation of leaf cells and mask generation.
 In standard-cell based design, leaf cells are already pre-designed and stored in a library for
logic design use.

DESIGN HIERARCHY-
 The use of hierarchy, or “divide and conquer” technique involves dividing a module into sub- modules
and then repeating this operation on the sub-modules until the complexity of the smaller parts
becomes manageable.
 This approach is very similar to the software case where large programs are split into smaller and
smaller sections until simple subroutines, with well-defined functions and interfaces, can be written.

 In the above diagram The adder can be decomposed progressively into one- bit adders, separate
carry and sum circuits, and finally, into individual logic gates. At this lower level of the hierarchy, the
design of a simple circuit realizing a well-defined Boolean function is much easier to handle than at
the higher levels of the hierarchy.
 In the physical domain, partitioning a complex system into its various functional blocks will provide
a valuable guidance for the actual realization of these blocks on chip.

VLSI DESIGN STYLES-

Field Programmable Gate Array (FPGA)

 Fully fabricated FPGA chips containing thousands of logic gates or even more, with programmable
interconnects, are available to users for their custom hardware programming to realize desired
functionality.
 This design style provides a means for fast prototyping and also for cost-effective chip design,
especially for low-volume applications.
 A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable
logic blocks (CLBs), and programmable interconnect structures. The programming of the
interconnects is implemented by programming of RAM cells whose output terminals are connected
to the gates of MOS pass transistors.
 The CLB is configured such that many different logic functions can be realized by programming its
array.
 The typical design flow of an FPGA chip starts with the behavioral description of its functionality,
using a hardware description language such as VHDL. The synthesized architecture is then
technology-mapped (or partitioned) into circuits or logic cells.
 At this stage, the chip design is completely described in terms of available logic cells. Next, the
placement and routing step assigns individual logic cells to FPGA sites (CLBs) and determines the
routing patterns among the cells in accordance with the netlist.
 After routing is completed performance of the design can be simulated and verified before
downloading the design for programming of the FPGA chip. The programming of the chip remains
valid as long as the chip is powered-on, or until new programming is done. In most cases, full
utilization of the FPGA chip area is not possible - many cell sites may remain unused.

Gate Array Design

 In view of the fast prototyping capability, the gate array (GA) comes after the FPGA. While the design
implementation of the FPGA chip is done with user programming, that of the gate array is done with
metal mask design and processing.
 Gate array implementation requires a two-step manufacturing process: The first phase, which is
based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip.
 In the second phase these uncommitted chips can be stored for later customization, which is
completed by defining the metal interconnects between the transistors of the array.
 Since the patterning of metallic interconnects is done at the end of the chip fabrication, the turn-
around time can be still short, a few days to a few weeks.
Standard-Cells Based Design
 The standard-cells based design is one of the most prevalent full custom design styles which
require development of a full custom mask set. The standard cell is also called the poly cell.
 In this design style, all of the commonly used logic cells are developed, characterized, and stored
in a standard cell library. A typical library may contain a few hundred cells including inverters,
NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops.
 Each gate type can have multiple implementations to provide adequate driving capability for
different fan outs. For instance, the inverter gate can have standard size transistors, double size
transistors, and quadruple size transistors so that the chip designer can choose the proper size
to achieve high circuit speed and layout density.
  To enable automated placement of the cells and routing of inter-cell connections, each cell layout
is designed with a fixed height, so that a number of cells can be abutted side-by-side to form
rows. The power and ground rails typically run parallel to the upper and lower boundaries of
the cell, thus, neighboring cells share a common power and ground bus.
Full Custom Design
 Although the standard-cells based design is often called full custom design, in a strict sense, it is
somewhat less than fully custom since the cells are pre-designed for general use and the same
cells are utilized in many different chip designs.
 In a full custom design, the entire mask design is done anew without use of any library. However,
the development cost of such a design style is becoming prohibitively high. Thus, the concept of
design reuse is becoming popular in order to reduce design cycle time and development cost.
 The most rigorous full custom design can be the design of a memory cell, be it static or dynamic.
Since the same layout design is replicated, there would not be any alternative to high density
memory chip design.
 For logic chip design, a good compromise can be achieved by using a combination of different
design styles on the same chip, such as standard cells, data-path cells and PLAs. In real full-custom
layout in which the geometry, orientation and placement of every transistor is done individually
by the designer, design productivity is usually very low - typically 10 to 20 transistors per day, per
designer.
 In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to
this include the design of high-volume products such as memory chips, high- performance
microprocessors and FPGA masters.