Devid Money Ha sd Sah L Matis, Digital Design ard Computer Architecture, © 2007 by Elsvir lc. Exercise Solin SOLUTIONS to odd-numbered exerciseswww.docin.comDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin CHAPTER 1 1.1 (@) Biologists study cells at many levels. The cells are built from or- ganelles such as the mitochondria, ribosomes, and chloroplasts. Organelles are built of macromolecules such as proteins, lipids, nucleic acids, and carbohy'= rates. These biochemical macromolecules are built simpler molecules such as carbon chains and amino acids, When studying at one of these levels of abstrac= ‘ion, biologists are usually interested in the levels above and helow: what the Structures at that Ievel are used 10 build, and how the structures themselves are built (b) The fundamental building blocks of chemistry are electwons, protons, and neutrons (physicists are interested in how the protons and neutrons are built) These blocks combine (o form atoms. Atoms combine to for For example, when chemists study molecules, thay can abstract away the lower levels of detail so that they can describe the general properties of a molecule such as benzene without ha ‘ros in the molecule. molecules. tw calculate the motion of the individual elee- 1.3 Ben can use a hierarchy to design the house. Fist, he ean decide how many bedrooms, bathrooms, kitchens, and ether rooms he would like. He can then jump upa level of hierarchy to decide the overall layout and dimensions of the house, At the top-level of the hierarchy, he material he would like © use, what kind of roof, ei. He can then jump to an even lower level of hierarchy to decile the specific layout ofeach mom, where he would like to place the doors, windows, etc, He can use the principle of regularity in planning the framing of the house, By using the same type of material, he can scale the framing depend ing on the dimensions of each room, He ean also use regularity to choose the same (or a small set of} doors and windows for each room, That way, when he places a new door or window he need not redesign the size, material, layout specifications from scratch. This is also an example of modularity: once be has designed the specifications for the windows in one room, for example, he needDavid Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions chapter 1 not respecify them when he uses the same windows in another room. This will save him both design time and, thus, money. He could also save by buying some items (like windows) in bulk 1.5 (a) The hour hand can be resolved to 12 * 4 = 48 positions, which rep resents logy 48 = 5.58 bits of information, (b) Knowing whether itis before or after noon addy one more bit Laie 19536 numbers. 1.9 (a) 2! = 65595; cb) 2!%1 = 32767. (6) 29.1 = 32767. 111 G) 10; (b) 54; (@) 240; @) 6911 1.13 (@) 165: (by 59; (©) 65535; (a) 3489660928 1.15 (2) -6; (0) 10; (€) 112; (a) -97 1.17 (a) 101010; (b) 111111; (e) 11100101; (d) 101001101 1.19 (a) 00101010; (b) 11000001; (c} 01111100; & 10000000; (€) over- flow 1.21 G@) 00000101; ¢o) 11111010 1.28 Ga) 52810) 77,945; (@) 1515 1.25 15 greater than (16 les-than 0; 15 greater and. 15 less for sign/mag- nitude 278 1.29 46.566 siabytes 1.31 128 ibis 1.33 (a) 101; (6) 11000 (estiows) 1.35 (a) 1OLL101; () 116001000 1.37 (a) 10: (b) 3B: (¢) E9;(d) 13C (overflow) 1.39 (a) 3: (b) O1LITILA; (©) 00000000, = 127g: H11111113 = 12849David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: 1.41 (a) GOLOLOQOLOOL; (b) 951: (c) 1O0OLD1; (4 each 4-bit group repre- sents one decimal digit, o conversion between binzty and decimal is easy. BCD can also be used to represent decimal fractions exactly. 1.43 Both of them are full of it, 42g = 1010103, which has 3 1's in its rep- resentation 145 : wot) one bin (0)1 peince(tertce ninary asnbors "7 Sane cheat, biel vette tases) t= 9) TE thintil == $00) dos = doo # 3p Slee 2f (ein{i} = "iy daa doe 42 + ay ies pine? (Mbsd eharaccae Se in the wumber. Any Din{S1)7 , Bee Gecsnat ogsivalant fe Salet, dec! 147 ae nigel. wertanxAcmeoy Eales, mur 8, runztatents2) = 0% Bxercise Selutions soLutions 3David Money Haris nd Sarah L. Haris, Digital Design and Computer Architecture, © 2X0 by Elsevier I. Exercise Soltions 4 SoLuTIONS chapter 1 Las LsL 153.2 1.55 No, there is no legal set of logic levels, The slope of the transfer char- ‘acteristic never is beter than -1, so the systern never has any gain to compet for noise, ate 1.57 The cireuit functions as a buffer with logic levels Viz = 1.5: Vig Vor = 1.2; Von = 30. It can receive inputs from LYCMOS and LVTTL gates because their output logic levels are compatible with this gate’s input levels, However, it cannot drive LVCMOS or LYTTL gates because the 1.2 Voy ex ‘ceeds the Vj of LYCMOS and LVTTL. 1.59 (a) NOR gate: (b) Vpp = 1.25: Vin =2: Vor = 0: Vow =3David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions s LoL veted cop | a hy cof A ase es 163 ap cly St ofa o 1 10 io ofa ii aile 165 : y ajie iio Question 1 D 7 c 2 A eee Question 1.3 17 minutes: (1) designer and freshman cross (2 minutes); (2) freshman re {ens 1 minute); G) professor and TA cross (10 minutes); (4) designer returns (2 minutes): (5) designer and freshman cross (2 minutes).SoLurioNS chapter 1 www.docin.comDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: CHAPTER 2 2a (a) Y= AB+AB+AB (©) ¥ = ABC +ABC+ABC +ABC+ABC @) Y = ABCD + ABCD + ABCD + ABCD +ABCD + ABCD + ABCD © ¥ = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD. 23 (a) Y= AGB tb) Y= ABC +ABC (©) ¥ = AC+AB+AC (@) Y= AB+RD+ACD © Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD ‘This ean also be expressed as: ¥ = A@B\CED)+(A@ BCD) 25 (a) Same as 24a) Exercise Solin 1David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 24 (b) — c 1 v oa © «) a eco ep CY te) i — WS, \. — -\n? I yy <<David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: (a Y= BAA 8 A 6 y= ae A . e vt (Y= As BC+ DE ABcoe = ty \ i J) ai A y 8 203 Exercise Solin 1BDavid Money Haris nd Sarah L. Haris, Digital Design and Computer Architecture, © 2X0 by Elsevier I. Exercise Soltions cy soLurtoNs chapter 2 «@ ) BC D BxC)+(B+0)| B(C+0) 01 9 ° ° o ° ° 1 0 a 0 rio 1 «© BC (B90) + (B60) oo a on ° ° 1 pol 1 2s ¥ = AD+ABC+ACD4 ABCD Z= ACD+BD 217 son @ c) ¢ ~ 2 vy Y=A+BXC+D) +EDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soturions 1s 219) “Two possible options are shown below: y y AB 4B ow om 0 ao 1 0 ol x oo ts oo} x | o fa fa a} x (x 1 | al x |x {a} o nloo | x nfo | x to] x | 0 wl x | o | x | x @ o 246464) 221 ‘Option (a) could have glitch when A C=, and D transitions from 110 0. The glitch could be removed by instead using the circuit in option (b). Option (b) does not have a glitch. Only one path exists from any given input {0 the output,David Money Haris nd Sarah L. Haris, Digital Design and Computer Architecture, © 2X0 by Elsevier I. Exercise Soltions 6 SoLurtoNs chapter 2 2.23 (a) 5. Sy Dae Pas oto of pS of ttt alfa |] eo | a | io wir] sie] o 54y~ DDD, 1 DyD.Dyr DD.D, + B,D.D.D, + D,0,0.0, §, 0, Oo mit a) oo fia oo | 0) 0 | 0 oo | + jo la 0.) oo.) 0 4] on) on] oo ole fre fv wl o |e DD, + 0,0,0, = DDD, + 00.0,» DDD, » 0,2,Devid Money Hacc and Sarah L. Haris, Distal Design al ConguterArchectare, © 2007 by Elsevier Ine Exercise Solin soLutions ” feo or ntDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 8 souvrioss chapter 2 ®) s, 6 », ooo ott oto or to oo} 1] o |i x |: wr ta | x |p) oo |i | x | s a+] o |x ila nia fia) x | x " ( ria] x |x| wo fs |x| x w 1) o | x || x S,-D,D,D, 0,0, D.D, + 0,0, + D, Sy. Dx oo ge, oon wo oof 1 | 1 or | tf x ° wood 1 x x mor | oo x x 1 wo fr) |x wos) ap & |x S.=0, +B +0, Sy" D,D,D, + D,Dy+ D,D, + B,D,David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions 19 s, Pre Pye No oo oto on os po] x is olf: > pel fo fo] xo wo ft x4 nfo fo) x. x sho lo x | x wl f+ | x ox wo} o ifs |x || x ,D, + Dr 0,0,» D, o 1" 10 5,-0.0, + D.Dy+ OD, -D,‘Davie Money Has and Sara L. Mami, Digital Design en Computer Architecture, © 2007 by Elsevae as [Exercise Solutions » sovurioys chapter 2 © 2, 2, 0, 0, = LY > 1) — ~ = H_> { L_} A , , A? | = LY GOUYYDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions au 2as OWE: A ° ° ° ° ° ° 1 Yq = Ay + Ag HAs t Ag xuescocse|> xxroeocoe|p keno oo[> xxxxxHooo|> sexo xe [a Y, = Ay +Ag+ Aggy + Aggy Yo = Ay + Ags + AeAads + AGAAaAy NONE = FAR LARAA, AAA A A AA A yyy tDavid Money Haris nd Sarah L. Haris, Digital Design and Computer Architecture, © 2X0 by Elsevier I. Exercise Soltions 2 SoLurtoNs chapter 2 227 Y= Ardy Ys = AyAy Vy = AyAy+Ay%g Y,= Ay Vy = AytAidg Y= A+, Yy = Ay+Ay +Ay AAA, 229Y = CD(A@B)+AB = ACD+BCD+ABDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 23 231 ABC aly L 0 [Be = —\o00 a ‘001 ‘10 on A too omer 101 110 ad "1 ® © 0 238 “y= Ipd_ NOT * tpl ANDS = 19 ps4 40ps = 55 ps fod Hed ANDS 30 psDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions vs A AAA MAA A, — . Dp! NONE Question 2.1David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Question 23 ‘A tristate buffer has two inputs and three possible outputs: 0, 1, and Z. One of the inputs isthe data input and the other input is a control input, often called the enable input, When the enable input is 1, the tistate buffer wansfers the data Input to the output; otherwise, the output is high impedance, Z. Tristate butters are used when multiple sourees drive a single cutput at diferent times, One and only one tristate buffer is enabled at any given time. Question 25 Acitcuit’s contamination delay might be less than its propagation delay be- cause the circuit may operate over a range of temperatures and supply voltages, for example, 3-3.6 V for LVCMOS (low voltage CMOS) chips. As temperature increases and voltage decreases, circuit delay increases. Also, the circuit may hhave different paths (critical and short paths) from the input to the output. A gate itself may have varying delays between different inputs and the autput, afect- ing the gate’s critical and short paths, For example, fora two-input NAND gate, 4 HIGH to LOW transition requires two nMOS transistor delays, whereas a LOW to HIGH wansition requires a single pMOS transistor delay. Exercise Solin asSoLuTtoNs chapter 2 www.docin.comDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions al CHAPTER 3 33 3.5 Sequential logic. This isa D flip-flop with active low asynchronous set and resct inputs. If and R are both |, the circuit behaves as an ordinary D fl flop. If 5 = 0, Q is immediately set o 0. IF R = 0, Q is immediately reset to 1 (This circuit is used in the commercial 7474 flip-flop.)David Money Haris nd Sarah L. Haris, Digital Design and Computer Architecture, © 2X0 by Elsevier I. Exercise Soltions 2 soLurtows chapter 3 33 rs » oh i a ok ok @ mel ee oe ck al oD Set L L 3.13 From =! to. Nig Wing 3.15 (a) No: no register. (b) No: feedback without passing through a regis- tor, (c) Yes. Satistias the definition, (A) Yes. Satisfies the definition, 3.17 The FSM has 5*= 625 slates. This requires at Ieast 10 its to represent all the states.Devid Money Hacc and Sarah L. Haris, Distal Design al ConguterArchectare, © 2007 by Elsevier Ine Exercise Solin soLutions 43 43.19 This finite state machine asserts the output Q for one clock eycle if A 1s TRUE followed by B being TRUE. Perera Percerts fra “FARLES2 Satan able wih Nay eos for OE AT Per Brrr ‘TABLE Oupa Gb wih Dany easangS Hr Feehe 3.19David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions “4 sovutions chapter 3 Sy = 58 So = 5,54 321 Pere ARLE (2 Se sosoling fr Bxsene 021David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions as "TABLES Site vansion Abie wit binary cocodigs or Eewse 37 5, = 5,85, 5, = Fs, So(Sata* Satp)David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 46 soturtons chapter 3 "TABLE 3 Output ble Fo Bxoeie 321 bay = 5,54 SH Lo = SS cal ae 60) Lp) = 55,4 ,5 Lao = 535)So re. uk SS ~, | | 8, SP “h FIGURE 3.1 Stale machine sitcut fo tfc High conti for Exencice 321David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions a7 Reset FIGURE 42 State wanston dlagram for soda machine capers of Exar 3.28David Money Haris nd Sarah L Mars, Digital Design and Compa Exercise Soltions tre, © 2007 by Eleva as 48 soLurtoNs chapter 3David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 49. TABLES Sat trian more for Exes 37David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 30. sovurions chapter 3 "TABLES Su wanniton wile for anne 32 Se = 850David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: So = SD+S N48) Ss = 5D +5,N+S,NDO S\Q+8,D = SQ +S D+5N SyD+5,N-+8,NDO $1 = SN 45,4DO So = SyNDO #5, 5445; 5648 Dispense ReturnNickel = 8,4 Sg y+ Sp 4S, 4 Sh 4S, ReturnDime = S,+ Sg Return TwoDimes = Sy Exercise Solin stSoLuTIoNS chapter 3 www.docin.comDs ney aS Ha Dig! sir a Conger, © 2907 by Ei Bxercise Selutions soLuTIONs 53 ReturTwodines "> reuoineDavid Money Haris nd Sarah L. Haris, Digital Design and Computer Architecture, © 2X0 by Elsevier I. Exercise Soltions 4 SoLuTtoNS chapter 3 3.25 up uP A Lg “sso FIGURE 3.4 Stu wansiton diagram for Bxerie 3.28David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: TABLE So Satta wore for Exes 373 Sy = UPS,5, + UPS,S, + 5)Sq 5) = 55,4 UPSS, + PSS, Sy = UP@S,95, Bxercise Selutions ssDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 36 sovurions chapter 3 's,s\s, FIGURES Fite te machine hardars for Exess 3.25David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 7 3aT FIGURE 6 Fectoned site asin diagram for Enscine 3.27 “TABLES TO Sexe tanivon able orca Pw Fxene S37David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 38 soLurtoNs chapter 3 "TABLES TT Sane wanton efor cuapar i for Excrse 327 5 = susita) Sq = 5A 455,44) Sy Ty = Tye TyA Py =A AT) 4 AT + Ty X= TyDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 9 oun sy Ss y a s, Reet +— oun me [> x 329,David Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions 60 SoLuTtoNS chapter 3 ear 1 FIGURE 4 Stae wanslon diagram for Excrche 3.28 Qasserts whenever A is HIGH for two oF more consecutive cycle. 331 (@) 9.09 GHz (b) 15 ps (©) 26 ps. 3.331.138 ns 335) ‘You know you've already entered metastability, so the probability hat the Le! signal is metastable ig 1. Thus, PUfailure) = xe * (a) Solving for the probability of sil being metastable (ailing) to be O01 P(failure) = ¢ © = 0.01 Thus, f= tx In(P(failure)) = -6 x In((0.01)) = 27.6 seconds (b) The probability of death is the chance of still being metastable after $ minutes Pifailor) = 1 © 3ODscconds /6seconds = ¢-50 = 1.9 « 10-22 en P(failure) = ese 8 ee = 19x10" 3.37 Alyssa is correct. Ben's circuit does not eliminate metastability. Afier the first transition on D, D2 s always 0 because as D2 transitions from to | or 140 0, it enters the forbidden region and Ben's “metastability detector” resets the frst flip-flop to 0. Even if Ben's citeuit could correctly detect a metastableDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 6 output, it would asynchronously reset the flip-flop which, if the reset occurred around the clock edge, this could cause the second flip-flop to sample a transi- tioning signal and become metastable. Question 3.1 — $1010 AD a=1 FIGURE 30 Stare anton digram for Question 3.1David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 62 soLurtoNs chapter 3 [vem fe fon ee [we fe fon _| [we fe fm | mom TABLES I Sete cannon te Tor Quesion ST S\A AUS, +83+89) Sy = AW) $825,480) 0-5;David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: FIGURE 3.10 Fite tate mochine hardware for Quovion 3. Question 33 A latch allows input D to flow thtiaugh 1 the output Q when the Clock HIGH. A flip-flop allows input D to flow through to the output Q atthe clock cecdge. A Mip-flop is preferable in systems with a single elock. Latches ate pref erable in nvo-phase clocking systems, with 1a clocks. The oo clocks are used {o eliminate system failure due to hold time violations. Both the phase and fre quency of each clock can be modified independently, Exercise Solin 63David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions ot soLurtoNs chapter 3 Question 3.5 FIGURES. See tanstion dagram for edge detect cuit of Question 33 Sp = ASSDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 6s FIGURE 3.12 Finite tte machine hardware for Question 35 Question 37 A Dip-flop with a negative hold time allows to start changing before the clock edge arrives, Question 39 ‘Without the added buffer, the propagation delay through the loging must be less than or equal 0 TU * fun) However i You ad a bute to the clock input of the eesiver. the clock arrives a the recsiver later. The carliest thatthe clock edge arrives at the receiver is tg pup after the actual clock edge. “Ths, thé propagation delay through the logic ismow Given ah ext, pups S0, fpanow must Be less than Te fa RUE Alpeg* atp-SoLuTIoNS chapter 3 www.docin.comDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin CHAPTER 4 sil oon 4 2 : y : ‘6David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 86 soLurtoNs chapter 4 4s Verilog assign y= ok bob | 4b oe | ob tor 47 ext Tay file fon iaiee enooensage': stosete:: Sunes: reeaiciest Howouciie: VHDL Adeaey TERE) use TFER,9TD_OGKC1264.431; ood oo beste P'S (noe a) and not BI) ox Lnoe ab an trot 6D) 1 Cesat band tase ebdyDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Option I: Verilog edule ext t_reattensht)) ize (520), 1) dawtantlate device under test ply cose Wactexs co xiakag Gash of ok Se Bpasetye etsy teatuectors(uect ormun| fiusue Unease 0) PES Bogie Ih ai a (gL ecoupached eg Aleoliy Greiers beruae Shins) anbany Bxercise Selutions soLutions 87 ee Hees. ersuiscascanai.ey Ea ers sand aento Tabs iy dt Sreegers for 3 in 10'dowrto 0 oop use tastvornare ti} (9) AL (VHDL continued on next page)David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 88 soLurtoNs chapter 4 (continued from previous page) Tiboke Une edhe’ trade ivadtotneny)David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Option 2 (VHDL only} yup, Bigaat daar sre teers vecron(3 downcs 0) BRO ctecie_vecvon(s domes 0} wenaos decease pare mapliate, 3) TatE Ss aedaed HORE Boece, ese eastuectoreio 1) Bxercise Selutions soLutions 89. process’ (sin) beste Process (eb), beste Pe Cuutewent and elk = "94 and eanet = 40") chen 16 fhe x tcuee taggers (ogee ean mitbeeiaonpietedvoseeetutly." (see Web site for file: tst_utilvhd)David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 0 soLurtoNs chapter 4 49 Verilog VHDL. 4.11 A shiftregister with feedbsck, shown below, eanpot be correctly de= sctibed with blocking assignments, OK faaDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: 413 Verilog atways 8) 45 (@ Y= Ac+ABC Verilog sodale oxlisalinpet_ 9, be 6s ste he esse y= EO) | ee ob Wb) ¥ = AB+ABC+(A+C) Verilog bo loots Bxercise Selutions soLutions 91 vu VHDL Aibeasy 1650) veo TEEE.£TD_to0re 164.117 scsty oxtise fo post(s, Bat in ST0_200%¢; pe” She sti=toeie) Sana RSE b ote) oe (nor Band )7 VHDL. Livracy 288; wpe THEE.72_oste_11s4.aly eresty exh tse be Portia, by st in eth testes (ot BI} 9s ((508 =) and & ond Gest elon tase 21David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 92 soLurtoNs chapter 4 © Verilog oe a eee Weegee tal teebeal | 47 BCD + ABC + ABCD + ABD + ABCD + BCD +A, VHDL Libeesy MERE) une Hens. srD_Locre anes Speer By ey a in. Srp Loar; eS Coe Seow isetey architecture behave of axle ts PE (pct a) ane (Oot b) and (aot =) and ‘net )) oF Vieot a) aad (228 B) and © ana [act 4) 36 ware act) anda) oe Inet aly VHDL. Vibesry TREE, ee SERRSTtectEaMedg!David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: 419) Verilog (7001 = Tao! stays 9 Cry 23) Bxercise Selutions soLutions 93 VHDL Peseossta) Sepin ohece) 2 SS ellie aco Gganpines 8 ele GO + Hy .David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 94 soLurtoNs chapter 4 442i Verilog VHDL sodas aonthitéaye input [3:0] aoethy ibesey IERE) wae SEEE.S0D_LocIe A164. at) 423 3 . wor Fewer se ak gy cn van ( ‘a * ify a 5 ee ee iaken LA - kon _ pre taken Been FIOURE-41 State wanction diagram for Eeersie 4.23David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: 4as Verilog edule j2Elop (input 5p hy lly output £09 6) svaye @ (poasdge cb) cise (rl Bxercise Selutions soLutions 95 VHDL Beg or aesDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 96 soLurtoNs chapter 4 aar Verilog ‘ouepar exg (1s) 15, 36)) U/ state Register Staaye diperedge ele, pocosge reset) 1) wont state Logid Stasye ei) ‘ate ineatell © die next a= VHDL oy" tbs Snoat ro_accie vaeion|: downto 0) type etatetype La (50, Sly 82, £2)) eccersicy fetes) Sepin pregoee (etates sa, =) beniDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: 429 Verilog Steps ag Sega alvays @ (goasdge cll basse Bxercise Selutions soLutions 7 VHDL Pedcossteti asinDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 98 soLurtoNs chapter 4 43l Verilog Slaape diperedge ele, pneesce reset) 1) wont state Legis Shaye er 1 ourput woe VHDL encity igh 66 1a VO Gus smeauecsely Sype eestetspe 12. (80, Sly 82) pregeeeicly fetes) Segin fPrcsoee (atater a) 6) begin sper sa = + sheDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: 433 Verilog seg (2:9) atatay next Wit 3° (atlinewterate —os2) S2) 15 (a) nextatate = 84) Sit 3° Gh nexestate = 183; else lnexcetste = 80 Bxercise Selutions soLutions 99, VHDL you i2 (£0, #1) 2, 3, 607 when 51 =Ay, Ag, Noes = AAA, and so on. The priority encoder’s delay is loz input AND gates followed by a final row of 2 isan (ND) covder is nput AND gates. The final stage OR gate. Thus, in general, the delay of an N- input priority en- 4pd_priority = (lOB2N*Dtpd_ AND? * "pe ORN?2David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions a yu % HRM MIN KINY, UU Y YY YY Z Z Z [FIGURE 5.2 Bengt print encoderDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions uaz soLuTtONS chapter Verilog nodule peteeityekt (iapat (7:01 2, ouepae (2:0) 37 wise (00 91 U1 cow of tmverters ee Sears) coe Bie 2 Beara] © Sorts B01 BeaeU2] Searls U/ second vow 9% 389 gatos gr nis abate a Se at ARMA] 11 this dee of a8 gph gp Searcy a (on 912 = RHODE wT Sesion Ah Mla ap Lule Jason ARO ACH vhs yop VHDL Porter dn ETDALSGI VECHOR(T dounto 01) Ss ove SunLoGtSoMcTORG? duet Olly ‘signal yy ‘$19_LOGECVECTOR|? dovato 0}, = thie row of aN gat aid) Sng yay se) apd MN Ca ane39 Verilog edute as22 (input (5110) 4, fousput #09 (9140) tir David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: saps (2001 8, wire [2110] Sy Rexty seeige aout = F121 7-8 Stag Poa ete rds atusys # (9) cae (F190) sins Bxercise Selutions soLutions 143 VHDL ee ZEEE. STD_LOGIe 164.212) ee bbs sta iopiscaeishs3iy She Stectecielescron(an ounces 7 prowess (FC dounto 0}, 2, Aout, 8} bagin ‘end provesDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions aa soLuTtONS chapter s2léepue (2110) ny By input 12001 F, Gefper eg (21001, wise [21:01 &, souty soatgn Rout - 72] 7-8 4 54 Sinise Sa bows eda yea, stays #0 fare F123) Sheu + ona aca fElago| «80 sala] ¢ saat dost aiid oversiow en SADIE BEY ES HL 1 vrcithgceratay AERC RBU 6380001, VHDL See ieee eta_iogueracisa-aily Dorey Bt dn S1D_t0CIC_vECTOR(3! downes 0} t Te “Hrouccr@vaczon (2 dawsea 9}y Rave < not) when (EI) = 12") wae 8) eons peat oFO) ‘eGutdedvoas)ov90ngoubotoeoRgoo* <-se8t)y 2 Feconst te asouye sy» A BE megDevid Money Hacc and Sarah L. Haris, Distal Design al ConguterArchectare, © 2007 by Elsevier Ine Exercise Solin soLutions 14s 5.13 A 2bit left shifter reates the output by appending two zeros to the least significant bits of the input and dropping the two most significant bits. A Aas Ae FIGURE SS 2.bie left ter, $2.0 npr and our Left Shifter nie} VHDL ecsty Leteoniee2 HaleDavid Money Haris nd Sarah L. Haris, Digital Design and Computer Architecture, © 2X0 by Elsevier I. Exercise Soltions ae soLustovs chapter § sus sham, Ao sham ant ° shat, f Ano u ° Ant Lig l Ano ! so aaa a [ct ot ! ao ° -y, ¥ % ¥ % 1 e 1 , | ° 1 FLOURE 5. Si et sir sing 2821 amie sur (a) B=0,C=4,& (b) B= Ay. (the most significant bit of A), repeated N times 10 fll all N bits ofBDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions wat 59. ‘Recall that a two's complement number has the same weights for the least Significant N-L bits, regardless of the sign. The sign bit has a weight of 2"! Thus, the produet of 10 N-bit complement numbers, y and is aitNod v2! “The two negative partial products are formed by taking the two's comple- ‘ment (inverting the bits and adding 1). Figure 5.5 shows a4 x 4 multiplier. Figure 5.5 (b) shows the partial products using the above equation. Figure S.5 (e) shows a simplified version, pushing through the 1's. Thisis known as a mod ‘fied Baugh- Wooley multiplier. Itcan be builtusing ahierarchy of adders, a Cy FIGURE 55 Maltipher (a symbol (b fonction, (0) sph fnetonDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 148 SoLuTIONS chapter 5 sal Ay? a KSB RRS PPae © FIGURE 56 Zero extension anit (symbol, (b) andr hander Verilog aeeiGlapa: (20) Relencpet (20) 2 VHDLDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 149 sas (a) 1111 0010 . 0111 0000 = OxF270 {b} 0010 L010 . 0101 0000 = 0x2A50 (©) 1110 1110. 1101 1000 = OxEEDS sat (ass (b) 000.0001 ©8 0.0625 529 @ OxCOD20004 = | 1000 DOL 101 0010 0000 2000 000 0100 1.101 0910 6000 9000 0000 01 x 22 (072407020 =0 1110 0100 100 0000 01 L1 9000 GOLD D000 1,100 0000 0111 0000 001 2!°! ‘When aciding these two numbers together, 0xCOD20004 becomes: 0.x 2!" hecause all ofthe significant bits shift off the right when making the exponents equal, Thus, the result of the addition is simply the second num ber 072407020 o) ‘0xCOD20004 = | 1000.01 101 0410 0900 000.0000 0100 1.101 0910 6009 0000 0000 01 » 2 0x401C0004 = 01000 D001. 101 1100 0000 0000 0900 0100 -101 1100 0000 0000 0000 O1 x 2 1.101 1100 0000 0000 0000 01 = 1.101 0010 0000 0000 0000 01 x 2 x /01.11 1101 010 0000 0000 0000 00¢0 0000 3400000 0 1011 1111 OF1 1110 0100 0000 0000 0000 0060 1011 111001 x 26 (0x3FF80000 = 0.0111 11 L1 111 1000 0000 0000 0000 0000David Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions 130 SoLuTIONS chapter 5 Lath x2 OxDFDEM000 = 1 JOLL 1111 101 11100109 0000 0000 0000 0000 1101 111001 x 2 Thus, (LLL L110 OL x 2% + L111 Lx 2°) = L011 111001 x 2 And, (1.011 1110 01 24+ L111 28) - 1.101 111001 x 2= = 0.01 x 2 =-1,0 x 284 11011 1101 000 0000 0060 0000 o0e0 0000, OxDES00000 “This is counterintuitive because the second number (Ox3FF80000) does not affect the result because ssorder of magaitud bers. This second number's significant bits are shified off when the expones are made equal sal (a) 291 9-275) = 2? - 2-24 = 4.278.190.0738 (b) 228! 1) =2°2 2 =4,294,967,204 jess than 2" of the other num- (6) 46 and NaN ate given special representations because they are often used in caleulations snd in representing results, These values also ve usefil information to the ser as Felum values, insted of returning garage upon overflows, underflow, or divide by aera,David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 151 533 Axe Be EPA, Marth, E9P6,, Mart. Exibyy EA, Cote tee 2 * ® Fo 8 ‘fom ii Exponent 2 Garmare irra 3 | 3 * g | 3 Exiye ExpAcEspB sharing BE) A < Ere8 shay ExpAcEspS MantAs MartB,.. SpA < E198 Mori, ai, Sham, shit 5 Mantissa & Shinedlant Preeti i a ‘ad vatesas i and Normale g a a z Frac z D9 Facts. fal Sao (b) FIGURE 5.7 Floating-point adder hrate: (a block diagram, (0) underying hardvareDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 12 soLuTtONS chapter Verilog nodule fpde input (21:0) 3, by output [21:0] 217 wise (7101 op: Shes [22:0] manta, manta, shanty Gite fier Pract fst20ez21, m3, 220114 fetao.2a1, imei, b22001}y VHDL sroninactuve ayath of fonds ta Po taleerbe on ta $19-tecrCMgeror |? downto O} fut etm recre.ymenar 1 daunes i gH6rah, SMB De, (Pep: STpQI CIC VECTOR Pdownto B+David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 153 (continued from previous page) Verilog vuDL nodule expoonptinget 17201 expay o4pb, Library seer ooo tame ers tocte_t16t.al4y Soper eg 1 CE Herlimciasieewesss) | sire (720) animus, abe ran? downto 019) atveys 2) cep = eeoas tinces oo aiph = Sate: endnetnle “Sep & supe sinen aleash = 13" ele (continued on next page)David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions isa soLuTtONS chapter (inpas ascot, seput (23:0) ear ascby angat’ atl Seepat £09 wire [22:0] shiftedraly (eanes 5» shane| + (antl >> shant staaye €1+) SP Garant (1) | anamel6) | ahane 18) (hone |) eansne 31) eit 129-0) nae antby shine, tnpee [146] e airamwletzel 2 Soaresuie (7321) + soaresvi (7220) assion oi | f/- Gogrdeate ae 4 (continued from previous page) VHDL See THRE.etd loqia_anoignod.s1iy fpeevislessb: oa 319_200x6) sertb La Suvecron {2} downea 9} ont: in SyaLuccatuvacror|? downeo 9)p ea snteoer tunesgned znane) Slee st0_togra, oncom (ahsfredea| Trmanr | th SB. rociuurctams3 anne 08www.docin.comSoLuTioNs chapter 5 www.docin.comi zg 2 z piad%David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 138 soLuTtONS chapter 5.35 (0) Verilog nodule peefiased(inpa: (21:0) 2, by input etn ctepae (31:01 ay sutpet costly wire [30:0] by gi W/'p tos prafluas foe cone 1 hee TEsCI" pl, par 3 of PSP Cire [18se] 0, 9, 98, 98) SE pang tow la, by pe oie Blactoos 044 (/p( 01-28) 6(261-p (28) -p(221- Pla plielepLel pial 2t PLL. ptaL pte lepiel e131 pL0i be POH pavep eee) ple ploletuiepbsl pli) epi Plott ciSL pt) p aie Boh, Sani a(8) (Sel 2104).9(221- Som atielcebel sala) egic2y” shanigtal gt OM aM gi1)eal21 Shalestlcabosh2(2)-34aahy Sai. 3t71 aist-9t4,3 icin VHDL Pier tail, ghke in atm-tocre_vtcron(:§ dovnes 095 I) dejs taatnctorseacron 8 owt 93 pore (a, beige an art toci@NBeron(3t dosne.a 0) st eth toee.RarDa(a) dounta 9)) PEO, po DROS, DEI oa 8 ga Ecwmnemy pie DDeidiep 2)ept-d)sp(sreptersbee)ap\2)ep(ahi + ome ‘Stisiea!a)egt-Dsatsrectersor)ael2] cata? pale Dpiisieps)epiai spt aveelapisyep|s)°09 one Pere Haylie Ay aIk 2, BRIA, aki ty (continued on next page)David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 159, (continued from previous page) Verilog bisekbox cov2((pif181,p 128) pii131,e125),p2 011, PIG GLIS1 p71 pic 7p), BUENO p12! 315] 0000},2110) Ser ane T2 ips Ear ese “ata e101, (2 pest, iziph eT Bien, eine GqAlhely (28,90 131, 91251,02 101, S211, S416, 9 1291, g60 7 gtk), EN at91.4312! at8] 3800, 9110) QE is eases, Bien Bint aalcel, Bap eisai, bzokoe cow (e226) -72104) (08) -21271.82112), PaO) Fs (20) p81 pa] ee e1 pllel-pitilae!(2 -p2itl-otletre (Ld, Teates 3) he 4 bbc deed watt, ig tsi erie gt (se1.g127ie21001, G2 (iu), 2: 110}, 4 00), 32 7)-02 Le), gleleai tie 22h -gtia1,s112, [eatGabe MT, 43 1 Ne 4ig2 (51 ata Ny B30: VHDL pik2 2 pt (5) op 126) 692 (12\cp(25) een 120 € pleat (ep iiitepi(Mepasne PhS}eg(0)ep4 (2}epiS|epL ep y etka ce giasreg@eyegs 12925) egt ane SGD eg 69 47g cgay mie . [91 (2431 (89691 le}egi tslegt @DEgT CE Piero unre Peas aka, eka 92005) co ay eps nap sBOHED ve PACD) REED ep 8 FpeC Nem Ce Pute)emtaa)ep2 3} e242) apt 2) ep(2)2 hd museg dae e 90H ane sUimpsavenoneg 19) seen sy 1095 Dens prsspzissspaiiiiapedste POTE nepiDINS, GTS. DLS OAS BH 94 (cominued on next page)David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 160 soLuTtONS chapter Verilog Dackten cowd | p3(251121 621130324 Pillai pt251 2174), p2ltispt alee 21, Cetpatii1h}, (tp 13191, gptiseial, g8taa21, ghiitl,g12%hyea (tsa), pEateatiiarn, (eigatkti ny, (ete i011, Dlackon cows |ipd(1504]-pa(31e81 21881, pital ptibi), reine (toed 3{t8) 99/908) giaankn, isteh oi, sean vou 195,96 (7: 149 92(380),-9212 049119), atody 11 geveeste oti Sesign cout 30a) € aft) Gsca ett) 1 bay VHDL Pika co pI/35 downto 12) €)) Bogie 5 pte ane cpg $i) Ge Be or tbik anaegh: Toy arn seoete veeTORETaDaneS 0):David Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions ez SoLuTIONS chapter 5 5.35 (c) Using Equation 5.11 to find the delay of the prefix adder: "ra pe * ENC oe petin) * KOR We find the delays for each block: yp = 100 ps 4pg_pefix= 200 Ds Bxon = 100 ps Thus, ty = [100 + 5(200) + 100) ps 200 ps = 1.2 nsDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 163 5.35 (d) To make a pipelined prefix acider, add pipeline registers between each of the rows of the prefix adder. Now each stage will take 200 ps (plus the sequencing overtiead, fy + fon)esDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 165 535(@) Verilog ance rext elk, aL Motel per ie Hopi ov seed, Piet oh (ean es 4035) ‘fLopt_potcie, (01281, 6127),po}25, 991231 eo4241, pe) 89111-20135), [PO(1514b0 (2290131, 00171-p0is1 pels), 2014), 9129) ,0012 401251, 9(251,901221,00)19|,a9(271- 4912514 ‘9011317a0/3.)fg0(3}- 9917100151 -<013] 901101, (pts29ij412pbjastyet 231yenizstye 91s oLL0 BL sh PUUAST sph (Deph hoe oB8 9 ea sn1(29) 02 29) ,98 (251, 9 (291, 92(231 93 29|, a4 Mpa) Sua31 642 5/431 ¢gH Ma |9),93 3}, f4) 95 4{p0130},p0 281, P0126), p0(241,p0 22), PbL29)99(201 ne [26 Beg (12) OLLaypeoKs) co el -pAs OTe], LOT 0l29),pat271 50a) e091. 9 (24), polt9},28(47Irec ter 6031960 (17 P0191, pOIP1, BOTT, p69) parti "BOF, 4901301, 391281,20126),90 (241, 991221, S129), a9{ehesc ie) ¢30 ee, 99122] $0L40}, 9918), G01 61,9014 aD{21, 9910) 90129), 99127) 20 287,90 (291, 99120), SolaayeaatarNysct ae y30 23-9943) S191, 99101 a6] 81 31 90 L tO), (301,63 (28) 43126) (241,04 (221,82(20), e129) yet 361 pt tlt aloe 20d gP Siledeea yet 2 etal fy 491(901 93 (28) 1921263 (241,41 (22),91(20), (29) 91/36) ,44 14], gh (a2), 94 (30],95 0 Bleeatonatla atl WH xen 2 flop 1G) Hop2pg atte) Ate t ih (tea aeny ioe ey Hhopt_patelly (o1(26027] 9224-291 e1 20049} yp3 16038) p01, Piteeop: 8a) a0 olyDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 166 chapter 5 gui2ss771 92 (2422811 (20219),01(26225) 1128101, Glas s),gh 4s) gill (p2tze025yp2 24223), 92120218) -p2 28215) 9212211 alee) epa(tes1-p2t01- 2128229) .92( 24225) 921200994 9234891 32U12801 Selesitegivess).g2t0is 41 (30226) 9125225) -p1 (22221 -p1118:17) . PLL] -p11 1088) -p1(9¢5) 912211 | A2epntze))e (2IDLIZE HH, IE ZINN, ABIL. 2ep121 16 went WEBI) 1, (2IpEIO1D) be {01 (30228) 92 (25:25) 91 22221] 01 (28:47) 4124228] 0114028) ,02(528) 012211 | aeanteiy ye ten IZeIN1, BIaEZOVN, BLE, ACaLEZI Ne zante WBodlahi 1, (2ia8 0101 be 49230228) p2(25:25) 02 28221] p2(8147] 92024225] p21028) p20 525) ,02(2211 {e2430228) 492252251, g21222211 92382271, g2ta4s231,02tdEwtvo2 (625)-42(2211 11 208 3 Thee #12) flop3 oa 1 elk UdlEa HD, fo_a 3.01.21; Hieg #130) fLapd_ogtediy feei26s29)9pH(40:251, 2213027122 1201, of [2es24],92{ 18215) 2130-8) fy t©3 26225] ,p3(13:13) 505 (20:7]4p9 (2201, fos [2e224)yo3( 8213] 98 12087] 4081226) get 20;20ig21cask9) ope(idsta) 5216: 3)h0, Paodico if Seeaensy Wiralaa uapeain b (2foGe24) ab 22:48) yaa zeeab) v2 (6:31 f Migatz6! tla ta(gatior yy faieapea} iy caigerayyy fpatse:2') pafaHt8),ostieeas ype es3| (e3f 0:29), (22119) 3314s) ye) [6311 Wy 208 4 Hop $156) foptegietk, tp3]a2i25 1,369), 82218) 03160017 tet 122135) 91/ 61004 ettezeasy gti seannny p3{30+23),p9(24:9)), (s9@9122))), 80636), 43120022) 03(36:70), Cregece2ni), Batre (eatseeas} patets7) (eatses2s)yatctea7) hy Wy wo. 6 Bop #2) Hops oa Moth, Hata, joa e181 fie $96) HlopeceaTedky fedlZave)egtT 00a) yy Wes [26s0),45(610))39David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 167 persoe1st t1eeea38) gatos), Tecaa nati i. pstsasIS1, g0(s0-1511 foun ove leit, (a3/a.4 5), aby BBs 892 Sesioe cout = (as(34) = bS(311) 1 199/30) s @siaty 1 Bs(saIn soaute pandg|iaput clk, Laput (3020) a, by outpus zag (5020) py git aluaye @ (poseaae cue) soduie Elgehbox(iapue otk, Anbar (1826) plect, ostant, ‘left, usishty outpace (15:0) peat, S204)? alnays @ Iposedse cto Ponte suffieplt ik inpis Ho) wie, Bieleow Nee (28) 2 F alnays @ Iposedye ct aluaye €Iposedge ostDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 68 chapter 5 535(@) VHDL. Ee'b. a: io SHE tecHe vECrORIS1 apance 0) = Sie Ste tease vaczonist dowce 0172 ‘@:()fJour Srb_toeze_vecton vidi 2-1 downcc ong pereiell ke er neezes porbicca: 1 aroBeac; Poy. go: Le af namie vecdonts9| owes 097 Pt tote aaetacssey PE gthcaat SR LoeIOAECTORES S| owes OD [pir g2s tn BED eeIG_NECTOR(39 domes 0}4 pay qos ove SEBLuccIe—usezen(99 dowse Oy iy gle to ao soeke wweroR(39 doento Oy <= p and 9 pretines tox roe 0 — $ ‘igtel poy pir pay 8) Bly EF §7D_20GE0.VBCTER ISO seunte 0)David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 169, Signal gslatis STO-LOSES ¥ECTORED downto Oz baste fuego? fob genesis 0152) poet Flocolb: {op genesis 0132) post fLobi_BE flap veterie mapta2) bore Eieeeb: i op geuerks =avt32) burt flges i Sop genesis aaptJ2)l port fleptie: flop genesis apt?) port Beech: Gap gossels eta ore 2) ahi 53, any ~ fing tte,» aad 3 for goluan 2 Bae Si: MSE. Bice: gore mena ff Bilby} ‘Abe: foes map (elke s 230 ae — gerevote sun snd cout cout TEE SE) and 662) ox «GE 130) ond (ERR) oe BERIT) Sort (elhs da 24a. zo0r5y Noy bs Sa ST2-400EG VECTOR (30 downto 9)9 By gi out StoLasrelvecton (a0 doves 1pDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 170 chapter 5 reain . bik, pls ales ae pli alls , Eoin bij <= Bie ad okie OL) aie OF abe ape oki: eng veces; Albeary IEEE) use T2=E-57 a6036. 1964.41, a "ooua Srapiecie weezer 3 dommes 0175 Weskidecuse Syacnjpe Quneach is oo fore ‘“ Eh Sreatecie-vecron(widei-t cenmto 694 TE ChdSeeane and clk = 12" eenDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Lioeaty TEBE: uae IEEE, STO_LOCIC_A16¢a1L; use TEBE. S4O_L0G1C ARES. aLLs Saat aesuiveceure aysth of row ts B2%, bed: La SIO EecIC vacHOR(:S downto 9); G24) Ghd sro_taeic_wnezon(-3 dowsca 0): Bi}! vnllode. 31> LEGKGVECTOR (LS downto O03, Sit: our SuD.Lecie VECTOR (LS dooneS OD} sheet at aeagesten ye |) | ‘slgne? pot_in, pyt_out: STP_LOGTC VECTOR(29 downto 0); a0_te <= 1p0(29) 490027) 40026) 4p0 129) 490211490429) 029) 4p0 (1514 Pod) 25 4p ep0 19) ae8 (91 9 (or a80 Oh ERODE 2D1@) 30127) (28) £90 (23) 699 21) 490 (25) 490 (271 699 2896 $03) 439 10490 [9] £481 449 (8) 439 4901) ftopt_pas fep generis mao (20) pert wap (oily Bgd-tny patel) PLES) <> pat_out (291) el ATS pet_oue 2b) LES) pat_ovt (2717 BLGS) <> paimeat (20h) BLED) < poiroa tasty etsy < pas eur2ty et GM < paieut (aay) BLCGE) S> potmoat (231) pt i23) So pareve 2t}y etn) = paimaut 20)) SEG! se polcous(tthy ghi27) < pareve (131) gt (25) < pai_aut (i2yy GHGS) ss potlowseiayy guian) <= parceutO}y ghG9) <= patmeut iy SHOD Se potloue (Bhp gts) <= pes_oue i) 4103) “> paimeat ely GUUS) <> pel_oat(2)7 gh) <= pol eut(siy" gi) <> pat_avtl0)y Bxercise Selutions amDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions im soLuTtONS chapter iE © ipoeainep9¢28) 400 26) 00 12614994229 e020) $00 E4086 ‘otk.0 < igueainsgotami ser te) sao 2tlng%¢aah san 20) 0 ES 4a0T8)6 sas.o « (pbizdeonte apo tstspt\estapstzipe cote ee p90 314 co EER Ep YORI! BIEELBOH BOS MApIELL, DIKO, PED, B1KG, ORL PIDD, 912.017 PIGO) <= pLLICs; BIZ) < pIz.NELds pIe) < pis.e1s) plus) <= pions; eliza) < pagtetts pitao) < pie it) PLite) <= pilaster ie) < psi (ely pLual <= ELT: phiiey * pllaesly SuCo) <= Bll 00317 BL) pL Oat BLIS) co pi) O¢e)s puis) = puLOlD}y Buda! <= BLL DU? BLIO) <= pL OtOrs o1ts0) «ats acsys ane < 2 8uns ae oLLelsi: Shae Bente Ob fod deaponedt: Fcighccrs. slp 19 suectctulten pategeeys Sigeed pokes glace ghia POEL HIG! Sadiadede’hetcontss downto 01» a 128 downto 27} 24 de 23 20 9) ¥2(20 dovnte 21) < vga cut 29 downto 22) P2120 dounte 23} <= pgaveve (9 downto 26)David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 173 Tp1{s0 aovaco 28) 41 126 aousto 25) 91422 acunta 2394 soe been pz t30 dente 29) < BAe donee 17cm bik Bye ty oe ota, etiars pid bas cows 26) 89 23) So BLy Las cewata, 2] C0 Attest pl 1taiuwito! 011 BLS ewes 8); (it downto 231 <= pss 31? downto 69) p2(20 dowata 8) [B2¢6 Gounte 3} <> pij1(® downte 5}; pele aowata 3) 220 downto 29) < gl}.10 dowto 14) S226 downto 251 <= gL} 11G9 downto 121 SEG cownto 2) © gL} 4{a2 domeo $01; SPGb sorete iI} ye- ghiuss coments Be 0 devadt 3) Soha covngo 09) exile Syne’) BG connto\s] “Vs @ downs 21,)aah2 domes 2) port teats be so tosisy ronivecture synth of coud to i 980. FOCKe YECTOR(25 downto O99 Uh Srockecienvaevon(ss dawats 9) Gu gr tecre-veeran{i5 dowses 3) Sie Sroitecrelveeron{i3 downs 9) Fp ns ‘ond components Mir fn Bra_togze ureter wsdth-t downto 099 Si ous BeaLnogseLuecren wcdth-t downto 943, fond component S slays vowee os Spa downo Oh7 rf onneo SOE | MowscelsDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions im soLuTtONS chapter Sioned piA2, Gk 2, Dedze OIA2, pote) gible! SIOLticie-VebroRIs abance obs reain BSUIU dovats F< aos aut (21 ovate oik.2 <= (G2{5) downte 2ipe0a (22 dave L316 Des.2 oe ibe i2bysszaeyspeczey sna 26h DE{UODGa2 sspe ushen2 (cals pain) so2quopsp2 copep2 (att peistapeca)apzicyspe tdi e for1_2 < pL 2cbsewto brs E2490 covavayzr) eat] 2108 dows}, [aide colato 19 © GHP at ovate 317 BEd Source 23) gid? dowate 017 $318 dowsso 3) < 914.213 downto O14 ey 9: Ln BTS EECHE VECTOR|20 donne 0) Bay ges oue SroLtecze_vecren(20 dowats Oy Dik, pki: in OTE Teese YECTOR(:5 downto 8) Sik, ges in sxectecsecvaeron(3 owes 8)y 1 dowte 8)David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions ws eain ‘Lopa-ea: flop generis maptoo yore rap (ait, pyvaer paso) Date ceunte bc pou-auci2i couse sit © (p36) 858) 3,8) 318) 45.61 49345) SDs BIESTOD TE (oe. gop 1051221263123) 595 22) 402 22) 69322) 4g8 2) as 22) 605 (22) 15/6) 44346) s43(ehao2 1) 405614346) B05 C8) 465 1012 pert wapicix, pik 3) ex 3 als, gk) 3, oli, ot ais P pets0 deuete 251 {__arexio aay) Ssp —>| Sra | j \ (©) I Sra were never stored on the stack, the compare funetion would re turn to the instruction after the call to subtract (sLt $v0,3v0, 30) in- stead of returning to the set _array function. The program would enter an infinite loop in the compare function between jx Sza and slt $vO, SvG, $0. ft would increment the stack during that loop until the stack space ‘was exceeded andl the program would likely crash, 623 Instructions (32 K ~ 1) wordy before the branch to instructions 32 K words after the branch instruction6s David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 2s Its advantageous to have a large address field in the machine format for {jump instructions to inerease the range of instruction addresses to which the in- struction can jump. oat ola viteleabigcuatt azzay) fore; scwaeae ny aeceyiti = Clazeaylil & Og) << 26) 11 claeavttl S930 6 Geri © cad $03,990, 10) = 10 (oop counter) eel Miele ee arte Be Bevin: s 629 4 eet the sans Ln ee gle date segaDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 216 chapter 6 Bea seh st2e oe 631 @ EES sed, tmasiso, & Gb sec, aisles Ht Sef get, LamiS:0 beg guar at ©) me Eee feu sc, beg Gets $6,°2 © aes gety tnedtets Sei fee) cety Lame Sa Feo) "ear o Be $2, dantis0(590 aos get innate SH ey Sia fee) SO Gee) ciedelessay Haan Sib Ma, Cope chins, 27 by in Bxercise Selutions soLuTions. 2u7 Question 6.1 se 9t0, $t0, st fee seis Stor ser se Ste, Ste) ct doc(ij zt www.docin.com o = suo mon ce Srisinel taiue o¢ sco Seiginel value © StLDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 28 SOLUTIONS chapter 6 Question 6.3 High-Level Code MIPS Assembly Code 1) digo Level agorsthn # 602 ~ 4, Ged = }y fot ~ Length old fevessoworde (chee) sx¥0y!_{ ssveroonetea: at Ly dy Lange ‘sdal cep, fap, “26 A make oon on stack Be eS, L3Goet Store rege om Ui #una Length of stung asch cot, 6,0 Rae LE SPEER oy engens oa Sets Gaby 392 4 Ged carcay’} Seah otha” 4 Sea = See) eck G22) a! ant Pe Seabee angen = ones aed S43, 6 f eraee Sees e035, aR Gat eagen Jf sevecas shacactess ta ateing ek $22, $3) hae ce evosvotaresjy Langth 1, 0) fel seedese 4 Salt eeverse 1) eevesaa woeda 4 ababes #0 org #0 eel #8) $0) Da bf chaste Be sence word: ie ety Gaby 622 Peer meer bes Bee 844) $0," soeaen TE Cute Lomaehy 11 azeay (Ay te O80) bea 42) fal, shoe a fcc fet, Sad S02 Beemagesay' a] fh stajoustsy Watts areay eg FAL SE tee else Tetbottce oT Tg aed 2 he weaes of sane wore feu Keer sou Preeaee e 1 fen: fFeys WS 1 Po sees ose 4 reture os seveesa¢onaet) array, iat Le Lae 3b reverse: Hi ‘le sto, saz, sal sto a arg ck nae eps fea Ste, Sa, anit fins <4, tetaen wmie > a feed St0, Sad, Sal #51 e tareaytil tap = aeeay its Sel sez) oust) Sez > areay detayit) = aeeay (sie ada Sta, Sade ga? Sts = eareayLd desayl) = enps Se Sul oles See Saray} oe Sei) OLE Farrag) sarenvcay you Se Sts) olsest |B arreyls) Sareayisl , feet Sez) sai 82 7 reverse ewer de oteDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Question 6.5 High-Level Code sun ~ swopiumy 2¢ OX55S555551) // nap bite Son > Stepineay 2, 8111931333), // suap paisa Sin 7 Stpinuny 4) ocavasavaeny 77 onop ubh Sin = Stepinuny €) Seaaesaoesty 77 suck bytes San > Stepinuny 36, S4zetree=4), // seap halves (1 swag aackes bite MIPS Assembly Code sa Seas oss fe Sas 52, ey da toy fo, 0 to 2 0, 0 so su, 9 fo, dadosrooee fo, 26 feo, 9 Bxercise Selutions soLutions 219David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 20 SoLuTIONS chapter 6 Question 6.7 High-Level Code MIPS Assembly Code boo paLiodcons(chae* axeay) | seo = 4) es - nen Sy 97 gecay sectces Palindecne fox ()~ 9} aeeay(S) 1 6 $50) Aengene sa ea, = 5-1) 17 5 ta eden of tase anae tones sch 286) sae = oF ages G03, 600 wns Gb roves he oF tee acesy (81 Beg 82, $5," gos DP easy) te see ney fab, BF Pe tatoos Been otra + + + + + eebu stealth aii ot ee 803) San, S80 hy See Et otstar 1 bee $02, S03y m9 asst #0) Sen) “1 oes ee3, Set 2 Po Soe yoor yoo s patladeons , feel ewer 60, 2 Syee 5 Ges 6 not a pat ndeome seat ave 50) fe" aeDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 233 CHAPTER 7 a (a) Reype, tv, acai (b) Raype osuDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 234 soLurtoNs chapter 7 73 (ett Furst, we modify the ALU. ohare Ak “4 ae \> 2 f ———- atucontrat, _! ary ay ER oh TABLE 7.1 Modified ALU opettion to support S11David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 235 une pee ree a eee Px non [an ecixn| TABLETS ALL deer ih abe ‘Then we modify the datapath, FIGURE 72 Modified Snglecyele MIPS prcesorextented torun 51 LDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 236, SoLurtoNs chapter 7 73 b)Lai wor oT x foo | oo | |x |» | oun P e Pe pepe Tee | "TABLETS Maun decoder walh able enhanced osappa LUE. FIGURE 7.3 Modiiodsingl-cyce datapath o support LaDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 27 13 (sata ‘The datapath doesn’t change. Only the controller changes, as shown in ‘Table 7.4 and Table 7.5. An ane eet a Pe a fovea ao oe i “TADLET © ALU decoder oth ae ae mem mito sWvop NC Ps fone x es Tw I ‘TABLETS Main decoder uinoble hanced wo sippon SELDavid Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions 238 SoLurtoNs chapter 7 73 @biez First, we modify the ALU mona Fah Php Hemost " — siete mon ‘Then, we modify the datapath,David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 239 Live [oof o x po pe Pe "TABLE 7.5 Main decoder vin able rwhansed vo sappon DLO?David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 240 soLurtoNs chapter 7 73 @) jab. ae erty elon Fee mga ee Wine TT Serene instrtion — i jai | coo Pt w | x x ° x Xx 1 1David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 24 73¢p 18 Pyceone | FIGURE 7.4 Modiiod single eyeledetpath to support 1h peo a ee A a Loe fw pee ee ee TABLETS Mate tcoler nu alleerhancelosappon LhDavid Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions 242 SoLurtoNs chapter 7 wo Pe aey ee a ee ed 000000) 100011 1ojo11 TABLE TD Main decoder trv able shanosd osippon ASG, 5) SUD. Gyand ULESDevid Money Hacc and Sarah L. Haris, Distal Design al ConguterArchectare, © 2007 by Elsevier Ine Exercise Solin soLutions us TABLETS Main decoler ih able enhanced oon ada -S, Sub S,anwult ss TABLE 710 Floaing point main decoder ath abs enbancedo mult.s TABLE 7 Addevebuacir ocsader De It would take 93 seconds to execute 100 billion instructions, 19 G) Raype, ads (b) Ly, 6m, acai, Retype (6) all instructionsDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions m4 soLurtoNs chapter 7 na (ayeriy First, we show the modifications to the ALU, "um 4 PrALUConttO Recut Next, We show the modifications to the ALU decoderDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 2as ‘Next, we show the ehanges to the datapath. “The only modification is the ‘width ef ALUComtrol, No changes are made to the datapath main control ESM. ete No changes are necessary in the datapath. Only the ALU decoder and main control FSM require modifications. fa alucentrol TTABLETI2 ALU decoder rut ableDavid Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 246 SoLurtoNs chapter 7 aren on ren) TABLETS ALU decoder oath te Mameng = 1 ogeeDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions ut TA Lfe) xork First, we modify the ALU and the ALU decoder. | ALUCentot,David Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions 248 SoLurtoNs chapter 7 Next, we modify the datapath. Again, the only change is the buswidth of the ALUControl signal irom 3 bits to 4 bits. ax g F ss Hs seme | {Sign Goer And finally, we modify the main control FSM.David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 249 setDavid Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions 250 SoLurtoNs chapter 7 TAL) je aDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 251 FAL @)bneDavid Money Haris and Sarh L Hass, Digital Design and Computer Archiectare, © Exercise Soltions 07 by Elev 2 SoLurtoNs chapter 7 TL Lb * The ZE unit is a zero extension unitDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 253David Money Haris and Sarh L. Haris Digital Design and Computer Architecture, © 2007 by Else In. Exercise Soltions 24 SoLurtoNs chapter 7 13 JarDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Exercise Solin soLutions 255 ars )/ ene ‘Your fiend should work on the memory unit. It shouk! have a delay of 225ps to equal the delay of the ALU plus multiplexer. The eycle time is now 300 ps. 27 Yes, Alyssa P, Hacker should switch tothe slower but lower power register file for her multicycle processor design. Tice the delay still does not make the register file in the critical path (160) ps propagation delay for a read, and 140 + 25 = 165 ps for « write). The critical path is still the memory access, so using the reduced power register file does not affect the processor speed, 25(6) + (0.525) + (01 + D.L1N4) + 0.0236)David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 256 SoLurtoNs chapter 7 721 XDA 43 444443) 10 4443) ‘The number of instructions executed is 3.4 (5 x 10) + 199 clock cycles / 35 instructions = 3.62 CPL 199 clock eyeles 5. Thus, che CPI 723 ‘We modify the MIPS multicycle processor to implement all instructions from Exercise 7.11. MIPS Top-Level Module Verilog VHDLDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: ‘Modified MIPS Multicycle Processor Verilog 1 stusess, poses, aluscrtvel, Ieely // 150 ae Bxercise Selutions soLuTIONs 2sT vupL,‘Davie Money Has and Sara L. Mami, Digital Design en Computer Architecture, © 2007 by Elsevae as [Exercise Solutions 258 sovurtons chapter 7 ‘Modified MIPS Multicycle Control VHDL. Verilog reor (5:0) Spe fancey output (240) elusreby // okey one Suteut (2:0) pac Steput (310) Siussncesl, 7 enue soepae 8! Tay se 0) aluoey // sons boop J aE slusesb, poaeay aluop, bao, boa) //Nay 10 sseign poo = cowetee | fibranen & deed) 1 ‘no ensanays ? ne ie te Rena og NE SyDavid Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: ‘Modified MIPS Multicycle Main Decoder FSM. Verilog depue [5:0] S0y [ocd etataregy’ cegaae, output (2.0) aluaeety 7) oat, ane Sispus (209) anes, Stspus (259) Sidepy 24 sont Siepue 8) SSP an Sieput Teh) 9) aa Paramter MBUER ~ $+800020y 2 Parameter MER > Stnb0a90y : Paeamkee HEGEL ~ 51801090) : Gheameces AotiEe > s'2ot303) : Geeanctes Appive |\S'201010y P Pramver (GEX” StapiO11; 7 State B Sirameee Ghusx _emesiso // sate e // car Sisamese crue 2 Sveezio!; 74 seata @ // Ser Bacsneeae Konsum 61201120) wj/ Grate @ // sent Biesuetae Kon = steauinay // state € (foxes preamcae BEEK = sm1000; // State 10 // axe Baeametae uma 1 dvmigooay // State 18 // 13 = Stetn991%; 17 opoode toe Ls S Steimaciy 74 gpeode fee Elanctan sive ~ crnosonee; J/oplbce toe B-type forester AEG aus*AQ00100;. #0 Opeadetoe net Pacghotas ncn \\ Di satoscvogls Speake eck. set Parbrotee! y\/F ubo0o0idy 71 Gpande tar phiameee er VC Phonic 77 pete soe ek fattnctor Gaz ethanatloy )//Sptcce for wort Bheameae Ehk = etbtG0i0%; 7 Dpooda fox bow rey (4:0) state, naeeeater Peg (1820) Goneroiss (7 OMT, CRT, RN, 180) Slvave Wipeseage ele oF posadge reset) Bxercise Selutions soLuTIONs 259 vupL,‘Davie Money Has and Sara L. Mami, Digital Design en Computer Architecture, © 2007 by Elsevae as [Exercise Solutions 260 a SoLuntons chapter 7 ete Spassoes Brgrony lout wentorage sata, aivaye at/* See VHDL. i fees (continued on next page)David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: (continued from previous page) Verilog & SoiBtin| 17 250 ae sees oc (sce FY should never happen ol, cee, ton eee nl a FF ely coed rea wen (continued on next page) Bxercise Selutions soLutions 261David Money Haris nd Sarah L. Maris, Digital Design and Computer Architecture, © 200) by Elsevier Ia. Exercise Soltions 262 sovurtons chapter 7 (continued from previous page) Verilog 41 ootpae Logis aiuop, | /7 extend aluop to 3 bite // oR TSI?! coneseisy 1/20 ‘onlex; auneeelelee 10"40bet0gt¢ 20080-03400, Vion cxsun: gaeteote 4= 15s6602_c69800 08099_000_05 med ors: sonbuend <= irweboeasGetce_ 9880108 8) WPT Redken, LD \David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: ‘Modified MIPS Multicyele ALU Decoder Verilog sodule alusec (input (5:0) functy sees (210) aiucpy ff not fouegut weg (249) alucontselyy // x00, SRV atwoye @¢ + 1 etait slusoateol < ataaooy /) 299 Bxercise Selutions 263 vupL,‘Davie Money Has and Sara L. Mami, Digital Design en Computer Architecture, © 2007 by Elsevae as [Exercise Solutions 264 SoLuntons chapter 7 ‘Modified MIPS Multicycle Datopath VHDL. cry ft, some dopst (219) aluowsty (7 REY one Tnput (130). Gopot (210) hussteeaty /7 ene np ia (ise foutpst (5:6) op," fant, Steps wie, Sheps f22s0) $dey"wetcaasta, Gnput™ (3510) asaaacary Jf taecnal aignaia of the dstapscn wosute ize (420) wettezegy (carcyletgninnany (eke sign exe ghdea Ln 222 asa ws, way edly 3113] Rowcaesy menbytouse 17 23 OLS 1720) momyeay 7 2a Ji op 454 Sunse tuetee to cont eat Seelgn op = Taser a3e26)¢ SENGn flnce Dinar ist nud HO 2 waarmee (eagy 24) repens HB2y ogee es fa moe AG)! Towsteessaieal see] rnen 216) eaaaat a5 ‘enaantai oh! Sts CTs (continued on next page)David Money Harts and Sarah L, Haris, Digital Design aed Computer Architecture, © 2007 by Bleavier ne: Bxercise Selutions soLutions 265 (continued from previous page) Verilog ud A1S)eqdenan(dnace( 20:26), Vneer isiii|y sagdat, weteceea)) sugen. —_aelasts(12t0}y signin) Fefoest —sotinate(s6i0]y Secesam)y"// O22, HERE Flope 402) aregisiny cesce, 208; 3)) floge 4103) beaglolt, Seasty a2, cetteaasa) Bid 4102) sfsansuipe, ay ausseey areal en tg se Bis 1G} SeteatlWeicatata, sotbsoe, 1 say mein. fe alutaceay exch, atuconteol, ea (4s0}y flee ml ot fiope [¥fo2y sturegtoity reset, suacenate g/Btvouey faith 4122) gamuatatacensityiaivest, fealstscey Lanee(assa}, 2%00), ‘The following deseribes the building blocks that are used in the MIPS mul- tieyele processor that are not found in Section 7.