VLSI Design

ECE314
Spring 2024
M1: VLSI Technology
Lecture 1
CMOS Fabrication & Layout
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE314 – M1 Lecture 1 1

 Outline

• Introduction
– What is CMOS
– Why CMOS
– Advanced CMOS
– What’s inside a Chip
• CMOS Fabrication & Layout
• Layout & Geometric Design Rules

D. Khalil ECE314 – M1 Lecture 1 2

 CMOS

• CMOS uses both NMOS and PMOS devices to realize circuits

• Wells must be used to accommodate both NMOS and PMOS
on the same area (p-sub & n-well or n-sub & p-well or twin well)
• Source/drain, substrate, and well junctions must always be
reverse-biased under all operating conditions
• Bulk ties are needed to bias the bulk properly (remember MOS
is a 4-terminal device: source, drain, gate, and bulk)

Connect to most Connect to most

negative voltage positive voltage

D. Khalil ECE314 – M1 Lecture 1 3

 Advanced CMOS
Further improvements are continuously added to CMOS
• Triple-well CMOS
• Strained-Silicon CMOS
• Silicon-on-Insulator CMOS
• Tri-gate CMOS
• Fin-FET CMOS

D. Khalil ECE314 – M1 Lecture 1 4

 What’s Inside a Chip
Cross-section showing silicon and
• Transistors metal layers including solder balls*

– Different types of
NMOS and PMOS
– Fabricated on the
silicon surface

• Wires
– Aluminum or copper wires
– Fabricated using several patterned
metal and contact layers
– Insulator fills the remaining volume in each layer
3D visualization of silicon and few
metal layers (transparent insulator )*
• Passive devices (optional)
– Integrated resistors, capacitors, inductors
– Mainly used in analog and RF circuits
* http://en.wikipedia.org/wiki/Integrated_circuit

D. Khalil ECE314 – M1 Lecture 1 5

 Outline

• Introduction
• CMOS Fabrication & Layout
– Wafer Fabrication
– Making Chips
– Basic Processing Steps
– Simplified CMOS Process Flow
• Layout & Geometric Design Rules

D. Khalil ECE314 – M1 Lecture 1 6

 Wafer Fabrication

• Separate facility to fabricate wafers

• Si ingots are fabricated from Si seeds
• Si ingots are sliced to thin wafers
• Wafer properties:
– resistivity 0.05 – 0.1 .cm
– diameter 10 – 30 cm
– thickness 500 – 1000 µm

wafers large single-crystal « ingot »

D. Khalil ECE314 – M1 Lecture 1 7

 Making Chips

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 Making Chips

Basic Idea:
• Integrated circuits are built over wafers in a layer-by-layer fashion
• An image of the desired layer mask is transferred to the wafer
(photolithography)
• That image is used as a guide to the desired fabrication step
(oxidation, diffusion, ion implantation, etch, …)
• There are other blanket fabrication steps that apply to the whole
wafer (deposition, metallization, polishing, annealing, …)
• Once wafers are fully processed, they are diced into dies
• Each die is packaged to become a chip
• Finally, chips are soldered on PCBs

Will briefly cover some processing steps in the next few slides
Optional course is dedicated to fabrication technology
D. Khalil ECE314 – M1 Lecture 1 9
 Basic Processing Steps

Photolithography
• Wafer covered with soft photoresist (PR)
• Mask exposure to harden selected areas of PR
• Soft PR dissolving to uncover surface
for next processing
• Note: The hardened PR is removed
after needed processing is done

• Two types of PR:

– Negative PR: hardens in exposed areas
– Positive PR: hardens in non-exposed areas

• Cost is proportional to the number of masks

D. Khalil ECE314 – M1 Lecture 1 10

 Basic Processing Steps

Oxidation
• Exposed silicon areas oxidized in controlled temperature furnace

Diffusion
• Dopants cover the exposed silicon areas
• Dopants diffuse into silicon proportional to time
• Dopants washed off the surface

Ion Implantaion
• Dopants projected at silicon surface with selected
angle/energy/dose
• Dopants penetrates silicon surface to desired depth
• Annealing step is necessary after implantation

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 Basic Processing Steps

Etch
• The material under exposed surface areas are etched (removed)
• Selective etch removes certain material and leave others
• Reactive ion etch removes material in the vertical direction much
faster than in the planer direction

Deposition
• Material layer deposited to cover the surface of the wafer
• Selective deposition only covers surface of selected material
• It is typically patterned by a subsequent etch step

Metallization
• Metal layer sputtered to cover the surface of the wafer

D. Khalil ECE314 – M1 Lecture 1 12

 Basic Processing Steps

Polishing
• The surface of the wafer is polished to make it even (planer)
• Chemical mechanical polishing is often used

Annealing
• Wafers placed in in controlled temperature furnace with inert
ambient or vacuum for some time
• Typically used after ion implantation to heal damage and
diffuse dopants

D. Khalil ECE314 – M1 Lecture 1 13

 Simple Flow - Making Transistors
Steps Description Cross-Section (After Steps) Masks (Cumulative)

1. N-well creation
N-well mask litho,
N-well implant

2. FOX creation
Si3N4 deposit,
Active mask litho,
Si3N4 etch, Grow
field oxide, Si3N4
etch, Threshold
adjust implants
3. Gate creation
Grow gate oxide,
Poly deposit,
Poly mask litho,
Poly etch

D. Khalil ECE314 – M1 Lecture 1 14

 Simple Flow - Making Transistors
Steps Description Cross-Section (After Steps) Masks (Cumulative)
4. Source/drain creation
N-select mask litho,
N+ source/drain
implant (self-aligned),
P-select mask litho,
P+ source/drain
implant (self-aligned)
5. Salicidation
Oxide deposit, Oxide
etch (gate spacer
created), Ti deposit,
Anneal to form TiSi2,
Ti etch (self-aligned
salicidation)
6. Contact creation
Fill oxide deposit,
Polish, Contact mask
litho, Contact etch,
W plug despoit, Polish

D. Khalil ECE314 – M1 Lecture 1 15

 Simple Flow - Making Wires
Steps Description Cross-Section (After Steps) Masks (Cumulative)
7. M1 creation
M1 Metallization,
M1 mask litho,
M1 etch

8. V1 creation
Fill oxide deposit,
Polish, Via1 mask
litho, Via1 etch,
Via1 despoit, Polish
Similar to 6
9. M2 creation
M2 Metallization,
M2 mask litho,
M2 etch
Similar to 7
Repeat 8 & 9 for subsequent metal layers

D. Khalil ECE314 – M1 Lecture 1 16

 Simple Flow - Passivation
• Top metal layer is dedicated to form bond pads
• Bond pads are used to electrically connect the integrated circuit
supplies and I/Os to the outside world through the package pins
• Final step is to cover the wafer with a passivation layer
• Passivation seals underlying layers from moisture and
contamination and protects against damage caused by
subsequent dicing and handling
• Passivation mask is needed to uncover the surface over bond
pads to allow external connection

Passivation

Pad

D. Khalil ECE314 – M1 Lecture 1 17

 Outline

• Introduction
• CMOS Fabrication & Layout
• Layout & Geometric Design Rules

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 Layout
• Process controls vertical dimensions and sets constraints
on planer dimensions (mask dimensions) that are set by the design
• Layout defines colored planer geometries on different layers
corresponding collectively to different masks used in fabrication
(Each layer has a unique color)
• Layout editor CAD tool is used by designers to draw the layout and
finally generate layers to send to fabrication in GDSII format
(a process called tapeout)
• IC design is concerned with
both schematic and layout
“views” of the design
• Most companies have
dedicated layout teams

D. Khalil ECE314 – M1 Lecture 1 19

 Layout Geometric Design Rules

• Fabrication process places many constraints on the layout

• A set of geometric design rules guarantees proper fabrication
• In general, two main categories of constraints:
1. Resolution constraints
Smallest width and spacing to margin for variations
2. Overlap constraints
Smallest extension and spacing to margin for alignment mismatch
• Two ways to define geometric design rules:
1. Scalable rules:
All dimensions in multiples of  (min gate poly line width = 2 )
As technology scales, changing  would change all rules
2. Absolute rules:
All dimensions in metric system

D. Khalil ECE314 – M1 Lecture 1 20

 Minimum Width Rules

• Dimensions must be equal or greater than minimum values

• Minimum values are imposed by the processing capabilities
of the target technology

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 Minimum Spacing Rules

• The same argument applies for spacing

• Dimensions must be equal or greater than minimum values
• On the same layer: Minimum values are imposed by the
processing capabilities of the target technology
• On different layers: Minimum values are imposed to avoid
parasitic devices or undesired connection

D. Khalil ECE314 – M1 Lecture 1 22

 Minimum Extension Rules

• Some geometries must extend beyond the edge of others by a

minimum value to margin for misalignment
• EG: Gate poly must extend beyond active-area by a minimum
value to ensure proper gate control at the edge

D. Khalil ECE314 – M1 Lecture 1 23

 Minimum Enclosure Rules

• Geometry enclosure means that an inner geometry is completely

inside another outer geometry
• Enclosure rules set a minimum distance between the inner
geometry and the outer geometry to margin for misalignment
• EG: Active-area edge distance to well edge, active-area edge
distance to n/p select edge, and contact/via edge distance to
metal edge

D. Khalil ECE314 – M1 Lecture 1 24

 Links

• Foundries (Fabs):
– TSMC: http://www.tsmc.com/
– Global Foundries: http://www.globalfoundries.com/
• Interface to Foundries:
– CMP: http://cmp.imag.fr/
– MOSIS: http://www.mosis.com/
• CAD Companies:
– Synopsys: http://www.synopsys.com/
– Cadence: http://www.cadence.com/
– Mentor Graphics: http://www.mentor.com/

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 Reference Reading

• Rabaey, chapter 2

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