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DigitalLogic ComputerOrganization L26 Revision

The document provides an overview and review of topics related to digital logic and computer organization including caches, virtual memory, multi-core processors, and assembly language. It contains example problems and their solutions related to these topics in preparation for a closed book final exam.

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Phan Tuấn Khôi
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28 views13 pages

DigitalLogic ComputerOrganization L26 Revision

The document provides an overview and review of topics related to digital logic and computer organization including caches, virtual memory, multi-core processors, and assembly language. It contains example problems and their solutions related to these topics in preparation for a closed book final exam.

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 26: REVISION
ELEC3010
FINAL EXAM
❑Closed book
▪ You can use 1 A4 page cheat sheet and 1 A4 Page listing all assembly
instructions of the processor discussed in class
❑Topics covered:
▪ Convert from C to Assembly
▪ Single cycle/Pipelined/Multi-core processors
▪ Caches
▪ Virtual memory
▪ IO
▪ Verilog
❑ You have 100 minutes to earn 100 points
2
CACHES

❑You are given the following specifications:


- Memory: 128MB, byte-addressable.
- Cache: 64KB, 8 bytes per block.
If the cache is direct-mapped, what is the number of
tag/index/offset bits respectively?
a. 12/12/3
b. 13/11/3
c. 11/13/3
d. 14/10/3

3
CACHES

❑You are given the following specifications:


- Memory: 256MB, byte-addressable.
- Cache: 128KB, 4 bytes per block.
If the cache is fully associative, what is the number of
tag/index/offset bits respectively?
a. 15/11/2
b. 25/0/3
c. 16/10/2
d. 26/0/2
4
CACHES

❑Find the AMAT given that the L1 cache access time is 1 ns,
L2 cache access time is 10 ns, memory access time is 100 ns,
L1 cache miss rate is 5%, L2 cache local miss rate is 10%.
a. 1 ns
b. 2 ns
c. 3 ns
d. 4 ns

5
CACHES

❑Which of the followings transfers faster?


a) Data between the cache and the CPU
b) Data between the RAM and cache
c) Data between the RAM and CPU
d) Data between the hard drive and CPU

6
MULTI-CORE

Given a program with a serial part and a parallel part. Assume that it
takes 20ms to execute the serial part and 20ms to execute the parallel
part on a 1-core processor. What will be the execution time of the
program and the corresponding speedup if the number of cores is 4?

A. 10ms and 4
B. 20ms and 2
C. 25ms and 1.6
D. 25ms and 1.8

7
MULTI-CORE

Suppose we have a program of which 10% can be parallelized to any


extent, 30% can be parallelized to run on up to 10 processors, and
60% can’t be parallelized at all. The program takes 70 seconds on a
single processor.
How long will it take to run on 2 processors?

A. 56 seconds
B. 70 seconds
C. 35 seconds
D. 60 seconds

8
MULTI-CORE

CPU Year Clock Pipeline Issue Out-of- Cores Power


Rate Stages width order/
Speculation

Core i5 Ivy 2012 3400MHz 14 4 Yes 4 (without 65 W


Bridge hyperthreading)

a) How many threads can the processor execute at the same time?
b) How many instructions can the processor execute at the same time?

9
VIRTUAL MEMORY

❑Given the following virtual memory of a process and the


page size, how large is the page table?
- Total virtual memory: 2GB.
- Page size: 8KB.
- Page Table Entry size: 4 bytes.
a. 4MB
b. 8MB
c. 2MB
d. 1MB
10
VIRTUAL MEMORY

❑Consider a byte-addressable virtual memory system with


32-bit virtual addresses, 32-bit physical addresses, and 1 KB
pages. If each entry in the single-level page table is 4 bytes
long, how much space does the page table occupy in
memory?

A. 16 MB
B. 4 MB
C. 32 MB
D. 8 MB
11
VIRTUAL MEMORY
The following problems concern the way virtual addresses are translated into physical addresses.

• The memory is byte addressable.


• Memory accesses are to 1-byte words.
• Virtual addresses are 16 bits wide.
• Physical addresses are 12 bits wide.
• The page size is 256B
• The TLB is 8-way associative with 16 entries and block size of 1 Byte
In the following tables all numbers are given in hexadecimal.
The contents of the TLB, the page table for the first 32 pages are as follows:

1. Which physical address corresponds to the virtual address 0x0DE2?

2. How many pages are there in the virtual memory?

12
ELEC3010 IN ONE SLIDE
C int x = 10; Interrupts system
x = 2* x + 15; I/O reserved PAGE
compiler stack TABLE
sub R5, R5, R5
addi R5, R5, 10
Assembly
shl R5, R5, 2
assembler addi R5, R5, 15 heap
00000000101000000000001010010100 global
machine 00000000101000000000001010010011 text
code 00000000001000101000001010000000
00000000111100101000001010010011
loader system reserved

CPU FSMs

Circuits RF
A Architecture -- ISA
L 32 32 Microarchitecture
Gates A U
B • Pipelining
• Caches
Transistors
HDL Parallelism:
• ILP KERNEL
Silicon
• TLP/Multicore
13

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