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DigitalLogic ComputerOrganization L25 IO Handout

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21 views21 pages

DigitalLogic ComputerOrganization L25 IO Handout

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 25: Exceptions
Input/Output
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang


School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture


❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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EXCEPTIONS AND INTERRUPTS

❑Useful methods for signaling the CPU that some event has
occurred that requires action
▪ In response, the CPU may suspend the running program in order to
handle the exception/interrupt
❑Exceptions are used to handle conditions that arise when
executing instructions on the processor
▪ Detected by the processor itself
❑Interrupts are used to handle (asynchronous) events
external to the processor
▪ I/O device request, external error or malfunction
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WHY ARE EXCEPTIONS USEFUL?

❑Allow user programs to get service from the OS


▪ A system call creates an exception that kicks out the user program
and transfers control to exception handler, which will invoke a
proper OS service routine

❑ Handle unexpected events


▪ Memory protection violation, divide-by-zero, invalid opcode, etc.

❑ Handle page faults

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HANDLING A PAGE FAULT

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COMPUTER WITH INPUT/OUTPUT

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I/O CONTROLLERS + BRIDGE
I/O connected with I/O Controllers
• high-performance interconnect: processor, memory, display
• lower-performance interconnect: disk, keyboard, network

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BUS TYPES
Processor – Memory (“Front Side Bus”)
▪ Short, fast, & wide
▪ Mostly fixed topology, designed as a “chipset”
• CPU + Caches + Interconnect + Memory Controller
I/O and Peripheral busses (PCIe, PCI, SCSI, USB…)
▪ Longer, slower, & narrower
▪ Flexible topology, multiple/varied connections
▪ Interoperability standards for devices
▪ Connect to processor-memory bus through a bridge
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FOR EXAMPLE…

source
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FOR EXAMPLE…

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I/O DEVICE API
Typical I/O Device API
▪ a set of read-only or read/write registers
Command registers
▪ writing causes device to do something
Status registers
▪ reading indicates what device is doing, error codes, …
Data registers
▪ Write: transfer data to a device
▪ Read: transfer data from a device

Every device uses this API


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HOW TO TALK TO A DEVICE?
1. Programmed I/O:
special instructions talk over special busses
Specify: device, data, direction
• inb x1, 0x64 (keyboard status register)
• outb x1, 0x60 (keyboard data register)
2. Memory-Mapped I/O:
map registers into virtual address space
▪ accesses to certain addresses redirected to I/O devices
▪ data goes over the memory bus (faster!)

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MEMORY-MAPPED I/O

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DEVICE DRIVERS
Memory Mapped I/O
struct kbd {
Programmed I/O char status;
char read_kbd() char data;
{ };
kbd *k = mmap(...);
do {
sleep(); char read_kbd()
status = inb(0x64); {
} while(!(status & 1)); do {
sleep();
status = k->status;
return inb(0x60); } while(!(status & 1));
} return k->data;
}

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PROGRAMMED I/O VS MEMORY MAPPED I/O

Programmed I/O
▪ Requires special instructions
▪ Can require dedicated hardware interface to devices
Memory-Mapped I/O
▪ Re-uses standard load/store instructions
▪ Re-uses standard memory hardware interface

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POLLING VS. INTERRUPTS
How does program learn device is ready/done?
1. Polling: Periodically check I/O status register
• Common in small, cheap, or real-time embedded systems
+Predictable timing, inexpensive
– Wastes CPU cycles
2. Interrupts: Device sends interrupt to CPU
• Cause register identifies the interrupting device
• Interrupt handler examines device, decides what to do
+Only interrupt when device ready/done
– Forced to save CPU context (PC, SP, registers, etc.)
– Unpredictable, event arrival depends on other devices’ activity

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DIRECT MEMORY ACCESS (DMA)
How to talk to device?
• Programmed I/O or Memory-Mapped I/O

How to transfer lots of data from disk to memory?


disk->cmd = READ_4K_SECTOR;
Very,
while (!(disk->status & 1) { } Very,
for (i = 0..4k) Expensive
buf[i] = disk->data;

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DIRECT MEMORY ACCESS (DMA)
1. Programmed: Device → CPU → RAM Transfer
for (i = 1 .. n)
CPU RAM
▪ CPU issues read request
▪ Device puts data on bus
& CPU reads into registers
▪ CPU writes data to memory DISK

2. Direct Memory Access (DMA): Device → RAM


▪ CPU sets up DMA request CPU RAM
▪ for (i = 1 ... n)
Device puts data on bus
& RAM accepts it
DISK
▪ Device interrupts CPU after done

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BUILDING A COMPLETE COMPUTER

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BEFORE NEXT CLASS

• Next time:
Revision

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