INDEX

Name of the Laboratory : MICROPROCESSOR LAB

Name of the Staff Lab In-Charge :

Date of Date of
S No Name of the Experiment Page No Marks Staff Signature
Experiment Submission

1 STUDY OF 8085 MICROPROCESSOR

2 8-BIT ADDITION

3 8-BIT SUBTRACTION

4 8-BIT MULTIPLICATION

5 8-BIT DIVISION

6 16-BIT ADDITION

7 16-BIT SUBTRACTION

8 MULTI BYTE ADDITION

9 MULTI BTE SUBTRACTION

10 16-BIT MULTIPLICATION

11 SEARCH LARGEST IN AN ARRAY

12 SEARCH SMALLEST IN AN ARRAY

13 SORTING – ASCENDING ORDER

14 SORTING – DESCENDING ORDER

15 REVERSE THE STRING

16 TABLE PROCESSING

17 BCD TO HEX CONVERSION

18 HEX TO BCD CONVERSION

19 SEARCH A DATA IN AN ARRAY

20 FACTORIAL OF A NUMBER
1.8085 architecture

Control Unit
Generates signals within uP to carry out the instruction, which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator to perform
arithmetic. Always stores result of operation in Accumulator.

Registers
The 8085/8080A-programming model includes six registers, one accumulator, and
one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack
pointer and the program counter. They are described briefly as follows.
The 8085/8080A has six general-purpose registers to store 8-bit data; these are
identified as B,C,D,E,H, and L as shown in the figure. They can be combined as
register pairs - BC, DE, and HL - to perform some 16-bit operations. The
programmer can use these registers to store or copy data into the registers by using
data copy instructions.
Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers. They are called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are
listed in the Table and their bit positions in the flag register are shown in the Figure
below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor
uses these flags to test data conditions.
For example, after an addition of two numbers, if the sum in the accumulator id larger
than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) -- is
set to one. When an arithmetic operation results in zero, the flip-flop called the
Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a register; five bit
positions out of eight are used to store the outputs of the five flip-flops. The flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the micro-
processor. The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to
change the sequence of a program when CY flag is set. The thorough understanding
of flag is essential in writing assembly language programs.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register
is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the
next byte is to be fetched. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer. The stack concept is explained
in the chapter "Stack and Subroutines."
Instruction Register/Decoder

Temporary store for the current instruction of a program. Latest instruction sent here
from memory prior to execution. Decoder then takes instruction and ‘decodes’ or
interprets the instruction. Decoded instruction then passed to next stage.
Memory Address Register
Holds address, received from PC, of next program instruction. Feeds the address bus
with addresses of location of the program under execution.
Control Generator
Generates signals within uP to carry out the instruction which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.

Register Selector

This block controls the use of the register stack in the example. Just a logic circuit
which switches between different registers in the set will receive instructions from
Control Unit.

General Purpose Registers

uP requires extra registers for versatility. Can be used to store additional data during a
program. More complex processors may have a variety of differently named registers.

8085 Pin description.

Pin Description

The following describes the function of each pin:

A6 - A1s (Output 3 State)
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0
address,3 stated during Hold and Halt modes.

AD0 - 7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)
appear on the bus during the first clock cycle of a machine state. It then becomes the
data bus during the second and third clock cycles. 3 stated during Hold and Halt
modes.

ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and
enables the address to get latched into the on chip latch of peripherals. The falling
edge of ALE is set to guarantee setup and hold times for the address information.
ALE can also be used to strobe the status information. ALE is never 3stated.

SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:
S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.

RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to be read and that the Data
Bus is available for the data transfer.

WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory
or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt
modes.

READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for
Ready to go high before completing the read or write cycle.

HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data
Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as
soon as the completion of the current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and
that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold
request is removed. The CPU takes the buses one half clock cycle after HLDA goes
low.

INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only
during the next to the last clock cycle of the instruction. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During
this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt
service routine. The INTR is enabled and disabled by software. It is disabled by Reset
and immediately after an interrupt is accepted.

INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD
during the Instruction cycle after an INTR is accepted. It can be used to activate the
8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except
they cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a
higher priority than the INTR.

TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as
INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of
any interrupt.

RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA
flipflops. None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is
synchronized to the processor clock.

X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can also be
an external clock input instead of a crystal. The input frequency is divided by 2 to
give the internal operating frequency.

CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an
input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and
Halt modes.

SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a
RIM instruction is executed.

SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.

Vcc
+5 volt supply.
Vss
Ground Reference.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9100]
9005 47 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9101]
9009 80 ADD B ;A ← A+B
; If no carry,
900A D2 0E 90 JNC 900E(L1)
go to L1
900D 0C INR C ;C ← C+1
900E 32 00 92 L1 : STA 9200 ; [9200] ← A
9011 79 MOV A, C ;A←C
9012 32 01 92 STA 9201 ; [9201] ← A
9015 CF RST 1 ; Reset
Expt. No: 2 Page No:

Expt. Name: 8-BIT ADDITION Date:

Aim:

To write an ALP to perform 8-bit addition.

Algorithm:

1. Clear one register for carry (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register (Reg B)
4. Load the accumulator with the second data
5. Add Reg B content to accumulator
6. Check for carry, if there is no carry, go to step 8
7. Increment reg C to indicate carry
8. Store the results – carry in Reg C and sum in accumulator to memory locations
9. Stop
Sample Data:

Input Output

9100 – 04 9200 – 0C

9101 – 08 9201 – 00

9100 – FF 9200 – FE

9101 – FF 9201 – 01
Program:

MVI C, 00
LDA 9100
MOV B, A
LDA 9101
ADD B
JNC L1:
INR C
L1 : STA 9200
MOV A, C
STA 9201
RST 1

Result:

The ALP to perform 8-bit addition was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9200]
9005 78 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9201]
9009 90 SUB B ;A ← A–B
; If no carry,
900A DA 10 90 JNC 9010(L1)
go to L1
900D 2F CMA
;A ←A
900E 3C INR A ;A ← A+1
900F 0C INR C ;C ← C+1
9012 32 00 92 L1 : STA 9200 ; [9200] ← A
9015 72 MOV A, C ;A←C
9016 32 01 92 STA 9201 ; [9201] ← A
9019 CF RST 1 ; Reset
Expt. No: 3 Page No:

Expt. Name: 8-BIT SUBTRACTION Date:

Aim:

To write an ALP to perform 8-bit subtraction.

Algorithm:

1. Clear one register for borrow (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register (Reg B)
4. Load the accumulator with the second data
5. Subtract Reg B content from accumulator content
6. Check for carry, if there is no carry, go to step 10
7. Complement accumulator content
8. Increment accumulator content
9. Increment reg C to indicate borrow
10. Store the results – borrow in Reg C and difference in accumulator to memory
locations
11. Stop
Sample Data:

Input Output

9200 – FF 9200 – 55

9201 – AA 9201 – 01

9200 – BB 9200 – 44

9201 – FF 9201 – 00
Program:

MVI C, 00
LDA 9200
MOV B, A
LDA 9201
SUB B
JNC L1
CMA
INR A
INR C
L1 : STA 9200
MOV A, C
STA 9201
RST 1

Result:

The ALP to perform 8-bit subtraction was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9100]
9005 47 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9101]
9009 57 MOV D, A ;D ← A
900A 3E 00 MVI A, 00 ; A ← 00
900C 82 L2 : ADD D ;A←A+D
; If no carry, go
900D D2 11 90 JNC L1
to L1
9010 0C INR C ;C ← C+1
9011 05 L1 : DCR B ;B ← B–1
; If not zero, go
9012 C2 0C 90 JNZ L2
to L2
9015 32 02 91 STA 9102 ; [9102] ← A
9018 79 MOV A, C ;A←C
9019 32 03 91 STA 9103 ; [9103] ← A
901C CF RST 1 ; Reset
Expt. No: 4 Page No:

Expt. Name: 8-BIT MULTIPLICATION Date:

Aim:

To write an ALP to perform 8-bit multiplication.

Algorithm:

1. Clear one register for carry (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register for counter (Reg B)
4. Load the accumulator with the second data
5. Move the accumulator content to one register (Reg D)
6. Clear the accumulator
7. Add Reg D content to accumulator
8. Check for carry, if there is no carry, go to step 10
9. Increment Reg C to indicate carry
10. Decrement the counter register (Reg B)
11. Check for zero, if not zero, go to step 7
12. Store the results – carry in Reg C and product in accumulator to memory
locations
13. Stop
Sample Data:

Input Output

9100 – 05 9102 – 14

9101 – 04 9103 – 00

9100 – FF 9102 – FE

9101 – FF 9103 – 01
Program:

MVI C, 00
LDA 9100
MOV B, A
LDA 9101
MOV D, A
MVI A, 00
L2 : ADD D
JNC L1:
INR C
L1 : DCR B
JNZ L2:
STA 9102
MOV A, C
STA 9103
RST 1

Result:

The ALP to perform 8-bit multiplication was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9100]
9005 47 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9101]

; Compare A
9009 B8 L1 : CMP B
and B
; If carry, go to
900A DA 12 90 JC 9012(L2) L2

900D 90 SUB B ;A ←A–B

900E 0C INR C ;C ← C+1
900F C3 09 90 JMP L1 ; Jump to L1
9012 32 03 91 L2 : STA 9103 ; [9103] ← A
9015 79 MOV A, C ;A←C
9016 32 02 91 STA 9102 ; [9102] ← A
9019 CF RST 1 ; Reset
Expt. No: 5 Page No:

Expt. Name: 8-BIT DIVISION Date:

Aim:

To write an ALP to perform 8-bit division.

Algorithm:

1. Clear one register to store the quotient (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register (Reg B)
4. Load the accumulator with the second data
5. Compare the contents of Reg B and accumulator
6. Check for carry, if there is carry, go to step 10
7. Subtract the content of Reg B from accumulator
8. Increment Reg C
9. Repeat from step 5
10. Store the results – quotient in Reg C and reminder in accumulator to memory
locations
11. Stop
Sample Data:

Input Output

9100 – 02 9102 – 03 (Q)

9101 – 06 9103 – 00(R)

9100 – 07 9102 – 05 (Q)

9101 – 25 9103 – 02(R)

Program:

MVI C, 00
LDA 9100
MOV B, A
LDA 9101
L1 : CMP B
JC L2:
SUB B
INR C
JMP L1:
STA 9103
MOV A, C
L2 : STA 9102
RST 1

Result:

The ALP to perform 8-bit division was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C, 00 ; C ← 00

; L ← [9100]
9002 2A 00 91 LHLD 9100
H ← [9101]

;E ← L
9005 EB XCHG
D←H

; L ← [9102]
9006 2A 02 91 LHLD 9102
H ← [9103]
;L ← L+E
9009 19 DAD D
H ←H+D
; If no carry, go
900A D2 0E 90 JNC 900E(L1)
to L1
900D 0C INR C ;C ← C+1
; [9104] ← L
900E 22 04 91 L1: SHLD 9104
[9105] ← H
9011 79 MOV A, C ;A ← C
9012 32 06 91 STA 9106 ; [9106] ← A
9015 CF RST 1 ; Reset
Expt. No: 6 Page No:

Expt. Name: 16-BIT ADDITION Date:

Aim:

To write an ALP to add two 16-bit numbers.

Algorithm:

1. Clear one register for carry (Reg C)

2. Load the first data in HL register pair
3. Swap the contents of HL and DE pairs
4. Load the second data in HL register pair
5. Double add the contents of HL and DE pairs
6. Check for carry, if there is no carry go to step 8
7. Increment Reg C
8. Store the result which is in HL pair in a memory location
9. Move the carry in Reg C to accumulator
10. Store the accumulator content in memory
11. Stop
Sample Data:

Input Output

9100 – 06 9104 – 09

9101 – 05 9105 – 0B

9102 – 03 9106 – 00

9103 – 06

9100 – 06 9104 – 09

9101 – F0 9105 – E0

9102 – 03 9106 – 01

9103 – F0
Program:

MVI C, 00
LHLD 9100
XCHG
LHLD 9102
DAD D
JNC L1
INR C
L1 : SHLD 9104
MOV A, C
STA 9106
RST 1

Result:

The ALP for adding two 16-bit numbers was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; L ← [9100]
9000 2A 00 91 LHLD 9100
H ← [9101]

;E ← L
9003 EB XCHG
D←H

; L ← [9102]
9004 2A 02 91 LHLD 9102
H ← [9103]

9007 7D MOV A, L ;A ← L
9008 93 SUB E ;A ← A–E
9009 6F MOV L, A ;L ← A
900A 7C MOV A, H ;A ← H
;A ← A–D–
900B 9A SBB D
CARRY
900C 67 MOV H, A ;H ← A
; [9200] ← L
900D 22 00 92 SHLD 9200
[9201] ← H
9010 CF RST 1 ; Reset
Expt. No: 7 Page No:

Expt. Name: 16-BIT SUBTRACTION Date:

Aim:

To write an ALP to subtract two 16-bit numbers.

Algorithm:

1. Load the first data in HL register pair

2. Swap the contents of HL and DE pairs
3. Load the second data in HL register pair
4. Subtract the content in E from content in L
5. Move the accumulator content to L
6. Subtract with borrow the content in D from content in H
7. Move the accumulator content to H
8. Store the result which is in HL pair in a memory location
9. Stop
Sample Data:

Input Output

9100 – 06 9200 – 03

9101 – 05 9201 – 01

9102 – 09

9103 – 06

9100 – 06 9200 – 02

9101 – 08 9201 – FE

9102 – 08

9103 – 06
Program:

LHLD 9100
XCHG
LHLD 9102
MOV A, L
SUB E
MOV L, A
MOV B, H
SBB D
MOV H, A
SHLD 9200
RST 1

Result:

The ALP for subtracting two 16-bit numbers was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 37 STC ; CY ← 1
9001 3F CMC ; CY ← CY
9002 3A 00 91 LDA 9100 ; A ← [9100]
9005 4F MOV C, A ;C←A

; H ←92
9006 21 00 92 LXI H, 9200
; L ← 00

; D ← 93
9009 11 00 93 LXI D, 9300
; E ← 00

900C 1A L 1: LDAX D ; A ← DE Pair

900D 8E ADC M ;A←A+M
900E 77 MOV M, A ;M ←A
900F 13 INX D ; DE ← DE + 1
9010 23 INX H ; HL ← HL + 1
9011 0D DCR C ;C←C–1

; If not zero
9012 C2 OC 90 JNZ 900C(L1)
jump to L1

9015 CF RST 1 ; Reset

Expt. No: 8 Page No:

Expt. Name: MULTI BYTE ADDITION Date:

Aim:

To write an ALP to add two multi byte data.

Algorithm:

1. Clear the carry flag

2. Initialize one register (Reg C) with the length of the data
3. Initialize one register pair (HL) with the starting address of the first data
4. Initialize one register pair (DE) with the starting address of the second data
5. Move the content of DE to accumulator
6. Add the contents of DE and memory with carry
7. Move the accumulator content to memory
8. Increment HL and DE pairs
9. Decrement the counter register (Reg C)
10. Check for zero, if not zero, go to step 5
11. Stop
Sample Data:

Input Output

9100 – 04

9200 – 05 9200 – 08

9201 – 03 9201 – 05

9202 – 08 9202 – 0B

9203 – 01 9203 – 09

9300 – 03

9301 – 02

9302 – 03

9303 – 08
Program:

STC
CMC
LDA 9100
MOV C, A
LXI H, 9200
LXI D, 9300
L1: LDAX D
ADC M
MOV M, A
INX D
INX H
DCR C
JNZ L1
RST 1

Result:

The ALP for adding two multi byte data was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; CY ← 1
9000 37 STC
9001 3F CMC ; CY ← CY

9002 3A 00 91 LDA 9100 ; A ← [9100]

9005
4F MOV C,A ;C←A

; H ← 92
9006 21 00 92 LXI H, 9200
; L ← 00

; D ←93
9009 11 00 93 LXI D, 9300
; E ← 00

900C 1A L1 : LDAX D ; A ← DC Pair

900D 9E SBB M ;A ←A-M
900E 77 MOV M, A ;M ←A
900F 13 INX D ; DE ← DE + 1
9010 23 INX H ; HL ← HL + 1
9011 OD DCR C ;C←C-1
; If not zero
9012 C2 0C 90 JNZ 900c(L1)
jump to L1
9015 CF RST 1 ; Reset
Expt. No: 9 Page No:

Expt. Name: MULTI BYTE SUBTRACTION Date:

Aim:

To write an ALP to subtract two multi byte data.

Algorithm:

1. Clear the carry flag

2. Initialize one register (Reg C) with the length of the data
3. Initialize one register pair (HL) with the starting address of the first data
4. Initialize one register pair (DE) with the starting address of the second data
5. Move the content of DE to accumulator
6. Subtract the memory content from accumulator content with borrow
7. Move the accumulator content to the address pointed by HL pair (M)
8. Increment HL and DE pairs
9. Decrement the counter register
10. Check for zero, if not zero, go to step 5
11. Stop
Sample Data:

Input Output

9100 – 02

9200 – 08 9200 – FB

9201 – 04 9201 – FD

9202 – 02 9202 – 00

9203 – 01 9203 – 07

9300 – 03

9301 – 02

9302 – 03

9303 – 08
Program:

STC
CMC
LDA 9100
MOV C , A
LXI H, 9200
LXI D, 9300
L1 : LDAX D
SBB M
MOV M, A
INX D
INX H
DCR C
JNZ L1
RST 1

Result:

The ALP for subtracting two multi byte data was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; H ← 00
9000 21 00 00 LXI H, 0000
L ← 00
; B ← 00
9003 01 00 00 LXI
B, 0000 C ← 00

9006 31 FF FF LXI SP, FFFF ; SP ← FFFF

9009 ; D ← FF
11 FF FF LXI D, FFFF
E ← FF

900C 39 L2 : DAD SP ; HL ← HL + SP

; If no carry,
900D D2 11 90 JNC L1
jump to L1

9010 03 INX B ; BC ← BC + 1
9011 1B L1 : DCX D ; DE ← DE - 1
9012 7A MOV A, D ;A ←D
9013 B2 ORA E ; A ← A OR E
; If no zero,
9014 C2 0C 90 JNZ 900c(L2)
jump to L2
; [9200] ← L
9017 22 00 92 SHLD 9200
[9201] ← H
901A 69 MOV L, C ;L ←C
901B 60 MOV H, B ;H ←B
; [9202] ← L
901C 22 02 92 SHLD 9202
[9203] ← H
901F CF RST 1 ; Reset
Expt. No: 10 Page No:

Expt. Name: 16-BIT MULTIPLICATION Date:

Aim:

To write an ALP to perform 16-bit multiplication.

Algorithm:

1. Clear one register pair (BC) for carry

2. Load the first data in stack pointer
3. Load the second data in DE pair
4. Clear one register pair (HL)
5. Double add the contents of HL and SP
6. Check for carry, if there is no carry go to step 8
7. Increment BC pair
8. Decrement DE pair
9. Move Reg E content to accumulator
10. OR the contents of accumulator and Reg E
11. Check for zero, if not zero, go to step 5
12. Store the product in HL pair in a memory location
13. Move the carry in BC pair to HL pair
14. Store the carry in HL pair in a memory location
15. Stop
Sample Data:

Input Output

FFFF 9200 – 01

FFFF 9201 – 00

9202 – FE

9203 – FF
Program:

LXI H, 0000
LXI B, 0000
LXI SP, FFFF
LXI D, FFFF
L2 : DAD SP
JNC L1
INX B
L1 : DCX D
MOV A, D
ORA E
JNZ L2
SHLD 9200
MOV L, C
MOV H, B
SHLD 9202
RST 1

Result:

The ALP to perform 16-bit multiplication was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; H ← 91
9000 21 00 91 LXI H, 9100
L ← 00
9003 06 07 MVI
B, 07 ; B ← 07

9005 7E MOV A, M ;A←M

9006
23 L2 : INX H ; HL ← HL + 1

; Compare A
9007 BE CMP M
and M

; If no carry,
9008 D2 0C 90 JNC L1
jump to L1

900B 7E MOV A, M ;A←M

900C 05 L1 : DCR B ;B ←B-1
; If no zero,
900D C2 0C 90 JNZ L2
jump to L2
9010 32 00 92 STA 9200 ; [9200] ← A
9013 CF RST 1 ; Reset
Expt. No: 11 Page No:

Expt. Name: SEARCH LARGEST IN AN ARRAY Date:

Aim:

To write an ALP to search the largest value in an array.

Algorithm:

1. Initialize one register pair (HL) with the starting address of the array
2. Initialize one register (Reg B) with one count less than the length of the array
3. Move the memory content to accumulator
4. Increment HL pair
5. Compare the contents of accumulator and memory
6. Check for carry, if no carry, go to step 8
7. Move the memory content to accumulator
8. Decrement Reg B
9. Check for zero, if not zero, go to step 4
10. Store the accumulator content in a memory location
11. Stop
Sample Data:

Input Output

9100 – 08

9101 – 0A

9102 – 02

9103 – 0C 9200 – 19

9104 – 08

9105 – 06

9106 – 00

9107 – 19
Program:

LXI H, 9100
MVI B, 07
MOV A, M
L2 : INX H
CMP M
JNC L1
MOV A, M
L1 : DCR B
JNZ L2
STA 9200
RST 1

Result:

The ALP to search the largest value in an array was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; H ← 91
9000 21 00 91 LXI H, 9100
L ← 00
9003 06 07 MVI
B, 07 ; B ← 07

9005 7E MOV A, M ;A←M

9006
23 L2 : INX H ; HL ← HL + 1

; Compare A
9007 BE CMP M
and M

; If carry, jump
9008 DA 0C 90 JC 900C(L1)
to L1

900B 7E MOV A, M ;A←M

900C 05 L1 : DCR B ;B ←B–1
; If no zero,
900D C2 0C 90 JNZ 9006(L2)
jump to L2
9010 32 00 92 STA 9200 ; [9200] ← A
9013 CF RST 1 ; Reset
Expt. No: 12 Page No:

Expt. Name: SEARCH SMALLEST IN AN ARRAY Date:

Aim:

To write an ALP to search the smallest value in an array.

Algorithm:

1. Initialize one register pair (HL) with the starting address of the array
2. Initialize one register (Reg B) with one count less than the length of the array
3. Move the memory content to accumulator
4. Increment HL pair
5. Compare the contents of accumulator and memory
6. Check for carry, if there is carry, go to step 8
7. Move the memory content to accumulator
8. Decrement Reg B
9. Check for zero, if not zero, go to step 4
10. Store the accumulator content in a memory location
11. Stop
Sample Data:

Input Output

9100 – 08

9101 – 0A

9102 – 02

9103 – 0C 9200 – 00

9104 – 08

9105 – 06

9106 – 00

9107 – 19
Program:

LXI H, 9100
MVI B, 07
MOV A, M
L2 : INX H
CMP M
JC L1
MOV A, M
L1 : DCR B
JNZ L2
STA 9200
RST 1

Result:

The ALP to search the smallest value in an array was executed and its output
verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 06 07 MVI
B, 07 ; B ← 07
; H ← 91
9002 21 00 91 L3 : LXI H, 9100
L ← 00
9005 0E 08 MVI
C, 08 ; C ← 08

9007 0D DCR C ;C←C–1

9008
7E L2 : MOV A, M ;A←M

9009 23 INX H ; HL ← HL + 1

; Compare A
900A BE CMP M
and M
; If carry, jump
900B DA 13 90 JC 9013(L1) to L1

900E 56 MOV D, M ;D ←M
900F 77 MOV M, A ;M ←A
9010 2B DCX H ; HL ← HL – 1
9011 72 MOV M, D ;M ←D
9012 23 INX H ; HL ← HL + 1
9013 0D L1 : DCR C ;C←C–1
; If no zero,
9014 C2 08 90 JNZ 9008(L2)
jump to L2
9017 05 DCR B ;B←B–1
; If no zero,
9018 C2 02 90 JNZ L3
jump to L3
901B CF RST 1 ; Reset
Expt. No: 13 Page No:

Expt. Name: SORTING – ASCENDING ORDER Date:

Aim:

To write an ALP to sort an array in ascending order.

Algorithm:

1. Initialize one register (Reg B) with one count less than the length of the array
2. Initialize one register pair (HL) with the starting address of the array
3. Initialize one register (Reg C) with the length of the array
4. Decrement the inner counter - Reg C
5. Move the memory content to accumulator
6. Increment HL pair
7. Compare the contents of accumulator and memory
8. Check for carry, if there is carry, go to step 13
9. Move the memory content to Reg D
10. Move the accumulator content to memory
11. Decrement HL pair
12. Move the content of Reg D to memory
13. Increment HL pair
14. Decrement the inner counter – Reg C
15. Check for zero, if not zero, go to step 5
16. Decrement the outer counter - Reg B
17. Check for zero, if not zero, go to step 2
18. Stop
Sample Data:

Input Output

9100 – 08 9100 – 00

9101 – 0A 9101 – 02

9102 – 02 9102 – 06

9103 – 0C 9103 – 08

9104 – 08 9104 – 08

9105 – 06 9105 – 0A

9106 – 00 9106 – 0C

9107 – 19 9107 – 19
Program:

MVI B, 07
L3 : LXI H, 9100
MVI C, 08
DCR C
L2 : MOV A, M
INX H
CMP M
JC L1
MOV D, M
MOV M, A
DCX H
MOV M, D
L1 : INX H
DCR C
JNZ L2
DCR B
JNZ L3
RST 1

Result:

The ALP to sort an array in ascending order was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 06 07 MVI
B, 07 ; B ← 07
; H ← 91
9002 21 00 91 L3 : LXI H, 9100
L ← 00
9005 0E 08 MVI
C, 08 ; C ← 08

9007 0D DCR C ;C←C–1

9008
7E L2 : MOV A, M ;A←M

9009 23 INX H ; HL ← HL + 1

; Compare A
900A BE CMP M
and M
; If no carry,
900B DA 13 90 JNC L1
jump to L1
900E 56 MOV D, M ;D ←M
900F 77 MOV M, A ;M ←A
9010 2B DCX H ; HL ← HL – 1
9011 72 MOV M, D ;M ←D
9012 23 INX H ; HL ← HL + 1
9013 0D L1 : DCR C ;C←C–1
; If no zero,
9014 C2 08 90 JNZ L2
jump to L2
9017 05 DCR B ;B←B–1
; If no zero,
9018 C2 02 90 JNZ L3
jump to L3
901B CF RST 1 ; Reset
Expt. No: 14 Page No: 50

Expt. Name: SORTING – DESCENDING ORDER Date: 05/08/2012

Aim:

To write an ALP to sort an array in descending order.

Algorithm:

1. Initialize one register (Reg B) with one count less than the length of the array
2. Initialize one register pair (HL) with the starting address of the array
3. Initialize one register (Reg C) with the length of the array
4. Decrement the inner counter - Reg C
5. Move the memory content to accumulator
6. Increment HL pair
7. Compare the contents of accumulator and memory
8. Check for carry, if there is no carry, go to step 13
9. Move the memory content to Reg D
10. Move the accumulator content to memory
11. Decrement HL pair
12. Move the content of Reg D to memory
13. Increment HL pair
14. Decrement the inner counter – Reg C
15. Check for zero, if not zero, go to step 5
16. Decrement the outer counter - Reg B
17. Check for zero, if not zero, go to step 2
18. Stop
Sample Data:

Input Output

9100 – 08 9100 – 19

9101 – 0A 9101 – 0C

9102 – 02 9102 – 0A

9103 – 0C 9103 – 08

9104 – 08 9104 – 08

9105 – 06 9105 – 06

9106 – 00 9106 – 02

9107 – 19 9107 – 00
Program:

MVI B, 07
L3 : LXI H, 9100
MVI C, 08
DCR C
L2 : MOV A, M
INX H
CMP M
JNC L1
MOV D, M
MOV M, A
DCX H
MOV M, D
L1 : INX H
DCR C
JNZ L2
DCR B
JNZ L3
RST 1

Result:

The ALP to sort an array in descending order was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 06 06 MVI B, 06 ; B ← 06

; H ← 91
9002 21 00 91 LXI H, 9100
; L ← 00

; D ←92
9005 11 05 92 LXI D, 9205
; E ← 05

9008 7E L1 : MOV A, M ;A ←M
9009 12 STAX D ; DE ← A
900A 23 INX H ; HL ← HL + 1
900B 1B DCX D ; DE ← DE – 1
900C 05 DCR B ;B←B–1
; If no zero
900D C2 08 90 JNZ L1
jump to L1
9010 CF RST 1 ; Reset
Expt. No: 15 Page No:

Expt. Name: REVERSE THE STRING Date:

Aim:

To write an ALP to reverse a given string.

Algorithm:

1. Initialize one register (Reg B) with the length of the string

2. Initialize one register pair (HL) with the starting address of the source array
3. Initialize one register pair (DE) with the ending address of the destination array
4. Move the memory content to accumulator
5. Store the accumulator content in DE pair
6. Increment HL pair
7. Decrement DE pair
8. Decrement the counter register – Reg B
9. Check for zero, if not zero, go to step 4
10. Stop
Sample Data:

Input Output

9100 – 0E 9200 – 0C

9101 – 0E 9201 – 00

9102 – 0F 9202 – 0F

9103 – 0F 9203 – 0F

9104 – 00 9204 – 0E

9105 – 0C 9205 – 0E
Program:

MVI B, 06
LXI H, 9100
LXI D, 9205
L1 : MOV A, M
STAX D
INX H
DCX D
DCR B
JNZ L1
RST1

Result:

The ALP for reversing a given string was executed and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; H ← 91
9000 21 00 91 LXI H, 9100
; L ← 00

9003 3A 00 92 LDA 9200 ; A ← [9200]

9006 6F MOV L, A ;L ←A
9007 7E MOV A, M ;A ←M
9008 32 01 92 STA 9201 ; [9201] ← A
900B CF RST 1 ; Reset
Expt. No: 16 Page No:

Expt. Name: TABLE PROCESSING Date:

Aim:

To write an ALP to find the square of a given data from a lookup table.

Algorithm:
1. Initialize one register pair (HL) with the starting address of the source array
2. Load the accumulator with the input data stored in a memory location
3. Move the accumulator content to L
4. Move the memory content to accumulator
5. Store the accumulator content in memory
6. Stop
Sample Data:

Lookup Table Input Output

9100 – 00

9101 – 01

9102 – 04 9200 – 03 9201 – 09

9103 – 09 9200 – 05 9201 – 19

9104 – 10

9105 – 19
Program:

LXI H, 9100
LDA 9200
MOV L, A
MOV A, M
STA 9201
RST 1

Result:

The ALP for finding the square of a given number from a lookup table was executed
and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 3A 00 91 LDA 9100 ; A ← [9100]
9003 06 0A MVI B, 0A ; B ← 0A
9005 57 MOV D, A ;D ←A
9006 3E 00 MVI A, 00 ; A ← 00
9008 82 L1 : ADD D ;A ←A+D
9009 05 DCR B ;B ←B–1
; If no zero,
900A C2 08 90 JNZ L1
jump to L1
900D 4F MOV C, A ;C ←A
900E 3A 01 91 LDA 9101 ; A ← [9101]
9011 81 ADD C ;A ←A+C
9012 32 02 91 STA 9102 ; [9102] ← A
9015 CF RST 1 ; Reset
Expt. No: 17 Page No:

Expt. Name: BCD TO HEX CONVERSION Date:

Aim:

To write an ALP to convert a given BCD number to HEX number.

Algorithm:

1. Load the accumulator with the MSB of the given BCD number from a memory
address
2. Initialize one register (Reg B) with immediate data 0A
3. Move the accumulator content to a register (Reg D)
4. Clear the accumulator
5. Add Reg D content to accumulator
6. Decrement Reg D
7. Check for zero, if not zero, go to step 5
8. Move the accumulator content to Reg C
9. Load the accumulator with the LSB of the given BCD number from a memory
address
10. Add Reg C content to accumulator
11. Store the accumulator content in a memory location
12. Stop
Sample Data:

Input Output

9100 – 09 (MSB) 9102 – 62

9101 – 08 (LSB)
Program:

LDA 9100
MVI B, 0A
MOV D, A
MVI A, 00
L1 : ADD D
DCR B
JNZ L1
MOV C, A
LDA 9101
ADD C
STA 9102
RST 1

Result:

The ALP for converting a given BCD number to HEX number was executed and its
output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; B ← 00
9000 01 00 00 LXI B, 0000
C ← 00
9003 3A 00 91 LDA 9100 ; A ← [9100]
9006 D6 64 L2 : SUI 64 ; A ← A – 64
; If carry, jump
9008 DA 0F 90 JC L1
to L1
900B 04 INR B ;B ←B+1
900C C3 06 90 JMP L2 ; Jump to L2
900F C6 64 L1 : ADI 64 ; A ← A + 64
9011 D6 0A L4 : SUI 0A ; A ← A – 0A
; If carry, jump
9013 DA 1A 90 JC L3
to L3
9016 0C INR C ;C ←C+1
9017 C3 11 90 JMP L4 ; Jump to L4
901A C6 0A L3 : ADI 0A ; A ← A + 0A
901C 32 00 92 STA 9200 ; [9200] ← A
901F 79 MOV A, C ;A ←C
9020 32 01 92 STA 9201 ; [9201] ← A
9023 78 MOV A, B ;A ←B
9024 32 02 92 STA 9202 ; [9202] ← A
9027 CF RST 1 ; Reset
Expt. No: 18 Page No: 66

Expt. Name: HEX TO BCD CONVERSION Date: 19/08/2012

Aim:

To write an ALP to convert a given HEX number to BCD number.

Algorithm:

1. Clear one register pair (BC) for storing hundreds and tens
2. Load the accumulator with the HEX number from a memory address
3. Subtract 64H (100D) from accumulator
4. Check for carry, if there is carry go to step 7
5. Increment Reg B
6. Go to step 3
7. Add 64H (100D) to accumulator
8. Subtract 0AH (10D) from accumulator
9. Check for carry, if there is carry go to step 12
10. Increment Reg C
11. Go to step 8
12. Add 0AH (10D) to accumulator
13. Store the ones in accumulator in a memory location
14. Move the tens in Reg C to accumulator
15. Store the tens in accumulator in a memory location
16. Move the hundreds in Reg B to accumulator
17. Store the hundreds in accumulator in a memory location
18. Stop
Sample Data:

Input Output

9100 – FE 9200 – 04 (1’s)

9201 – 05 (10’s)

9202- 02 (100’s)
Program:

LXI B, 0000
LDA 9100
L2 : SUI 64
JC L1
INR B
JMP L2
L1 : ADI 64
L4 : SUI 0A
JC L3
INR C
JMP L4
L3 : ADI 0A
STA 9200
MOV A, C
STA 9201
MOV A, B
STA 9202
RST 1

Result:

The ALP for converting a given HEX number to BCD number was executed and its
output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C, 00 ; C ← 00
; H ← 91
9002 21 00 91 LXI H, 9100
L ← 00
9005 06 06 MVI
B, 06 ; B ← 06

9007 7E MOV A, M ;A←M

9008
23 L2 : INX H ; HL ← HL + 1

; Compare A
9009 BE CMP M
and M

; If no zero,
900A C2 0E 90 JNZ L1
jump to L1

900D 0C INR C ;C ←C+1

900E 05 L1 : DCR B ;B ←B–1
; If no zero,
900F C2 08 90 JNZ L2
jump to L2
9012 79 MOV A, C ;A←C
9013 32 00 92 STA 9200 ; [9200] ← A
9016 CF RST 1 ; Reset
Expt. No: 19 Page No:

Expt. Name: SEARCHING A DATA IN AN ARRAY Date:

Aim:

To write an ALP to search a given data and count its occurrences in an array.

Algorithm:

1. Clear one register (Reg C) for the count of occurrence of the given data
2. Initialize one register pair (HL) with the starting address of the array
3. Initialize one register (Reg B) with the count of elements in the array
4. Move the memory content to accumulator
5. Increment HL pair
6. Compare the contents of accumulator and memory
7. Check for zero, if not zero, go to step 9
8. Increment Reg C
9. Decrement Reg B
10. Check for zero, if not zero, go to step 5
11. Move the content of Reg C to accumulator
12. Store the accumulator content in a memory address
13. Stop
Sample Data:

Input Output

9100 – 04 (Data to be searched)

9101 – 02

9102 – 05

9103 – 04 9200 – 02

9104 – 06

9105 – 01

9106 – 04
Program:

MVI C, 00
LXI H, 9100
MVI B, 06
MOV A, M
L2 : INX H
CMP M
JNZ L1
INR C
L1 : DCR B
JNZ L2
MOV A, C
STA 9200
RST 1

Result:

The ALP to search a given data and count its occurrences in an array was executed
and its output verified.
Program Format:

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 3A 00 91 LDA 9100 ; A ← [9100]
9003 47 MOV B, A ;B←A
9004 4F MOV
C, A ;C←A

9005 0D DCR C ;C←C–1

9006
51 L2 : MOV D, C ;D←C

9007 3E 00 MVI A, 00 ; A ← 00
9009 80 L1 : ADD B ;A←A+B
900A 15 DCR D ;D ←D–1
; If no zero,
900B C2 09 90 JNZ L1
jump to L1
900E 47 MOV B, A ;B←A
900F 0D DCR C ;C ←C–1
; If no zero,
9010 C2 06 90 JNZ L2
jump to L2
9013 32 01 91 STA 9101 ; [9101] ← A
9016 CF RST 1 ; Reset
Expt. No: 20 Page No:

Expt. Name: FACTORIAL OF A NUMBER Date:

Aim:

To write an ALP to find the factorial of a given number.

Algorithm:

1. Load the accumulator with the given data

2. Move the accumulator content to a register (Reg B)
3. Move the accumulator content to another register (Reg C)
4. Decrement Reg C
5. Move the content of Reg C to Reg D
6. Clear the accumulator content
7. Add Reg B content to accumulator
8. Decrement Reg D
9. Check for zero, if not zero, go to step 7
10. Move accumulator content to Reg B
11. Decrement Reg C
12. Check for zero, if not zero, go to step 5
13. Store the accumulator content in a memory address
14. Stop
Sample Data:

Input Output

9100 – 04 9101 – 18
Program:

LDA 9100
MOV B, A
MOV C, A
DCR C
L2 : MOV D, C
MVI A, 00
L1 : ADD B
DCR D
JNZ L1
MOV B, A
DCR C
JNZ L2
STA 9101
RST 1

Result:

The ALP to search a given data and count its occurrences in an array was executed
and its output verified.
KIT ENTERING PROCEDURE

1. TO ENTER THE PROGRAM 4.TO CHECK THE PROGRAM

-A9000 -D9000(FOR EXAMPLE)

MVI C,00  SPACE BAR

NEXT INSTRUCTION  .

. .

RST 1

2. TO ENTER DATA

-M9100(FOR EXAMPLE)

DATA 1

SPACE BAR

DATA 2

SPACE BAR 

3. TO EXECUTE THE PROGRAM

- G9000(FOR EXAMPLE)

4. TO SEE THE RESULT

-MRESULT LOCATION(FOR EG(9102)) 

RESULT 1

SPACE BAR

RESULT 2