FA5612, FA5613

FUJI Power Supply Control IC

Power Factor Correction

FA5612 / FA5613

Application Note

’11-4
Fuji Electric Co.,Ltd.

.0.08Fuji Electric
AN-049J Co., Ltd.
Rev.1.0
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Apr.-2011
 FA5612, FA5613

WARNING
1. This Data Book contains the product specifications, characteristics, data, materials, and structures as of Apr. 2011. The
contents are subject to change without notice for specification changes or other reasons. When using a product listed
in this Data Book, be sure to obtain the latest specifications.

2. All applications described in this Data Book exemplify the use of Fuji’s products for your reference only. No right or
license, either express or implied, under any patent, copyright, trade secret or other intellectual property right owned
by Fuji Electric Co., Ltd. is (or shall be deemed) granted. Fuji makes no representation or warranty, whether express or
implied, relating to the infringement or alleged infringement of other’s intellectual property rights which may arise from
the use of the applications described herein.

3. Although Fuji Electric is enhancing product quality and reliability, a small percentage of semiconductor products may
become faulty. When using Fuji Electric semiconductor products in your equipment, you are requested to take
adequate safety measures to prevent the equipment from causing a physical injury, fire, or other problem if any of the
products become faulty. It is recommended to make your design fail-safe, flame retardant, and free of malfunction.

4. The products introduced in this Data Book are intended for use in the following electronic and electrical equipment
which has normal reliability requirements.
▪ Computers ·OA equipment ▪ Communications equipment (terminal devices)
▪ Measurement equipment ▪ Machine tools ·Audiovisual equipment ▪ Electrical home appliance
▪ Personal equipment ▪ Industrial robots etc.

5. If you need to use a product in this Data Book for equipment requiring higher reliability than normal, such as for the
equipment listed below, it is imperative to contact Fuji Electric to obtain prior approval. When using these products for
such equipment, take adequate measures such as a backup system to prevent the equipment from malfunctioning
even if a Fuji’s product incorporated in the equipment becomes faulty.
▪ Transportation equipment (mounted on cars and ships) ▪ Trunk communications equipment
▪ Traffic-signal control equipment ▪ Gas leakage detectors with an auto-shut-off feature
▪ Emergency equipment for responding to disasters and anti-burglary devices ▪ Safety devices

6. Do not use products in this Data Book for the equipment requiring strict reliability such as (without limitation)
▪ Space equipment ▪ Aeronautic equipment ▪ Atomic control equipment
▪ Submarine repeater equipment ▪ Medical equipment

7. Copyright © 1995 by Fuji Electric Co., Ltd. All rights reserved. No part of this Data Book may be reproduced in any
form or by any means without the express permission of Fuji Electric.

8. If you have any question about any portion in this Data Book, ask Fuji Electric or its sales agents before using the
product. Neither Fuji nor its agents shall be liable for any injury caused by any use of the products not in accordance
with instructions set forth herein.

.0.08Fuji Electric
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Apr.-2011
 FA5612, FA5613

CONTENTS

1. Description .................... 4
2. Features .................... 4
3. Outline .................... 4
4. Types of FA5612/13 .................... 4
5. Block diagram .................... 5
6. Pin assignment .................... 5
7. Ratings and characteristics .................... 6~10
8. Characteristics curves .................... 11~13
9. Outline of circuit operation .................... 14
10. Description of each circuit block .................... 15~19
11. Descriptions of use for each pin .................... 20~26
12. Advice for design .................... 27~29
13. Example of application circuit .................... 30

Note
▪ The contents are subject to change without notice for specification changes or other reasons.
▪ Parts tolerance and characteristics are not defined in all application described in this Date book.
When design an actual circuit for a product, you must determine parts tolerance and characteristics
for safe and economical operation.

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 FA5612, FA5613

1. Description

FA5612/13 is control IC for power factor correction converter. It realizes low power consumption by using high voltage
CMOS process. Thanks to a average current control, a stable operation is obtained, whereby a power factor of 99% or
more is easily available. DC output voltage is controlled under a wide range of load from rated to no load. Further, a
unique switching frequency diffusion function incorporated simplifies the line filter.

2. Features

▪ Unique switching frequency diffusion function incorporated

▪ Selectable switching frequency : Diffuse or Fix (60 kHz, 65 kHz)
▪ High-precision over current protection : 0.5V ± 5%
▪ No audible noise at startup by dynamic OVP circuit
▪ Low current consumption by high voltage CMOS process
Operating : 2mA (typ.)
▪ Enabled to drive power MOSFET directly.
Output peak current, source : 1.5A, sink : 1.5A.
▪ Open/short protection at feedback (FB) pin
▪ Under-voltage lockout
FA5612 : 9.6V ON / 9V OFF FA5613 : 13V ON / 9V OFF
▪ 8-pin package: SOP-8, DIP-8

3. Outline
SOP-8 DIP-8

8 5
6.5

1 4
9.4
4.5 Max.

3.5 Max.
3.4

°
15
～
0.25 ±0.1 0°
2.54 0.5±0.1

7.6
2.54×3=7.62

4. Type of FA5612/13

Type Startup Threshold Package

FA5612N 9.6V (typ.) SOP-8
FA5612P 9.6V (typ.) DIP-8
FA5613N 13V (typ.) SOP-8

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 FA5612, FA5613

5. Block diagram

6. Pin assignment

FB 1 8 VCC

VCMP 2 7 OUT
FA5612N
VDET 3 6 GND

IS 4 5 ICMP

Pin Pin
Function Description
No. symbol
Inverting input for voltage error amplifier.
1 FB Voltage Feedback Input
Input terminal of converter output voltage.
Output of voltage error amplifier.
2 VCMP Voltage Loop Compensation
Phase compensator circuit is connected. *2
3 VDET AC Voltage Input Input terminal for sinusoidal AC input voltage waveform.
4 IS Current Sense Input Input terminal for inductor current signal.
Output of current error amplifier.
5 ICMP Current Loop Compensation
Phase compensator circuit is connected. *2
6 GND Ground Ground
7 OUT Output Output for driving a power MOSFET.
8 VCC Power Supply Power supply for IC control circuit and output circuit. *1
*1 connect the capacitor.
*2 connect capacitor and the resistor.

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 FA5612, FA5613

7. Ratings and characteristics

The contents are subject to change without notice. When using a product, be sure to obtain the latest specifications.
Stress exceeding absolute maximum ratings may malfunction or damage the device.
“+” shows sink and “–“ shows source in current prescription.
(1) Absolute Maximum Ratings
Item Symbol Ratings Unit
Total power supply and Zener Current (VCC) *1 Icc+Iz 15 mA
Supply Voltage (VCC) Icc > 4.8mA Vcc1 - 0.3 to 28 V
*1 Icc < 4.8mA Vcc2 - 0.3 to Self Limiting V
Output voltage (OUT) *4 Vout - 0.3 to VCC + 0.3 V
Output current (OUT) *1 Iout - 1500 to 1500 mA
Output peak current (OUT) *2 Iout_pk Self Limiting mA
input voltage (FB , VDET) Vfb,Vvdet - 0.3 to 5.0 V
Input current (FB , VDET) *3 Ifb,Ivdet -100 to 100 μA
Input voltage (VCMP) Vvcmp - 0.3 to 5.0 V
Input current (VCMP) *3 Ivcmp - 0.5 to 30 mA
Input voltage (ICMP) Vvcmp - 0.3 to 5.0 V
Input current (ICMP) *3 Iicmp - 0.2 to 30 mA
Input voltage (IS) Vis - 5.0 to 1.0 V
Input current (IS) *3 Iis - 300 to 100 μA
Power dissipation DIP-8 Pd1 800 mW
SOP-8 Pd2 400 mW
Operating Junction Temperature Tj - 30 to +150 °C
Storage temperature Tstg - 40 to +150 °C
*1 Must not exceed power dissipation.
*2 Period exceeding 1500mA must be 100ns or less.
*3 When the pin current flows continuously for 100ns or more.
*4 The period of 100ns (dead time period) when the voltage of the terminal OUT changes Low⇒High is out of
the question.

Maximum dissipation curve

Package thermal resistor *5

400mW(SOP)
800mW(DIP) θj-a= 312°C/W, θj-c= 72°C /W (SOP-8)

θj-a= 156°C/W, θj-c= 50°C /W (DIP-8)

許容損失 Pd (mW)
Maximum disspation

-40 25 105 150

Ambience
周囲温度 temperature
Ta(℃) Ta (°C)
*5 JEDEC standard test board

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 FA5612, FA5613

(2) Recommended Operating Conditions

Item Symbol Min. Typ. Max. Unit
Supply Voltage Vcc 10 18 26 V
VDET pin input voltage Vvdet 0 - 2.4 V
VDET pin peak input voltage Vpvdet 0.54 - 2.4 V
IS pin voltage Vis - 1.0 - 0.5 V
IS pin connection noise filter resistance Risf - - 100 Ω
Ambiance temperature in operation Ta -40 - 105 ℃

Item Symbol Resistance Accuracy Temperature

characteristics
Frequency setting Frequency diffusion Rg1 4.7kΩ ±5% 200ppm/°C
resistance *2 65kHz fixed Rg2 12kΩ ±2% 200ppm/°C
13kΩ ±5% 200ppm/°C
60kHz fixed Rg3 27kΩ ±5% 200ppm/°C
*2) For connection in Fig.2, Ro range: 0 to 100Ω

VCC
8
Driver
OUT
7
Ro
Rg
6
GND

Fig.1 IS pin-connected filter resistance Fig.2 Frequency setting resistance

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(3) Electrical Characteristics (Unless otherwise specified, Vfb=2.5V, Vvcmp=2.5V, Vvdet=0V, Vis=0V, Vicmp=2.0V,
Vcc=18V, Rg=4.7kΩ, Tj=25°C)
“+” shows sink and “–“ shows source in current prescription.
Voltage amplifier (FB, VCMP pin)
Item Symbol Condition Min. Typ. Max. Unit
Voltage feedback input threshold Vref Ivcmp = 0uA 2.450 2.500 2.550 V
Line regulation Regline Vfb = Vref, Vcc = 10V to 26V - 12.5 - 12.5 mV
Temperature stability VrefdT Vfb = vref, Tj = - 30°C to 150°C - 0.5 - 0.5 mV/°C
Transconductance Gmv Vfb = Vref ± 0.3V 70 90 120 µmho
Ivsrc Source : Vfb = 1.5V - 70 - 50 - 30 µA
VCMP output current
Ivsnk Sink : Vfb = 3.5V 30 50 70 µA
VCMP output H voltage Vvcmph Vfb = 1.5V - - 5.5 V
VCMP transient response Source : Vfb = 1.5V
Iresp - 170 - 140 - 110 µA
output current
VCMP transient response 0.902 0.940 0.978
Vresp V
detection voltage *Vref *Vref *Vref

Current amplifier (ICMP pin)

Item Symbol Condition Min. Typ. Max. Unit
Transconductance Gmc Vis= - 0.2V to - 0.4V, Vvdet *1 40 60 80 µmho
Icsrc Source : Vvdet = 3.5V - 70 - 50 - 30 µA
Output current
Icsnk Sink : Vis = -2.0V, 30 50 70 µA
Vicmp = 3.0V
ICMP clamp voltage Vclamp 2.6 2.7 2.9 V
Iicmp max = 320μA
*1 Vvdet is for when Vis = -0.3V, Iicmp = 0µA

Multiplier
Item Symbol Condition Min. Typ. Max. Unit
VDET input bias current Ivdet Vvdet = 0V, - 1.5 -0.5 0 μA
VCMP threshold voltage Vthvcmp Vvdet = 2.4V 0.3 0.5 0.7 V
Vvcmp = 1V, Iicmp = 0μA
Output voltage coefficient K Vvdet = 0.3V, 1.3V 0.5 0.70 0.95 -
Vis = 0.1V to -0.2V

Oscillator
Item Symbol Condition Min. Typ. Max. Unit
Frequency diffusion Vvdet = 0.88V, Vis = - 0.18V,
Fswref 54 60 66 kHz
(reference frequency) Vvcmp *1, Iicmp = 0µA,
Vvdet = 0.88V, Vis = - 0.18V,
Frequency
FswrefdT Vvcmp *1, -0.06 - 0.06 kHz/°C
temperature stability
Iicmp = 0µA,Tj=-30°C to 125°C
Frequency diffusion
Fswmax Vvcmp = 0V, Vvdet = 2.4V 64 68 70 kHz
(maximum frequency)
Frequency diffusion,
Fswmin Vvcmp = 0V, Vvdet = 0V 50 52 55 kHz
(minimum frequency)
Fixed frequency 1 Fsw1 Vout2 < Vout 54 60 66 kHz
Fixed frequency 2 Fsw2 Vout1 < Vout < Vout2 58.5 65 71.5 kHz
Vvdet = 2.4V,
Maximum duty cycle DMAX 91 94 97 %
ICMP no connect
*1 Vvcmp is for when Vvdet = 0.88V, Vis = -0.18V, Iicmp = 0µA

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 FA5612, FA5613

Overvoltage protection comparator (FB pin)

Item Symbol Condition Min. Typ. Max. Unit
Vfb = 2.5V to 2.9V,
Static OVP threshold voltage Vsovp 1.070*Vref 1.090*Vref 1.105*Vref V
Vvcmp = 0V, Vvdet = 0V
Vfb = 2.9V to 2.5V,
Hysteresis Vsovphys 0.005*Vref 0.020*Vref 0.040*Vref V
Vvcmp = 0V, Vvdet = 0V
Vfb = 2.5V to 2.9V, Vvcmp = 0V
Static OVP temperature stability VsovpdT -0.0001*Vref - 0.0001*Vref V/°C
Vvdet = 0V, Tj= -30°C to 125°C
Dynamic OVP threshold voltage Vfb = 2.5V to 2.8V,
Vdovp 1.025*Vref 1.050*Vref 1.075*Vref V
Vvcmp = 1V, Vvdet = 2V
⊿OVP ⊿OVP Vsovpn -Vdovp 50 95 140 mV

FB short detection comparator (FB pin)

Item Symbol Condition Min. Typ. Max. Unit
Input threshold voltage Vthfb Vfb = 0V to 1V,
0.1 0.3 0.5 V
Vvcmp = 0V
Pull-down resistance Rfb Vfb = 2.5V 2.0 2.5 3.0 MΩ

Overcurrent detection comparator (IS pin)

Item Symbol Condition Min. Typ. Max. Unit
IS offset voltage Visof Vvdet = -0.25V, Vvcmp = 0.6V 0 30 60 mV
IS pin voltage Vis_054 Vvdet = 0.54V, Vvcmp = 5.0V - 0.43 - 0.38 - 0.33 V
Vvdet max = 1.2V,
Vocpl Vvdet min = 0V, Fvdet = 50kHz, - 0.525 - 0.50 - 0.475 V
Dvdet=50%
IS threshold voltage
Vvdet max = 1.8V,
Vocph Vvdet min = 0V, Fvdet = 50kHz, - 0.432 - 0.40 - 0.368 V
Dvdet=50%
Vvdet max = 1.2V,
IS threshold voltage Vvdet min = 0V, Fvdet = 50kHz
VocpldT - 0.1 - 0.1 mV/°C
temperature characteristics Dvdet=50%,Vis = -0.4V to -0.6V
Tj=-30°C to 125°C
Vvdet max = 1.2V, to 1.8V
Vvdeth Vvdet min = 0V, Fvdet = 50kHz 1.54 1.60 1.66 V
Dvdet=50%,Vis= -Vocpl + 0.05V
VDET threshold voltage
Vvdet max = 1.8V to 1.0V,
Vvdetl Vvdet min = 0V, Fvdet = 50kHz 1.30 1.35 1.40 V
Dvdet=50%,Vis= -Vocpl + 0.05V
Vvdet max = 1.8V
IS threshold change voltage Vvdets Vvdet min = 0V, Fvdet = 50kHz 0.25 0.30 0.35 V
Dvdet=50%,Vis= -Vocpl + 0.05V
Blanking time *1 Tblk Vis= -0.6V 300 450 600 ns
Vis = Vocpl + 30mV to-1.0V
Delay time Tdly 200 350 500 ns
Pulse signal
Input bias current Iis Vvcmp = 0V, Vis = 0V - 170 - 120 - 70 μA
*1 Includes delay time

Output (OUT pin)

Item Symbol Condition Min. Typ. Max. Unit
Vfb = 0V, Vvcmp = 0.3V,
Output voltage (L) Voutl Vicmp = 3V to 2V, - 0.5 1.0 V
Sink : Iout = 100mA
Vvcmp = 0.3V,
Output voltage (H) Vouth Vicmp = 3V to 2V, 15.5 16.5 - V
Source : Iout = - 100mA
Output rise time Tr CL = 1nF - 50 - ns
Output fall time Tf CL= 1nF - 50 - ns

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 FA5612, FA5613

Frequency setting (OUT pin)

Item Symbol Condition Min. Typ. Max. Unit
Detection current Istate Tj=-30°C to 125°C 34 40 46 μA
Vout1 Tj=-30°C to 125°C 260 310 390 mV
OUT threshold voltage
Vout2 Tj=-30°C to 125°C 700 760 830 mV
Vvcmp = 0V, Vicmp = 0V
Frequency setting time *1 Tset 4.1 5.9 7.7 ms
Vfb = 2V
Tdet Vvcmp = 0V, Vicmp = 0V
Detection time *2 420 530 640 μs
VFfb= 2V
*1: Time elapsing until detection current is outputted from OUT pin after removal of UVLO
*2: Period during which detection current is outputted from OUT pin

Low voltage protection (VCC pin)

Item Symbol Condition Min. Typ. Max. Unit
FA5612: Vcc= 8V to 11V 8.6 9.6 10.6 V
ON threshold voltage Vccon
FA5613: Vcc= 11V to 15V 11.5 13 14.5 V
OFF threshold voltage Vccoff Vcc= 11V to 7V 8.0 9.0 10.0 V
FA5612 0.4 0.6 0.8 V
Hysteresis Vcchys
FA5613 3.5 4.0 4.5 V

All devices (VCC pin)

Item Symbol Condition Min. Typ. Max. Unit
Vcc = 8V, Vvcmp = 0V
Start-up current Istart 70 90 110 µA
Vicmp =0V
Operating current Icc OUT pin no load - 2.0 4.0 mA
OUT pin no load
OFF time current Iccoff - 1.8 3.8 mA
Vvcmp=0V
Vcc = 18V, Vfb = 0V
Standby current Istb 80 110 180 µA
Vvcmp=0V, Vicmp =0V

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8. Characteristics curves

(Unless otherwise specified, Vfb = 2.5V, Vvcmp = 2.5V, Vvdet = 0V, Vis = 0V, Vicmp = 2.0V, Vcc = 18V, Rg = 4.7kΩ, Tj = 25°C)

Voltage error amplifier: Input threshold (Vref) Voltage error amplifier: Input threshold (Vref)
vs. Supply voltage (Vcc) vs. Junction temperature (Tj)
2.55 2.55

2.53 2.53

2.51 2.51

Vref [V]
Vref [V]

2.49 2.49

2.47 2.47

2.45 2.45
10 15 20 25 30 -50 0 50 100 150
Vcc [V] Tj [°C]

Oscillator: Reference, maximum, minimum frequency ） Oscillator: Reference, maximum, minimum frequency
(Fswref, Fswmax, Fswmin) vs. Supply voltage (Vcc) (Fswref, Fswmax, Fswmin) vs. Junction temperature (Tj)
70 75
Fswref,Fswmax,Fswmin [kHz]

Fswref,Fswmax,Fswmin [kHz]
Fswmax
70
66 Fswmax
65
62
60 Fswref
Fswref
58
55 Fswmin
54 50
Fswmin
50 45
10 15 20 25 30 -50 0 50 100 150
Vcc [V] Tj [°C]

Oscillator: Fixed frequency 1,2 (Fswr1, Fsw2) Oscillator: Fixed frequency 1,2 (Fswr1, Fsw2)
vs. Supply voltage (Vcc) vs. Junction temperature (Tj)
70 75

70
66
Fsw2(65kHz)
Fsw1,Fsw2 [kHz]

Fsw1,Fsw2 [kHz]

65 Fsw2(65kHz)
62
Fsw1(60kHz) 60
58
55 Fsw1(60kHz)

54 50

50 45
10 15 20 25 30 -50 0 50 100 150
Vcc [V] Tj [°C]

Oscillator: Maximum duty cycle (Dmax) Overcurrent detection: IS threshold voltage (Vocpl, Vovph)
vs. Junction temperature (Tj) vs. Junction temperature (Tj)
98.0 -0.37
97.0 -0.39
96.0 -0.41
Vocpl,Vocph [V]

Vocph
95.0
Dmax [%]

-0.43
94.0 -0.45
93.0 -0.47
Vocpl
92.0 -0.49
91.0 -0.51
90.0 -0.53
-50 0 50 100 150 -50 0 50 100 150
Tj [°C] Tj [°C]

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Current error amplifier: Output current (Iicmp) Current error amplifier: Output current (Ivcmp)
vs. IS pin voltage (Vis) vs. FB pin voltage (Vfb)
60 60

40 40

20 20

Ivcmp [uA]
Iicmp [uA]

0 0

-20 -20

-40 -40

-60 -60
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Vis [V] Vfb [V]

Multiplier: IS pin voltage (Vis) Overvoltage comparator: Dynamic/static OVP

vs. VDET pin voltage (Vvdet) (Vdovp/Vref, Vsovp/Vref) vs. Junction temperature (Tj)
100 1.105

0 1.095

Vdovp / Vref, Vsovp / Vref

Vvcmp=0.6V 1.085 Vsovp
-100
Vvcmp=2.0V 1.075
Vis [V]

-200
Vvcmp=1.5V 1.065
-300 Vvcmp=1.0V
1.055
-400
1.045 Vdovp
Vvcmp=3.0V
-500 1.035
-600 1.025
0.0 0.5 1.0 1.5 2.0 2.5 3.0 -50 0 50 100 150
Vvdet [V] Tj [°C]

OUT pin: Output voltage(L) (Voutl) OUT pin: Output voltage(H) (Vouth) vs. Supply voltage (Vcc)
vs. Supply voltage (Vcc) Vcc - Vouth
0.8 2
0.7 1.8
1.6
0.6
Vcc - Vouth [V]

1.4
0.5 1.2
Voutl [V]

0.4 1
0.3 0.8
0.6
0.2
0.4
0.1 0.2
0 0
10 15 20 25 30 10 15 20 25 30
Vcc [V] Vcc [V]

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Current consumption: Operating current (Icc) Under voltage lockout: VCC threshold voltage (Vccon, Vccoff)
FA5612 vs. Supply voltage (Vcc) FA5612 vs. Junction temperature (Tj)
4.0 10.5
3.5 10.3
10.1
3.0

Vccon, Vccoff [V]

9.9 Vccon
2.5
Icc [mA]

9.7
2.0 9.5
1.5 9.3
9.1
1.0
8.9 Vccoff
0.5
8.7
0.0 8.5
0 5 10 15 20 25 30 -50 0 50 100 150
Vcc [V] Tj [°C]

Current consumption: Operating current (Icc) Under voltage lockout: VCC threshold voltage (Vccon, Vccoff)
FA5613 vs. Supply voltage (Vcc) FA5613 vs. Junction temperature (Tj)
4.0 14.5
3.5
13.5
3.0

Vccon, Vccoff [V]

2.5 12.5
Vccon
Icc [mA]

2.0 11.5
1.5
10.5
1.0
Vccoff
0.5 9.5

0.0 8.5
0 5 10 15 20 25 30 -50 0 50 100 150
Vcc [V] Tj [°C]

Current consumption: Operating current (Icc)

vs. Junction temperature (Tj)
4.0
3.5
3.0
2.5
Icc [mA]

2.0
1.5
1.0
0.5
0.0
-50 0 50 100 150
Tj [°C]

電圧誤差増幅 過渡応答検出電圧（Vresp）
Current error amplifier. Output current (Iicmp) Overvoltage comparator ⊿OVP ⊿OVP
過電圧コンパレータ
vs. Junction temperature (Tj)
vs. ジャンクション温度（Tj） vs. ジャンクション温度（Tj）
vs. Junction temperature (Tj)
0.970 140
0.965 130
0.960 120
⊿OVP [mV]
Vresp [V/V]

0.955 110
0.950 100
0.945 90
0.940 80
0.935 70
0.930 60
0.925 50
-50 0 50 100 150 -50 0 50 100 150
Tj [℃] Tj [ ℃]

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 FA5612, FA5613

9. Outline of circuit operation

FA5612/FA5613 are controllers for power factor correction converter using
boost topology. These IC are designed for the CCM mode operation with the
average current control.
The operations, (1) Switching and (2) Power factor collection, are explained
as below with the simplified circuit diagram shown in Fig.1.

(1) Switching operation

Fig. 2 outlines the waveform of each part of switching operation at a steady
state. The operation is as follows.
I. Set signal of switching frequency outputted from the oscillator sets RS. F/F,
whereby OUT pin voltage goes high, thus turning on Q1. ... (t1)
II. Q1 turned on raises the current of L1. The current of L1 is converted by
Rs connected on GND side into a voltage and is inputted to IS pin (VIS). VIS
is compared by current amplifier (CUR. AMP) with reference voltage that is
obtained via arithmetic output by multiplier (MUL) from input voltage
monitoring VDET and VCMP that is obtained by feedback from output and
error amplification.
Current amplifier output (ICMP) is compared by PWM comparator (PWM.
COMP) with slope waveform outputted from oscillator and, as soon as it Fig.1 Block diagram of operating circuit
attains the reference value, reset signal enters RS. F/F, thereby turning off
Q1. ... (t2)
III. Q1 turned off inverts the voltage of L1. While a current is being fed to the
output via D1, the current of L1 reduces. Set signal outputted from internal
oscillator transfers the circuit to the next switching cycle. ... (t1)

(2) Power factor correcting operation

The voltage at VCMP pin that constitutes output of error amplifier
(ERR.AMP) is almost DC voltage at a steady state, because of connected
phase compensation capacitance. This voltage is inputted to multiplier.
Another input to multiplier is a waveform obtained by rectifying AC input
voltage. A multiplier multiplies these two of input and outputs a sinusoidal
wave proportional to AC input voltage.
This outputted sinusoidal voltage waveform is applied as a reference
inductor current to current amplifier (CUR.AMP).
Therefore, the inductor current's mean value forms a sinusoidal waveform.
The current of inductor L1 is deprived of switching ripples by C1 and is
turned into a average current. Thus, the current from AC input voltage
becomes practically sinusoidal, thus improving the power factor.
L1 D1 Fig.2 Waveforms of switching operation (outline)
AC I
C1 Q1
t Rs

V IS ICMP
4 5
V IL Detector
C1 removes ripples caused
t CUR.AMP
VDET by switching from current
V
3 MUL
t ERR.AMP FB
(正弦波)
Sinusoidal V 1
t
(正弦波)
Sinusoidal

2
VCMP
V

t
(ほぼDC)
Almost DC

Fig.3 Aspects of waveforms at different parts Fig.4 Power factor corrected waveform

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10. Description of each circuit block

OUT Ro
(1) Frequency setting circuit Driver 7
The switching frequency is selectable out of 3 modes by resistance Rg connected Istate Rg
between OUT and GND pins.

END信号：
▪ Mode 1: Frequency diffusion 50 kHz to 70 kHz State
END signal:
各 ブロック始動開始
Each block starts up
▪ Mode 2: Fixed frequency 1 65 kHz Set
UVLO_L
▪ Mode 3: Fixed frequency 2 60 kHz OSC

The status setting is completed after FB short detection or UVLO are canceled. The
switching operation will start after this completion. Therefore, the mode will not Fig.5 Frequency setting circuit
change while operating.
VCC
Vccon
As an example, the operation of frequency setting which is in case of a cancellation
Internal
of UVLO is shown in Fig. 6. 内部電源
power
IC starts to operate after Vcc exceeds Vccon. Then after 5.9ms, the OUT pin supply

outputs current Istate (40mA (typ.)) during 530us.

Istate
The current generates a voltage at OUT pin because external resistors (Ro and Rg)
are connected to OUT pin.
END信号
END
The frequency setting is done with based on this OUT pin voltage. signal
The internal circuits start switching operation after frequency setting. 0.5V VCMP

Likewise, in case of cancellation of FB short detection, 5.9ms after the cancellation,

a current is outputted from OUT pin for 530us, and then switching starts. Istate*(Ro+Rg)
OUT
0V
OUT pin has in its inside reference voltages of 2 levels, or Vout1 (310mV (typ.)) and 時間
time
Vout2 (760mV (typ.)) To select a frequency, a reference voltage is compared with Tset Tdet
5.9ms 530us
OUT pin voltage while current Istate is flowing. The relationship is as follows.
Fig.6 Frequency setting sequence

OUT pin voltage OUT pin < Vout1 Vout1 < OUT pin < Vout2 Vout2 < OUT pin
Mode Mode1 Mode2 Mode3
Frequency Frequency diffusion Fixed frequency 65kHz Fixed frequency 60kHz

(2) Oscillator
Oscillator outputs two signals. One is a set signal to flip-flop for setting the OUT pin to Vcc level. Another is a sawtooth signal for PWM
comparison.
The oscillation frequency is set by frequency setting circuit to either the frequency diffusion mode or 2 kinds of the fixed frequency mode.

(2-1) Frequency diffusion

When the frequency diffusion mode is selected, the frequency changes
between 50 and 70 kHz according to the input/output status of PFC power
VDET
supply. The optimized frequency diffusion based on input/output status 3
CUR.AMP.
realizes a low noise operation with a wide operation range. VCMP Multiplier
OSC block determines the frequency based on VDET pin input voltage and 2
multiplier block output voltage. When the phase angle is range of 0° to 30°
or 150° to 180° approximately, the frequency rises in proportion to VDET pin IL
Detector
voltage. When it is range of 30° to 150° approximately, the frequency is
PWM Comp.
reversely proportional to the multiplier output. (Fig.8) OSC
F.F. Set
Set信号
signal
When the multiplier output is high like when PFC output current is large, the
frequency drop is bigger. And it is small in case of reverse situation.
Fig.7 Block diagram for oscillator area

The approximate frequency (Fsw_b) is given by an equation below when the phase angle is range of 30° to 150°.

Fsw_b = 75 – 71.4 × (IS pin voltage) [kHz]

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(2-2) Maximum and minimum frequencies in frequency diffusion mode

As stated above, the switching frequency in the frequency diffusion mode Region subject
乗算器出力により
depends on VDET pin or multiplier output voltage within maximum and Fsw
to変化する領域
multiplier output
minimum frequencies determined. However, maximum or minimum
frequency may never appear under some conditions while 1/2 of AC cycle. 70kHz

(3) Error amplifier VDET電圧により

Region subject
The error amplifier is a circuit for controlling PFC output to a certain level. 変化する領域
to VDET voltage
50kHz
This IC adopts a transconductance amplifier.
The non-inverting input terminal for the error amplifier is connected to the
30° 60° 90° 120° 150° 180°
internal reference voltage of 2.5 V (typ.) The inverting input terminal (FB)
位相角
Phase angle
receives the output voltage, usually resistively divided, from power factor
correction converter. For FB open detecting function, this terminal is Fig.8 Oscillation frequency vs. phase angle
connected to a pull-down resistor of 2.5MΩ inside the IC. Error amplifier
output (VCMP) is connected to multiplier (MUL) to control the inductor
current.
Output voltage Vout of power factor correction converter usually contains a R3
C4
lot of ripples of double the AC line frequency (50 or 60 Hz). When ripples
C5
corresponding to double the AC frequency appear excessively on the error
Vout VCMP
amplifier output, power factor correction converter will not operate stably. So, 2
a capacitor and resistor network is connected between pin 2 (VCMP) which
VREF(2.5V)
is output of the error amplifier and GND for phase compensation.
Increasing the capacitance in the phase compensation network improves R1
FB
the power factor, but the transient responsivity becomes slow. MUL
1
The error amplifier in FA5612/13 has a function of improving the transient R2 C3 2.5M ERRAMP
responsivity. Ω Open/Short Ｃｏｍｐ

When the load has suddenly become so heavy, the FB pin voltage drops SP
much. If lowered FB pin voltage is below transient response detection Vthfb(0.3V)

voltage (Vresp), the transient response correction circuit increases output

Ｄｙｎａｍｉｃ ＯＶＰ
current of error amplifier up to the transient response output current (Iresp). O.V.P
Static ＯＶＰ
Thus, the VCMP pin voltage rises quickly to increase the output current and
suppress the output voltage drop.
Fig.9 Error amplifier and overvoltage
(4) Overvoltage protection circuit (OVP)
This is a circuit for limiting the voltage when the output voltage of power protection circuit
factor correction converter has exceeded the setting.
When converter is started up or when the load has suddenly changed, the
converter output voltage may rise beyond the setting. In such a case, OVP
circuit prevents an over voltage and protects the converter.
FA5612/13 has a dynamic OVP function and a static OVP function. The Vo
7 OUT
dynamic OVP function restricts the multiplier gain depending on rising of FB
SP
pin voltage while FB pin voltage exceeds 2.5 V. The static OVP function
Output stop
出力停止 R1 Open
makes OUT pulses stop while FB pin voltage exceeds 1.09 time of the 0.3V オープン
FB
reference voltage. Detect
検出
1
In normal operation, the FB pin voltage is 2.5 V that is almost the same as
the reference voltage of error amplifier. 2.5MΩ R2 ショート
Short
When the FB pin voltage exceeds 2.5 V by startup or a sudden change of VFB=0V
load, the dynamic OVP function reduces output current by lowering the
multiplier gain. Then, if the FB pin voltage still rises and exceeds the
reference voltage of a static OVP function, FA5612/13 stops the output Fig.10 FB open/short detector
pulses.
OUT pulses stopped by the overvoltage protection are resumed as soon as
the output voltage lowers back to 1.07 times the reference voltage.

(5) FB short/open detector

On the circuit of Fig. 10, if the FB pin voltage is zero because of R2 short or R1 open, the error amplifier can not control the constant voltage.
Therefore, the output voltage rises abnormally. In such a case, the overvoltage protection circuit could not operate because the output voltage
detection is faulty.

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To avoid such inconvenience, the IC has FB short detector.

The circuit consists of reference voltage of 0.3 V (typ.) and comparator
(SP).
When the FB pin input voltage has dropped below 0.3 V because of R2
short or R1 open, the output of comparator (SP) is inverted to stop the IC
output.

The PFC converter outputs a voltage corresponding to the input voltage

even before startup because of the boost topology. That is why, this
function never operate as long as the converter is normal.
In case of an open failure of the FB pin FA5612/13 stops the output pulse
by this function because a pull-down resistor of 2.5 MΩ inside the IC is
Sinusoidal
Sinusoidal
connected to the FB pin.
If the FB pin voltage has dropped to almost zero, the IC output will stop.
When the FB pin voltage returns normal then, OUT pulses will reappear.
Almost DC
(6) Multiplier
Multiplier is the circuit for controlling the input current as the sinusoidal
wave forms the same as input voltage. Fig.11 Multiplier
An input is connected to VDET pin and is inputted the dividing voltage
after being rectified from AC input voltage. The other input is connected to
error amplifier output (VCMP). Normally, the error amplifier output is
almost DC, and multiplier outputs a sinusoidal waveform voltage whose
amplitude changes according to the error amplifier output voltage. The
multiplier output constitutes a reference for current comparator to control
the input current to a sinusoidal waveform (Fig. 11).

It usually makes MUL pin peal voltage set to 0.65 to 2.4 V in the all AC
input range.
The voltage obtained by rectifying the AC input voltage contains many
noises attributable to switching by Q1. To eliminate the influence by the
noise, filtering capacitance C6 is provided usually.

(7) Current detector

IL. Detector inverts and amplifies a voltage obtained by voltage-current
conversion via current detecting resistance Rs of the inductor current.
Current amplifier (CUR. AMP) is error amplifier that composes a current
loop to make the input current follow a sinusoidal waveform.
Current amplifier receives IL. Detector output and multiplier (MUL) output,
subjects them to comparison and error amplification, and outputs the
result to PMW comparator (PWM. COMP).
Current amplifier is a transconductance amplifier the same as error
amplifier. Capacitance and resistance connected between output
terminal (ICMP) and GND for phase compensation eliminate switching
ripples of the input current.
The current detector output is clamped to Vclamp: 2.7 V by clamp circuit
that constitutes an upper limit of voltage.
Fig.12 Current detector and overcurrent
(8) Overcurrent protection circuit (OCP)
OCP circuit is the circuit to detect the inductor current, and is to stop the protection circuit
output pulse to protect MOSFET when detected current exceeds certain
intensity.
A detected voltage by sense resistor Rs connected to GND is inputted to the IS pin, is converted by the IL_Detector which is an inverting
amplifier, and is compared by overcurrent detection comparator. When IS pin voltage lowers below a threshold value (OCP level), overcurrent
protection circuit outputs a signal of an overcurrent status.
The signal of overcurrent status resets a flip-flop for the OUT pulse, and then turns MOSFET off.
When IS voltage gets near a threshold value, overcurrent protection circuit lowers the gain of multiplier (MUL) to suppress the input current,
thereby suppressing the audible noise of inductor attributable to an overcurrent.

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OCP level is changed depending on the peak voltage of VDET pin by VIN_Detector as follows.
While period A, OCP level is set to Vocph (-0.4 V) because VDET pin voltage exceeds threshold voltage Vvdeth (1.6 V). OCP level is changed
only when VDET pin voltage is below Vvdets (0.3V). At this time, the inductor current is low enough, and therefore will not abruptly change.
Further, if the load current is very low such VDET will not be below 0.3 V, the OCP level will not change over regardless of VDET.

During period B, VDET will never go below threshold voltage Vvdetl: 1.35 V. Therefore, OCP level will not change either.
Some time in period C, VDET will be below threshold voltage Vvdetl: 1.35 V, whereby OCP level is set to Vocpl (-0.5 V). The same as period A,
OCP level is changed only when VDET pin voltage is below Vvdets (0.3 V).

VDET terminal voltage Period A Period B Period C

OCP level

Fig.13 Overcurrent protection (OCP) level and VDET voltage

(9) Undervoltage lockout circuit (UVLO)

FA5612/13 has the UVLO circuit to avoid unexpected operation when the source voltage has dropped.
The IC starts operation when the source voltage rising from zero has reached 9.6 V (typ.) for FA5612, or 13 V (typ.) for FA5613.
After startup, each of ICs stops operating when the source voltage has dropped to 9 V (typ.)
While the IC stops a switching operation by UVLO circuit, the IC keeps OUT pin voltage low and further reduces IC consumption current
to below 100 μA.

(10) Output circuit

The output circuit consists of a push-pull circuit, directly drives MOSFET.
Its maximum peak current is 1.5 A for sink, and 1.5 A for source.

(11) Zero current correction circuit

Unless multiplier output or current error amplifier input has offset voltage, the input current to converter will be almost zero when PFC converter
has completely no load.
However, if the offset voltage viewed from IS pin is negative, the input current corresponding to offset voltage might flow to converter even
when no load or light load. In such a case, the output voltage of power factor correction converter will rise abnormally because the input current
will be excessive.
Offset voltage in the IS pin (Visof) is 0 mV. However, the offset voltage of the IS pin against sense resistor voltage may be negative because a
voltage will be generated by an external filter resistance connected to the IS pin. Therefore, FA5612/13 has this correction circuit to avoid rising
the output voltage when light load with such case.

Usual output voltage from error amplifier is 0.5 V or higher. When its output voltage has dropped below 0.5 V, zero current correction circuit
operates.
Error amplifier output voltage drops below 0.5 V when an input current flows under no or light load on account of offset in multiplier output or
current error amplifier input. Then, zero current correction circuit corrects the offset voltage of multiplier output. This function prevents the output
voltage of power factor correction converter from rising excessively, so that the output voltage is kept at a constant level.
The correction amount varies in a linear function of the output of current error amplifier, thereby ensuring a stable run.
Fig. 14 shows effects of zero current correction circuit.

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Consumption diagram of operations when IS pin offset is negative

Input current

軽負荷時補正回路なし
Without zero current correction circuit 軽負荷時補正回路あり
With zero current correction circuit

定格負荷 定格負荷
AC 交流入力電流

AC 交流入力電流
input current

input current
Rated load Rated load

Effect by light load

軽負荷時補正回路
No load による効果
correction circuit
無負荷

オフセットに相当する電流
Current corresponding to offset
無負荷
No load
0 時間 0 時間
Time Time
交流入力電圧の1/2周期 交流入力電圧の1/2周期
1/2 cycle of AC input voltage 1/2 cycle of AC input voltage

Output voltage
Without zero current correction circuit
軽負荷時補正回路なし
factor correction
力率改善コンバータ
Vo
Output voltage Vo
出力電圧
of power

軽負荷時補正回路あり
With light load correction circuit

0 力率改善コンバータ
Output power Po
出力電力 Po
of power factor correction
Fig.14 Effects of zero current correction circuit

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11. Description of use for each pin

(1) Terminal No.1 (FB pin)

Functions
Vout
(i) Inputs feedback signal of output voltage setting
(ii) Detects FB pin open/short
(iii) Detects output overvoltage state VREF(2.5V)
Applications R1
FB
(i) Feedback signal input VCMP
1
▪ Wiring
R2 ERRAMP
Connect the node of dividing resistance for output voltage setting C3 Rfb
Open/Short Ｃｏｍｐ
▪ Operation SP
The PFC output voltage is controlled so that the FB pin voltage will correspond
Vthfb(0.3V)
to the internal reference voltage (2.5 V).
For FB pin open circuit, FB pin is connected with pull-down resistance in IC
inside. Therefore, take its resistance into account when choosing the resistance Ｄｙｎａｍｉｃ ＯＶＰ
O.V.P
Static ＯＶＰ
of R1 and R2 to set the output voltage (Vout).
Vout  (R2  Rfb) /(R2  Rfb)  VREF  R1  VREF
where:
VREF: Reference voltage = 2.5 V (typ.) Fig.15 FB pin circuit
Rfb: FB pin pull-down resistance = 2.5 MΩ (typ.)
To avoid an erratic operation by noises, connect capacitance C3 of 100 to 3300
pF between FB pin and GND.
(ii) FB pin open/short detection
▪ Wiring
Same as feedback signal input in (i)
▪ Operation
When, on account of FB pin open circuit or short circuit of R2 in resistive divider,
the FB input voltage has dropped below 0.3 V, the output of comparator (SP) is
inverted, thereby stopping the IC output.
(iii) Output overvoltage detection
▪ Wiring
Same as feedback signal input in (i)
▪ Operation
In normal operation, FB pin voltage is almost the same as reference voltage of
error amplifier (2.5 V). Like when the output voltage has risen for some reason, if
the FB pin voltage reaches comparator reference voltage (1.09*VREF),
comparator (OVP) output is inverted to stop OUT pulses. As soon as output
voltage returns to a normal level, OUT pulses are recovered.

(2) Terminal No.2 (VCMP pin)

Function
(i) Phase compensation of output of incorporated voltage error amplifier
(ERRAMP) VCMP
Application 2
(i) Phase compensation of incorporated ERRAMP output
▪ Wiring ERRAMP R3
Connect R and C between COMP and GND as shown in Fig. 16 C4
MUL C5
▪ Operation
COMP pin avoids an appearance of the double frequency ripple of the AC line
on the FB pin voltage with connecting R and C.
Reference: Fig.16 VCMP pin circuit
Example of applied circuit: C4 = 0.47 uF
C5 = 2.2 uF
R3 = 10 kΩ
The above is an example. Determine them upon sufficiently verifying your
instrument.

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Besides, Soft start function is realized by slowing a voltage rise of COMP pin
with adjustment of capacitance connected between COMP and GND.
When starting, VCMP voltage rises and a switching operation starts at 0.5 V.
At this time, MOSFET ON width increases gradually in proportion to the COMP C1
voltage rise. The soft start time is adjustable with adjustment with changing
capacitors C4 and C5.
R6
Increasing C4, C5 capacitance → prolongs soft start time VDET
Decreasing C4, C5 capacitance → shortens soft start time 3
C6 R7
(3) Terminal No.3 (VDET pin)
Function
(i) Input voltage detection (multiplier input)
Application Fig.17 VDET terminal circuit
(i) Input voltage setting for VDET pin
Multiplier generates current reference signal. Its VDET pin (pin 3) receives
sinusoidal full-waveform rectified waveforms. Considering the dynamic range of
multiplier operation, VDET pin peak value would be used within 0.65 to 2.4 V.
Therefore, set R6 and R7 in Fig. 17 so that the peak voltage of sinusoidal L1 D1
waveforms at VDET pin will be between 0.65 and 2.4 V with the entire range of
AC input voltage.
C1 Q1
Recommended dividing ratio: R6:R7 = 160:1 C2
Rs
Caution:
Because multiplier has dispersions of characteristics, even if VDET pin voltage R4
is 2.4 V or lower, multiplier might be saturated and the input peak current would
slightly be truncated like trapezoidal waves.
C6
IS
(4) Terminal No.4 (IS pin) 4
Functions
(i) Inductor current detection 12kΩ
(ii) Turn off OUT output upon detecting an overcurrent IL
Applications Detector
(i) Via IS pin, inductor current signal is applied to current error amplifier 28kΩ
(CUR_AMP) that constitutes a current loop for making the input current follow
sinusoidal waveforms. CUR_AMP that is connected with multiplier output 5V
receives current reference signal. IS pin is current input terminal, and receives a Fig.18 IS pin circuit
potential of 0 to -0.4 V with respect to GND level.
(ii) When IS pin voltage is lower than IS threshold voltage, comparator output
signal is inverted to turn off OUT output.
▪ Supplement
When MOSFET turns on, MOSFET gate drive current and surge current are
generated by discharge of stray capacitance, and then those currents flow to L1 D1
current detecting resistance Rs. An excessively large surge current may cause
an erratic operation to disturb the input current waveform. Depending on the C2
surge current intensity, timing, etc., pulse shoots may mix with turn-on parts of Q1
IC's OUT pulses. So, RC filter shown in Fig. 18 is connected in generally.
Since the level is determined by resistive division as shown in Fig. 18, 100 Ω or
lower is recommended for input resistance R4.
Rated voltage at IS pin for input of inductor current signal is -5 V.
Rs
In case of a general boost circuit, a rush current flows for charging the output 7
smoothing capacitance C2 the instant an AC input voltage has been connected. GND
R4 ZD
This current may be considerably greater than at a steady operation. C6 FA5610
As a result, IS pin may receive a voltage that is far higher than usual. Even if 4
such AC voltage is connected, IS pin must not be exposed to a potential higher IS
than -5 V that is an absolute maximum rated voltage.
There may be the case that a voltage higher than the rated is applied to IS pin. Fig.19 IS pin circuit (2)
In such case, it needs to use a preventive circuit for suppression of a rush
current or to add the Zener diode to IS pin as shown in Fig. 19.

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Caution:
Maximum power design
It needs a notice about a setting of the sense resistance to output maximum power at whole input condition because a power limitation
may occur by IC functions.
Fig. 20 shows a block diagram concerning the input current control.
The VDET voltage is relatively high at high RMS input voltage, and the input current is limited by OCP function shown in the path B of Fig.
20 in such case. (Reference figure is shown in Fig. 21.)
The VDET voltage is relatively low at the low RMS input voltage, and the maximum output voltage of multiplier is low too. So, the input
current is limited by the multiplier shown in the path A of Fig. 20 in such case. (Reference figure is shown in Fig. 22.)
This means that the maximum inductor current is limited by an above function unless the reasonable sense resistance is chosen.
Therefore, it needs to choose the sense resistor Rs which satisfies each condition shown in the next page.

M _OUT = K × A × B
CUR. AMP
VDET A M_OUT ICMPcurrent
電流
Multiplier ICMP
ICMP
VCM P B

A
5V PWM COMP
OUT
Gate
28kΩ OSC
IL IL_DET Driver
Detector
12kΩ O.C.P
B

IS Fig.20 Current control area block diagram

Fig.20 Current control area block diagram

OCPに達する前に
Limited by multiplier
inductor current

inductor current

乗算器で制限される。
インダクタ最大電流

before reaching OCP

インダクタ最大電流

OCP OCP
Maximum

Maximum

時間
Time 時間
Time

Fig.21 Maximum inductor current at high input voltage Fig.22Maximum inductor current at low input voltage

Note that the limitation of maximum inductor current is different as shown in Fig. 23 according to whether by OCP or by multiplier.
▪ By OCP: Current peaks including switching ripples are subjected to limitation.
▪ By multiplier: Current excluding switching ripples is subjected to limitation.
インダクタ電流
Inductor current

時間
Time
拡大
Detail

Limitation
OCPによる制限
by OCP
(スイッチングリップル含む)
(cover switching ripples)
inductor current
インダクタ最大電流

乗算器による制限
Limitation by multiplier
(スイッチングリップル
含まない)
(do not cover switching ripples)
Maximum

時間
Time
Fig.23 Maximum current limitation

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 FA5612, FA5613

Design current detecting resistance Rs so as to meet a maximum power in the

input voltage range, and also to clear 2 power limiting conditions below (Fig. 24).

(1) Power limitation by multiplier

0.54V VDET（V)
Design current detecting resistance Rs so that VIS voltage (mean) will be
-0.33 V or greater that is maximum of item “ IS pin voltage (Vis_054) “.
In case of settling as output power Po (W), efficiency η, and minimum input
voltage Vacmin (V), maximum inductor current Iinmax (A) is given by
following equation. Vis_054 VIS(平均値）
VIS (mean)
(-0.33Vmax)
Po
Iinmax  2・ Vocpl VIS(ピーク値）
VIS (peak)
η Vacmin (-0.475Vmax)

VIS voltage (mean) will be -0.33 V or higher when:

①乗算器による制限
(1) By multiplier ②過電流ｽﾚｯｼｭによる制限
(2) By overcurrent threshold
VIS（V)
Rs  Iinmax ＞ - 0.33V
Po
 Rs  2・ ＞  0.33V Fig.24 Maximum power limitation
η Vacmin
Therefore, design current detecting resistance Rs (Ω) so as to meat:
0.33 η Vacmin
Rs ＜ (Ω) ..... (1)
2  Po

(2) Power limitation by OCP

Design current detecting resistance Rs so that VIS voltage (peak) will be -0.475 V or greater that is maximum of IS threshold voltage
(Vocpl).
In case of settling as ripple current Iripple (A), switching frequency fsw, output voltage Vout, boost inductance L, and ON duty D, ON duty
D is given by following equation.

Vout  2 Vac min

D
Vout

VIS voltage (peak) will be -0.475 V or higher when:

Iripple
 Rs  (Iinmax  ) ＞ - 0.475V
2
2  Po 2  Vac min D
 Rs  (  )＞  0.475V
η Vacmin 2  fsw Ｌ
Therefore, design current detecting resistance Rs (Ω) so as to meat:

0.475
Rs＜ (Ω) ..... (2)
2  Po Vac min D

η Vacmin 2  fsw Ｌ

In order to output maximum power at a minimum input voltage, therefore, select Rs determined by expression (1) or (2), whichever

smaller.

Caution:

To define a current limitation by multiplier, select the voltage at VDET pin so as to be 0.54 V or higher even at a minimum input voltage.

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 FA5612, FA5613

(5) Terminal No. 5 (ICMP pin)

Function
(i) Phase compensation for output of incorporated current error amplifier (CUR_AMP)
Application
(i) Phase compensation for output of incorporated CUR_AMP
ICMP
▪ Wiring
Connect R and C between ICMP and GND as shown in Fig. 25. 5
▪ Operation CUR_AMP R8
R and C are connected to ICMP pin to block ripple components of switching frequency that C8
could otherwise appear on IS pin input. PWM_COMP C9
(Reference)
Example of applied circuit: C8 = 100 pF
C9 = 680 pF
Fig.25 ICMP pin circuit
R8 = 47 kΩ
The above is an example. Determine them upon sufficiently verifying your instrument.

(6) Terminal No. 6 (GND pin)

Function
Constitutes the reference of each part of IC.

(7) Terminal No. 7 (OUT pin)

Functions
(i) Drives MOSFET
(ii) Sets oscillation frequency
Fig.26 OUT pin circuit (1)
Applications
(i) Drive of MOSFET
▪ Wiring
Connected via resistance Ro to gate terminal of MOSFET
▪ Operation
Goes high when MOSFET is turned on. Nearly VCC voltage is outputted.
Goes low when MOSFET is turned off. Voltage of nearly 0 V is outputted.
▪ Supplement
Connect a gate resistance for current limitation at OUT pin, prevention of oscillation of gate
terminal voltage, etc.
Rated output currents of IC: Source ... 1.5 A, sink ... 1.5 A.
Connection in Fig. 27 or 28 allows to distinctly set the gate drive currents for turning on and
off MOSFET. Fig.27 OUT pin circuit (2)

(ii) Setting of oscillation frequency

▪ Wiring
(1) Ordinary connection
Connect resistance Rg between MOSFET gate and GND if no buffer is connected on IC
output as shown in Fig. 26, 27 and 28. According to resistance Rg, switching frequency can
be selected out of 3 different modes given in table below.

Resistance Temperature
Accuracy
Rg characteristics
Mode1 Frequency diffusion 4.7kΩ ±5%max 200ppm/°Cmax
12kΩ ±2%max 200ppm/°Cmax
Mode2 65kHz fixed
13kΩ ±5%max 200ppm/°Cmax Fig.28 OUT pin circuit (3)
Mode3 60kHz fixed 27kΩ ±5%max 200ppm/°Cmax
* Ro: 100 Ω max.
Caution:
▪ Resistance Ro between OUT pin and FET gate must be 100 Ω or less
▪ If mode 3 is selected (27 kΩ used), starting up the frequency setting raises the OUT-GND voltage up to 1.4V

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 FA5612, FA5613

(2) If buffer is connected on IC output

If buffer is connected on IC output, select a configuration shown in Fig. 29, and select the
Vcc R11
frequency setting resistance as given in table below.
R12
Resistance Temperature OUT Ro
Accuracy 7
Rg characteristics
R21
Mode1 Jittering 4.7kΩ ±5%max 200ppm/°Cmax Rg

Mode2 65kHz fixed 13kΩ ±5%max 200ppm/°Cmax R22

Mode3 60kHz fixed 30kΩ ±5%max 200ppm/°Cmax
* Ro: 100 Ω max.
If combined resistance connected on buffer output is Rx, set Rx to 3 kΩ or higher taking
合成抵抗Rx
Combined
into account dispersion and temperature characteristics. resistance Rx
Fig.29 Buffer
Example:
Select R11 = 10 Ω, and R12 = 10 kΩ. Suppose their resistance may change by 10% maximum on account of their dispersion and
temperature characteristics. If 3 of them each are connected in parallel,
Rx = 10.01 kΩ × 90% ÷ 3 = 3.003 kΩ
holds, thereby clearing the requisite.

Caution:
▪ Resistance Ro between OUT pin and buffer must be 100 Ω or less
▪ If mode 3 is selected (30 kΩ used), starting up the frequency setting raises the OUT-GND voltage up to 1.2 V
▪ Above conditions presuppose hFE of transistor used in buffer is 50 minimum, and that Vbe is 0.3 V maximum taking the temperature
characteristics into account. Unless characteristics of a particular transistor to use clear the requisites, set the frequency resorting to a
method in “(3) Other circuit configuration.”

(3) Other circuit configuration

Unless the circuit configuration connected to OUT pin clears the specifications in (1) nor (2), determine the frequency based on the current
and voltage defined by specified frequency setting.
( See p. 15 Fig. 5 Frequency setting circuit )
Be sure to take into account the IC characteristics, and dispersion and temperature characteristics of parts connected to OUT pin.

General precaution about frequency setting:

In setting the frequency, make sure, in addition to respecting our recommendations in (1) and (2) above, there is no problem of influences
by dispersion and temperature characteristics of your resistors, wiring, noise (influence of auxiliary power supply that operates before PFC
starts, in particular) and other matters than resistance itself based on the current and voltage regarding the specified frequency setting.
In setting of the frequency, please confirm whether there is no bad influence of following items including our setting recommendation and
our setting specification.
- Dispersion of or the temperature characteristic of resistance used, a design of wiring, noise (especially from sub power supply before the
PFC start operation), etc.

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 FA5612, FA5613

(8) Terminal No. 8 (VCC pin)

Function
(i) Supplies IC with power
Application
(i) Supplies IC with power
▪ Wiring
Connect a startup resistance between rectified voltage line and VCC pin.
Generally, connect a rectified and smoothed voltage from auxiliary winding provided
on transformer.
Or connect an external DC source.
▪ Operation
At the time of startup in case VCC voltage is obtained from auxiliary winding, the 8
current via the startup resistance charges the smoothing capacitance and, when the
VCC
level rises up to UVLO ON threshold voltage, IC starts up. Immediately before startup,
a current of at least 110 uA (max.) that is a startup current for IC must be fed. During a
Fig.30 VCC pin circuit (1)
steady operation, VCC is supplied from inductor's auxiliary winding (Fig. 30).

As the source voltage rises from zero, the operation starts at 9.6 V (typ.) for FA5612,
or at 13 V (typ.) for FA5613.
Any of started-up ICs stops operating when the source voltage drops down to 9 V
(typ.)
While IC stops operation by under voltage lockout circuit, OUT pin keeps low level and
外部DC電源
External DC source
shuts the output of power supply off. 8
Supplement: VCC
Under voltage lockout function avoids an erratic operation of circuit when source
voltage has dropped.
Noise applied to VCC pin will cause an erratic operation. To avoid the noise, connect a
capacitance near VCC pin whether IC is operated by another source or not. Fig.31 VCC pin circuit (2)
Determine the capacitance so that the noise generated on VCC pin will be within ±0.6
V, and make doubly sure no erratic operation occurs by noise (Fig. 31).

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 FA5612, FA5613

12. Advice for design

(1) Advice in pattern designing
Main circuit MOSFET, inductor, diodes, etc. perform switching under high
voltage and large current. If wiring of IC or signals inputted to IC gets too near
such main circuit parts, they may operate erratically upon being affected by
noise generated there.

Attention must be paid particularly in following cases (examples of faulty cases).

▪ IC is arranged under inductor or other main circuit parts, or immediately behind
main circuit parts on double sided circuit board (Fig. 32)
▪ IC is arranged close to inductor, MOSFET or diode (Fig. 33)
▪ Signal wiring is placed under inductor or near MOSFET or diode (Fig. 34) インダクタの下(基板の裏面の場合
IC is arranged under inductor
も含む）にICが配置されている。
(or on immediately opposite side on circuit board)

Fig.32 Example of inadvisable arrangement (1)

インダクタやMOSFETのすぐ近くに
IC is arranged close to inductor or MOSFET インダクタの下やMOSFETのすぐ近く
Signal wiring passes under inductor
ICが配置されている。 を信号の配線が通過している。
or close to MOSFET

Fig.33 Example of inadvisable arrangement (2)

Fig.34 Example of inadvisable pattern

(2) Typical GND wiring in IC area

To minimize influences on IC of noises from main circuit, separate GND of IC and signal lines for parts of IC area, and GND of PFC main circuit
away from each other, and connect them via one point near current detecting resistance Rs and output capacitance.
IS signal whose voltage level is low is liable to noise. Minimize lengths of IS pin-Rs and Rs-GND wiring.
Arrange VCC-GND capacitance close to IC. Otherwise, the effect will be poor.
Arrange the capacitance between IC area input terminal and GND close to IC. It also has a function of noise elimination and, if away from IC, it
will be affected by noise.

Caution:
Wiring is exemplified for you to understand how to connect the GND line.
Noise and incidental erratic operations differ from one instrument to another. Adopting any wiring exemplified in Fig. 35 will not necessarily
guarantee normal operations of your instruments.

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 FA5612, FA5613

Rs

IS VDET VCMP FB

FA5612
/FA5613
ICMP GND OUT VCC

Fig.36 Example of inadvisable GND wiring

(GND is common to signal line parts and main circuit)

Fig.35 Example of advisable GND wiring

Rs

Drive current ターンオン時

Drive current
when turning on 駆動電流
when turning on
IS VDET VCMP FB

FA5612
/FA5613
ICMP GND OUT VCC

Fig.37 Example of inadvisable GND wiring Fig.38 Example of GND wiring

(Liable to noise when turning on if GND is (GND of VCC capacitance is

common to VCC capacitance and signal line) distinct from signal line GND)

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 FA5612, FA5613

(3) Precautions in use regarding terminal noise

If noise is applied to any IC pin, an erratic operation may be caused. Proceed to design upon respecting the precautions below.
Condition Pin Malfunction in fear Input regulations Cautions in design

switching may stop when noise is over over voltage protection level input signal is only for connect condenser near

FB IC may become stanbay mode when noise is under short detection level feedback voltage of terminal pin

offset occurs in output voltage and output voltage rises or falls output voltage

output of multiplier output becomes unstable, and input current waveform may cancel noise confirm sufficiently phase

disturbed compensation constant

VCMP
switching may become when noise is over threshold voltage

switching may stop when noise is under threshold voltage

output of multiplier output becomes unstable, and input current waveform may be cancel noise connect condensor near pin
VDET
Input noise disturbed

(within absolute current may be detected incorrectly cancel noise connect condensor near pin
IS
maximum ratings) It may turn off when noise is over overcurrent protection level

because a duty changes, input current waveform may be disturbed cancel noise confirm sufficiently phase
ICMP
compensation constant

reference voltage changes, IC may not behave normally cancel noise ground wiring should be a
GND
wide wiring

the output may fall not to be able to drive Mos normally when signals more than the cancel noise
OUT -
ability of the driver are input

IC may stop when noise under UVLO is input don't input noise under connect condensor near pin
VCC
UVLO when moving

FB a parasitism element works, and the malfunction such as IC stop may occur don't input minus voltage

VCMP less than maximum

VDET absolute voltage

Input minus voltage
ICMP
(less than absolute -
VCC
maximum voltage)
IS IC may be destroyed

OUT IC may be destroyed

VCC a parasitism element works, and the malfunction such as IC stop may occur

FB IC may be destroyed don't input minus voltage

VCMP more than maximum

Input plus voltage VDET absolute voltage

(more than absolute ICMP -

maximum voltage) IS gnd level may be changed

OUT IC may be destroyed

VCC

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 FA5612, FA5613

13. Example of application circuit ( 390V / 1.5A output )

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