This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics.

This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3342123

A Voltage-Boosting Seven-Level Switched

Capacitor Multilevel Inverter with Reduced
Device Count
V S Prasadarao K, Senior Member, IEEE, Sankar Peddapati, Senior Member, IEEE, Balram Kumar,
Member, IEEE

U-cell (PUC) with reduced switches and DC sources has been

Abstract—This article introduces a novel Switched-Capacitor proposed [5-6] for generating higher voltage levels. However,
Multilevel Inverter (SCMLI) that offers a minimum number of the voltage gain of this topology is limited to one. To address
components. The inverter generates a seven-level output these issues, modified configuration of the PUC topology [7]
waveform across the load by utilizing a single DC source, two and several switched capacitor MLI (SCMLI) topologies with
capacitors with a rating of half the input voltage, and nine boosting ability are introduced in the literature. The boosting
semiconductor switches. The key features of this proposed SCMLI
include voltage boosting ability (up to 1.5 times the input voltage),
ability in SCMLIs can be achieved in two ways: 1) Two-stage
reduced device count, absence of bidirectional switches, self- conversion using a front-end dc-dc boost converter and an
balancing of capacitors, and lower Total Standing Voltage (TSV). inverter [8-9]. 2) Single-stage conversion without using an
The paper presents a detailed analysis covering the operating intermediate converter. The SCMLIs employ two-stage
principles, capacitor voltage balancing, and control strategy. conversion systems are inefficient. The single-stage
Comprehensive evaluations such as power loss, efficiency analysis, conversion-based SCMLIs are compact, lightweight, and have
cost function per level (CF/Nl), and switching device power (SDP) higher power density. The various SCMLI topologies and their
ratings are also provided. The steady-state and dynamic operating principle are well elaborated in [10]. Among the
performance of the proposed topology are verified through different types of SCMLIs, single DC source topologies have
simulation studies using MATLAB/SIMULINK software, and
experimental studies validate the results. Furthermore, the article
gained much importance in various applications like gradient
includes a comparative study between the proposed SCMLI and driver circuit for MRI applications [11], EV chargers, and
other recently introduced multilevel inverters. Finally, the uninterruptible power supplies (UPS) [12].
performance of the proposed topology for single-stage grid The SCMLIs proposed in [13] and [14] using a single dc
connected photovoltaic (PV) system has been verified and source achieves the voltage boosting ability. Nevertheless,
corresponding results are presented. these topologies incorporate the H-bridge unit for polarity
generation, resulting in a high total standing voltage (TSV). The
Index Terms— Boosting ability, multilevel inverter, switched above disadvantage is eliminated in the topologies developed in
capacitor, self-balancing and total standing voltage. [15] and [16], but these topologies require a higher number of
switching devices. A new hybrid SCMLI topology with the
I. INTRODUCTION possibility of the symmetric and asymmetric mode of operation
Multilevel inverters (MLIs) are showing better performance is presented in [17]. Although it uses a lower number of
in DC to AC conversion over the conventional two-level switches, the topology needs one extra capacitor and
inverters in terms of switching stress, harmonic profile, bidirectional switch to generate the seven-level output with a
switching frequency, efficiency, and electromagnetic voltage gain of 1.5. A novel seven-level MLI with low voltage
interference (EMI). These features make MLIs popular in stress across the switches is proposed in [18]. This inverter
various medium and high-power applications like motor drives, requires 11 number of switching devices, resulting in an
power quality improvement devices, microgrids, and aircraft increased overall cost. To reduce the device count in the above
[1]. Recently, MLIs are also popularly used in single-phase AC topology, a new switched capacitor-based ANPC inverter was
systems [2-3]. However, the classical topologies, such as developed in [19]. A dual T-type seven-level ANPC inverter
neutral point clamped (NPC), flying capacitor (FC), and [20] has the demerits of higher TSV, and demands greater
cascaded H-bridge (CHB) MLIs, require a more significant number of capacitors, making the entire system bulky and
number of components for higher voltage levels. In addition, costly. A novel high-gain ANPC for grid-connected
the NPC and FC MLIs are suffering from the drawback of the applications has been proposed in [21] to address the above
capacitor voltage balancing problem. Several MLI topologies issues, but the topology requires one additional floating
with fewer component count have been introduced to address capacitor. In [22], a new eight switch, seven-level boost ANPC
the above issues [4]. One such topology known as the packed (8S-7L-BANPC) topology is presented. Although it employs

V S Prasadarao K1, Sankar Peddapati2 and Balram Kumar3 are with the National
Institute of Technology Andhra Pradesh, Tadepalligudem, 534101, India.(e-
mail:[email protected],[email protected],balramkrishnamada
[email protected])

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
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fewer switches, the inability of the bidirectional power flow in II. PROPOSED SCMLI TOPOLOGY
supporting inductive loads is the major setback of this topology.
A. Topology Description and operating principle
An improved seven-level inverter with the natural balancing of
the capacitors is presented in [23], the converter is shown less The structure of the proposed SCMLI is given in Fig. 1; the
efficient due to presence of higher number of diodes and topology produces the seven-level output voltage using two
switches. Another SCMLI with reduced device count for seven- capacitors and nine power switches. With the help of two self-
level output generation is introduced in [24], but the converter balanced capacitors, C1 and C2, rated at half of the input voltage,
requires additional floating capacitor. Further, this inverter the proposed MLI boosts the input voltage by 1.5 times. The
utilizes the bidirectional switch to avoid the short circuit of the switch S9 is turned ON only during the charging of the
input dc-link capacitor, thereby increasing the conduction capacitors. The switching states, along with the charging and
losses in the inverter. The requirement of the floating capacitor discharging status of the capacitors at each voltage level in the
in the topologies [18-24] has been eliminated in the T-type proposed SCMLI, are given in Table I. From the table, it can be
SCMLI [25]; higher TSV will limit the application of this observed that the converter has more switching states to charge
topology in high voltage systems. A newly proposed seven- the capacitors and therefore, resulting in reduced voltage
level ANPC topology [26] achieves the voltage gain of 1.5 with ripples. It is worth mentioning that the switches S 3 and S6 are
lower TSV. But it employs two switched capacitors and two dc operated at fundamental frequency of the output voltage.
link capacitors to get the voltage boosting capability. An The generation of each voltage and corresponding current
improved version of PUC topology using a single capacitor [27] paths for the proposed topology is shown in Fig. 2. The
has been introduced for generating the seven-level output with charging path indicated in blue color shows that the capacitors
a voltage gain of 1.5. However, the above PUC topologies C1 and C2 are charged to the half of the input voltage during the
utilizes the voltage sensor to balance the capacitor voltage at voltage levels zero and ±Vdc. The capacitor C1 is discharging
half of the input DC source. In recent times, the hybrid SCMLI during the voltage levels +0.5Vdc and +1.5Vdc. Likewise, C2 is
topologies integrating the FC structure [28-31] are gaining discharging during the -0.5Vdc and -1.5Vdc voltage levels. It can
popularity. The FC clamped five-level inverter topology [28] be seen that the operation of the both capacitors is symmetric in
achieves the quadruple voltage gain with twelve switches and positive and negative half cycles of the output voltage and
four capacitors. The FC based hybrid topology [29] produces therefore the capacitor voltage balance can be easily achieved.
the nine-level output voltage with a voltage gain of 1.33. The S4 S5 S6
main drawback of this topology is the utilization of H-bridge
C1
unit for polarity generation, which increases the TSV of the
entire topology. The topologies [30-31] with fewer switches

+
Vdc S7 S9
employs the FC unit to utilize the full dc-link voltage. however, S8
the gain of these topologies is limited to unity.
A recently developed switched-capacitor-based modular T- C2
type inverter [32] address current spikes during capacitor S1 S2 S3
switching but at the cost of a higher device count. A newly VL + iL
developed SC inverter [33] generates the seven-level output Load
with a lower number of switches and low voltage stress across Fig.1. The structure of the proposed seven-level SCMLI
the switches. However, it requires an extra capacitor to achieve
TABLE I
1.5 voltage gain. A novel seven-level boost ANPC inverter [34] SWITCHING STATES AND STATUS OF THE CAPACITORS FOR
has been implemented to mitigate the harmonics and reactive THE PROPOSED SCMLI
power compensation. Though this topology incorporates a Voltage
S1 S2 S3 S4 S5 S6 S7 S8 S9 C1 C2
minimum number of switches, it requires more diodes to level
achieve the boosting ability. A modified MLI [35] based on the 0 0 1 0 1 1 1 0 0 1 C C
+1.5Vdc 1 0 0 0 0 1 1 0 0 D -
back-to-back T-type configuration generates different output 1
voltage levels according to the boosting factor. The utilization +Vdc 1 1 0 0 1 0 0 1 C C
of a higher number of switches and capacitors makes the +0.5Vdc 0 0 0 1 0 1 1 0 0 D -
topology costly and heavy. 0 1 1 1 0 1 0 0 0 1 C C
This article proposes a novel seven-level SCMLI with the -0.5Vdc 1 0 1 0 0 0 0 1 0 - D
-Vdc 0 1 1 1 1 0 0 0 1 C C
following features to resolve the above issues. -1.5Vdc 0 0 1 1 0 0 0 1 0 - D
• Reduced number of components 1 = ON, 0 = OFF, C = charging, D = discharging, *-* = no effect
• Absence of bidirectional switches
• Boosting ability (Vo= 1.5*Vin) B. Control Strategy
• Self-balancing of capacitors The conventional level-shifted carrier pulse width
• Bidirectional power flow capability modulation (LSCPWM) technique is used in this work to
• Lower TSV generate the switching pulses for the proposed topology. In this
• Lower SDP rating technique, the reference signal of the fundamental frequency is
• Low cost compared with the six carrier signals of high frequency, as
shown in Fig. 3. The resultant signals obtained from the
comparisons are used to generate the gate signals for the
switches according to the switching logic given in Fig. 4. From

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3342123

the figure, it can be noted that the switches S 3 and S6 are Charging path
S4 S5
Load current path
S6 S4 S5
complementary and also operated at a fundamental frequency. S6
C1 C1
Further, the magnitude of the load voltage can be controlled by

+
varying the amplitude of the reference wave (Aref). Vdc S7 S9
S8
Vdc S7 S9
S8

C. Capacitor voltage balancing C2 C2

The self-voltage balancing feature of the capacitors in S1 S2

VL + iL
S3 S1 S2
VL + iL
S3

SCMLIs eliminates the requirement voltage balancing circuitry Load Load

VL = 0V VL = 0V
and complex control algorithms. The balanced voltage across S4 S5 S6 S4 S5 S6
the capacitors can be achieved by connecting them in parallel C1 C1
with the DC source during the charging and series with the DC

+
Vdc S7 S9 Vdc S7 S9
source during the discharging. The same principle is adapted S8 S8
for the proposed topology using LSCPWM technique to make C2 C2
the capacitors self-balanced. Here, both capacitors are charged
S1 S2 S3 S1 S2 S3
to half of the input voltage during the voltage levels of zero and VL + iL VL + iL
Load Load
±Vdc. The capacitor C1 is discharged during the positive half VL = +0.5Vdc VL = -0.5Vdc
S5
cycle of the voltage levels 0.5Vdc, and 1.5Vdc and the capacitor S4 S6

C2 is discharged during the negative half cycle of the voltage C1 C1

levels 0.5Vdc, and 1.5Vdc. Further, the LSCPWM is ensured to

+
Vdc S7 S9 Vdc S7 S9
S8
achieve ampere-second balance through both the capacitors, S8

indicating that the proposed MLI capacitors are self-balanced. C2 C2

S1 S2 S3 S1 S2 S3
D. Sizing of the capacitors VL + iL VL + iL
Load Load
The parameters that decide the size of the capacitor in VL = +Vdc VL = -Vdc
S5 S4 S5 S6
inverters are the longest discharging period, voltage ripple, S4 S6

output frequency, and load. In the proposed topology, the C1 C1

capacitors C1 and C2 have the equal longest discharging period

+
Vdc S7 S9 Vdc S7 S9
S8 S8
during +1.5Vdc and -1.5Vdc voltage levels, respectively. From
Fig. 3, it can be observed that the longest discharging time C2 C2

interval for C1 is t3-t2 and for C2 is t8-t7. The amount of the S1

S2 S3
S1
S2 S3
VL + iL VL + iL
charge discharged by the capacitors during the above time Load Load
VL = +1.5Vdc VL = -1.5Vdc
intervals is calculated as follows:
t3 t8
Fig. 2. Current paths of the proposed SCMLI topology during each
voltage level
Qc1 =  I L sin(2 f o t )dt =Qc2 =  I L sin(2 f o t )dt (1)
t2 t7 3Ac
Aref
By considering the maximum allowable ripple voltage 2Ac
Ac
factor k, the capacitances for the proposed topology are
0 t
obtained as, -Ac
Qc2 -2Ac
C1 = C2  (2) -3Ac
kVc2
1.5Vdc
Where, Vc2 is the rated voltage across the capacitor C2. Vdc
0.5Vdc
0 t
E. Startup inrush current limitation process -0.5Vdc
-Vdc
During the starting instant of the inverter operation, the -1.5Vdc

large voltage difference between the input dc source and t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

capacitor causes a huge instantaneous inrush current in the Fig. 3. Implementation of level shifted carrier pulse width moduation
charging loop. A startup process shown in Fig. 5 is employed (LSCPWM) technique
to suppress this large inrush current. This can be achieved by
pre-charging all the capacitors using a pre-charge circuit III. COMPREHENSIVE EVALUATION OF THE
consisting of a limiting resistor Rch and normally closed relay PROPOSED SCMLI TOPOLOGY
[32]. When all the capacitors are fully charged, the Rch is
bypassed by opening the relay to allow the normal operation of A. Power loss and Efficiency Analysis
the inverter. Fig. 6 shows the simulated capacitor currents for The different types of losses occurring in the SCMLIs are
the proposed topology with and without a pre-charge circuit. It voltage ripple loss of the capacitor and conduction and switching
can be seen that a huge inrush current is flowing at the losses of the power devices. These losses are evaluated for the
beginning without the pre-charge circuit. In contrast, with the proposed topology in this section.
pre-charge circuit consisting of a relay and resistor, the inrush i) Voltage ripple loss of the capacitor
current of the capacitors is reduced drastically and thereby the The voltage fluctuations of the capacitor during its charging
lifetime of the capacitor and switch can be enhanced. period will result in voltage ripple loss (Pr).

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
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Aref
From eq (2), the voltage ripple for both the capacitors is t
D
E S1
given as, B

Qc1 Qc2
C
3Ac
Vc1 = = Vc2 = (3) 2Ac t > A
D

C1 C2 E
S2
2Ac F
S5
Finally, the voltage ripple loss for the capacitors over one Ac t > B B
S9
fundamental cycle period can be obtained as, A
D S3
f o C1VC21 f o C2 VC22 Ac
t
C S6
Pr1 = = Pr 2 = (4) 0 > C
D

2 2 C
S4
The ripple loss is identical for both capacitors since their 0
t >
D
B
E
behavior is symmetric in both positive and negative half cycles. -Ac
C

ii) Conduction losses of the power devices and capacitors -Ac

t
>
B
A
S7
E
The conduction losses occurring during the ON state of the -2Ac D

devices are mainly due to the internal resistance and forward t

E
F
S8
-2Ac >
voltage drop across the devices. The conduction losses for the -3Ac
F

power switch and diode are obtained from the following

Fig. 4. Control logic for the proposed SCMLI
expressions.
Pc , s = VSF * I s , avg + Rs ,ON * I s2, rms  S4 S5 S6
 (5)
Pc , d = VDF * I d , avg + Rd ,ON * I d2, rms  S7 C1

Where VSF and VDF are the forward voltage drop across the

+
Vdc Rch
switch and diode, Rs,ON and Rd,ON are the internal resistances of Relay
S9
S8
the switch and diode, Is,avg and Id,avg are the average current flows
through the switch and diode, Is,rms and Id,rms are the rms value of C2
the current flow through the switch and diode respectively. S1 S3
S2
The conduction loss of the capacitor, which is due to the
VL + iL
equivalent series resistance (ESR), can be given as, Load
PC ,cl = I C2 * rESR (6) Fig. 5. Inrush current limiting method for the proposed SCMLI

Where IC is the rms value of the current flowing through the

capacitor and rESR is the ESR of the capacitor.
Therefore, the total conduction losses (PT,cl) in the proposed
topology are given as,
9 9 2
PT ,cl =  ( Pc , s ) k +  ( Pc , d ) k +  ( I C2 ) k * rESR (7)
k =1 k =1 k =1
(a) (b)
iii) Switching losses of the power devices
Fig. 6. Simulated capacitor currents for the proposed SCMLI (a) without pre-
The switching losses in the semiconductor devices will occur charge circuit (b) with pre-charge circuit
during the transition from the ON state to the OFF state and vice
versa. These are mainly due to the intrinsic time delays of the TABLE II
power semiconductor devices. The power loss during both COMPONENTS AND PARAMETER LIST FOR PLECS SIMULATION
transitions can be obtained as [18], Device/Parameter Model Name/Value
 Switching device (IGBT) IKW30N60H3
Psw,ON = Vsw,ON * I sw,ON * TON  * f sw
1
6  IGBT thermal resistance junction-case 0.8 K/W
 (8)

Psw,OFF = Vsw,OFF * I sw,OFF * TOFF  * f sw 
1 Diode thermal resistance junction-case 1.9 K/W
25o C
6  Ambient Temperature
Capacitors C1, C2 2200uF
The total switching losses for the proposed SCMLI are given as Input DC Source (Vdc) 100V
follows, Output frequency fo = 50Hz
9
PT , sw =  Psw,ON , k + Psw,OFF , k  (9) Switching frequency fsw = 5kHz
k =1

Finally, the efficiency of the proposed topology for a given The power loss and efficiency analysis for the proposed
output power (Po) can be obtained as: SCMLI is evaluated using PLECS simulation software with the
Po parameters given in Table II.
% = *100 . (10) The analysis of each semiconductor device’s conduction and
Po + Pr1 + Pr 2 + PT ,cl + PT , sw switching losses, capacitor losses, and efficiency is carried out
for the different output power, as shown in Fig. 7. From the
figure, it can be noted that the conduction losses in both
capacitors and switches are dominating. Further, the proposed
topology attains the maximum efficiency of 97.18% at the

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
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output power of 1000W. After that, the efficiency slightly S1 S2 S3 S4 S5 S6 S7 S8 S9

decreases as the power losses increase for the proposed inverter.

Power loss(Watts)
B. Total Standing Voltage (TSV) 5
4
The TSV of the converter is the summation of peak inverse 3
2
1
voltage (PIV) across all the switches and is generally 0

Pc

Pc

Pc

Pc

Pc

Pc
Psw

Psw

Psw

Psw

Psw

Psw
represented in terms of per unit. The per unit value of the TSV
for the inverter having ‘n’ number of switches is given as, 200W 600W 1000W 1400W 1800W 2000W
n

V PIV , k
Output Power
TSV pu = k =1
(11) (a)
VL ,max C1 C2

Power Loss
3

(Watts)
The voltage stress across each switch at different voltage 2
1
levels and their peak inverse voltage for the proposed topology 0
Pc Pr Pc Pr Pc Pr Pc Pr Pc Pr Pc Pr
are given in Fig. 8. From the figure, the switches S 3 and S6
experience highest voltage stress. After knowing the PIV of 200W 600W 1000W 1400W 1800W 2000W
switching devices, the TSV is computed for proposed SCMLI Output Power
using above equation and is equal to 7.5Vdc, and the per unit (b)
value is equal to 5. 98
97.18 97.07
97 96.6 96.51 96.26

%Efficiency
C. Cost function per level (CF/Nl) 96
The estimation of the total cost for the proposed topology by 95
94 94.83
considering the different parameters is presented in this section.
200W 600W 1000W 1400W 1800W 2000W
Here, the cost function per level (CF/Nl) is obtained by taking Output Power
the total number of components required, such as switches (c)
(Nsw), drives (Ndriver), diodes (Nd), and capacitors (Ncap), DC
Fig. 7. (a) Conduction (Pc) and swicthing losses (Psw) of the swicthes (b)
sources (Ndc) and TSV of the inverter into account. The CF/Nl Conduction (Pc) and voltage ripple losses(Pr) for C1 and C2 (C) Efficiency of
for the given inverter [36] can be obtained as, the proposed SCMLI at diferent power ratings
 N sw + N driver + N d + N cap + ( * TSVpu )  * N DC
CF / Nl = 
Voltage stress(*Vdc)

(12)
Nl
where,  = weightage of the TSV. 1.5
1.2
The α value lies in the range of 0    1 , if switch count 0.9 PIV
-1.5VDC
-VDC
0.6 -0.5VDC
is given more priority, otherwise α value is chosen >1 if TSV is 0.3
0
1.5VDC
VDC
0 0.5VDC
of more important. For different values of α, the CF/Nl is
S1 S2 S3 S4 S5 S6 S7 S8 S9
obtained for the proposed topology using the equation (12) and 0.5VDC VDC 1.5VDC 0
is shown in Fig. 9. From the figure, it can be noticed that the -0.5VDC -VDC -1.5VDC PIV
CF/Nl for the proposed topology slightly increases when the
value of α increases. Fig.8. Voltage stress across the switches during each voltage level of the
proposed inverter
D. Switching device power (SDP) rating
The voltage and current ratings are required to select any
power semiconductor device in the converter. These ratings, in
turn, decide the cost of the inverter. The parameter which
quantifies the voltage and current ratings is the switching device
power (SDP) rating and is defined as the product of the
maximum voltage (Vm) and maximum current (Im) of the
switching device [37] as shown in equation (13). The SDP Fig. 9. CF/Nl for the proposed topology at different values of α
rating for the entire inverter is obtained from the summation of
the SDP ratings of all the switching devices. TABLE III
SDP RATING OF THE PROPOSED INVERTER
SDPdevice = Vm * Im (13) Switch Vm Im SDP (VA) =Vm*Im
S1 100 3 300
The SDP rating for the proposed SCMLI is obtained by S2 50 2 100
S3 150 3 450
considering the parameters given in Table II. Further, Table III S4 100 3 300
outlines each switch's SDP rating, and it is found that the total S5 50 2 100
SDP rating for the proposed SCMLI is 2150 VA, which is less S6 150 3 450
compared to most of the recently developed topologies; lower S7 50 3 150
SDP rating of the converter indicates reduced system cost. S8 50 3 150
S9 50 3 150
Total SDP rating = 2150 VA

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3342123

IV. RESULTS AND DISCUSSIONS TABLE IV

SIMULATION AND EXPERIMENTAL PARAMETERS
The working of the proposed SCMLI is verified with the help Parameter/component Value/rating
of MATLAB/SIMULINK software and validated through IGBT Switch: FGA15N120ANTD 1200V, 15A
experimental studies. The various components and parameters Capacitors: PG-6TUPS 2200µF
used in both simulation and experimental study are given in Controller SPARTAN6 FPGA
Gate driver TLP250
Table IV. The experimental prototype of the proposed inverter Input DC Sources Vdc = 100V
is depicted in Fig. 10. The proposed inverter prototype shown in Output frequency fo = 50Hz
Fig. 10 is implemented using the FGA15N120ANTD switches, Switching frequency fs = 5kHz
and TLP250 optocouplers are used to drive them. The Load resistance R = 50Ω
LSCPWM technique is implemented using the SPARTAN6 Load inductance L = 50mH
FPGA controller to generate the gate pulses. The simulation and
experimental waveforms of the proposed inverter for an input DC Source Capacitors
DSO
voltage of 100V with RL load are shown in Fig. 11. From the R
figure, the output voltage has seven levels and achieved a
voltage gain of 1.5. Further, the nonappearance of spikes during
Proposed 7-level SCMLI
transition between positive and negative in output voltage
indicates the proposed inverter's bidirectional power flow
capability. Furthermore, from Fig. 11, the capacitor currents and
capacitor voltages show the voltage balancing ability of
LSCPWM technique and the same is reflected in FFT spectrum Spartan6 FPGA
of the load voltage depicted in Fig. 12. From the figure, the Controller Current probe L
voltage THD is 22.45%, whereas, the THD of the current
waveform is 0.63%. Further, the spectrum indicates that both Fig.10. Experiemental setup of the proposed SCMLI
voltage and current harmonics reside around the switching
frequency (i.e., 5kHz), and hence small filter is enough to bring
even the voltage THD within the limits of IEEE-519 standards.
The performance of the proposed inverter is tested for the
dynamic change in the loading conditions. Fig. 13 shows the
waveforms of the capacitor voltages, output voltage, and current
for the change in the load from Z=50Ω to Z=(50+j0.05ω) Ω. It
can be seen that the output voltage remains unaffected, and the (a)
current is changed to nearly sinusoidal for the step change in VL(100V/div) IL(10A/div) IDC(10A/div)

load. Meanwhile, the capacitor voltages remain balanced at 50V, IC1(10A/div)

which shows the good transient performance of the proposed
SCMLI. IC2(10A/div)

Further, to show the effectiveness of the topology, a step VC1(20V/div) VC2(20V/div)

change in modulation index is considered, and the

corresponding results are depicted in Fig. 14. The modulation (b)
index (ma) is changed from 0.5 to 0.9 at t=0.46s in the simulation Fig.11. (a) Simulation (b) Experiemental results for R=50 Ω and L=50mH
study, and the corresponding output voltage levels are increased
from five to seven, and the output current also increases nearly
by two times. During this transient operation, the capacitor
voltages remain balanced at 50V. The experimental results also
confirm the ability of the proposed SCMLI for dynamic change
in the modulation index.
To verify the operational capability of the proposed inverter
under dynamic changing in the frequency, a step change in the (a) (b)
frequency from 50Hz to 400Hz is considered in both simulation Fig.12. FFT of the (a) load voltage (b) load current
and experimental studies. As the voltage ripple in the capacitor
VL(100V/div) IL(10A/div)
is inversely proportional to the frequency, both capacitors in the
proposed inverter have less voltage ripple for 400Hz operation
than that for 50Hz operation. The simulation and experimental
results shown in Fig. 15 confirm the same. In addition, the
capacitor voltages are balanced at half of the input voltage VC1(20V/div) VC2(20V/div)

during the entire frequency operation range. R= 50ohm R=50ohm, L= 50mH

(a) (b)
Fig.13. (a) Simulation (b) Experiemental results for dynamic load change

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
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x
It is worth mentioning that both simulation and experimental VL(100V/div)
IL(10A/div)

results exhibit the capability of the proposed inverter to operate

at higher frequencies which is an essential requirement for the
HFAC power distribution systems [38].
Further, to test the dynamic performance of the proposed
inverter, a step change in the input voltage from 50V to 100V VC1(20V/div) VC2(20V/div)

has been considered in this paper. The corresponding

(a) (b) Ma= 0.5 Ma= 0.9
simulation and experimental results under this dynamic
(a) (b)
condition are depicted in Fig. 16. It can be noticed that the
Fig.14. (a) Simulation (b) Experimental results for dynamic change in the
inverter output voltage and currents quickly attain a new steady modulation index
state value. In addition, the capacitors are also reaching the new VL(100V/div)

steady state value quickly with balanced voltages across them.

Finally, the performance of the proposed topology has been
assessed under harmonic load conditions. In this study, the IL(10A/div)
chosen harmonic load comprises a diode bridge rectifier with a
load resistance of 335Ω and capacitance of 1.2mF. The VC1(20V/div) V (20V/div)
C2

simulation results shown in Fig. 17 demonstrate the good

performance of the proposed topology for nonlinear load fo= 50 Hz fo= 400 Hz

conditions. (a) (b)

From the simulation and experimental results, the proposed Fig.15. (a) Simulation (b) Experiemental results for dynamic change in the
SCMLI shows good performance under steady state and output frequency
transient conditions. VL(100V/div) IL(10A/div)

V. GRID CONNECTED PV SYSTEM USING PROPOSED

SCMLI TOPOLOGY
One of the significant applications of the proposed topology is VC2(20V/div)
the single-stage grid interconnection of the PV system, shown VC1(20V/div)

Vdc=50V Vdc=100V
in Fig. 18. It consists of a PV array, DC link capacitor, proposed
(a) (b)
inverter, and filter circuit. In grid connected PV system, the
Fig.16. (a) Simulation (b) Experiemental results for dynamic change in the
MPPT is employed to get the maximum available power from input voltage
the PV system and the inverter is controlled to inject the active
power into the grid with reduced current THD. In the proposed
work, a closed loop control system shown in Fig. 18 consisting
outer voltage control loop and inner current control loop is used.
Here, a simple perturbation and observation (P & O) method is
employed to generate the reference voltage for tracking
maximum power from the PV array. Later, the reference current
(iref) is generated such that the actual PV voltage follows
reference voltage and simultaneously the corresponding phase
of the reference current is obtained through the phase locked
loop (PLL). Then the proportional resonant (PR) current
controller [39] regulates the error between the actual and
reference grid current and generates the modulating signal
required for the implementation of the LSCPWM control
Fig. 17. Simulation results of the proposed SCMLI topology under a diode
technique and thereby the gating signals of all switches are bridge rectifier load
generated as shown in Fig. 4.
TABLE V
The performance of the grid connected PV system using the PARAMETRS FOR THE GRID CONNECTED PV SYSTEM
Parameter Specifications
proposed SCMLI topology is verified with the help of
PV Array Zytech Engineering Technology ZT190S
MATLAB/SIMULINK software by considering the parameters Peak power (PMP) 1.3 KW at G = 1000W/m2; 0.65KW at G = 500W/m2
given in Table V. Fig. 19 shows the simulation results of the
Grid voltage 230V rms
proposed grid connected PV system for the change in irradiance
(G) from 1000 to 500 W/m2. It can be seen that the proposed Capacitors C1, C2 2200uF
inverter with P&O MPPT algorithm effectively tracks the Li 4.06mH
maximum power from the PV. From Fig. 19, the grid current is Ci 6.01uF
near sinusoidal and is in phase with the grid voltage which Lg 4.35mH
indicates the active power transfer capability of the proposed 7- Grid frequency fo = 50Hz
level inverter to the grid.
Switching frequency fsw = 10kHz

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3342123

In transformerless grid integrated PV system, the leakage Filter Circuit

0.5Li 0.5Lg
currents due to parasitic capacitance of the PV array is
S6 S3
inevitable. In order to limit the leakage current magnitude as per C1 S9 C2 Ci

the VDE 126-1-1 grid standards for the proposed inverter, a Vinverter
common mode (CM) filter is employed across the output S5 S7 S8 S2
+
Vg
terminals of the inverter as shown in Fig. 18 [40]. The midpoint IPV
Rd
P N
of the split capacitor is connected to the negative terminal of the + ig
Vpv
PV source to the provide a path to the common mode current. S4 S1 Ci
Cpv/2 Cpv/2
The simulated leakage current of the proposed inverter with a 0.5Li 0.5Lg

CM filter for the grounding resistance (Rg) value of 50Ω and ileakage Rg
PV parasitic capacitance (Cpv) value of 50nF is shown in Fig. iactual
iref = igm Sin
S1 PR + Sin Vg g
19(d). From the figure it can be observed that the leakage S9
LSCPWM
Controller
PLL
igm
currents are well under the limits of VDE 126-1-1 grid Vpv PI
standards for the proposed inverter using a CM filter.
+ +
MPPT +
IPV Controller
Finally, it can be concluded that the proposed inverter with Ppv
2 * PPV
CM filter and associated closed loop control strategy is well Vg
Vg
Closed loop control system
suited for grid integrated PV system due to its ability in tracking
Fig. 18. Single stage grid connected PV system using the proposed topology
MPPT with low leakage current.

VI. COMPARATIVE STUDY

The superiority of the proposed SCMLI in terms of different
parameters such as the number of power switches (Nsw),
number of gate drivers (Ngd), number of diodes (Nd), number of
capacitors (Nc), number of switches in the charging path of the Irradiance (G= 1000 W/m2) Irradiance (G= 500 W/m2) Irradiance (G= 1000 W/m2) Irradiance (G= 500 W/m2)

capacitors (Ncp), total standing voltage (TSV), switching device

(b)
power (SDP) rating, and cost function per level (CF/Nl) over (a)

other converters has been verified in this section. The

parameters mentioned above for different SCMLI topologies
Irradiance (G= 1000 W/m2) Irradiance (G= 500 W/m2)
are given in Table VI. From the table, it can be understood that
(d)
the proposed SCMLI utilizes fewer power switches than most (c)

Fig. 19. (a) PV array power, voltage and currents (b) Inverter output voltage
inverters. Though the inverters proposed in [22] and [34] and capacitor voltages (c) grid voltage and currents (d) leakage current
employ fewer switches than the proposed one, they require a
huge number of diodes. Among all, the converters [18] and [32]
require more switches to generate the seven-level output 5.52 5.95
6
voltage, leading to increased gate drivers. It is worth 5 3.95 3.67 3.57 4.00 3.67
4 3.38 3.24 3.24 3.293.67 3.243.60 3.21
CF/Nl

mentioning that the proposed SCMLI does not employ any 3

diodes. Whereas the converters [17], [22], [23], and [34] utilize 2
the diodes to avoid the short-circuiting of either the DC source 1
0
or switched capacitors. Due to this, the conduction losses are
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
[23]
[24]
[25]
[26]
[27]
Proposed
high for these converters. Table VI shows that most converters
=0.5
require more than two capacitors to achieve a voltage gain of
1.5. However, the topologies [25], [33], and proposed inverters (a)
are achieving the 1.5 voltage gain with only two capacitors. The 8 6.57 7.29
7 5.14
topology proposed in [27] utilizes the single capacitor for 6 4.71 4.71 4.43 4.71
4.43 4 4.5
5 4.14 4 4 4.14 3.93
CF/Nl

achieving voltage gain of 1.5 but at the cost of additional 4

voltage sensors. Further, the TSV is an important parameter that 3
2
influences the cost of the converter. The TSV for the proposed 1
0
inverter is 7.5Vdc, which is less compared to all the topologies
[12]

[14]
[15]

[18]
[19]

[21]
[22]

[24]
[25]
[13]

[16]
[17]

[20]

[23]

Proposed

mentioned in Table V except the topology [27]. Another

important parameter that gives insight into the voltage and =1.5
current ratings of the power switch is the SDP rating and is (b)
obtained as mentioned in section III for all the converters and Fig. 20. CF/Nl of different SC inverters for (a) α=0.5 (b) α=1.5
are given in Table VI. Table VI indicates that the proposed
In Table VI, the CF/Nl, which is a function of total
inverter has a lower SDP rating than all the topologies except
component count and TSV, is obtained for each inverter using
the topology [27] and [28]. However, the topology [28] has the
equation (12). Fig. 20 shows the CF/Nl for two different values
drawback of higher switch count and TSV. Also, it can be
of α. It can be seen that the proposed inverter has a lower value
observed that the topologies [23], [29], and [32] experiences a
for both α=0.5 and α=1.5. The lower value of CF/Nl indicates
higher SDP rating compared to the remaining topologies.
that the proposed SCMLI is cost-effective compared to the
remaining topologies.

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3342123

Further, the efficiency of the different topologies is estimated

using PLECS software for various load power conditions. The
parameters listed in Table II are considered for the efficiency
S3
calculations. Fig. 21 depicts the efficiencies for the different S6
S9 C2
C1
SCMLIs, and it is observed that the efficiency of the proposed C
inverter is slightly less compared to [17], [23], [27], and [33] at
+
B
Vdc
S7 S8 A
lower power ratings. However, at higher power ratings, the S5 S2

efficiency of the proposed SCMLI is high.

In addition, the cost analysis for different topologies have
S4 S1
been carried out and presented in Table VII. For fair
comparisons, an input DC source value of 100V is considered
N
for all the topologies and the device ratings are chosen
Fig. 22. Three phase configuration of the proposed topology
according to their structure. A noteworthy observation from TABLE VI
Table VII is that the proposed topology (PT) exhibits a lower COMPARISION OF DIFFERENT SCMLI TOPOLOGIES
implementation cost compared to all other topologies. Topology Nsw Ngd Nd Nc TSV
SDP Rating Voltage gain
In breif, the merits of proposed boost capable inverter (VA) (Vo/Vin)
interms of lower TSV, reduced device count is shown [17] 9 8 1 3 8Vdc 2200 1.5
[18] 11 11 0 3 8Vdc 2300 1.5
promising in applications like photovoltaic systems, electric [19] 9 8 0 3 8Vdc 2300 1.5
vehicles and uninterruptable power supplies. Further, the [20] 10 8 0 4 11Vdc 2400 1.5
configuration of the proposed topology can be extended to the [21] 10 9 0 3 9Vdc 2600 1.5
three-phase system, as shown in Fig. 22. It is worth mentioning [22] 8 8 16 3 11Vdc 2600 1.5
that single DC source is enough in generating three phase [23] 10 9 2 3 12Vdc 2750 1.5
[24] 9 8 0 3 8Vdc 2300 1.5
higher voltage level at the output.
[25] 10 8 0 2 9Vdc 2200 1.5
98 97.18 97.07 [26] 10 9 0 4 9Vdc 2300 1.5
% of Efficiency

96.6 96.51 96.26

96 94.83 [27]* 9 9 0 1 7Vdc 2100 1.5
[28] 12 12 0 4 20 Vdc 1925 4
94
[29]* 10 10 0 1 9Vdc 2700 1.3
92 [32] 16 15 0 6 14Vdc 2800 1.5
200W 600W 1000W 1400W 1800W 2000W
[33] 10 8 0 2 8Vdc 2200 1.5
Output power
[34] 8 7 4 3 10Vdc 2150 1.5
17 18 19 20 21 22
[35] 10 8 0 4 11Vdc 2400 1.5
23 24 25 26 27 28
Proposed 9 9 0 2 7.5Vdc 2150 1.5
29 32 33 34 35 Proposed
*- Additional sensor is required to balance the capacitor voltage
Fig. 21. Efficiency of the different seven-level SCMLI topologies at various
output powers

TABLE VII
COST COMPARISION OF DIFFERENT SEVEN LEVEL SCMLI TOPOLOGIES
Unit Topology
Component Part Number Rating Price
($) 17 18 19 20 21 22 23 24 25 26 32 33 34 35 PT
100V,
IRF540PBF 1.78 3 6 2 2 2 - 2 2 2 2 8 4 4 2 5
20A
200V,
IRFP240PBF 2.84 6 5 7 6 8 4 8 7 8 8 4 6 4 6 2
Switch 20A
300V,
IRFB4137PBF 3.43 - - - - - 2 - - - 2 - 2
20A
400V,
FDH20N40 4.09 - - - 2 - 2 - - - 2 - 2 -
20A
100V,
FCH20E10 0.87 1 - - - - 16 - - - - - 2 -
20A
VS-20ETF02- 200V,
Diode 1.42 - - - - - - 2 - - - - - -
M3 20A
300V,
SBR20A300CT 2.38 - - - - - - - - - - - 2 -
20A
Gate driver TLP250 - 1.71 8 11 8 8 9 8 9 8 8 9 15 8 7 8 9
B43501E2228 200V,
Capacitor 13.8 3 3 3 4 3 3 3 3 2 4 6 2 3 4 2
M000 2200uF
78. 85. 78. 97. 83. 95. 85. 78. 67. 96. 149. 65. 78. 97. 64.
Total Cost ($)
33 09 52 66 07 4 91 52 56 87 09 44 35 66 43

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3342123

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3342123

[32] S. S. Lee and K. -B. Lee, "Switched-Capacitor-Based Modular T-Type V S Prasadarao K (M’20-SM’22) received B. Tech
Inverter," in IEEE Transactions on Industrial Electronics, vol. 68, no. 7, and M. Tech degrees from Jawaharlal Nehru
pp. 5725-5732, July 2021. Technological University, Kakinada, India, in 2011,
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Inverter Based on Symmetrical Capacitors," in IEEE Journal of Emerging time Ph.D. at National Institute of Technology (NIT),
and Selected Topics in Power Electronics, vol. 10, no. 3, pp. 3033-3044, Andhra Pradesh, India. His research interests include
June 2022. fault tolerant multilevel inverters and dc–dc
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and S. Kaliyaperumal, "Performance Evaluation of Seven Level Reduced
Switch ANPC Inverter in Shunt Active Power Filter With RBFNN-Based Sankar Peddapati (M’11-SM’20) received B. Tech
Harmonic Current Generation," in IEEE Access, vol. 10, pp. 21497- degree from Jawaharlal Nehru Technological
21508, 2022. University, Hyderabad and M. Tech degree from
[35] K. Suresh and E. Parimalasundar, "A Modified Multi Level Inverter with Acharya Nagarjuna University, Guntur, in 2006, and
Inverted SPWM Control," in IEEE Canadian Journal of Electrical and 2009 respectively. He received the Ph.D. degree in
Computer Engineering, vol. 45, no. 2, pp. 99-104, Spring 2022. Electrical and Electronics Engineering from the
[36] Tapas Roy, Pradip Kumar Sadhu, and Abhijit Dasgupta, “Cross-Switched National Institute of Technology, Tiruchirappalli,
Multilevel Inverter using Novel Switched Capacitor Converters”, in IEEE Tamil Nadu, India, in 2015. Currently, he is with the
Transactions on Industrial Electronics, vol. 66, no. 11, pp. 8521-8532, Department of Electrical Engineering, National
Nov. 2019. Institute of Technology (NIT), Andhra Pradesh,
[37] M. Shen, A. Joseph, J. Wang, F. Z. Peng and D. J. Adams, "Comparison India. His research interests include power electronics and renewable energy
of Traditional Inverters and Z -Source Inverter for Fuel Cell Vehicles," in systems.
IEEE Transactions on Power Electronics, vol. 22, no. 4, pp. 1453-1463,
July 2007. Balram Kumar (Graduate Student Member, IEEE)
[38] J. Zeng, J. Wu, J. Liu and H. Guo, "A Quasi-Resonant Switched-Capacitor received the B. Tech degree in Electrical Engineering
Multilevel Inverter with Self-Voltage Balancing for Single-Phase High- from Guru Gobind Singh Educational Society’s
Frequency AC Microgrids," in IEEE Transactions on Industrial Technical Campus, Bokaro, Jharkhand, India, in
Informatics, vol. 13, no. 5, pp. 2669-2679, Oct. 2017. 2019, and the M. Tech degree in Power Electronics
[39] Zhang N, Tang H, and Yao C, “A systematic method for designing a PR Control and Drives from the Veer Surendra Sai
controller and active damping of the LCL filter for single- phase grid- University of Technology, Burla, Odisha, India, in
connected PV inverters,” Energies Vol. 7, No. 6, pp. 3934–3954, 2014. 2021. He is currently working toward the Ph.D.
[40] S. K. Kuncham, K. Annamalai and S. Nallamothu, "Single-Phase Two- degree in Electrical Engineering at the National Institute of Technology Andhra
Stage Seven-Level Power Conditioner for Photovoltaic Power Generation Pradesh, Tadepalligudem, India. His research interests include power electronic
System," in IEEE Journal of Emerging and Selected Topics in Power converters and drives.
Electronics, vol. 8, no. 1, pp. 794-804, March 2020.

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