Design of springs

Instruction Sets and

Data Formats
03
1. When RET instruction is executed by any RET
subroutine then When RET is executed [ESE-2001]
[ESE-2001]
1. Op-code of IN is fetched
(a) the top of the stack will be popped out and
2. port address 30H is decoded
assigned to the PC
3. Op-code of IN is decoded
(b) without any operation, the calling program
4. I/O read operation is performed
would resume from instruction immediately
following the call instruction The correct sequence of these operations is
(c) the PC will be incremented after the (a) 3, 1, 4, 2 (b) 1, 3, 2, 4
execution of the instruction (c) 1, 3, 4, 2 (d) 3, 1, 2, 4
(d) without any operation, the calling program Sol. (b)
would resume from instruction immediately First of all, op-code of IN is fetched then it is
following the call instruction, and also the decoded after that port address is decoded from
PC will be incremented after the execution of where the data has to be read. Now I/O read
the instruction operation is performed. Hence, the correct option
Sol. (a) is (b).
When we call any subroutine during the execution
of a main program then the address (location) of 3. In 8085 microprocessor, a number of the form
next instruction is stored in stack. After we 000XXXX0 stored in the accumulator is processed
complete the execution of subroutine then program by the programme (Assume CY = 0) as follows
will have to return at original program so it pop the
ANI FFH
address that is stored in stack during the execution
RAL
of call and assigned to program counter PC.
MOV B, A
Hence, the correct option is (a).
ANI FFH
RAL
2. Consider the following set of 8085 instructions
used to read a byte of data from the output of an ANI FFH
ADC. The byte represents digital equivalent of RAL

analog input voltage Vin applied to ADC when ADD B

is asserted The operation carried out by the programme is
ADC : EQU 30H [ESE-2001]
GETADC: N 30H (a) multiplication of accumulator content by 10

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 Microprocessors

(b) complement of accumulator content (d) Moves the contents of HL pair to C register
(c) multiplication of accumulator content by 9 Sol. (b)
(d) rotation of accumulator content three times MOV instruction work like MOV D, S
Sol. (a) D  Destination
Since in program instruction RAL is used three S  Source
times so content of accumulator is rotated left three So content of source is copied in destination and
times. content of S remains unchanged.
Hence, the correct option is (a).
MOV H, C  content of C is copied to H.
Hence, the correct option is (b).
4. Consider the execution of the following
instructions by a 8085 microprocessor :
6. For 8085 microprocessor, the instruction RST6
[ESE-2002]
restarts subroutine at address [ESE-2002]
LXIH, 01FFH
(a) 00H (b) 03H
SHLD 2050H
(c) 30H (d) 33H
After execution the contents of memory locations
Sol. (c)
2050H and 2051H and the registers H and L, will
be To find the address of any RST like RST 6 
multiply 6 by 8 then convert it into Hexadecimal as
(a) 2050H  FF; 2051H  01; H  FF; L 
01 6  8 = (48)10 = (30)H.
Hence, the correct option is (c).
(b) 2050H  01; 2051H  FF; H  FF; L 
01
(c) 2050H  FF; 2051H  01; H  01; L  7. Examine the following instruction to be executed
FF by a 8085 microprocessor. The input port has an
address of 01H and has a data 05H to input: IN
(d) 2050H  FF; 2051H  01; H  00; L 
01H ANI 80H After execution of the two
00
instructions the following flag portions may occur :
Sol. (c)
1. Zero flag is set
LXIH, 01FFH  H  01 & L  FF
2. Zero flag is reset
SHLD 2050H  2050H  FF
3. Carry flag is cleared
2051H  01 4. Auxiliary carry flag is set
Hence, the correct option is (c). Select the correct answer using the codes given
below: [ESE-2003]
5. Which one of the following functions is performed (a) 1 and 3 (b) 2, 3 and 4
by the 8085 instruction MOV H, C? [ESE-2002] (c) 1, 3 and 4 (d) 1, 2 and 4
(a) Moves the contents of H register to C Sol. (c)
register
In AND operation CY = 0 and AC = 1 By default
(b) Moves the contents of C register to H
register
(c) Moves the contents of C register to HL pair

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 Instruction Sets and Data
Formats
9. If the accumulator of an Intel 8085 A
microprocessor contains 37H and the previous
operation has set the carry flag, the instruction
ACI56H will result in [ESE-2003]
(a) 8EH (b) 94H
Hence, the correct option is (c). (c) 7EH (d) 84H
Sol. (a)
8. After an arithmetic operation, the flag register of a ACl 56H  implies add the immediate with
8085 microprocessor has the following look: accumulator along with carry.

D7 D6 D5 D4 D3 D2 D1 D0 SO 37H
+ 56H
1 0 × 1 × 0 × 1 Hence, the correct option is (a).

The arithmetic operation has resulted in [ESE-

10. Assertion (A) : The zero-flag of a 8085
2003]
microprocessor is not affected after the execution
(a) A carry and an odd parity number having 1
of the following couple of instructions:
as the MSB
MVI B, 03
(b) Zero and the auxiliary carry flag being set
MOV A, B
(c) A number with even parity and 1 as the MSB
Reason (R) : After the execution of a data transfer
(d) A number with odd parity and 9 as the MSB
instruction, zero-flag is set if the accumulator
Sol. (a) content is zero [ESE-2003]
S Z X AC X P X CY (a) Both A and R are true and R is the correct
explanation of A
S – sign flag  represent MSB of result zero flag (b) Both A and R are true but R is not the correct
 Z  set if result is zero explanation of A

Auxiliary flag AC  if carry is generated by lower (c) A is true but R is false

nibble it is set (d) A is false but R is true
Parity flag P  If no. of 1's in result is even then it Sol. (c)
is set i.e. result has even parity A data transfer instruction does not affect any flag.
Carry flag  Set if carry is generated from most Hence, the correct option is (c).
significant bit.
From the question CY = 1, P = 0 (odd parity), 11. Match List-I (Introduction) with List-II (Type of
AC = 0 No auxiliary carry Addressing) and select the correct answer:
Z = 0 so result is not zero List-I [ESE-2003]
S=1 A. MOV A, M
So MSB of result is 1. B. LXI H, E400H
Hence, the correct option is (a). C. LDAF1CDH
D. CMC

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List-II A B C D
1. Direct addressing (a) 4 1 2 3
2. Register addressing (b) 4 2 1 3
3. Implicit addressing (c) 3 2 1 4
4. Register indirect addressing (d) 3 1 2 4
5. Immediate addressing Sol. (b)
Codes : RAL  implicit addressing
A B C D MOV A, M  Register indirect, address of
(a) 5 4 1 3 memory location is taken from HL pair.
(b) 4 5 3 1 JMP 3FAOH  immediate addressing since
(c) 5 4 2 3 immediate data 3FAO is copied to program
counter.
(d) 4 5 1 3
Sol. (d) LDA 03FCH  direct addressing since address of
memory location is directly specified as 03FC in
MOVA, M  Content at memory location M
the instruction.
whose address is stored in HL pair (by default) is
Hence, the correct option is (b).
copied to A.
So this is register indirect addressing.
13. Match List-I (Instruction) with List-II (Operation)
LXIH, E400H the data E400 is copied to HL pair
for Intel 8085 and select the correct answer using
directly so this is immediate addressing.
the codes given below : [ESE-2004]
LDA F1CDH the content at location F1CD are
List-I
copied to accumulator so it is a direct addressing
(address is directly given). A. PCHL

CMC  implicit addressing (complement the B. SPHL

carry). C. XTHL
Hence, the correct option is (d). D. XCHG
List-II
12. For Intel 8085, match List-I (Addressing Mode) 1. Exchange the top of the stack with the
with List-II (Instruction) and select the correct contents of HL pair
answer using the codes given below: 2. RAL
[ESE-2004] 3. Exchange the contents of HL with those of
List-I DE pair
A. Implicit addressing 4. Transfer the contents of HL to the stack
B. Register-Indirect pointer
C. Immediate 5. Transfer the contents of HL to the
D. Direct addressing programme counter

List-II Codes :
A B C D

Codes : (a) 3 4 1 2

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 Instruction Sets and Data
Formats
(b) 3 4 2 1 SPHL  Transfer the content of HL to stack
(c) 4 3 2 1 painter SP i.e. (Initializing the stack pointer).
(d) 4 3 1 2 Hence, the correct option is (b).
Sol. (d)
PCHL  Transfer the content of HL to PC 15. Which one of the following 8085 assembly
language instructions does not affect the contents
SPHL  Transfer the content of HL to SP
of the accumulator? [ESE-2004]
XTHL  Exchange top of stack with HL
(a) CMA (b) CMP B
XCHG  Exchange the contents of HL with those
(c) DAA (d) ADD B
of DE pair.
Sol. (b)
Hence, the correct option is (d).
CMP B will not affect the content of accumulator
in this instruction content of A is compared with
14. Match List-I (Instruction) with the List-II respect to B by checking (A – B),
(Application) and select the correct answer using
if A > B  Z = 0, CY = 0
the codes given below: [ESE-2004]
A < B  Z = 0, CY = 1
List-I
A = B  Z = 1, CY = 0
A. SIM
But content of A remains same.
B. DAD
Hence, the correct option is (b).
C. DAA
D. SPHL
16. Consider the following statements about register
List-II
indirect addressing:
1. 16-bit addition
1. It helps in writing code that executes faster
2. Initializing the stack pointer
2. It helps in writing compact code
3. Serial output data
3. It allows reuse of memory CPU data transfer
4. Checking the current interrupt mask setting
instruction
5. BCD addition
4. It is essential for stack operations
Codes :
Which of these statements are correct? [ESE-2005]
A B C D
(a) 1, 3 and 4 (b) 1, 2 and 4
(a) 5 4 2 1
(c) 2, 3 and 4 (d) 1, 2 and 3
(b) 4 1 5 2
Sol. (b)
(c) 5 1 2 4
Register indirect addressing i.e. MOV A, M doesn't
(d) 3 4 5 1 allow the reuse of memory CPU data transfer
Sol. (b) instruction. It executes faster as compared to direct
SIM  Set the interrupt mask addressing as required lesser T-states.

DAD  16 bit addition used as Hence, the correct option is (b).

DAD B  add the content of BC to HL

DAA  used for BCD addition (Decimal adjust
accumulator)

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17. Consider the program given below, which transfer Whole part is executed 10 times and at 11th times
a block of data from one place in memory to JNZ required 7 T states but 3 memory access since
another: condition becomes false.
MVI C, OB H So total memory access
LXI H, 2400H T = 2 + 3 + 3 + 10 [2 + 2 + 1 + 1 + 1 + 3]
LXI D, 3400H + (2 + 2 + 1 + 1 + 1 + 3)
L1: MOV A, M T = 118
STAX D Hence, the correct option is (a).
INR L
INR E 18. Consider the following 8085 instructions:
DCR C ANA A, ORA A, XRA A, SUB A, CMP A
JNZ L1 Now, consider the following statements:
What is the total number of memory accesses 1. All are arithmetic and logic instructions
(including instruction fetches) carried out? 2. All cause the accumulator to be cleared
[ESE-2005] irrespective of its original contents
(a) 118 (b) 140 3. All reset the carry flag
(c) 98 (d) 108 4. All of them are 1-byte instructions
Sol. (a) Which of these statements is/are correct?
MVI C, OBH  2 byte instruction = 2 memory [ESE-2005]
accesses (a) 1, 2, 3 and 4 (b) 2 only
LXI H, 2400H  3 byte instruction = 3 memory (c) 1, 2 and 4 (d) 1, 3 and 4
accesses. Sol. (d)
LXI D, 3400H  3 byte instruction = 3 memory ANA A
accesses
ORA A
L1 : MOV A, M  1 byte instruction = 2 memory
XRA A logical instructions, 1 byte instruction
access (two read)
STAX, D  1 byte instruction = 2 memory access
(1 read + 1 write) Arithmetic instructions, 1 byte instruction
INR L  1 byte instruction = 1 memory access as A – A = (00)H so borrow required at most
INR E  1 byte instruction = 1memory access significant bit
DCR C  1 byte instruction = 1 memory access ( A = A) so CY = 0
JNZ L1  1 byte instruction = 3 SUB A  Cleared the content of A
memory access if condition is true/false. but CMP A  Content of A remains same as
So from L1 to JNZ till condition is satisfied i.e. till previous to this instruction.
content of C does not zero i.e. till content of C Hence, the correct option is (d).
become 1 i.e. 10 times (as C = OB initially after 10
times decrement it becomes = 1).

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 Instruction Sets and Data
Formats
19. INR instruction of 8085 does not affect carry flag.
Which of the following is correct about INR
instruction? [ESE-2005]
(a) Overflow cannot be detected
(b) Overflow can be detected
Hence, the correct option is (c).
(c) If a programme requires overflow to be
detected, ADD instruction should be used
instead of INR 21. When an 8086 executes an INT type instruction, it?
(d) It can be used to increase the contents of the [ESE-2005]
BC register pair (a) Resets both IF and TF flags
Sol. (c) (b) Resets all flags
With use of INR  Overflow can't be detected as (c) Sets both IF and TF
carry flag is not affected. (d) Resets the CF and TF
But ADD instruction can be used for detection of Sol. (a)
overflow as carry flag is affected due to this It resets both IF and TF flags.
instruction.
Hence, the correct option is (a).
Hence, the correct option is (c).

22. The contents of memory locations 2000H, 2001H

20. The following sequences of instructions are and 2002H are AAH, BBH and CCH respectively.
executed by an 8085 microprocessor: What are the contents of H and L registers after
1000 LXI SP, 27FF executing the following instructions in sequence?
1003 CALL 1006 LXI H, 2001H
1006POSH LHLD 2001H
What are the contents of the stack pointer (SP) and Select the correct answer using the codes given
the HL register pair on completion of execution of below: [ESE-2006]
these instruction? [ESE-2005] (a) Contents of H and L registers are 20H and
(a) SP = 27FF, HL = 1003 01H, respectively
(b) SP = 27FD, HL = 1003 (b) Contents of H and L registers are AAH and
(c) SP = 27FF, HL = 1006 BBH, respectively
(d) SP = 27FD, HL = 1006 (c) Contents of H and L registers are BBH and
Sol. (c) CCH, respectively

1000LXISP, 27FF  SP = 27FF (d) Contents of H and L registers are CCH and
BBH, respectively
1003 CALL, 1006
Sol. (d)
11006POPH
LXI H, 2001H : H  20
H  10
LHL D, 2001H : L  01
L  06
L  [2001]
HL  1006
 L = BBH

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 Microprocessors

H = CCH DAA  stand for decimal adjust accumulator, it is

Hence, the correct option is (d). used for BCD additions.
Hence, the correct option is (c).
23. How many times will the following loop be
executed? 25. Consider the following statements:
LXI B 0010H 1. Indirect addressing is not possible for 1/0
LOOP: DCX B mapped I/O port addresses
MOV A, B 2. Pointers cannot be used to access memory
ORA C mapped I/O addresses

JNZ LOOP 3. Fewer machine instructions can be used with

I/O mapped I/O addressing as compared to
Select the correct answer using the code given
memory mapped 1/0 addressing
below: [ESE-2006]
4. With an 8085 microprocessor, one can
(a) 10 (b) 100
access at the most 512 devices with unique
(c) 16 (d) 15 addresses using 1/0 mapped 1/0 addressing
Sol. (c) Which of these statements are correct? [ESE-2006]
LXI, B, 0010H  B = 00H(0010)H = (16)10 (a) 1, 2 and 3 (b) 2 and 4
 C = 10H (c) 3 and 4 (d) 1 and 3
LOOP : DCX B  Decrement content of BC pair Sol. (d)
by 1 Pointer (HL pair) can be used to access memory
MOV A, B  A = 00 always mapped I/O.
ORA C  Logical OR of content of C with A with 1/O mapped l/O, address is of 8 bit so we can
JNZ LOOP address maximum

So this loop continues till ORA C result in zero i.e. = 28I/O devices
zero flag set so this will happen when content of C = 256I/O devices
become zero. Since initial content of C is (16) 10 so Hence, the correct option is (d).
after 16 times execution of DCX it will become
zero so loop will be executed 16 times.
26. Which one of the following instructions is a 3-byte
Hence, the correct option is (c).
instruction? [ESE-2006]
(a) MVI A (b) LDAXB
24. In 8085, the DAA instruction is used for
(c) JMP 2050 (d) MOV A, M
[ESE-2006]
Sol. (c)
(a) Direct Address Accumulator
JMP 2050 is 3 byte instruction
(b) Double Add Accumulator
1 byte for opcode JMP
(c) Decimal Adjust Accumulator
1 byte for lower address 50
(d) Direct Access Accumulator
1 byte for upper address 20
Sol. (c)
Hence, the correct option is (c).

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 Instruction Sets and Data
Formats
27. Which one of the following statement does not MOV A, L
describe property/characteristic of a stack pointer ORI FOH
register in 8085 microprocessor? [ESE-2007]
MOV L, A
(a) It points to top of the stack
MOV A, H
(b) It is UP/DOWN counter
ANI FOH
(c) It is automatically initialized to 0000H on
MOV H, A
power-on
HLT
(d) It is a 16-bit register
What are the contents of A, H and L registers after
Sol. (c)
executing the above set of instructions in sequence?
To initialize the stack we have to use LXIRP or
(a) Contents of A, H and L registers are 25, 20
SPHL.
and F1, respectively
Hence, the correct option is (c).
(b) Contents of A, H and L registers are 05, 25
and 01, respectively
28. On execution of the following segment of (c) Contents of A, H and L registers are 20, 20
instructions in sequence and F1, respectively
MVI A, 91H (d) Contents of A, H and L registers are 25, 05
XRI 91H and 01, respectively
Which one of the following is correct? [ESE-2007] Sol. (c)
(a) Content of accumulator is 00H. Carry, LXI H2501H  H = 25H, L = 01H
Auxiliary Carry and Zero flag set to 0, 1 and (Higher order bit in higher order register)
0, respectively.
MOV A, L  A = 01H, L = 01H
(b) Content of accumulator is 91H. Carry,
ORI F0H  A = F1H
Auxiliary Carry and Zero flag set to 0, 0 and
1, respectively. MOV L, A  L = F1H & A = F1H
(c) Content of accumulator is 00H. Carry, (Data is copied)
Auxiliary Carry and Zero flag set to 0, 0 and MOV A, H  A = 25H, H = 25H
1 respectively
ANI F0H  A = 2H
(d) Content of accumulator is 91H. Carry
MOV H, A  H = 20H, A = 20H
Auxiliary Carry and Zero flag set to 0, 1 and
0 respectively Hence, the correct option is (c).

Sol. (c)
30. Assertion (A) : A subroutine is a program written
91H  91H = 00, by default CY = 0, AC = 0
separately from the main program to perform a
Result zero so zero flag set.
function that occurs repeatedly in the main
program.
Hence, the correct option is (c). Reason (R) : A subroutine can be called by a CALL
instruction. [ESE-2007]
29. Read the following Assembly Language Program (a) Both A and R are true and R is the correct
Segment of 8085 Micro-processor: [ESE-2007] explanation of A
LXI H, 2501 H

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(b) Both A and R are true but R is not the correct Hence, the correct option is (a).
explanation of A
(c) A is true but R is false 33. Match List-I (Feature of instruction) with List-II
(d) A is false but R is true (Instruction) and select the correct answer using the
Sol. (b) code given below the lists: [ESE-2008]
Both are correct but R is not explanation of A i.e. List-I List-II
subroutine are written outside the main program A. Maskable 1. RST 5.5
because they required in the program many times interrupt
so if we do not make a subroutine then we have to
B. Signal 2. XTHL
write same instructions again and again and our
C. Instruction 3. SID
program will become lengthy.
D. Memory location 4. RST 6.5 002CH
Hence, the correct option is (b).
Codes :
A B C D
31. The content of the Program Counter of an intel
8085 A microprocessor specifies which one of the (a) 4 1 2 3
following? [ESE-2008] (b) 2 3 4 1
(a) The address of the instruction being executed (c) 4 3 2 1
(b) The address of the instruction executed (d) 2 1 4 3
earlier Sol. (c)
(c) The address of the next instruction to be RST 6.5 and RST 5.5 both are Maskable interrupt.
executed address location of RST 5.5
(d) The number of instructions executed so far = (8  5.5)10 = (44)10 = (2C)16
Sol. (c) XTHL  is a instruction which exchanges top of
PC points the location of next instruction to be stack with HL pair.
executed. SID is signal used for serial input data.
Hence, the correct option is (c). Hence, the correct option is (c).

32. In an Intel 8085 A, what is the content of the 34. The stack pointer of an 8085 A microprocessor
Instruction Register (IR)? [ESE-2008] contains ABCDH.
(a) Op-code for the instruction being executed PUSH PSW
(b) Operand for the instruction being executed XTHL
(c) Op-code for the instruction to be executed PUSH D
next
JMP EC75H
(d) Operand for the instruction to be executed
At the end of the execution of the above
next
instructions, what would be the content of the stack
Sol. (a) pointer?
IR contains the opcode for the instruction being [ESE-2008]
executed while PC contains address of next
(a) ABCBH (b) ABCAH
instruction to be executed.

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 Instruction Sets and Data
Formats
(c) ABC9H (d) ABC8H
Sol. (c) 36. The contents of Program Counter (PC), when the
SP = ABCD microprocessor is reading from 2FFF H memory
location, will be [ESE-2008]
PUSH PSW decremented the content of SP by 2
(a) 2FFEH (b) 2FFFH
(c) 3000H (d) 3001H
Sol. (c)
PC shows the address from which next byte is to be
fetched. Hence while p is reading from 2FFFH PC
will show 3000H.
XTHL  Exchange top of stack with HL pair in H Hence, the correct option is (c).
content at ABCC copied and at ABCC content of H
copied in L content at ABCB copied and at ABCB 37. Carry flag is not affected after the execution of
content of L copied.
[ESE-2008]
Again PUSHD
(a) ADD B (b) SBB B
Content of SP decremented by two and content of
(c) INR B (d) ORA B
DE pair is copied to stack Now SP = (ABCB) H –
(2)H = (ABC9)H. Sol. (c)

JMP EC75H it has no effect on SP INR and DCR instructions do not effect carry flag
other flags are affected while almost all other
So content of SP = (ABC9)H.
logical and arithmetical operations affect all the
Hence, the correct option is (c). flags.
Hence, the correct option is (c).
35. If the HLT instruction of an Intel 8085 A
microprocessor is executed [ESE-2008]
38. The addressing mode used in the instruction JMP
(a) the microprocessor is disconnected from the F347 H in case of an Intel 8085 A microprocessor
system bus till the RESET is pressed. is which one of the following? [ESE-2008]
(b) the microprocessor halts the execution of the (a) Direct (b) Register-indirect
program and returns to the monitor.
(c) Implicit (d) Immediate
(c) the microprocessor enters into a HALT state
Sol. (d)
and the buses are tri-stated.
JMP F347 H this is a immediate addressing as the
(d) the microprocessor reloads the program
immediate data F347H is copied to program
counter from the locations 0024H and
counter.
0025H.
Hence, the correct option is (d).
Sol. (c)
On execution of HLT microprocessor finishes
executing current instructions and halts any further 39. Which one is the indirect addressing mode in the
execution and address and data buses are place in following instructions? [ESE-2008]
high impedance state (i.e. tri state). (a) LXIH2050H (b) MOV A, B
Hence, the correct option is (c). (c) LDAXB (d) LDA 2050H

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Sol. (c) JMP 2021H is a immediate addressing as

LDAXB  load the accumulator indirect i.e. immediate data copied to program counter PC.
content of location whose address is given by LDAX B  Indirect addressing mode the content
content of BC pair is copied into accumulator so it at location whose address is given by content of BC
is a register indirect addressing mode. register pair is copied to accumulator. Here address
Hence, the correct option is (c). is indirectly given through register pair. IN 10H 
Direct addressing mode as address (10) H of input
port is directly given in instruction. RLC 
40. In an instruction of 8085 microprocessor, how
Implicit addressing.
many bytes are present? [ESE-2009]
Hence, the correct option is (b).
(a) One or two (b) One, two or three
(c) One only (d) Two or three
42. Which one of the following addressing technique is
Sol. (b)
not used in 8085 micro-processor? [ESE-2009]
In 8085 maximum size of any instruction = 3 byte
(a) Register (b) Immediate
In 8085 minimum size of any instruction = 1 byte
so instruction size can be 1, 2, or 3 byte. (c) Register indirect (d) Relative

Hence, the correct option is (b). Sol. (d)

Relative addressing technique is used in 8086
microprocessor not in 8085 microprocessor, all
41. Match List-1 (Instruction code) with List-II
other given in question are used in 8085
(Addressing mode) and select the correct answer
microprocessor.
using the code given below the lists: [ESE-2009]
Hence, the correct option is (d).
List-I
A. JUMP 2021H
43. When the operand requires for an instruction is
B. LDAX B
stored inside the processor, then what this
C. IN10H addressing mode is called? [ESE-2009]
D. RLC (a) Direct (b) Register
List-II (c) Implicit (d) Immediate
1. Direct addressing Sol. (b)
2. Immediate addressing In direct and immediate data (operand) is in
3. Indirect Register addressing memory while in implicit operand (data) is in p,
4. Implicit addressing like CMC, CMA. In register addressing mode also
Codes : data is in p but register indirect addressing mode
A B C D (operand) data is in memory so best option is
implicit.
(a) 4 3 1 2
Hence, the correct option is (b).
(b) 2 3 1 4
(c) 4 1 3 2
44. Match List-I (Microprocessor pin) with List-II
(d) 2 1 3 4
(Signals on pin) and select the correct answer using
Sol. (b) the code given below the Lists : [ESE-2009]

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 Instruction Sets and Data
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List-I List-II 46. The stack pointer of an 8085 micro-processor is
A. TRAP 1. Interrupt ABCDH. At the end of execution of the sequence
of instructions, what will be the content of the stack
B. HLDA 2. Initializing
pointer? [ESE-2009]
C. RESET 3. Enable
PUSH PSW
D. ALE 4. Memory access
XTHL
Codes :
PUSHD
A B C D
JMPFC70H
(a) 1 2 4 3
(a) ABCBH (b) ABCAH
(b) 3 2 4 1
(c) ABC9H (d) ABCBH
(c) 1 4 2 3
Sol. (c)
(d) 3 4 2 1
Push instruction decreases the stack pointer by 2.
Sol. (c)
 Two push instruction in programme
TRAP  is a interrupt
decrement it by 4
HLDA  is used for memory access (direct
 SP = ABCD – 4 = ABC9H
memory access/DMA) acknowledgment given by
Hence, the correct option is (c).
p to DMA.
RESET  To initialize p from (0000)H
47. An 8085 microprocessor is executing the
ALE  address latch enable, to demultiplex
programme as follows:
address bus and data bus
MVI A, 20H
if ALE = 1 enable lower order bus as address bus
MVI B, 10H
= 0 enable lower order bus as data bus
BACK : NOP
Hence, the correct option is (c).
ADD B
RLC
45. What is the correct 8085 assembly language
JNC BACK
instruction that stores the contents of H and L
registers into the memory locations 1080H and HLT
1081 H respectively? [ESE-2009] How many times the instruction NOP will be
(a) SPHL 1080H (b) SHLD 1080H executed? [ESE-2009]
(c) STAX 1080H (d) SPHL 1081H (a) 4 (b) 3
Sol. (b) (b) 2 (d) 1
SHLD 1080 Sol. (b)
When this instruction is executed then H – L pair MVI A, 20H  A = 20H
content is stored into 2 memory locations MVI B, 10H  B = 10H
[(1080)]  L BACK : NOP
[(1081)]  H ADD B
Hence, the correct option is (b). RLC
JNC BACK

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 Microprocessors

HLT INR A
when we go inside the loop 1st time What are the contents of A and PSW registers after
ADDB  A = 30H = (00110000)2, CY = 0 executing the above set of instructions in sequence?

RLC  A = (01100000)2 = (60)H, CY = 0 [ESE-2010]

(a) AAH and 00H (b) FFH and 66H
Carry is zero so control will be transfer to
BACK again (c) 00H and 54H (d) 00H and 00H

Now loop will be executed 2nd time as Sol. (c)

ADDB  A = 70H = (01110000)2, CY = 0 MVI A, AAH  A = 10101010

RLC  A = (11100000)2 CY = 0, A = (E0)H Now ORI FFH  A = 11111111

CY = 0 so control again goes to BACK Now NOP RRC  A = 11111111  C=1
will be executed 3rd time again RRC  A = 11111111  C=1
ADDB  A = (F0)H = (11110000)2 CY = 0 CMC  C = 0
RLC  A = 11100001, CY = 1 INR A
Now JNC  is not satisfied as CY = 1 A = 00000000
so loop will be terminated F = 01010101
so NOP is executed 3 times. PSW = 01010101  54H
Hence, the correct option is (b). Hence, the correct option is (c).

48. For which one of the following, the instruction 50. The opcode for the instruction "Add Immediately
XRA A in 8085 microprocessor can be used?[ESE- to Accumulator with carry" in 8085 microprocessor
2009] is
(a) Set the carry flag [ESE-2010]
(b) Set the zero flag (a) ADI (b) ACI
(c) Reset the carry flag and clear the (c) ADC (d) ADD
accumulator
Sol. ()
(d) Transfer FFH to the accumulator
Hence, the correct option is ().
Sol. (c)
AA=0 51. The content of the programme counter of an 8085
It will clear the accumulator content and CY and microprocessor is [ESE-2010]
AC are reset. (a) the total number of instructions in the
Hence, the correct option is (c). program already executed.
(b) the total number of times a subroutine is
49. MVI A, AAH called.
ORI FFH (c) the memory address of the instruction that is
being currently executed.
RRC
(d) the memory address of the instruction that is
RRC
to be executed next.
CMC

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 Instruction Sets and Data
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Sol. (d) S Z AC P CY
PC contains the address of instruction to be 0 0 0 1 0
executed next. PSW = AF = 2704H
Hence, the correct option is (d). (iv) PUSH PSW
(v) POP H H = 00100111 = 27H
52. Assertion (A) : The port address in IN/OUT (vi) MOV A, L A = 00000100 = 04H
instruction is 8 bit.
(vii) ORI 10H A = 00010100 = 14H
Reason (R) : The address byte is duplicated in
PSW = AF = 1404H
machine cycle for IN/OUT instruction. [ESE-2010]
after execution of (iv) line
(a) Both A and R are true and R is the correct
explanation of A 7FFCH
(b) Both A and R are true but R is not the correct
explanation of A
(c) A is true but R is false
7FFDH 04H
(d) A is false but R is true
Sol. () 7FFFH 27H
Hence, the correct option is ().
7FFFH

53. LXI SP, 7FFFH Fig. Stack

MVI A, 25H Hence, the correct option is (b).
XRI 02H
PUSH PSW 54. If the status of the control lines S1 and S0 is LOW,
POP H then 8085 microprocessor is performing
MOV A, L [ESE-2011]
ORI 10H (a) Reset operation
HLT (b) HOLD operation
What are the contents of A, H, L, SP and PSW (c) Halt operation
registers after executing the above set of (d) Interrupt acknowledge
instructions? Assume undefined flags always Sol. (c)
remain cleared. [ESE-2010]
S1 = 0
(a) 10H, 25H, 00H, 7FFFH, 00H respectively
S0 = 0 {Corresponds to Halt operation
(b) 14H, 27H, 04H, 7FFFH, 04H respectively
Hence, the correct option is (c).
(c) 14H, 25H, 00H, 7FFFH, 04H respectively
(d) 10H, 27H, 04H, 7FFFH, 00H respectively
55. The description of a program counter (PC) in 8085
Sol. (b) microprocessor is [ESE-2011]
(i) LXI SP,7FFFH (a) An up/down counter
(ii) MVI A, 25H  A = 25H = 00100101 (b) An 8-bit register
(iii) XRI 02H  A = 00100111

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 Microprocessors

(c) Initialized automatically by microprocessor Reason (R) : PUSH and POP instructions are used
(d) Used to point to stack memory area to send or retrieve the data from the STACK.
Sol. (c) (a) Both A and R are true and R is the correct
explanation of A
Program counter points the next memory address to
be fetched and initialized automatically by (b) Both A and R are true but R is not the correct
microprocessor and is 16-bit register. explanation of A
Hence, the correct option is (c). (c) A is true but R is false
(d) A is false but R is true
56. While a program is being executed in an Intel 8085 Sol. (b)
microprocessor, the program counter of the Stack is used to temporarily store the data. PUSH
microprocessor contains: [ESE-2011] and POP instructions are used to send or retrieve
(a) The memory address of the instruction that is the data from stack. So A & R, both are correct but
being currently executed. R is not the reason for A.
(b) The memory address of the instruction that is Hence, the correct option is (b).
to be executed next.
(c) The number of instructions that have already 59. The instruction that exchanges top of stack with
been executed. HL, pair is
(d) The total number of instructions in the [ESE-2012]
current program still to be executed. (a) XTHL (b) SPHL
Sol. (b) (c) PUSHH (d) POSH
PC contains address of next instruction that is to be Sol. (a)
executed. The instruction XTHL exchange H and L with top
Hence, the correct option is (b). of stack. The contents of the L are exchanged with
the stack location pointed out by the contents of the
stack pointer register are exchanged with the next
57. In 8085 microprocessor, during PUSH/PSW
stack location (SP + 1); however, the contents of
operation, stack pointer is [ESE-2011]
the stack pointer register are not altered.
(a) Decremented by one
Hence, the correct option is (a).
(b) Decremented by two
(c) Incremented by one
60. The following instruction copies a byte of data
(d) Incremented by two
from the accumulator into the memory address
Sol. (b) given in the instruction [ESE-2012]
PUSH PSW, during PUSH SP is always (a) STA address (b) LDAX B
decremented by two.
(c) LHLD address (d) LDA address
Hence, the correct option is (b).
Sol. (a)
STA : (store accumulator direct) in this instruction
58. Assertion (A) : STACK is used to temporarily store the contents of the accumulator are copied to a
the data in a RAM locations specified by the memory location specified by the operand.
programmer in main program. [ESE-2011]
Hence, the correct option is (a).

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 Instruction Sets and Data
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(c) Only the upper nibble is reset to zero
61. The instruction PCHL, in 8085 is used for (d) Only the lower nibble is reset to zero
[ESE-2012] Sol. (a)
(a) Load PC with contents of HL. Data in accumulator 00H
(b) Load HL with contents of memory location EX-OR 0000 0000  00
pointed by PC. 1111 0000  F0
(c) Load HL with contents of PC. 1111 0000 Store in accumulator
(d) Load PC with the contents of memory i.e. only upper nibble of accumulator is
location pointed by HL pair. complemented.
Sol. (a) Hence, the correct option is (a).
PCHL : (load program counter with HL contents)
the contents of registers H and L are copied into the
64. A software delay subroutine is written as given
program counter. The contents of H are placed as a
below :
high-order byte and of L as a low order byte.
DELAY: MVI H, 255D
Hence, the correct option is (a).
MVI L, 255 D
LOOP: DCR L
62. The 8085 programming manual says that it takes
seven T states to fetch and execute the MOV JNZ LOOP
instruction. If the system clock has a frequency of DCR H
2.5 MHz, how long is an instruction cycle? JNZ LOOP
[ESE-2013] How many times DCR instruction will be
(a) 2.8 s (b) 2.5 ns executed?
(c) 2.8 ns (d) 2.8 s [ESE-2013]
Sol. (d) (a) 255 (b) 510

Time taken to execute each T state (c) 65025 (d) 65279

Sol. (d)
DCR instructions executed
(255  255) + 254 = 65279 times
 Time taken to execute 7 T-states
Hence, the correct option is (d).

65. The content of accumulator are 70H. Initially all

Hence, the correct option is (d). flags are zero. What will be values of CY and S
after executing instruction RLC?
63. What is content of accumulator of 8085 P after [ESE-2013]
the execution of XRI FO H instruction?[ESE-2013] (a) CY = 0 and S = 0
(a) Only the upper nibble of accumulator is (b) CY = 1 and S = 1
complemented (c) CY = 1 and S = 0
(b) Only the lower nibble is complemented (d) CY = 0 and S = 1

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 Microprocessors

Sol. (d) 68. Find the content of the accumulator after the
RLC  rotate left without carry execution of the following program: [ESE-2013]
MVI A, FOH
ORI FFH
XRI FOH
(a) 00H (b) F0H
(c) 0FH (d) FFH
As per RLC instruction only 'CY' is affected and Sol. (c)
remaining unchanged.
Hence, the correct option is (d).

66. The difference between 8085 instructions RST n

and PCHL is [ESE-2013]
(a) RST n is equivalent to a sub-routine call
Hence the content of accumulator will be 0FH.
while PCHL is equivalent to unconditional
branch. Hence, the correct option is (c).
(b) RST n uses direct addressing while PCHL
uses register indirect addressing. 69. It is desired to multiply the numbers 0AH by 0BH
(c) RST n is a software interrupt while PCHL and store the result in the accumulator. The
simulates a hardware interrupt. numbers are available in registers B and C
respectively. A part of the 8085 program for this
(d) RST n resets the processor while PCHL
purpose is given below:
restarts the processor.
MVI A, 00H
Sol. ()
Loop;
Hence, the correct option is ().
HLT END
The sequence of instruction to complete the
67. The following program starts at location 0100H
program would be [ESE-2013]
LXI SP, OOFFH
(a) JNZ LOOP; ADD B, DCR C
LXI H, 0107H
(b) ADD B; JNZ LOOP; DCR C
MVI A, 20H
(c) DCR C; JNZ LOOP; ADD B
SUB M
(d) ADD B; DCR C; JNZ LOOP
The content of accumulator when the program
Sol. ()
counter reaches 0107H is [ESE-2013]
Hence, the correct option is ().
(a) 20H (b) 02H
(c) 00H (d) FFH
70. Assume that the accumulator and the register C of
Sol. ()
8085 microprocessor contain respectively F0H and
Hence, the correct option is ().
0FH initially. What will be the content of
accumulator after execution of instruction ADDC ?
[ESE-2013]

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 Instruction Sets and Data
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(a) 00H (b) FFH 3. STA (Store accumulator direct) is a 3 byte
(c) EFH (d) FEH instruction.
Sol. (b) Hence, the correct option is (d).

73. In 8085 microprocessor, which mode of addressing

does the instruction CMP Muse? [ESE-2014]

Hence, the correct option is (b). (a) Direct addressing

(b) Register addressing

71. Statement (I): Program counter is a register that (c) Indirect addressing
contains the address of the next instruction to be (d) Immediate addressing
executed. Sol. (c)
Statement (II): IR (Instruction Register) is not CMP M (compare memory with accumulator) The
accessible to programmer. [ESE-2013] addressing mode is 'register indirect'.
(a) Both Statement (I) and Statement (II) are Hence, the correct option is (c).
individually true and Statement (II) is the
correct explanation of Statement (I).
74. Which of the following 8085 instruction will
(b) Both Statement (I) and Statement (II) are require maximum T-states for execution? [ESE-
individually true but Statement (II) is not the 2014]
correct explanation of Statement (I).
(a) XRI byte (b) STA address
(c) Statement (I) is true but Statement (II) is
(c) CALL address (d) JMP address
false.
Sol. (c)
(d) Statement (I) is false but Statement (II) is
true. CALL address

Sol. () T-states are 18, so this require the maximum T-

states for execution among the given instructions.
Hence, the correct option is ().
Hence, the correct option is (c).

72. With reference to 8085 microprocessor, which of

the following statements are correct? [ESE-2014] 75. How many machine cycles are required by STA
instruction? [ESE-2014]
1. INR is 1 byte instruction
(a) 2 (b) 3
2. OUT is 2 byte instruction
(c) 4 (d) 5
3. STA is 3 byte instruction
Sol. (c)
(a) 1 and 2 only (b) 2 and 3 only
STA Addr (Store Accumulator direct)
(c) 1 and 3 only (d) 1, 2 and 3
The number of machine cycles required are 4.
Sol. (d)
Hence, the correct option is (c).
1. INR (Increment register content) is a 1 byte
instruction.
2. OUT (Output from accumulator to I/O port) 76. Which of the following instructions is closest
is a 2 byte instruction. match to the instruction POP PC?
[ESE-2014]

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(a) RET (b) PCHL 78. Which of the following data transfer is not possible
(c) POP PSW (d) DAD SP in microprocessor? [ESE-2014]
Sol. (a) (a) Memory to accumulator
POP (pop the content of register pair, which was (b) Accumulator to memory
saved, from the stack). (c) Memory to memory
 The content of the register pair, which was (d) I/O device to accumulator
saved earlier is moved from the stack to the Sol. (c)
register pair. In a microprocessor system or in a computer data
RET instruction is used at the end of a subroutine. transfer takes place between two devices such as
Before the execution of a subroutine the address of microprocessor and memory, micro processor and
the next instruction of the main program is saved I/O devices, and memory and I/O device. But
address from the stack to the program counter. The where as data transfer between memory to memory
content of the stack pointer is incremented by 2 to is not possible in microprocessor.
indicate the new stack top. Then the program jumps Hence, the correct option is (c).
to the instruction of the main program next to
CALL instruction which called the subroutine.
79. Statement (I) : Branch instructions in a
Hence, the correct option is (a).
microprocessor are used to change the sequence of
program.
77. LOADER is a program that [ESE-2014] Statement (II) : All logical instructions are branch
(a) loads the memories and generates a hex file instructions. [ESE-2014]
(b) loads the hex file and coverts to the Codes :
executable file (a) Both Statement (I) and Statement (II) are
(c) loads the COM file and generates the binary individually true and Statement (II) is the
code correct explanation of Statement (I).
(d) loads english like command and generates (b) Both Statement (I) and Statement (II) are
the binary code individually true but Statement (II) is not the
Sol. (b) correct explanation of Statement (I).
A LOADER is a program which loads object code (c) Statement (I) is true but Statement (II) is
into system memory. It can accept programs in false.
absolute or re-locatable format. If the actual (d) Statement (I) is false but Statement (II) is
address of instructions and data are given by the true.
programmer, i.e. the program is in the absolute Sol. ()
format, the loader simply loads the program into
Hence, the correct option is ().
memory. If programs are in relocatable format the
specific memory addresses are assigned by the
locator before the loader loads the program in to 80. When a program is being executed in an 8085
memory. microprocessor, its program counter contains
Hence, the correct option is (b). [ESE-2015]
(a) the memory address as the instruction that is
to be executed next.

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 Instruction Sets and Data
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(b) the memory address of the instruction that is 84. What will be the contents of DE and HL register
being currently matched. pairs respectively after the execution of the
(c) the total number of instructions in the following instructions? [ESE-2015]
program being executed. LXIH, 2500H
(d) the number of instructions in the current LXID, 0200H
program that have already been executed. DADD
Sol. () XCHG
Hence, the correct option is (). (a) 0200H, 2500H (b) 0200H, 2700H
(c) 2500H, 0200H (d) 2700H, 0200H
81. A 'DAD H' instruction is the same as shifting each Sol. (d)
bit by one position to the [ESE-2015]
LXIH, 2500H : Store 2500H in HL pair
(a) left
LXID, 0200H : Store 0200H in DE pair
(b) right
DADD : DE + HL  HL
(c) left with a zero inserted in LSB position
So, HL pair contain 2700H
(d) right with a zero inserted in LSB position
XCHG : Exchange content HL pair and DE pair,
Sol. () thus HL pair will contain 0200H and DE pair will
Hence, the correct option is (). contain 2700H.
Hence, the correct option is (d).
82. Which one of the following statement is correct
about 8086 ? [ESE-2015] 85. Direction flag is used with [ESE-2015]
(a) It is 46 PIN IC and uses 5 V dc supply (a) String instructions
(b) It uses 20 lines for data bus (b) Stack instructions
(c) It multiplexes status signals with address bus (c) Arithmetic instructions
(d) It is manufactured using CMOS technology (d) Branch instructions
Sol. (c) Sol. ()
Status signals S3, S4, S5 and S6 are multiplexed with Hence, the correct option is ().
A16, A17, A18, A19 respectively.
Hence, the correct option is (c).
86. XCHG instruction of 8085 exchanges the content
of
83. In 8085 microprocessor, the address for 'TRAP' [ESE-2015]
interrupt is [ESE-2015]
(a) top of stack with contents of register pair
(a) 0024H (b) 002CH
(b) CB and DE register pairs
(c) 0034H (d) 003CH
(c) HL and DE register pairs
Sol. ()
(d) None of the above
Hence, the correct option is ().
Sol. ()
Hence, the correct option is ().

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87. Among the given instructions, the one which (a) 1 and 2 only (b) 1, 2, 3 and 4
affects maximum number of flags is (c) 5 only (d) 1 only
[ESE-2015]
Sol. (d)
(a) RAL (b) POP PSW
INTR is non-vectored so no specific location.
(c) XRA A (d) DCR A
Hence, the correct option is (d).
Sol. (c)
RAL : affects only carry flag
90. The instruction JNC 16-bit refers to jump to 16 -bit
POP PSW : affects no flag address if [ESE-2016]
XRA A : affects all flag (a) Sign flag is set (b) CY flag is reset
DCR A : affects all except carry flag (c) Zero flag is set (d) Parity flag is reset
Hence, the correct option is (c). Sol. (b)
JNC 16 bit address
88. Consider the following statements: Jump if no carry / if CY = 0 i.e., reset.
1. Auxiliary carry flag is used only by the DAA Hence, the correct option is (b).
and DAS instruction.
2. Zero flag is set to 1 if the two operands
91. Which one of the following statements is correct
compared are equal.
regarding the instruction CMP A? [ESE-2016]
3. All conditional jumps are long type jumps.
(a) Compare accumulator with register A
Which of the above statements are correct?
(b) Compare accumulator with memory
[ESE-2016]
(c) Compare accumulator with register H
(a) 1, 2 and 3 (b) 1 and 2 only
(d) This instruction does not exist
(c) 1 and 3 only (d) 2 and 3 only
Sol. (a)
Sol. (b)
CMP A  Compare accumulator with itself i.e.,
AC  Auxiliary carry flags status is used only in register 'A'.
DAA {DAS}
Hence, the correct option is (a).
Decimal adjust after additions {subtraction}
All conditional jumps are short jumps z = 1 if data
92. The instruction RET executes with the following
is same when compared.
series of machine cycle [ESE-2016]
Hence, the correct option is (b).
(a) Fetch, read, write
(b) Fetch, write, write
89. Consider the following interrupts for 8085
(c) Fetch, read, read
microprocessor:
(d) Fetch, read
1. INTR 2. RST 5.5
Sol. (c)
3. RST 6.5 4. RST 7.5
RET  Unconditional returns
5. TRAP
1 B instruction, 3 machine cycles (Fetch, Read,
If the interrupt is to be vectored to any memory
Read), 10 T-states.
location then which of the above interrupt is/are
correct? [ESE-2016] Read operations are from state memory.

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 Instruction Sets and Data
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Hence, the correct option is (c). (a) Fetch instruction, Read data, Decode
instruction, Store data and Execute
instruction
93. The contents of the accumulator and register C are
2EH and 6CH respectively. The instruction ADDC (b) Decode instruction, Read data, Execute
is used. The values of AC and P flags are instruction, Fetch Next instruction and Store
data
[ESE-2019]
(c) Decode instruction, Decode next operands,
(a) 0 and 0 (b) 1 and 1
Fetch Next instruction and Store data
(c) 0 and 1 (d) 1 and 0
(d) Fetch instruction, Decode instruction, Read
Sol. (b)
operands, Execute instruction and Store data
Content of accumulator = 2E Content of register C
Sol. (d)
= 6C
Basic steps of execution of an instruction.
After addition operation result is 9 A
Hence, the correct option is (d).
Binary equivalent of 9 A is (10011010)2

96. Which one of the following registers holds the data

on which the system has to operate, intermediate
 AC = 1 results and results of operations performed?

P=1 [ESE-2021]

Hence, the correct option is (b). (a) Program control register

(b) Accumulator register

94. Which of the following instructions of 8085 are the (c) Instruction register
examples of implied addressing? [ESE-2019] (d) Input/output register
1. CMA Sol. (b)
2. IN byte  Accumulator contains one of the operand in
3. RET most of the ALU operations and result is also
stored in accumulator.
(a) 1, 2 and 3 (b) 1 and 2 only
 Program Counter (PC) is a register in the
(c) 2 and 3 only (d) 1 and 3 only
processor which has the address of the next
Sol. (d)
instruction to be executed from memory.
CMA : Implicit/Implied as the instruction does not
 It is a digital counter needed for faster
have any operands and address of operand is in
execution of tasks as well as for tracking the
mnemonics itself.
current execution point.
RET: Indirect//mplied
 Instruction Register (IR) is a special purpose
Hence, the correct option is (d). register, which is used to receive the 8 -bit
opcode portion of an instruction. It is not
95. Which one of the following is the correct sequence accessible to the programmer.
of steps for executing an instruction during CPU's Hence, the correct option is (b).
processing? [ESE-2020]

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 Microprocessors

97. Which one of the following addressing mode leads 99. Which one of the following is NOT a general
to poor programming practice? [ESE-2021] operation of machine cycle in a central processing
(a) Direct addressing mode unit? [ESE-2021]
(b) Indirect addressing mode (a) Fetch (b) Decode
(c) Immediate addressing mode (c) Return (d) Store
(d) Implied addressing mode Sol. (c)
Sol. () Basic operations are Fetch, Read and Write/ Store.
return is an instruction used in a subroutine in order
Hence, the correct option is ().
to return to the main program.
Hence, the correct option is (c).
98. Which one of the following is not correct for the
AAA instruction in 8086 microprocessors?
[ESE-2021]
(a) It works only on the AL register.
(b) It updates AF and CF.
(c) It checks the result for correct unpacked
BCD.
(d) It updates all the flags.
Sol. (b)
ASCII adjust (accumulator) after addition is used to
convert result of addition of two unpacked BCD
digits to a valued two digit BCD number.
AL of AX is default register to hold operand.
Actually it adds 6 internally and converters the
result two valid BCD.

E is not BCD (0 to 9)
So add 6
6 = (20)10
(20)10 = (14)16
It affect carry flag and auxiliary carry flag. Hence it
checks AF and CF.
Hence, the correct option is (b).

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