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COA Syllabus Acad Coun Apprved

The document outlines the learning objectives and outcomes of the ECE302 Computer Organization and Architecture course. The key topics covered include the central processing unit, memory systems and I/O organization, operating system support, and computing system performance and architecture evolution. Specific areas of focus are the control unit, instruction sets, pipelining, parallel architectures, cache memories, virtual memory, and RISC vs. CISC architectures.

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Rohin Bommena
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0% found this document useful (0 votes)
81 views

COA Syllabus Acad Coun Apprved

The document outlines the learning objectives and outcomes of the ECE302 Computer Organization and Architecture course. The key topics covered include the central processing unit, memory systems and I/O organization, operating system support, and computing system performance and architecture evolution. Specific areas of focus are the control unit, instruction sets, pipelining, parallel architectures, cache memories, virtual memory, and RISC vs. CISC architectures.

Uploaded by

Rohin Bommena
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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ECE302-COMPUTER ORGANIZATION AND ARCHITECTURE Learning Objectives:

LTPC 3003

To demonstrate the application of discrete mathematics, Boolean algebra, and simple digital design to the field of computers and computer architecture. To describe the functioning of the control unit and look at the different implementations of the control unit (hardwired and micro programmed) Recognize and analyze the basics of hierarchical memory and virtual memory. To describe I/O system and its interconnection with CPU and memory. To expose the learners the different architectural and organizational design issues that can affect the performance of a computer such as Instruction Sets design, Pipelining, RISC architecture, and Superscalar architecture. Recognize and illustrate parallel architectures and interconnection networks Learning Outcomes The knowledge of how previous engineering science curricula have been applied in the field of computers and computer architecture. The ability to perform basic computer system component designs, defines an instruction set architecture and assembly language for the computer system, analyze the performance of the computer and identify a range of performance enhancements. An ability to engage in lifelong learning of the computing system performance and architecture evolution. A knowledge of contemporary issues related to the architecture, design, implementation and use of Computers. COMPUTING SYSTEMS- AN INTRODUCTION 3 Hr. Definitions - Organization and Architecture, Structure and Functional blocks, Bus Interconnection, designing for Performance, Structure of IAS computer CENTRAL PROCESSING UNIT 10 Hr

Register organization, Arithmetic and Logic Unit- numbering systems, Integer Representation, Integer Arithmetic Addition , 2s Complement subtraction, Multiplication and division, Floating point Representation and Arithmetic

Instruction set, Addressing modes, Data path implementation, Register Transfer Notation (RTN), Abstract RTN, and Concrete RTN, Control Unit - Hardwired control unit and Micro instruction, sequencing and execution. MEMORY SYSTEM & I/O ORGANIZATION 10 Hr

Semiconductor RAM memories-Internal organization of Memory Chips, SRAM , DRAM, Read-Only memories-ROM, PROM,EPROM,EEPROM ,Secondary storage- magnetic disk, optical memory . Cache Memories-Mapping Function-Direct, Set Associative, (Replacement algorithms), Performance consideration-Interleaving, Hit Rate and Miss Penalty. Virtual memory - Address translation, Paging and segmentation. I/O Organization4 Hr Interfacing I/O Devices with CPU- Programmed I/O, Interrupt driven I/O, DMA controlled I/O OPERATING SYSTEM SUPPORT 4 Hr Overview, Scheduling-FCFS, SJF, Priority, Mutual exclusion, Memory management COMPUTING SYSTEM PERFORMANCE AND ARCHITECTUREEVOLUTION: 10 Hr Von-Neumann vs. Harvard architectures, Instruction Cycle- Fetch, Decode, Execute Decode, Moores law, RISC -Instruction execution Characteristics, use of a large register file, compiler-based registers optimization, pipelining and Pipeline hazards, No. of Pipeline stage, Performance consideration .Instruction level parallelism-overview, Design issues, Super Scalar Processors, VLIW MULTIPROCESSORS 4 Hr Processor level parallelism-Dependency, Flynn taxonomy, Memory organization for Multiprocessors system, Symmetric Multiprocessor, Cache Coherence and The MESI Protocol Text Books: 1. Computer Organization and Architecture - William Stallings Sixth Edition, Pearson/PHI 2003 2. Computer Systems Architecture - M.Moris Mano, IIIrd Edition, Pearson/PHI 2003 Reference Books: 1. Computer Organization and Design-the hardware/software interface -David A. Patterson, John L. Hennessy, Third edition, Morgan Kaufmann Publishers,2009 Mode of evaluation: CAT- I & II, Quiz, Assignments, Term End Examination Proceedings of the Standing Committee of the Academic Council of VIT [7.8.2010]

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