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CA 06 Datapath

This document discusses the design of a RISC-V processor datapath. It describes building up a datapath incrementally, including logic for instruction fetch, R-type instructions, load/store instructions, and branch instructions. It also discusses issues with performance in the simple non-pipelined design and how pipelining can help improve performance.

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wlsh2001
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13 views

CA 06 Datapath

This document discusses the design of a RISC-V processor datapath. It describes building up a datapath incrementally, including logic for instruction fetch, R-type instructions, load/store instructions, and branch instructions. It also discusses issues with performance in the simple non-pipelined design and how pipelining can help improve performance.

Uploaded by

wlsh2001
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COMPUTER ORGANIZATION AND RISC-V

Edition
DESIGN Interface
The Hardware/Software

Week 6
The Processor Datapath
(Chapter 4)
§4.1 Introduction
Introduction
■ CPU performance factors
■ Instruction count
■ Determined by ISA and compiler
■ CPI and Cycle time
■ Determined by CPU hardware
■ We will examine two RISC-V implementations
■ A simplified version
■ A more realistic pipelined version
■ Simple subset, shows most aspects
■ Memory reference: ld, sd
■ Arithmetic/logical: add, sub, and, or
■ Control transfer: beq

Chapter 4 — The Processor — 2


§4.2 Logic Design Conventions
Logic Design Basics
■ Information encoded in binary
■ Low voltage = 0, High voltage = 1
■ One wire per bit
■ Multi-bit data encoded on multi-wire buses
■ Combinational element
■ Operate on data
■ Output is a function of input
■ State (sequential) elements
■ Store information

Chapter 4 — The Processor — 3


Combinational Elements
■ AND-gate ■ Adder A
Y
+
■ Y=A&B ■ Y=A+B B

A
Y
B

■ Arithmetic/Logic Unit
■ Multiplexer ■ Y = F(A, B)
■ Y = S ? I1 : I0
A
I0 M
u Y ALU Y
I1 x
B
S F

Chapter 4 — The Processor — 4


Sequential Elements
■ Register: stores data in a circuit
■ Uses a clock signal to determine when to
update the stored value
■ Edge-triggered: update when Clk changes
from 0 to 1

Clk
D Q
D

Clk
Q

Chapter 4 — The Processor — 5


Sequential Elements
■ Register with write control
■ Only updates on clock edge when write
control input is 1
■ Used when stored value is required later

Clk

D Q Write

Write D
Clk
Q

Chapter 4 — The Processor — 6


Clocking Methodology
■ Combinational logic transforms data during
clock cycles
■ Between clock edges
■ Input from state elements, output to state
element
■ Longest delay determines clock period

Chapter 4 — The Processor — 7


Instruction Execution
■ PC → instruction memory, fetch instruction
■ Register numbers → register file, read registers
■ Depending on instruction class
■ Use ALU to calculate
■ Arithmetic result
■ Memory address for load/store
■ Branch comparison
■ Access data memory for load/store
■ PC ← target address or PC + 4

Chapter 4 — The Processor — 8


CPU Overview

Chapter 4 — The Processor — 9


Multiplexers
■ Can’t just join
wires together
■ Use multiplexers

Chapter 4 — The Processor — 10


Control

Chapter 4 — The Processor — 11


§4.3 Building a Datapath
Building a Datapath
■ Datapath
■ Elements that process data and addresses
in the CPU
■ Registers, ALUs, mux’s, memories, …
■ We will build a RISC-V datapath
incrementally
■ Refining the overview design

Chapter 4 — The Processor — 12


Instruction Fetch

Increment by
4 for next
64-bit instruction
register

Chapter 4 — The Processor — 13


R-Format Instructions
■ Read two register operands
■ Perform arithmetic/logical operation
■ Write register result

Chapter 4 — The Processor — 14


Load/Store Instructions
■ Read register operands
■ Calculate address using 12-bit offset
■ Use ALU, but sign-extend offset
■ Load: Read memory and update register
■ Store: Write register value to memory

Chapter 4 — The Processor — 15


Branch Instructions
■ Read register operands
■ Compare operands
■ Use ALU, subtract and check Zero output
■ Calculate target address
■ Sign-extend displacement
■ Shift left 1 place (halfword displacement)
■ Add to PC value

Chapter 4 — The Processor — 16


Branch Instructions
Just
re-routes
wires

Sign-bit wire
replicated

Chapter 4 — The Processor — 17


R-Type/Load/Store Datapath

Chapter 4 — The Processor — 18


Full Datapath

Chapter 4 — The Processor — 19


§4.4 A Simple Implementation Scheme
ALU Control
■ ALU used for
■ Load/Store: F = add
■ Branch: F = subtract
■ R-type: F depends on opcode
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract

Chapter 4 — The Processor — 20


ALU Control
■ Assume 2-bit ALUOp derived from opcode
■ Combinational logic derives ALU control

ALU
opcode ALUOp Operation Opcode field ALU function control
ld 00 load register XXXXXXXXXXX add 0010
sd 00 store register XXXXXXXXXXX add 0010
beq 01 branch on equal XXXXXXXXXXX subtract 0110

R-type 10 add 100000 add 0010


subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001

Chapter 4 — The Processor — 21


Datapath With Control

Chapter 4 — The Processor — 22


R-Type Instruction

Chapter 4 — The Processor — 23


Load Instruction

Chapter 4 — The Processor — 24


BEQ Instruction

Chapter 4 — The Processor — 25


Performance Issues
■ Longest delay determines clock period
■ Critical path: load instruction
■ Instruction memory → register file → ALU →
data memory → register file
■ Not feasible to vary period for different
instructions
■ Violates design principle
■ Making the common case fast
■ We will improve performance by pipelining

Chapter 4 — The Processor — 26

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