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COA Lab Report3

The document describes implementing an arithmetic logic unit in Verilog HDL. It includes objectives, an introduction on ALUs and Verilog, and two lab tasks - writing code for basic logic operations and a 4-bit adder using half and full adders.

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mudasirhussainf22
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17 views

COA Lab Report3

The document describes implementing an arithmetic logic unit in Verilog HDL. It includes objectives, an introduction on ALUs and Verilog, and two lab tasks - writing code for basic logic operations and a 4-bit adder using half and full adders.

Uploaded by

mudasirhussainf22
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 6

NATIONAL UNIVERSITY OF

TECHNOLOGY
COMPUTER ENGINEERING DEPARTMENT

LAB # 03

Implementation of Arithmetic-Logic Unit (ALU)


Submitted By: Mudassir Hussain

NUTECH ID: F22604036

Submitted To: Pro. Abdul Qadeer Khan

Date of Submission: 19-03-2023


Table of Contents
Objectives...........................................................................................................................................................................3
Introduction........................................................................................................................................................................3
Lab Tasks:..........................................................................................................................................................................4
Lab Task 01:.......................................................................................................................................................................4
Code:.................................................................................................................................................................................. 4
Testbench..............................................................................................................................................................................
Lab Task 02:.......................................................................................................................................................................5
Code................................................................................................................................................................................... 5
TestBench:..........................................................................................................................................................................5

Conclusion...............................................................................................6
Objectives
 Provide hands-on experience in designing and implementing an ALU using Verilog HDL.
 Develop insights into digital logic circuits and proficiency in coding complex hardware components.
 Understand the core functionality of an ALU and design similar modules for various computational tasks.

Introduction
 Understanding digital logic circuits and their implementation is fundamental in computer engineering.
 The Arithmetic Logic Unit (ALU) is a key component of a processor, responsible for arithmetic and
logical operations.
 Verilog Hardware Description Language (HDL) is commonly used for describing electronic systems,
making it essential for hardware-level programming.
In this lab we are going to design an arithmetic logic unit in Verilog HDL. The AND and OR operations are
performed by Logical gates whereas addition or subtraction operations are selected by the binvert and carryin .
Lab Tasks:

Lab Task 01:


Write a Verilog code for the following design.

Code:

Testbench:
Lab Task 02:
Write Verilog code for 4bit Adder using (instantiating) Half and Full Adders and simulate the results using
test-bench, attach waveform screenshots of results showing for different instances.

Code

TestBench:
Conclusion:
The successful implementation of fundamental adder circuits establishes a robust groundwork for continued
advancement within the realm of digital design. Future endeavours may encompass the following:
 Complex Arithmetic Units: Expand knowledge by designing more intricate arithmetic logic
units (ALUs) capable of performing multiplication, division, and other advanced operations.
 Optimization Strategies: Investigate and apply diverse optimization techniques to enhance
the speed, power efficiency, and area utilization of digital designs.
 System-Level Integration: Incorporate adder circuits into broader system-on-chip (SoC)
architectures, exploring the intricacies of interfacing and communication between various
digital components.

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