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An Efficient Implementation of Combinational and Sequential

Circuits with Reversible Logic Gates Using Verilog HDL
Mr.Nalla Kiran Tej Mrs.G.Srujana
M.Tech Student, Assistant Professor,
Department of VLSI &ES, Department of VLSI &ES,
Godavari Institute of Engineering and Technology, Godavari Institute of Engineering and Technology,
Rajahmundry-533296, Andhra Pradesh, India. Rajahmundry-533296, Andhra Pradesh, India.

Abstract : This enables the system to run backwards and while do-
ing so, any intermediate design stage can be thoroughly
Reversible logic has presented itself as a prominent tech- examined. The fan-out of each block in the circuit has to
nology which plays an imperative role in Quantum Com- be one.This research paper focuses on implementation of
puting. Quantum computing devices theoretically operate at reversible logic circuits in which main aim is to optimize
ultrahigh speed and consume infinitesimally less pow-er. speed of the design. A Reversible adder is designed
Research done in this paper aims to utilize the idea of using basic reversible gates. Using this adder, an 8-bit
reversible logic to break the conventional speed-power trade-
revers-ible ripple-carry adder is devised and then
off, thereby getting a step closer to realise Quantum
compared with the conventional 8-bit adder in terms of
computing devices. To authenticate this research, various
speed, critical paths,hardware used.
combinational and sequential circuits are implemented such as
a 4-bit Ripple-carry Adder, (8-bit X 8-bit) Wallace Tree Then using the same reversible adder, a Wallace tree
Multiplier, and the Control Unit of GCD processor using mul-tiplier has been implemented, and compared with
Reversible gates. The power and speed parameters for the the conventional Wallace tree multiplier. With the
circuits have been indicated, and compared with their known fact that sequential circuits are the heart of digital
conventional non-reversible counterparts. We are ex-tending designing, the design for the control unit of a reversible
this project with 16-bit Ripple Carry Adder, 4-bit Shift GCD pro-cessor has been proposed using Reversible
registers (SISO and SIPO). The comparative statisti-cal study logic gates. The shift registers are the most exhaustively
proves that circuits employing Reversible logic thus are used func-tional devices in digital system design for
faster and power efficient. The designs presented in this multiple bits storing & shifting of the same if required.
paper were simulated using Xilinx 9.2 software. In this paper, we are presenting reversible realization of
two shift regis-ters naming Serial-in Serial-out and
Key Terms: Serial-in Parallel-out for their application.

Reversible logic, Quantum Computing, high speed, less II.REVERSIBLE LOGIC:

power, speed-power trade-off, Ripple carry adder, Wal-
lace tree multiplier, GCD processor, SISO,SIPO, non- Boolean logic is said to be reversible if the set of inputs
reversible counterparts. mapped have an equal number of outputs mapped i.e. they
have one-to-one correspondence. This is realized employ-
I. INTRODUCTION: ing reversible gates in the designs. Any circuit having only
reversible gates is capable of dissipating no power [2].
Reversible logic is widely used in low power VLSI. Re-
versible circuits are capable of back-computation and Goals of Reversible Logic:
reduction in dissipated power, as there is no loss of in-
formation [1]. Basic reversible gates are employed to A. Quantum Cost: Quantum cost of a circuit is the mea-
achieve the required functionality of a reversible circuit. sure of implementation cost of quantum circuits. More
The uniqueness of reversible logic is that, there is no precisely, quantum cost is defined as the number of
loss of information since there is one-to-one el-ementary quantum operations needed to realize a gate.
correspondence between inputs and outputs.

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A Peer Reviewed Open Access International Journal

B. Speed of Computation: The control bit here is A, depending on the value of A,

bits B and C are selected at outputs Q and R. When A=0,
The time delay of the circuits should be as low as pos- (Q=B, R=C) whereas when A=1, (Q=C, R=B). Its block
sible as there are numerous computations that have to be diagram is as shown in Fig.2.
done in a system involving a quantum processor; hence
speed of computation is a very important parameter
while examining such systems.

C. Garbage Outputs: Fig. 2: Fredkin Gate

Garbage outputs are those output signals which do not 3. Peres Gate:
contribute in driving further blocks in the design. These
outputs become redundant as they are not required for It is a basic reversible gate which has 3-inputs and 3-out-
computation at a later stage. The garbage outputs make puts having inputs (A, B, C) and the mapped outputs
the system slower; hence for better efficiency it is (P=A, Q=A^B, R=(A.B)^C). The block diagram is as
neces-sary to minimize the number of garbage outputs. shown in fig. 3:
D. Feedback:

Looping is strictly prohibited when designing reversible

circuits. Fig. 3: Peres Gate

E. Fan-out: 4. Toffoli Gate:

The output of a certain block in the design can only Toffoli gate is a universal reversible gate which has three
drive at most one block in the design. Hence it can be inputs (A, B, C) mapped to three outputs (P=A, Q=B, R=
said that the Fan-out is restricted to 1. (A.B)^C). The block diagram of Toffoli gate is shown in
III.REVERSIBLE GATES: fig. 4:

There are many reversible gates such as Feynman, Tof-

foli, TSG, Fredkin, Peres, etc [3]. As the universal gates
inboolean logic are Nand and Nor, for reversible logic, Fig. 4: Toffoli Gate
the universal gates are Feynman and Toffoli gates.
5.TSG Gate:
1.Feynman Gate:
TSG gate is a reversible gate which has four inputs (A,
Feynman gate is a universal gate which is used for signal
B, C, D) mapped to four outputs (P=A,Q=A^B,
copying purposes or to obtain the complement of the in-
R=A^B^D, S=(A^B)^D^AB^C). The block diagram of
put signal. The block diagram of Feynman gate is shown
TSG Gate is shown in fig. 5:
in fig.1:

Fig. 1: Feynman Gate

2.Fredkin Gate: Fig. 5: TSG Gate
It is a basic reversible 3- bit gate used for swapping last
two bits depending on the control bit.

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A Peer Reviewed Open Access International Journal

6. Proposed Modified Fredkin (MF) Gate: V.WALLACE TREE MULTIPLIER:

It is the proposed modified version of 3*3 Fredkin A Wallace treeis an efficient hardwired
gate with a quantum cost of 4 and a delay of 4∆. implementation of a digital circuit that multiplies
When A = 0, it does the same as Fredkin Gate, but twointegers [5]. The Wal-lace tree has three steps:
when A = 1, B and complement of C is swapped in the
output. Quantum rep-resentation of this gate is 1. Every bit of the multiplicand is multiplied (i.e. AND)
by every bit of multiplier, thus yielding n2 results (for n
X n multiplication). Depending on position of the
multiplied bits, the wires carry different weights, i.e.
weight of bit carrying result of a5b6 is 65.
2. The number of partial products is reduced to 2 by
layers of full and half adders.
Fig.6: MF gate and its Quantum representation 3. The wires are grouped in two numbers, and added us-
ing a conventional adder.
IV.REVERSIBLE 4- BIT FULL ADDER: The circuit diagram of Wallace tree multiplier using re-
versible gates is shown in fig. 9:
The gate used in implementing a reversible ripple-carry
fulladder is the TSG gate [4]. The TSG gate functions
like a full adder. A reversible ripple-carry adder is faster
than the non-reversible adder, since the computation of
carry in a reversible adder does not require the computa-
tion of previous stage carry (as indicated in the critical
paths). When previous stage carry is being forwarded in
the reversible adder, the computation of previous stage
carry and computation regarding sum is done simultane-
ously whereas in an irreversible adder the next stage
carry cannot start any computation till previous stage
Fig. 9: 8X8 reversible Wallace treeMultiplier
carry is fully generated. The critical paths of 4bit
reversible and irreversible ripple-carry adders are as
shown in fig.7and fig.8.
VI.DESIGN OF CONTROL UNIT FOR
GCD PROCESSOR:
To illustrate the classical and reversible approaches to
the Sequential Control Unit Design, reversible logic
isem-ployed for a special purpose processor that
computes the GCD of two numbers. This GCD
Fig. 7: Critical Path of 4-bit reversible adder processorincorporates standard Euclid’s Algorithm
involving Subtract-Com-pare-Swap operation of two
numbers. Thebasic principle is to subtract smaller of the
two numbers repeatedly from the other number until we
get the number that divides an-other [6].

A. Control Unit:

Control unit of GCD processor generates the control sig-

Fig. 8: Critical Path of 4 bit irreversible adder
nals to manipulate the operations in Data-path.

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A Peer Reviewed Open Access International Journal

Fig 12: RTL schematic Diagram of GCD Control Unit

Fig. 10: Block diagram of GCD Control Unit
VII. REVERSIBLE SHIFT REGISTER:
B.Block Diagram Description:
1)Flip-flop Module: Flip-flops are the basic memory element used for
storage of single bit data. To store more number of bits,
The control unit for GCD processor requires two Flip-flops as combi-nation of FF is used and called shift registers.
binary state encoding is used for FSM. In this design Loading of data may be serial or parallel. In serial loading,
reversible edge-triggered D Flip-flop is employed for data shifted from one FF to another in serial form, i.e. 1-bit
state transitions [7]. Two D-latches are connected in at a time, upon triggering clock. In parallel loading, all
Master-Slave mode to act as an edge-triggered D Flip- data-bits appear in parallel form at a time upon triggering
flop.Reversible D-latch is designed using Feynman clock. In this section, we have proposed Serial-in Serial-out
and Fredkin gates [8]. RTL schematic of reversible and Serial-in Parallelout shift registers. To design re-
D flip-flop obtained is shown in fig. 11: versible shift register for Pulse generation we are using
master-slave D-FF block diagram.

A. Reversible D-FF:

Characteristic equation of reversible D-Latch can be

writ-ten as Q+=D where output is equal to its input
value. The characteristic equation of clock enabled
Fig. 11: RTL schematic of Reversible D flip-flop reversible D-Latch (D-FF) can be written as

2) Regeneration Module:

To avoid multiple fan-out condition in the design, it is

necessary to duplicate signals used for computation
ofoutput and next state. The duplication of input signals Fig.13: Clock enabled D-latch and D-FF with output
is achieved using Feynman gates. Q and Qbar

3) Output Module: Fig.13 shows the clock enable D-latch (QC = 5)

where output Q+=D for E=1 and output Q+=Q for E=0
The computation of the outputs and Next-state signals is output remain in its previous state. For the input D=1
done using reversible Fredkin gates. The functioning and Q=0, the output of MF gate when E=1 is Q+=1
which is applied to FG gate to provide feedback.
ofoutput signals is driven by the algorithm.

C. Final RTL schematic: B.Proposed Reversible Serial-in Serial-out

(SISO) Shift Register:
The complete RTL schematic of GCD control unit is
Serial-in Serial-out shift register accepts data in serial
shown in fig. 12.
form and produces output serially.

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A Peer Reviewed Open Access International Journal

For N-bit shift register it takes n-1 clock pulse to store It takes n-1 clock pulse to store data in register and 1
data serially and n-clock pulse to generate output. The clock pulse to produce output. In the above
following fig.14 shows the reversible N-bit serial-in figuredata input is same as in SISO shift register and
seri-al-out shift register for edge triggering & pulse output appears as data, stored in shift register on a single
triggering applications. clock pulse. This pro-posed design is also optimized in
terms of quantum cost, delay and garbage outputs.

VIII. CONLUSION:

In this paper, it can be seen that the performance of digital

Fig.14:. Edge-triggered N-bit SISO registers using D- circuits can be enhanced using reversible gates and have
FF compared 8-bit ripple carry reversible adder with an ir-
reversible adder in terms of speed and power; thereby
When serial data is applied, each new bit is entered into first concluding that reversible designs are faster and poweref-
FF upon application of each clock pulse. The bit that ficient. Furthermore, this concept is extended to
was previously stored by first FF transferred to second combi-national circuits such as a Wallace tree multiplier
FF on application of second clock pulse and n-1 FF bit using reversible gates, which were simulated and respective
transferred to n–bit FF on application of n-1 clock pulse. re-sults validate prior inferences.
The bit that was stored by last FF, i.e. n-FF, is outputted
on the application of n clock pulse. The proposed design Then a reversible sequential control unit of a GCD pro-
of SISO is optimized in terms of Quantum cost, delay cessor was designed.we have demonstrated novel archi-
and garbage output. tecture of pulse triggered and edge triggered SISO & SIPO
registers and analyzed their quantum cost, delay and
C. Proposed Reversible Serial-in Parallel-out garbage outputs. Thus, all the designs implemented were
(SIPO) Shift Register: compared with their irreversible counterparts, and the speed
and power parameters for the reversible designs were
SIPO takes input data serially and the data stored in the observed to have improved significantly.
register produces output in parallel form. Data input ap-
pears on register bit-by-bit basis whereas when data is Reversible logic design finds applications in various
stored in register then all output appears in their respec- fields including Quantum computing, Nano-computing,
opti-cal computing, Quantum Computing Automata (QCA:
tive FF at a time.
study of mathematical objects called Abstract machines and
the computational problems that can be solved us-ing
them),Ultra - low power VLSI designing, Quantum dot
cellular etc. The future of computer chips is limited by
Moore’s law; hence an alternative is to build quan-tum
Fig.15. using D-FF chips. Our future research topic is designing a new
reversible gate and to implement reversible logic into a
complete Quantum processor capable of ultra-high speed
and infinitesimally low power computing.

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International Journal & Magazine of Engineering,
Technology, Management and Research
A Peer Reviewed Open Access International Journal

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