An Analysis on a Pseudo-Differential Dynamic Comparator

with Load Capacitance Calibration

Daehwa Paik, Masaya Miyahara, and Akira Matsuzawa
Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan
Email: [email protected]

Abstract dynamic amplifier will also be deduced for this analysis.

This paper analyzes a pseudo-differential dynamic com- 2. Comparator under Analysis

parator with a dynamic pre-amplifier. The transient gain
of a dynamic pre-amplifier is derived. This analysis en- A pseudo-differential dynamic comparator will be briefly
hances understanding of the roles of a transistor’s pa- analyzed in this section. Its schematic is described in
rameters in a pre-amplifier’s gain. Based on the calcu- figure 1. The comparator is comprised of two stages. The
lated gain, a load capacitance calibration method is ana- first stage is a dynamic amplifier, or a pre-amplifier,
lyzed. The analysis helps designers’ estimation for the which integrates differential input signals as time passes.
accuracy of the calibration and the influence of PVT The second stage actually performs the regeneration. In
variation. The analyzed comparator uses 90-nm CMOS this paper, the size of all transistors are designed as 2
technology as an example and each estimation is com- µm/100 nm.
pared with the simulation results. Before analyzing the comparator, we describe its
transient performance. As shown in figure 2, when
1. Introduction CLKLatch is low, M5 and M6 are on while M3 and M4 are
off. Then, parasitic capacitors on nodes Outp_int and
A comparator is the essential building block in an ADC Outn_int are charged up to supply voltage. The second
to convert an analog signal into a digital signal. To sup- stage is turned off, because M15 and M16 are off. After
press its power dissipation, recently published researches CLKLatch becomes high, M3 and M4 are on; while M5 and
have used dynamic comparators [1]-[3]. Since the cur- M6 are off. Accordingly, electric charge on the node
rent flows only when they are triggered, they are more Outp_int and Outn_int flows into gnd. Drain currents of M3
power efficient than comparators dissipating static cur- and M4 are determined by input signals of M1 and M2.
rent. However, this topology, an inverter chain, has defi- Differences of flowing electric charge per time at the
ciency, because, regeneration depends on the gain of an nodes Outp_int and Outn_int induces a voltage difference at
inverter—or the intrinsic gain of a transistor—, and as the nodes, and the voltage difference becomes larger as
process is scaled down, its accuracy will become worse. time passes. If voltages on the node Outp_int and Outn_int
To address this issue, a latch with a dynamic ampli-
fier, whose gain is approximately 5 times in 65-nm Vdd Vdd
process [4], is proposed by D. Schinkel, et al. in 2007 [5]. M15 M16
However, this requires two phase of latching clocks. In M13 M11 M12 M14
2008, We proposed a modified version of the double-tail
gnd gnd
latch comparator [6]. We removed the tail current of the Outn
Outp
second stage, which was triggered by inverse phase of a
latching clock, and generated a trigger signal by using
M9 M7 M8 M10
the outputs of a pre-amplifier. This modification can gnd gnd
suppress the influence of skew between two phases of CLKLatch
latching clocks in [6]. However, both comparators suffer Vdd
M5 M6
Vdd

kick-back noise. To suppress the kick-back noise, in Outp_int Outn_int

2010, pseudo-differential topology was introduced [7]. M3 M4
Those comparators with calibration circuits should
be analyzed for their characteristics and optimizations. DB[0:NCal – 1] M1 M2 D[0:NCal – 1]
Inp Inn
Thermal noise [4], [8]-[12] and mismatch [13] analysis
gnd gnd
methods about a dynamic comparator were already re-
ported. In this paper, a load capacitance calibration Figure 1. A pseudo-differential dynamic comparator
method [2], [3] for a pseudo-differential dynamic com-
parator will be analyzed in 90-nm process. The gain of a with load capacitance calibration
 Outp_int Outn_int Outp Outn
1.2
1.0
1st
0.8 stage
Voltage [V]

0.6
CLKLatch 2nd
0.4 becomes high stage

0.2
0
– 0.2
0 50 100 150 200
Time [ps]

Figure 2. Transient waveform of a comparator (a) various Veff

drop sufficiently, then the second stage regenerates the a. (W/L)input = 6 m/300 nm

voltage difference between node Outp_int and Outn_int. b. (W/L)input = 2.4 m/120 nm
c. (W/L)input = 2 m/100 nm
To simplify the analysis, we set the rising time of 6
CLKLatch to 1 ps as the simulation condition and M3 and 5
Simulation results a
b
Estimation
M4 are in the deep triode region when CLKLatch is high. Estimation ( = 0)
c
4
When M3 (or M4) is in the deep saturation region, Vout_int
3
which is voltage of node Outint can be approximated as
the drain voltage of M1 (or M2). 2
1
2.1 Gain of a Dynamic Amplifier 0
0 0.1 0.2 0.3 0.4 0.5 0.6
A pre-amplifier increases the difference between the dif- Vdd – VDS [V]
ferential input signals. To figure out its gain, Gamp, let us
simplify the first stage of a dynamic comparator when (b) various channel length when Veff is 0.2 V
CLKLatch is high as depicted in figure 3. The output of a Figure 3. Gain of a pre-amplifier
pre-amplifier is described as below;
I current due to gm, iDS1, are expressed as below;
Vout_int = Vdd − DS t (1)
Veff (1 + λ(V DS − V DS_sat ))
C W
g m = µC OX (6)
where IDS is the drain current of the input transistors, C is L
the total load capacitance on its output node, and t is the iDS1 = g mv in (7)
integration time. IDS with channel-length modulation is where vin is an input signal. From the equation (2), small
expressed as below; signal output conductance, gDS, and a signal current due
1
I DS = µC OX
2
W 2
L
(
V eff 1 + λ V DS − V DS_sat (2) ( )) to gDS, iDS2, are expressed as below;
1 W
g DS = µC OX Veff2 λ (8)
Veff ≡ VGS − Vth (3) 2 L
where VDS_sat is the saturation condition of drain-source i DS2 = g DSv out (9)
voltage, which equals Veff, and λ indicates the chan- where vout is an output signal integrated on a load ca-
nel-length modulation coefficient. When Vout_int is de- pacitor. Substituting equations (4) and (5) into equation
creased from Vdd to VDS, average drain current, I DS , is (1), then an output differential signal, vout_diff, of a
expressed as below; pre-amplifier is deduced;
1 Vdd
v out_diff ≡ Voutp_int (t ) − Voutn_int (t )
I DS = ∫ I DSdVDS
Vdd − VDS VDS 2(Vdd − VDS ) (10)
=− v in_diff
1 W ⎛ λ ⎞ Veff
= µCOX Veff2 × ⎜1 + (Vdd + VDS − 2Veff )⎟
2 L ⎝ 2 ⎠ where vin_diff is an input differential signal, 2vin. Substi-
(4) tuting equation (10) into equation (9), then
Substituting equation (4) into equation (1), then the inte- 2(Vdd − VDS )
i DS2 = − g DS v in . (11)
gration time can be represented as; Veff
(V − VDS )C As shown in equation (11), the signal current due to gDS
t = dd . (5)
I DS has the opposite sign of vin and attenuates an integrated
From equation (2), transconductance, gm, and a signal output signal by gm. iDS2 becomes larger as the integrated
output signal increases—or Vout_int decreases from Vdd.
 (a) before calibration (b) after calibration
Figure 4. Error reduction by calibration Figure 5. Input-referred compensated voltage
When the total signal current, iDS, is a sum of iDS1 and by the capacitance calibration
iDS2, then the average total signal current is (Vdd = 1.0 V, Vin_com = 0.5 V, calibration resolution is 6 bits,
1 t 1 VDS
iDS = ∫0 iDSdt = ∫ iDSdVDS and unit PMOS capacitor size is W/L = 600 nm/100 nm)
t VDS − Vdd Vdd
W
= µCOX Veff (1 + λ(VDS − Veff )) × v in (12) where Con and Coff are the capacitances of a unit-sized
L
= g m (Vout_int =VDS )v in varactor which is turned on and off, respectively, NCode is
the calibration code, Ncal is the calibration resolution, and
From equations (1) and (12), transient gain, Gamp_trans, is vin_diff_cal is the input-referred compensated voltage in
expressed as below; differential. Figure 5 compares equation (15) with the
v i t simulation results.
Gamp_trans = out = − DS
v in Cv in
2(Vdd − VDS ) 1 + λ(VDS − Veff ) (13) 3.2 PVT Variation
=− × . PVT variation degrades compensation accuracy. Influ-
Veff λ
1 + (Vdd + VDS − 2Veff ) ence of the process is fixed in the factory and this
2 doesn’t affect the offset after calibration. Only voltage
Equation (13) is compared with simulation results in fluctuation and temperature change are considered. From
figure 3. Equation (2) is satisfied only when Vout_int is equation (13), Gamp_tran is decided by a ratio of Vdd to Veff
larger than Veff. If Vout_int falls to Veff, Gamp_trans reaches its and λ. If temperature is changed, then Vth and λ are var-
maximum. ied. Influence of voltage fluctuation is easy to under-
stand. From equation (15), input-referred compensated
3. Load Capacitance Calibration voltages also change and the variation differs in each
calibration code. If error due to PVT variation, σV_PVT, is
The load capacitance calibration [2], [3] changes the uncorrelated with offset after calibration, σV_offset0, then
load capacitance where a signal is integrated as depicted total offset voltage, σV_offset, can be expressed as
in the figure 1. From equation (1), the slew rate, IDS/C, is
inversely proportional to the load capacitance. When the σ 2V_offset = σ 2V_offset0 + σ 2V_PVT . (16)
calibration is conducted, these slew rates become closer From equation (15), when standard deviation of calibra-
together and the offset voltage is compensated as de- tion code is σCode, σV_PVT due to input common-mode
scribed in figure 4. voltage, σV_PVT_Vcom, is deduced as below;
V ⎛ λ ⎞
3.1 Input-Referred Compensated Voltage σ V _ PVT _ VCOM = eff ⎜1 + (Vdd − Veff )⎟
C ⎝ 2 ⎠
Based on equation (1), let us estimate the input-referred
1
compensated voltage of the capacitance calibration. First, ⎛ ⎛ ∆V ⎞ ⎞⎟
2 2
differentiate equation (1) with respect to capacitance; ⎜ ⎜ eff − λ∆Veff
⎟
⎜⎜ V 2 + λ(Vdd − Veff ) ⎟⎠ ⎟
dVout_int Vdd − VDS
= . (14) × ⎜ ⎝ eff ⎟ (Con − Coff )σ Code .
⎛ (Vdd − Veff )∆λ ⎞
2
dC C ⎜ ⎟
⎜ + ⎜⎜ ⎟⎟ ⎟
⎝ 2 + λ(Vdd − Veff ) ⎠
Assuming an input signal of the second stage is decided
when gain reaches its maximum, input-referred variation ⎝ ⎠
is deduced as below; (17)
Influences of supply voltage and temperature can be de-
V ⎛ λ ⎞
v in_diff_cal = − eff ⎜1 + (Vdd − Veff )⎟ duced by the same way. Figure 6 compares the estima-
C ⎝ 2 ⎠ (15) tion with the simulation results. Calibration is conducted
( )
× N Code − 2 Ncal −1 × (Con − Coff ) when Vdd is 1.0 V, Vin_com is 0.5 V, and T is 27 °C. Figure
 4. Summary

This work analyzed a pseudo-differential dynamic com-

parator with load capacitance calibration. The analyzed
comparator uses 90-nm CMOS process as an example.
The gain of a dynamic amplifier was expressed by a ratio
of Vdd to Veff and λ of an input transistor. Based on the
deduced gain, input-referred compensate voltage and
influence of PVT variation are analyzed and compared
with the simulation results.

(a) input common-mode voltage Acknowledgments

This work was partially supported by MIC, CREST in

JST, NEDO, Berkeley Design Automation for the use of
the Analog FastSPICE(AFS) Platform, and VDEC in
collaboration with Cadence Design Systems, Inc.

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