A multiplexer is a combinational circuit that has 2" input lines and a single output line. Simply, the multiplexer is a multi-input and single-output combinational circuit. The binary information is received from the input lines and directed to the output line. On the basis of the values of the selection lines, one of these data inputs will be connected to the output. Unlike encoder and decoder, there are n selection lines and 2" input lines. So, there is a total of 2‘ possible combinations of inputs. A multiplexer is also treated as Mux. There are various types of the multiplexer which are as follows:2x1 Multiplexer: In 2x1 multiplexer, there are only two inputs, ie, Ag and A; | selection line, ie. So and single outputs, ie. Y. On the basis of the combination of inputs which are present at the selection line S°, one of these 2 inputs will be connected to the output. The block diagram and the truth table of the 2x1 multiplexer are given below. Block Diagram:Select (S) Truth Table:[as [oe Pe The logical expression of the term Y is as follows: Y=SqAgtSoA Logical circuit of the above expression is given below:Logical circuit of the above expression is given below: Ae Y=Ao 5+A; S Ai Select input S 4x1 Multiplexer:In the 4x1 multiplexer, there is a total of four inputs, ie. Ao, Ay Az, and A3, 2 selection lines, ie, So and S, and single output, ie, Y. On the basis of the combination of inputs that are present at the selection lines S° and S; one of these 4 inputs are connected to the output. The block diagram and the truth table of the 4x1 multiplexer are given below. Block Diagram:INPUTS The logical expression of the term Y is as follows:Y=S; So AgtS So Ay Sy So A7S, So Ag Logical circuit of the above expression is given below:8 to | Multiplexer ADVERTISEMENT In the 8 to 1 multiplexer, there are total eight inputs, ie, Ao: Ap Az, Ag, Ag As, Ag, and Az. 3 selection lines, ie, So. Sjand S> and single output, ie, Y. On the basis of the combination of inputs that are present at the selection lines $°, s! and Sz, one of these 8 inputs are connected to the output. The block diagram and the truth table of the 8x1 multiplexer are given below. Block Diagram:Enable E S$; So SoTruth Table: ADVERTISEMENT INPUTSThe logical expression of the term Y is as follows: ADVERTISEMENT Y=Sq'Sy.Sp-AgtSgSyS7-Ay*Sp SS7-A7*SpS,S7-Az*S Sy So Ag*SpS)S2 As+So.S,S7 Ag*SyS,S3A78 xX! multiplexer using 4x! and 2x1 multiplexerWe can implement the 8X1 multiplexer using a lower order multiplexer. To implement the 8x1 multiplexer, we need two 4x1 multiplexers and one 2%! multiplexer. The 4x1 multiplexer has 2 selection lines, 4 inputs, and 1 output. The 2%1 multiplexer has only 1 selection line. For getting 8 data inputs, we need two 4x1 multiplexers. The 4x1 multiplexer produces one output. So, in order to get the final output, we need a 2*1 multiplexer. The block diagram of 8x1 multiplexer using 4*1 and 2*1 multiplexer is given below.0 For getting 8 data inputs, we need two 4x1 multiplexers The 4x1 multiplexer produces one output. So. in order te get the final output, we need a 2x1 multiplexer. The block diagram of 8*1 multiplexer using 4*1 and 2x! multiplexer is given below.16 to { Multiplexer In the 16 to { multiplexer, there are total of 16 inputs, ie. Ag. Ay. .- Aig 4 Selection lines. ie, So, S, Sz, and S3 and single output, ie, Y. On the basis of the combination of inputs that are present at the selection lines s°, s! and S), one of these 16 inputs will be connected to the output. The block diagram and the truth table of the 16x1 Block Diagram: 16x1 Multiplexer PPPPPP >rpr>IPUUN radic,The logical expression of the term Y is as follows: Y=Ao.S'.81'.S9'.S3'+Ay.Sq'-S4'.S2 "Sg+Ap.S9'.$1'.S2.$3'tAg.S0'-S1 ' So.83+Ag.So'.S4.S2'.S3'+As.So '.$1.S9'.S3+Ag.S7.S2.S3'+A7-So ' $1.S.53+Ag.So.81'.S2'.S3'tAg So.$1'-82'.S3+¥10.Sp.$1'.S2-53 '+A41.S9.S1'.S2.53+A12 So.S1.S2 '$3'+Aq3.S9.51.S9'.93+A14.S9.S1 So.S3'tA15.89.51-52'-53Logical circuit of the above expression is given below: Sy Si Sx) 83