SANFOUNDRY QUESTIONS AND ANSWERS:

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SANFOUNDRY: COMBINATION LOGIC

. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

a) a
b) b
c) c
d) d
View Answer

Answer: d
Explanation: SOP means Sum Of Products form which represents the sum of product terms having
variables in complemented as well as in uncomplemented form. Here, the diagram of d contains the OR
gate followed by the AND gates, so it is in SOP form.

2. Which of the following logic expressions represents the logic diagram shown?

a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
View Answer

Answer: d
Explanation: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.

3. The device shown here is most likely a ________

a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
View Answer

Answer: d
Explanation: The given diagram is demultiplexer, because it takes single input & gives many outputs. A
demultiplexer is a combinational circuit that takes a single output and latches it to multiple outputs
depending on the select lines.
4. What type of logic circuit is represented by the figure shown below?

a) XOR
b) XNOR
c) AND
d) XAND
View Answer

Answer: b
Explanation: After solving the circuit we get (A’B’)+AB as output, which is XNOR operation. Thus, it will
produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.

5. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is
correct?

a) d
b) a
c) c
d) b
View Answer

Answer: a
Explanation: When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
001
010
100
1 1 1.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd
number of 1s.

6. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter
View Answer

Answer: b
Explanation: For decoding any number output must be high for that code and this is possible in One 4-
input NAND gate, one inverter option only. A decoder is a combinational circuit that converts binary
data to n-coded data upto 2n outputs.

7. What is the indication of a short to ground in the output of a driving gate?

a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state
View Answer

Answer: b
Explanation: Short to ground in the output of a driving gate indicates of a signal loss to all load gates.
This results in information being disrupted and loss of data.

8. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW.
What is the status of the Y’ outputs?

a) All are HIGH

b) All are LOW
c) All but Y0 are LOW
d) All but Y0 are HIGH
View Answer

Answer: d
Explanation: In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0 and rest all are HIGH.

9. The carry propagation can be expressed as ________

a) Cp = AB
b) Cp = A + B
c) All but Y0 are LOW
d) All but Y0 are HIGH
View Answer

Answer: b
Explanation: This happens in parallel adders (where we try to add numbers in parallel via more than one
adders). A carry propagation occurs when carry from one adder needs to be forwarded to other adder
and that second adder is holding the computation (addition) because carry from first adder has not
come yet. So, there is a slight delay for second adder and this is known as carry propagation.

10. 3 bits full adder contains ________

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
View Answer

Answer: d
Explanation: Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY and SUM.
Three bits full adder requires 23 = 8 combinational circuits

SANFOUNDRY: DEMUX – 1

. The word demultiplex means ___________

a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
View Answer

Answer: d
Explanation: The word demultiplex means “one into many” and distributor. A demultiplexer sends a
single input to multiple outputs, depending on the select lines. It is clear from the diagram:

2. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
View Answer

Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For
one input, the demultiplexer gives several outputs. That is why, it is called a data distributor.

3. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
View Answer

Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines.
Demultiplexer converts single input into multiple outputs.

4. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
View Answer

Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
Therefore, for 1:4 demultiplexer, 2 select lines are required.

5. In a multiplexer the output depends on its ___________

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
View Answer

Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As
the select input changes, the output of the multiplexer varies according to that input.

6. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________

a) Y0
b) Y1
c) Y2
d) Y3
View Answer

Answer: b
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =0, Y1 will be the output as 0 and 1 are the bit combinations of 1.

7. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________

a) Y0
b) Y1
c) Y2
d) Y3
View Answer

Answer: d
Explanation: It can be calculated from the figure shown below:
For C0 =1 and C1 =0, Y3 will be the output as 0 and 1 are the bit combinations of 1.

8. How many select lines are required for a 1-to-8 demultiplexer?

a) 2
b) 3
c) 4
d) 5
View Answer

Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this
case n = 3 since 23 = 8.

9. How many AND gates are required for a 1-to-8 multiplexer?

a) 2
b) 6
c) 8
d) 5
View Answer

Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.
10. The output Q4 of this 1-to-8 demultiplexer is ____________

a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
View Answer

Answer: c
Explanation: The output Y4 = Q2.(Q1)’.(Q0)’.I. since the bit combinations of 4 are 100.

11. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
View Answer
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input

SANFIUNDRY: DEMUX - 2

1. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input gives single output
View Answer

Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For
one input, the demultiplexer gives several outputs. That is why it is called a data distributor.

2. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
View Answer

Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines.
Demultiplexer converts single input into multiple outputs.

3. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
View Answer

Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
Therefore, for 1:4 demultiplexer, 2 select lines are required.

4. In a multiplexer the output depends on its ____________

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
View Answer

Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As
the select input changes, the output of the multiplexer varies according to that input.
5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ____________
a) Y0
b) Y1
c) Y2
d) Y3
View Answer

Answer: d
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =1, Y3 will be the output as 0 and 1 are the bit combinations of 1.

6. How many select lines are required for a 1-to-8 demultiplexer?

a) 2
b) 3
c) 4
d) 5
View Answer

Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this
case n = 3 since 23 = 8.

7. How many AND gates are required for a 1-to-8 multiplexer?

a) 2
b) 6
c) 8
d) 5
View Answer
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.

8. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
View Answer

Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

SANFOUNDRY: MUX - 2

1. 4 to 1 MUX would have ____________

a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
View Answer

Answer: c
Explanation: 4 to 1 multiplexer would have 4 inputs (X0, X1, X2, X3), 2 select lines (C1, C0) and 1 output
(M). It can be observed from this diagram:

2. The two input MUX would have ____________

a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
View Answer

Answer: a
Explanation: The two input multiplexer would have n select lines in 2n. Thus n =1. Therefore, it has 1
select line.

3. A combinational circuit that selects one from many inputs are ____________
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
View Answer

Answer: d
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer.
Whereas, a combinational circuit that divides one input into multiple outputs is known as Demultiplexer.

4. 4 to 1 MUX would have ____________

a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
View Answer

Answer: a
Explanation: 4 to 1 multiplexer would have 4 inputs (X0, X1, X2, X3), 2 select lines (C1, C0) and 1 output
(M). It can be observed from this diagram:

5. Which of the following circuit can be used as parallel to serial converter?

a) Multiplexer
b) Demultiplexer
c) Decoder
d) Digital counter
View Answer

Answer: a
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. In
multiplexer, different inputs are inserted parallely and then it gives one output which is in serial form.

6. A combinational circuit is one in which the output depends on the ____________

a) Input combination at the time
b) Input combination and the previous output
c) Input combination at that time and the previous input combination
d) Present output and the previous output
View Answer

Answer: a
Explanation: A combinational circuit is one in which the output depends on the input combination at the
time, whereas, a sequential circuit is one in which the output depends on present input as well past
outputs.

7. Without any additional circuitry an 8:1 MUX can be used to obtain ____________
a) Some but not all Boolean functions of 3 variables
b) All function of 3 variables but none of 4 variables
c) All functions of 3 variables and some but not all of 4 variables
d) All functions of 4 variables
View Answer

Answer: d
Explanation: A 2^n:1 MUX can implement all logic functions of (n+1) variables without any additional
circuitry. Thus 8:1 MUX can implement all logic functions of (3+1) variables, for 4 variables there are 16
possible combinations. So to use 8:1 MUX use 3 inputs as select lines of MUX and the 4th input as input
of MUX.

8. A basic multiplexer principle can be demonstrated through the use of a ____________

a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
View Answer

Answer: c
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. A basic
multiplexer principle can be demonstrated through the use of a rotary switch. Because rotary switch
gives one output corresponding to their inputs.

9. One multiplexer can take the place of ____________

a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
View Answer

Answer: d
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer. One
multiplexer can take the place of several SSI logic gates or combinational logic circuits because it has a
lot of functions to perform different operations.

10. The inputs/outputs of an analog multiplexer/demultiplexer are ____________

a) Bidirectional
b) Unidirectional
c) Even parity
d) Binary-coded decimal
View Answer

Answer: a
Explanation: One multiplexer can be used as demultiplexer. Hence, it is called bidirectional or two-way
transmission.

11. If enable input is high then the multiplexer is ______________

a) Enable
b) Disable
c) Saturation
d) High Impedance
View Answer

Answer: b
Explanation: If enable input is high then the multiplexer is disabled because enable input is in inverted
mode always (i.e. E’).

12. What is data routing in a multiplexer?

a) It spreads the information to the control unit
b) It can be used to route data from one of several source to destination
c) It is an application of multiplexer
d) Both it can be used to route data and it is an application of multiplexer
View Answer

Answer: d
Explanation: Multiplexing means passing more than one data through the same channel. Data routing is
an application of multiplexer and it can be used to route data from one of several source to destination

SANFOUNDRY: MUX

1. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
View Answer

Answer: b
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals
and forwards the selected input into a single line, depending on the active select lines.

2. Which combinational circuit is renowned for selecting a single input from multiple inputs & directing
the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
View Answer

Answer: a
Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device that
selects one of several analog or digital input signals and forwards the selected input into a single line,
depending on the active select lines.

3. It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the
digital multiplexer with the proficiency of large number of ___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines
View Answer

Answer: a
Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs
to the digital multiplexer with the proficiency of large number of inputs.

4. Which is the major functioning responsibility of the multiplexing combinational circuit?

a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) Encoding of binary information
View Answer

Answer: c
Explanation: The major functioning responsibility of the multiplexing combinational circuit is generation
of selected path between multiple sources and a single destination because it makes the circuit too
flexible. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line, depending on the active select lines.
5. What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
View Answer

Answer: c
Explanation: Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when
enable is low the chip does not work (MEMORY). However, Enable can be Active-High or Active-Low,
indicating it is active either when it is connected to VCC or GND respectively.

6. One multiplexer can take the place of ___________

a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
View Answer

Answer: d
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals
and forwards the selected input into a single line, depending on the active select lines. Since many
operational behaviour can be performed by using a multiplexer. Whereas, a combinational circuit is a
combination of many logic gates which makes the circuit more complex.

7. A digital multiplexer is a combinational circuit that selects ___________

a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information
View Answer

Answer: a
Explanation: A digital multiplexer is a combinational circuit that selects one digital information from
several sources and transmits the selected information on a single output line depending on the status
of the select lines. That is why it is also known as a data selector.

8. In a multiplexer, the selection of a particular input line is controlled by ___________

a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
View Answer

Answer: b
Explanation: The selection of a particular input line is controlled by a set of selected lines in a
multiplexer, which helps to select a particular input from several sources.
9. If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
View Answer

Answer: b
Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines to
select one of m select lines.

10. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
View Answer

Answer: d
Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean
23 inputs. So, 3 control lines are possible. Depending on the status of the select lines, the input is
selected and fed to the output.

11. A basic multiplexer principle can be demonstrated through the use of a ___________
a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
View Answer

Answer: c
Explanation: A basic multiplexer principle can be demonstrated through the use of a rotary switch. Since
its behaviour is similar to the multiplexer. There are around 10 digits out of which one is selected one at
a time and fed to the output.

12. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
b) 4
c) 2
d) 5
View Answer

Answer: c
Explanation: There are two NOT gates required for the construction of 4-to-1 multiplexer. x0, x1, x2 and
x3 are the inputs and C1 and C0 are the select lines and M is the output.

The diagram of a 4-to-1 multiplexer is shown below:

13. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is ___________

a) X0
b) X1
c) X2
d) X3
View Answer

Answer: b
Explanation: The output will be X1, because c1 = 0 and c0 = 1 results into 1 which further results as X1.
And rest of the AND gates gives output as 0.

14. The enable input is also known as ___________

a) Select input
b) Decoded input
c) Strobe
d) Sink
View Answer

Answer: c
Explanation: The enable input is also known as strobe which is used to cascade two or more multiplexer
ICs to construct a multiplexer with a larger number of inputs. Enable input activates the multiplexer to
operate.
SANFOUNDRY: PLA

1. What is memory decoding?

a) The process of Memory IC used in a digital system is overloaded with data

b) The process of Memory IC used in a digital system is selected for the range of address assigned

c) The process of Memory IC used in a digital system is selected for the range of data assigned

d) The process of Memory IC used in a digital system is overloaded with data allocated in memory cell

View Answer

Answer: b

Explanation: The Memory IC used in a digital system is selected or enabled only for the range of
addresses assigned to it and this process is called memory decoding. It decodes the memory to be
selected for a specific address.

2. The first step in the design of memory decoder is __________

a) Selection of a EPROM

b) Selection of a RAM

c) Address assignment

d) Data insertion

View Answer

Answer: c

Explanation: Memory decoder decodes the memory to be selected for a specific address. The first step
in the design of memory decoder is address assignment in non-overlapped manner.

3. How many address bits are required to select memory location in Memory decoder?

a) 4 KB

b) 8 KB

c) 12 KB

d) 16 KB

View Answer
Answer: c

Explanation: Memory decoder decodes the memory to be selected for a specific address. Since, the
given EPROM and RAM are of 4 KB (4 * 1024 = 4096) capacity, it requires 12 address bit to select one of
the 4096 memory locations.

4. How memory expansion is done?

a) By increasing the supply voltage of the Memory ICs

b) By decreasing the supply voltage of the Memory ICs

c) By connecting Memory ICs together

d) By separating Memory ICs

View Answer

Answer: c

Explanation: Memory ICs can be connected together to expand the number of memory words or the
number of bits per word.

5. IC 4116 is organised as _________

a) 512 * 4

b) 16 * 1

c) 32 * 4

d) 64 * 2

View Answer

Answer: c

Explanation: IC 4116 is organised as 16 * 1 K which has capability to store 16 KB.

6. To construct 16K * 4-bit memory, how many 4116 ICs are required?

a) 1

b) 2

c) 3

d) 4

View Answer
Answer: d

Explanation: Since, IC 4116 is organised as 16K * 1, which can store about 16KB data. So, four ICs are
required for 16K * 4 memory implementation.

7. How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system?

a) 4

b) 6

c) 8

d) 12

View Answer

Answer: c

Explanation: One 1024 * 1 RAM chips is of 1-bit. SO, for construction of 1024 * 8 RAM chip of 8-bits, it
will require 8 chips.

8. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length
of 8 bits?

a) 2

b) 4

c) 6

d) 8

View Answer

Answer: d

Explanation: 16K * 4 = 64K RAM is of 64K. Therefore, for a word of length 8-bits,

64 * 8 = 512K RAM required. Thus, number of 16K * 4 RAMs = 512/64 = 8.

9. The full form of PLD is _________

a) Programmable Load Devices

b) Programmable Logic Data

c) Programmable Logic Devices

d) Programmable Loaded Devices

View Answer
Answer: c

Explanation: The full form of PLD is Programmable Logic Devices. It is a collection of gates, flip-flops and
registers on a single chip.

10. PLD contains a large number of _________

a) Flip-flops

b) Gates

c) Registers

d) All of the Mentioned

View Answer

Answer: d

Explanation: Programmable Logic Devices is a collection of a large number of gates, flip-flops, registers
that are interconnected on the chip. Thus, it is used for designing logic circuits.

11. Logic circuits can also be designed using _________

a) RAM

b) ROM

c) PLD

d) PLA

View Answer

Answer: c

Explanation: Programmable Logic Devices is a collection of large number of gates, flip-flops, registers
that are interconnected on the chip. Thus, it is used for designing logic circuits.

12. In PLD, there are provisions to perform interconnections of the gates internally, because of
_________

a) High reliability

b) High conductivity

c) The desired logic implementation

d) The desired output

View Answer

Answer: c

Explanation: Programmable Logic Devices is a collection of a large number of gates, flip-flops, registers
that are interconnected on the chip. In PLD, there are provisions to perform interconnections of the
gates internally so that the desired logic can be implemented.

13. Why antifuses are implemented in a PLD?

a) To protect from high voltage

b) To increase the memory

c) To implement the programmes

d) As a switching devices

View Answer

Answer: c

Explanation: Programmable Logic Devices is a collection of a large number of gates, flip-flops, registers
that are interconnected on the chip. Programming is accomplished by using antifuses in a PLD and it is
fabricated at the cross points of the gates.

14. How many types of PLD is?

a) 2

b) 3

c) 4

d) 5

View Answer

Answer: a

Explanation: There are two types of PLD, viz., devices with fixed architecture and devices with a flexible
architecture. The main categories of PLDs are PROM, PAL and PLA.

15. PLA refers to _________

a) Programmable Loaded Array

b) Programmable Array Logic

c) Programmable Logic Array

d) Programmed Array Logic

View Answer

Answer: c

Explanation: PLA refers to Programmable Logic Array. It is a type of PLD having programmable AND and
OR gates.

SANFOUNDRY: LATCHES:

1. A latch is an example of a ___________

a) Monostable multivibrator

b) Astable multivibrator

c) Bistable multivibrator

d) 555 timer

View Answer

Answer: c

Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one in which

the circuit is stable in either of two states. It can be flipped from one state to the other state and vice-
versa.

2. Latch is a device with ___________

a) One stable state

b) Two stable state

c) Three stable state

d) Infinite stable states

View Answer

Answer: b
Explanation: Since, a latch works on the principal of bistable multivibrator. A Bistable multivibrator is
one in which the circuit is stable in either of two states. It can be flipped from one state to the other
state and vice-versa. So a latch has two stable states.

3. Why latches are called a memory devices?

a) It has capability to stare 8 bits of data

b) It has internal memory of 4 bit

c) It can store one bit of data

d) It can store infinite amount of data

View Answer

Answer: c

Explanation: Latches can be memory devices, and can store one bit of data for as long as the device is
powered. Once device is turned off, the memory gets refreshed.

4. Two stable states of latches are ___________

a) Astable & Monostable

b) Low input & high output

c) High output & low output

d) Low output & high input

View Answer

Answer: c

Explanation: A latch has two stable states, following the principle of Bistable Multivibrator. There are
two stable states of latches and these states are high-output and low-output.

5. How many types of latches are ___________

a) 4

b) 3

c) 2

d) 5

View Answer
Answer: a

Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a modified
form of SR latch whereas, T latch is an advanced form of JK latch.

6. The full form of SR is ___________

a) System rated

b) Set reset

c) Set ready

d) Set Rated

View Answer

Answer: b

Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.

7. The SR latch consists of ___________

a) 1 input

b) 2 inputs

c) 3 inputs

d) 4 inputs

View Answer

Answer: b

Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states.

The diagram of SR latch is shown below:

digital-circuits-questions-answers-latches-q7

8. The outputs of SR latch are ___________

a) x and y

b) a and b

c) s and r

d) q and q’

View Answer
Answer: d

Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states.
The inputs of SR latch are s and r while outputs are q and q’. It is clear from the diagram:

digital-circuits-questions-answers-latches-q7.

9. The NAND latch works when both inputs are ___________

a) 1

b) 0

c) Inverted

d) Don’t cares

View Answer

Answer: a

Explanation: The NAND latch works when both inputs are 1. Since, both of the inputs are inverted in a
NAND latch.

10. The first step of analysis procedure of SR latch is to ___________

a) label inputs

b) label outputs

c) label states

d) label tables

View Answer

Answer: b

Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so because the flip
flops have inverting gates inside them, hence in order to have both Q and Q complement available, we
have atleast one output labelled.

11. The inputs of SR latch are ___________

a) x and y

b) a and b

c) s and r
d) j and k

View Answer

Answer: c

Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states.
The inputs of SR latch are s and r while outputs are q and q’. It is clear from the diagram:

digital-circuits-questions-answers-latches-q7

12. When a high is applied to the Set line of an SR latch, then ___________

a) Q output goes high

b) Q’ output goes high

c) Q output goes low

d) Both Q and Q’ go high

View Answer

Answer: a

Explanation: S input of a SR latch is directly connected to the output Q. So, when a high is applied Q
output goes high and Q’ low.

13. When both inputs of SR latches are low, the latch ___________

a) Q output goes high

b) Q’ output goes high

c) It remains in its previously set or reset state

d) it goes to its next set or reset state

View Answer

Answer: c

Explanation: When both inputs of SR latches are low, the latch remains in it’s present state. There is no
change in the output.

14. When both inputs of SR latches are high, the latch goes ___________

a) Unstable

b) Stable
c) Metastable

d) Bistable

View Answer

Answer: c

Explanation: When both gates are identical and this is “metastable”, and the device will be in an
undefined state for an indefinite period.

SANFOUNDRY FLIP FLOPS:

1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which
configuration feature?

a) Low input voltages

b) Synchronous operation

c) Gate impedance

d) Cross coupling

View Answer

Answer: d

Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are
directly connected to the other’s output. Such types of structure is called cross coupling and due to
which latches remain in the latched condition.

2. One example of the use of an S-R flip-flop is as ___________

a) Transition pulse generator

b) Racer

c) Switch debouncer

d) Astable oscillator

View Answer
Answer: c

Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the
unwanted noise caused during the switching of electronic devices.

3. The truth table for an S-R flip-flop has how many VALID entries?

a) 1

b) 2

c) 3

d) 4

View Answer

Answer: c

Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or
Undefined State occurs at both S and R being at 1.

4. When both inputs of a J-K flip-flop cycle, the output will ___________

a) Be invalid

b) Change

c) Not change

d) Toggle

View Answer

Answer: c

Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1.
After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip-
flop has 4 stable states: Latch, Reset, Set and Toggle.

5. Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW

b) The output complement follows the input when enabled

c) Only one of the inputs can be HIGH at a time

d) The output toggles if one of the inputs is held HIGH

View Answer
Answer: a

Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise
reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then
output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.

6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?

a) AND or OR gates

b) XOR or XNOR gates

c) NOR or NAND gates

d) AND or NOR gates

View Answer

Answer: c

Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross
coupling means the output of second gate is fed to the input of first gate and vice-versa.

7. The logic circuits whose outputs at any instant of time depends only on the present input but also on
the past outputs are called

a) Combinational circuits

b) Sequential circuits

c) Latches

d) Flip-flops

View Answer

Answer: b

Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits
whose outputs at any instant of time depends only on the present input but also on the past outputs are
called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then
it’s known as combinational circuits.

8. Whose operations are more faster among the following?

a) Combinational circuits

b) Sequential circuits
c) Latches

d) Flip-flops

View Answer

Answer: a

Explanation: Combinational circuits are often faster than sequential circuits. Since, the combinational
circuits do not require memory elements whereas the sequential circuits need memory devices to
perform their operations in sequence. Latches and Flip-flops come under sequential circuits.

9. How many types of sequential circuits are?

a) 2

b) 3

c) 4

d) 5

View Answer

Answer: a

Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii)
asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock
signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.

10. The sequential circuit is also called ___________

a) Flip-flop

b) Latch

c) Strobe

d) Adder

View Answer

Answer: b

Explanation: The sequential circuit is also called a latch because both are a memory cell, which are
capable of storing one bit of information.

11. The basic latch consists of ___________

a) Two inverters

b) Two comparators

c) Two amplifiers

d) Two adders

View Answer

Answer: a

Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the
second output Q’ = 1 and vice versa.

12. In S-R flip-flop, if Q = 0 the output is said to be ___________

a) Set

b) Reset

c) Previous state

d) Current state

View Answer

Answer: b

Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

13. The output of latches will remain in set/reset untill ___________

a) The trigger pulse is given to change the state

b) Any pulse given to go into previous state

c) They don’t get any pulse more

d) The pulse is edge-triggered

View Answer

Answer: a

Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the
state.

14. What is a trigger pulse?

a) A pulse that starts a cycle of operation

b) A pulse that reverses the cycle of operation

c) A pulse that prevents a cycle of operation

d) A pulse that enhances a cycle of operation

View Answer

Answer: a

Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.

15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?

a) Because of inverted outputs

b) Because of triggering functionality

c) Because of cross-coupled connection

d) Because of inverted outputs & triggering functionality

View Answer

Answer: c

Explanation: The cross-coupled connections from the output of one gate to the input of the other gate
constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as
asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they function
in the absence of a clock pulse.

SANFOUNDRY: FLIP FLOP 2

1. What is an ambiguous condition in a NAND based S’-R’ latch?

a) S’=0, R’=1

b) S’=1, R’=0

c) S’=1, R’=1

d) S’=0, R’=0

View Answer
Answer: d

Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and
this condition is called as ambiguous/forbidden state. This state is also known as an Invalid state as the
system goes into an unexpected situation.

2. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________

a) No change

b) Set

c) Reset

d) Forbidden

View Answer

Answer: a

Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the state. It
remains in its prior state. This state is used for the storage of data.

3. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________

a) A D latch at each of its input

b) An inverter at each of its input

c) It can never be converted

d) Both a D latch and an inverter at its input

View Answer

Answer: d

Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D latch or an
inverter at its input as it’s operations will be complementary.

4. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________

a) The inputs of NOR latch are 0 but 1 for NAND latch

b) The inputs of NOR latch are 1 but 0 for NAND latch

c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch

d) The output of NOR latch is 1 but 0 for NAND latch

View Answer
Answer: a

Explanation: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for
NAND latch.

5. The characteristic equation of S-R latch is ____________

a) Q(n+1) = (S + Q(n))R’

b) Q(n+1) = SR + Q(n)R

c) Q(n+1) = S’R + Q(n)R

d) Q(n+1) = S’R + Q'(n)R

View Answer

Answer: a

Explanation: A characteristic equation is needed when a specific gate requires a specific output in order
to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R’.

6. The difference between a flip-flop & latch is ____________

a) Both are same

b) Flip-flop consist of an extra output

c) Latches has one input but flip-flop has two

d) Latch has two inputs but flip-flop has one

View Answer

Answer: c

Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an additional
control input is provided to the latch.

7. How many types of flip-flops are?

a) 2

b) 3

c) 4

d) 5

View Answer
Answer: c

Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced version of S-
R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.

8. The S-R flip flop consist of ____________

a) 4 AND gates

b) Two additional AND gates

c) An additional clock input

d) 3 AND gates

View Answer

Answer: b

Explanation: The S-R flip flop consist of two additional AND gates at the S and R inputs of S-R latch.

9. What is one disadvantage of an S-R flip-flop?

a) It has no Enable input

b) It has a RACE condition

c) It has no clock input

d) Invalid State

View Answer

Answer: d

Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is
referred to as Invalid State.

10. One example of the use of an S-R flip-flop is as ____________

a) Racer

b) Stable oscillator

c) Binary storage register

d) Transition pulse generator

View Answer
Answer: c

Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as
binary storage element. It functions as memory storage during the No Change State.

11. When is a flip-flop said to be transparent?

a) When the Q output is opposite the input

b) When the Q output follows the input

c) When you can see through the IC packaging

d) When the Q output is complementary of the input

View Answer

Answer: b

Explanation: Flip-flop have the property of responding immediately to the changes in its inputs. This
property is called transparency.

12. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

a) The clock pulse is LOW

b) The clock pulse is HIGH

c) The clock pulse transitions from LOW to HIGH

d) The clock pulse transitions from HIGH to LOW

View Answer

Answer: c

Explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered
when transition takes place from low to high, while, it is negative edge triggered when the transition
takes place from high to low.

13. What is the hold condition of a flip-flop?

a) Both S and R inputs activated

b) No active S or R input

c) Only S is active

d) Only R is active
View Answer

Answer: b

Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is the No
Change State or Memory Storage state if a flip-flop.

14. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to
0, the latch will be ________

a) SET

b) RESET

c) Clear

d) Invalid

View Answer

Answer: b

Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it
remains in reset. If S=1, R=0, the flip flop is at the set condition.

15. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the
_____________

a) Edge-detection circuit

b) NOR latch

c) NAND latch

d) Pulse-steering circuit

View Answer

Answer: a

Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as edge-
triggered is the edge-detection circuit.

SANFOUNDRY: FLIP FLOP 3:

1. Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the
number of inputs?

a) Gated JK-latch

b) Gated SR-latch

c) Gated T-latch

d) Gated D-latch

View Answer

Answer: d

Explanation: Since, both inputs of the D flip-flop are connected through an inverter. And this causes
reduction in the number of inputs.

2. The characteristic of J-K flip-flop is similar to _____________

a) S-R flip-flop

b) D flip-flop

c) T flip-flop

d) Gated T flip-flop

View Answer

Answer: a

Explanation: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same behaviour is
shown by J-K flip-flop.

3. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________

a) Two AND gates

b) Two NAND gates

c) Two NOT gates

d) Two OR gates

View Answer

Answer: a

Explanation: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.
4. How is a J-K flip-flop made to toggle?

a) J = 0, K = 0

b) J = 1, K = 0

c) J = 0, K = 1

d) J = 1, K = 1

View Answer

Answer: d

Explanation: When j=k=1 then the race condition is occurs that means both output wants to be HIGH.
Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is device is either
set or reset.

5. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called
___________

a) Parity error checking

b) Ones catching

c) Digital discrimination

d) Digital filtering

View Answer

Answer: b

Explanation: Ones catching means that the input transitioned to a 1 and back very briefly
(unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the
1. Similarly for 0’s catching.

6. In J-K flip-flop, “no change” condition appears when ___________

a) J = 1, K = 1

b) J = 1, K = 0

c) J = 0, K = 1

d) J = 0, K = 0

View Answer
Answer: d

Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.

7. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________

a) Constantly LOW

b) Constantly HIGH

c) A 20 kHz square wave

d) A 10 kHz square wave

View Answer

Answer: d

Explanation: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-
flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition
state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the
clock. Frequency is inversely related to time period and hence frequency gets halved.

8. What is the significance of the J and K terminals on the J-K flip-flop?

a) There is no known significance in their designations

b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J
input is also HIGH

c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit

d) All of the other letters of the alphabet are already in use

View Answer

Answer: c

Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated
circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the toggling of states.

9. On a J-K flip-flop, when is the flip-flop in a hold condition?

a) J = 0, K = 0

b) J = 1, K = 0

c) J = 0, K = 1

d) J = 1, K = 1
View Answer

Answer: a

Explanation: At J=0 k=0 output continues to be in the same state. This is the memory storing state.

10. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four
input clock pulses, the binary count is ________

a) 00

b) 11

c) 01

d) 10

View Answer

Answer: a

Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So mod = 22 =
4). So after 4 clock pulses the O/P repeats i.e. 00.

11. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first
flip-flop is 32 kHz, the output frequency (fout) is ________

a) 1 kHz

b) 2 kHz

c) 4 kHz

d) 16 kHz

View Answer

Answer: b

Explanation: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:- fourth flip-
flop. Since the output frequency is determined on basis of the 4th flip-flop.

12. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an
input clock frequency of 20.48 MHz.

a) 10.24 kHz

b) 5 kHz
c) 30.24 kHz

d) 15 kHz

View Answer

Answer: b

Explanation: 12 flip flops = 212 = 4096

Input Clock frequency = 20.48*106 = 20480000

Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.

13. How many flip-flops are in the 7475 IC?

a) 2

b) 1

c) 4

d) 8

View Answer

Answer: c

Explanation: There are 4 flip-flops used in 7475 IC and those are D flip-flops only

SANFOUNDRY TRIGGER:

1. The characteristic equation of J-K flip-flop is ______________

a) Q(n+1)=JQ(n)+K’Q(n)

b) Q(n+1)=J’Q(n)+KQ'(n)

c) Q(n+1)=JQ'(n)+KQ(n)

d) Q(n+1)=JQ'(n)+K’Q(n)

View Answer

Answer: d

Explanation: A characteristic equation is needed when a specific gate requires a specific output in order
to satisfy the truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K’Q(n).

2. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________

a) D flip-flop

b) S-R flip-flop

c) T flip-flop

d) S-K flip-flop

View Answer

Answer: c

Explanation: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.

3. In J-K flip-flop, the function K=J is used to realize _____________

a) D flip-flop

b) S-R flip-flop

c) T flip-flop

d) S-K flip-flop

View Answer

Answer: c

Explanation: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

4. The only difference between a combinational circuit and a flip-flop is that _____________

a) The flip-flop requires previous state

b) The flip-flop requires next state

c) The flip-flop requires a clock pulse

d) The flip-flop depends on the past as well as present states

View Answer

Answer: c

Explanation: Both flip-flop and latches are memory elements with clock/control inputs. They depend on
the past as well as present states. Whereas, in case of combinational circuits, they only depend on the
present state.

5. How many stable states a combinational circuits have?

a) 3

b) 4

c) 2

d) 5

View Answer

Answer: c

Explanation: The two stable states of combinational circuits are 1 and 0. Whereas, in flip-flops there is
an additional state known as Forbidden State.

6. The flip-flop is only activated by _____________

a) Positive edge trigger

b) Negative edge trigger

c) Either positive or Negative edge trigger

d) Sinusoidal trigger

View Answer

Answer: c

Explanation: Flip flops can be activated with either a positive or negative edge trigger.

7. The S-R latch composed of NAND gates is called an active low circuit because _____________

a) It is only activated by a positive level trigger

b) It is only activated by a negative level trigger

c) It is only activated by either a positive or negative level trigger

d) It is only activated by sinusoidal trigger

View Answer

Answer: b

Explanation: Active low indicates that only an input value of 0 sets or resets the circuit.

8. Both the J-K & the T flip-flop are derived from the basic _____________

a) S-R flip-flop
b) S-R latch

c) D latch

d) D flip-flop

View Answer

Answer: b

Explanation: The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are
derived. A latch is similar to a flip-flop, only without a clock input.

9. The flip-flops which has not any invalid states are _____________

a) S-R, J-K, D

b) S-R, J-K, T

c) J-K, D, S-R

d) J-K, D, T

View Answer

Answer: d

Explanation: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an
invalid or forbidden state where no output could be determined.

10. What does the triangle on the clock input of a J-K flip-flop mean?

a) Level enabled

b) Edge triggered

c) Both Level enabled & Edge triggered

d) Level triggered

View Answer

Answer: b

Explanation: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas the absence
of triangle symbol implies that the flip-flop is level-triggered.

11. What does the circle on the clock input of a J-K flip-flop mean?

a) Level enabled
b) Positive edge triggered

c) negative edge triggered

d) Level triggered

View Answer

Answer: c

Explanation: The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the
absence of triangle symbol implies that the flip-flop is level-triggered.

12. What does the direct line on the clock input of a J-K flip-flop mean?

a) Level enabled

b) Positive edge triggered

c) negative edge triggered

d) Level triggered

View Answer

Answer: d

Explanation: The direct line on the clock input of a J-K flip-flop mean level triggered. Whereas the
presence of triangle symbol implies that the flip-flop is edge-triggered.

13. What does the half circle on the clock input of a J-K flip-flop mean?

a) Level enabled

b) Positive edge triggered

c) negative edge triggered

d) Level triggered

View Answer

Answer: d

Explanation: The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the
presence of triangle symbol implies that the flip-flop is edge-triggered.

14. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________

a) Constantly LOW
b) Constantly HIGH

c) A 20 kHz square wave

d) A 10 kHz square wave

View Answer

Answer: d

Explanation: As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is
available at the output.

15. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

a) The clock pulse is LOW

b) The clock pulse is HIGH

c) The clock pulse transitions from LOW to HIGH

d) The clock pulse transitions from HIGH to LOW

View Answer

Answer: c

Explanation: Edge triggered device will follow the input condition when there is a transition. It is said to
be positive edge triggered when transition occurs from LOW to HIGH. While it is said to be negative
edge triggered when a transition occurs from HIGH to LOW.

SANFOUNDRY REGISTERS:

1. A register is defined as ___________

a) The group of latches for storing one bit of information

b) The group of latches for storing n-bit of information

c) The group of flip-flops suitable for storing one bit of information

d) The group of flip-flops suitable for storing binary information

View Answer

Answer: d
Explanation: A register is defined as the group of flip-flops suitable for storing binary information. Each
flip-flop is a binary cell capable of storing one bit of information. The data in a register can be
transferred from one flip-flop to another.

2. The register is a type of ___________

a) Sequential circuit

b) Combinational circuit

c) CPU

d) Latches

View Answer

Answer: a

Explanation: Register’s output depends on the past and present states of the inputs. The device which
follows these properties is termed as a sequential circuit. Whereas, combinational circuits only depend
on the present values of inputs.

3. How many types of registers are?

a) 2

b) 3

c) 4

d) 5

View Answer

Answer: c

Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-Out, Parallel-
In/Serial-Out and Parallel-In/Parallel-Out.

4. The main difference between a register and a counter is ___________

a) A register has no specific sequence of states

b) A counter has no specific sequence of states

c) A register has capability to store one bit of information but counter has n-bit

d) A register counts data

View Answer
Answer: a

Explanation: The main difference between a register and a counter is that a register has no specific
sequence of states except in certain specialised applications.

5. In D register, ‘D’ stands for ___________

a) Delay

b) Decrement

c) Data

d) Decay

View Answer

Answer: c

Explanation: D stands for “data” in case of flip-flops and not delay. Registers are made of a group of flip-
flops.

6. Registers capable of shifting in one direction is ___________

a) Universal shift register

b) Unidirectional shift register

c) Unipolar shift register

d) Unique shift register

View Answer

Answer: b

Explanation: The register capable of shifting in one direction is unidirectional shift register. The register
capable of shifting in both directions is known as a bidirectional shift register.

7. A register that is used to store binary information is called ___________

a) Data register

b) Binary register

c) Shift register

d) D – Register

View Answer
Answer: b

Explanation: A register that is used to store binary information is called a binary register. A register in
which data can be shifted is called shift register.

8. A shift register is defined as ___________

a) The register capable of shifting information to another register

b) The register capable of shifting information either to the right or to the left

c) The register capable of shifting information to the right only

d) The register capable of shifting information to the left only

View Answer

Answer: b

Explanation: The register capable of shifting information either to the right or to the left is termed as
shift register. A register in which data can be shifted only in one direction is called unidirectional shift
register, while if data can shifted in both directions, it is known as a bidirectional shift register.

9. How many methods of shifting of data are available?

a) 2

b) 3

c) 4

d) 5

View Answer

Answer: a

Explanation: There are two types of shifting of data are available and these are serial shifting & parallel
shifting.

10. In serial shifting method, data shifting occurs ____________

a) One bit at a time

b) simultaneously

c) Two bit at a time

d) Four bit at a time

View Answer

Answer: a

Explanation: As the name suggests serial shifting, it means that data shifting will take place one bit at a
time for each clock pulse in a serial fashion. While in parallel shifting, shifting will take place with all bits
simultaneously for each clock pulse in a parallel fashion

SANFOUNDRY SHIFT REGISTERS:

1. What is a recirculating register?

a) Serial out connected to serial in

b) All Q outputs connected together

c) A register that can be used over again

d) Parallel out connected to Parallel in

View Answer

Answer: a

Explanation: A recirculating register is a register whose serial output is connected to the serial input in a
circulated manner.

2. When is it important to use a three-state buffer?

a) When two or more outputs are connected to the same input

b) When all outputs are normally HIGH

c) When all outputs are normally LOW

d) When two or more outputs are connected to two or more inputs

View Answer

Answer: a

Explanation: When two or more outputs are connected to the same input, in such situation we use of
tristate buffer always because it has the capability to take upto three inputs. A buffer is a circuit where
the output follows the input.
3. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing
________

a) 1110

b) 0111

c) 1000

d) 1001

View Answer

Answer: d

Explanation: Stored nibble | waiting nibble

0111 | 1110, Initially

111 | 1100, 1st pulse

11 | 1001, 2nd pulse.

4. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses,
the data outputs are ________

a) 1110

b) 0001

c) 1100

d) 1000

View Answer

Answer: b

Explanation: Parallel in parallel out gives the same output as input. Thus, after three clock pulses, the
data outputs are 0001.

5. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift
register with an initial state 11110000. After two clock pulses, the register contains

a) 10111000

b) 10110111

c) 11110000
d) 11111100

View Answer

Answer: d

Explanation: After first clock pulse, the register contains 11111000. After second clock pulse, the register
would contain 11111100. Since, the bits are shifted to the right at every clock pulse.

6. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a ________
________ and ________ out register.

a) Parallel-in, serial, parallel

b) Serial-in, parallel, serial

c) Series-parallel-in, series, parallel

d) Bidirectional in, parallel, series

View Answer

Answer: a

Explanation: One bit shifting takes place just after the output obtained on every register. Hence, by
adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a Parallel-in, Serial, and
Parallel-out register. Since, the bots can be inputted all at the same time, while the data can be
outputted either one at a time or simultaneously.

7. What type of register would have a complete binary number shifted in one bit at a time and have all
the stored bits shifted out one at a time?

a) Parallel-in Parallel-out

b) Parallel-in Serial-out

c) Serial-in Serial-out

d) Serial-in Parallel-out

View Answer

Answer: c

Explanation: Serial-in Serial-out register would have a complete binary number shifted in one bit at a
time and have all the stored bits shifted out one at a time. Since in serial transmission, bits are
transmitted or received one at a time and not simultaneously.

8. In a 4-bit Johnson counter sequence, there are a total of how many states, or bit patterns?
a) 1

b) 3

c) 4

d) 8

View Answer

Answer: d

Explanation: In johnson counter, total number of states are determined by 2N = 2*4 = 16

Total Number of Used states = 2N = 2*4 = 8

Total Number of Unused states = 16 – 8 = 8.

9. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

a) 1101000000

b) 0011010000

c) 1100000000

d) 0000000000

View Answer

Answer: b

Explanation: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at 1st position
and 2nd position which came from the last two bits). As in a ring counter, the bits rotate in clockwise
direction.

10. How much storage capacity does each stage in a shift register represent?

a) One bit

b) Two bits

c) Four bits

d) Eight bits

View Answer

Answer: a
Explanation: A register is made of flip-flops. And each flip-flop stores 1 bit of data. Thus, a shift register
has the capability to store one bit and if another bit is to store, in such situation it deletes the previous
data and stores them

SANFOUNDRY UNIVERSAL SHIFT REGISTERS:

1. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

a) Ring shift

b) Clock

c) Johnson

d) Binary

View Answer

Answer: a

Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. Thus, it
generates equally spaced timing pulses.

2. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is
waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing
________

a) 1101

b) 0111

c) 0001

d) 1110

View Answer

Answer: b

Explanation: Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits are 011
and remained bit in register is 1. Therefore, 0111 is required solution.

1011 | 1101

101 | 1110 -> 1st clock pulse

10 | 1111 -> 2nd clock pulse

1 | 0111 -> 3rd clock pulse.

3. To operate correctly, starting a ring shift counter requires __________

a) Clearing all the flip-flops

b) Presetting one flip-flop and clearing all others

c) Clearing one flip-flop and presetting all others

d) Presetting all the flip-flops

View Answer

Answer: b

Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. To
operate correctly, starting a ring shift counter requires presetting one flip-flop and clearing all others so
that it can shift to the next bit.

4. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________
position for each clock pulse.

a) Right, one

b) Right, two

c) Left, one

d) Left, three

View Answer

Answer: a

Explanation: If register shifts towards left then it shift by a bit to the left and if register shifts right then it
shift to the right by one bit. Since, it receives parallel data, then by default, it will shift to right by one
position.

5. How many clock pulses will be required to completely load serially a 5-bit shift register?

a) 2

b) 3

c) 4

d) 5

View Answer
Answer: d

Explanation: A register is a collection of FFS. To load a bit, we require 1 clock pulse for 1 shift register.
So, for 5-bit shift register we would require of 5 clock pulses.

6. How is an strobe signal used when serially loading a shift register?

a) To turn the register on and off

b) To control the number of clocks

c) To determine which output Qs are used

d) To determine the FFs that will be used

View Answer

Answer: b

Explanation: A strobe is used to validate the availability of data on the data line. It (an auxiliary signal
used to help synchronize the real data in an electrical bus when the bus components have no common
clock) signal is used to control the number of clocks during serially loading a shift register.

7. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time
delay between the serial input and the Q3 output?

a) 1.67 s

b) 26.67 s

c) 26.7 ms

d) 267 ms

View Answer

Answer: b

Explanation: In serial-sifting, one bit of data is shifted one at a time. From Q0 to Q3 total of 4 bit shifting
takes place. Therefore, 4/150kHz = 26.67 microseconds.

8. What are the three output conditions of a three-state buffer?

a) HIGH, LOW, float

b) High-Z, 0, float

c) Negative, positive, 0

d) 1, Low-Z, float
View Answer

Answer: a

Explanation: Three conditions of a three-state buffer are HIGH, LOW & float.

9. The primary purpose of a three-state buffer is usually ____________

a) To provide isolation between the input device and the data bus

b) To provide the sink or source current required by any device connected to its output without loading
down the output device

c) Temporary data storage

d) To control data flow

View Answer

Answer: a

Explanation: The primary purpose of a three-state buffer is usually to provide isolation between the
input device or peripheral devices and the data bus. Three conditions of a three-state buffer are HIGH,
LOW & float.

10. What is the difference between a ring shift counter and a Johnson shift counter?

a) There is no difference

b) A ring is faster

c) The feedback is reversed

d) The Johnson is faster

View Answer

Answer: c

Explanation: A ring counter is a shift register (a cascade connection of flip-flops) with the output of the
last one connected to the input of the first, that is, in a ring. Whereas, a Johnson counter (or switchtail
ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter,
where the output from the last stage is inverted and fed back as input to the first stage.

SANFOUNDRY SHIFT REGISTER COUNTERS:

1. What is a recirculating register?

a) Serial out connected to serial in

b) All Q outputs connected together

c) A register that can be used over again

d) Parallel out connected to Parallel in

View Answer

Answer: a

Explanation: A recirculating register is a register whose serial output is connected to the serial input in a
circulated manner.

2. When is it important to use a three-state buffer?

a) When two or more outputs are connected to the same input

b) When all outputs are normally HIGH

c) When all outputs are normally LOW

d) When two or more outputs are connected to two or more inputs

View Answer

Answer: a

Explanation: When two or more outputs are connected to the same input, in such situation we use of
tristate buffer always because it has the capability to take upto three inputs. A buffer is a circuit where
the output follows the input.

3. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing
________

a) 1110

b) 0111

c) 1000

d) 1001

View Answer

Answer: d

Explanation: Stored nibble | waiting nibble

0111 | 1110, Initially

111 | 1100, 1st pulse

11 | 1001, 2nd pulse.

4. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses,
the data outputs are ________

a) 1110

b) 0001

c) 1100

d) 1000

View Answer

Answer: b

Explanation: Parallel in parallel out gives the same output as input. Thus, after three clock pulses, the
data outputs are 0001.

5. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift
register with an initial state 11110000. After two clock pulses, the register contains

a) 10111000

b) 10110111

c) 11110000

d) 11111100

View Answer

Answer: d

Explanation: After first clock pulse, the register contains 11111000. After second clock pulse, the register
would contain 11111100. Since, the bits are shifted to the right at every clock pulse.

6. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a ________
________ and ________ out register.

a) Parallel-in, serial, parallel

b) Serial-in, parallel, serial

c) Series-parallel-in, series, parallel

d) Bidirectional in, parallel, series

View Answer

Answer: a

Explanation: One bit shifting takes place just after the output obtained on every register. Hence, by
adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a Parallel-in, Serial, and
Parallel-out register. Since, the bots can be inputted all at the same time, while the data can be
outputted either one at a time or simultaneously.

7. What type of register would have a complete binary number shifted in one bit at a time and have all
the stored bits shifted out one at a time?

a) Parallel-in Parallel-out

b) Parallel-in Serial-out

c) Serial-in Serial-out

d) Serial-in Parallel-out

View Answer

Answer: c

Explanation: Serial-in Serial-out register would have a complete binary number shifted in one bit at a
time and have all the stored bits shifted out one at a time. Since in serial transmission, bits are
transmitted or received one at a time and not simultaneously.

8. In a 4-bit Johnson counter sequence, there are a total of how many states, or bit patterns?

a) 1

b) 3

c) 4

d) 8

View Answer

Answer: d

Explanation: In johnson counter, total number of states are determined by 2N = 2*4 = 16

Total Number of Used states = 2N = 2*4 = 8

Total Number of Unused states = 16 – 8 = 8.

9. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

a) 1101000000

b) 0011010000

c) 1100000000

d) 0000000000

View Answer

Answer: b

Explanation: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at 1st position
and 2nd position which came from the last two bits). As in a ring counter, the bits rotate in clockwise
direction.

10. How much storage capacity does each stage in a shift register represent?

a) One bit

b) Two bits

c) Four bits

d) Eight bits

View Answer

Answer: a

Explanation: A register is made of flip-flops. And each flip-flop stores 1 bit of data. Thus, a shift register
has the capability to store one bit and if another bit is to store, in such situation it deletes the previous
data and stores them.

SANFOUNDRY RING COUNTER:

1. Ring shift and Johnson counters are ____________

a) Synchronous counters

b) Asynchronous counters

c) True binary counters

d) Synchronous and true binary counters

View Answer

Answer: a

Explanation: Synchronous counters are the counters being triggered in the presence of a clock pulse.
Since, all of the clock inputs are connected through a single clock pulse in ring shift and johnson
counters. So, both are synchronous counters.

2. What is the difference between a shift-right register and a shift-left register?

a) There is no difference

b) The direction of the shift

c) Propagation delay

d) The clock input

View Answer

Answer: b

Explanation: In shift-right register, shifting of bit takes place towards the right and towards left for shift-
left register. Thus, both the registers vary in the shifting of their direction.

3. What is a transceiver circuit?

a) A buffer that transfers data from input to output

b) A buffer that transfers data from output to input

c) A buffer that can operate in both directions

d) A buffer that can operate in one direction

View Answer

Answer: c

Explanation: A transceiver circuit is a buffer that can operate in both directions right as well as left.

4. A 74HC195 4-bit parallel access shift register can be used for ____________

a) Serial in/serial out operation

b) Serial in/parallel out operation

c) Parallel in/serial out operation

d) All of the Mentioned

View Answer

Answer: d

Explanation: 74HC195 is an IC, which can be used for all of the given operations, as well as for, parallel-
in/parallel-out.

5. Which type of device may be used to interface a parallel data format with external equipment’s serial
format?

a) UART

b) Key matrix

c) Memory chip

d) Series in Parallel out

View Answer

Answer: a

Explanation: UART means Universal Asynchronous Receiver/Transmitter which converts the bytes it
receives from the computer along parallel circuits into a single serial bit stream for outbound
transmission. And also receives data in serial form and converts it into parallel form and sent to the
processor.

6. What is the function of a buffer circuit?

a) To provide an output that is inverted from that on the input

b) To provide an output that is equal to its input

c) To clean up the input

d) To clean up the output

View Answer

Answer: b

Explanation: The function of a buffer circuit is to provide an output that is equal to its input. A
transceiver circuit is a buffer that can operate in both directions right as well as left.

7. What is the preset condition for a ring shift counter?

a) All FFs set to 1

b) All FFs cleared to 0

c) A single 0, the rest 1

d) A single 1, the rest 0

View Answer

Answer: d

Explanation: A ring shift counter is a counter in which the output of one FF connected to the input of the
adjacent FF. In preset condition, all of the bits are 0 except first one.

8. Which is not characteristic of a shift register?

a) Serial in/parallel in

b) Serial in/parallel out

c) Parallel in/serial out

d) Parallel in/parallel out

View Answer

Answer: a

Explanation: There is no such type of register present who doesn’t have output end. Thus, Serial
in/Parallel in is not a characteristic of a shift register. There has to be an output, be it serial or parallel.

9. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ____________

a) Divide-by-4 clock pulse

b) Sequence generator

c) Strobe line

d) Multiplexer

View Answer

Answer: c

Explanation: In computer or memory technology, a strobe is a signal that is sent that validates data or
other signals on adjacent parallel lines. Thus, in registers the strobe line is there to check the availability
of data.

10. Another way to connect devices to a shared data bus is to use a ____________
a) Circulating gate

b) Transceiver

c) Bidirectional encoder

d) Strobed latch

View Answer

Answer: b

Explanation: A transceiver is a device comprising both a transmitter and a receiver which are combined
and share common circuitry or a single housing. When no circuitry is common between transmit and
receive functions, the device is a transmitter-receiver.

SANFOUNDRY IC

SANFOUNDRY OP AMP – 1:

This set of Linear Integrated Circuit Multiple Choice Questions & Answers (MCQs) focuses on
“Operational Amplifier Internal Circuit – 1”.

1. Which is not the internal circuit of operational amplifier?

a) Differential amplifier

b) Level translator

c) Output driver

d) Clamper

View Answer

Answer: d

Explanation: Clamper is an external circuit connected at the output of Operational amplifier, which
clamp the output to desire DC level.

2. The purpose of level shifter in Op-amp internal circuit is to

a) Adjust DC voltage

b) Increase impedance

c) Provide high gain

d) Decrease input resistance

View Answer

Answer: a

Explanation: The gain stages in Op-amp are direct coupled. So, level shifter is used for adjustment of DC
level.

3. How a symmetrical swing is obtained at the output of Op-amp

a) Providing amplifier with negative supply voltage

b) Providing amplifier with positive voltage

c) Providing amplifier with positive& negative voltage

d) None of the mentioned

View Answer

Answer: c

Explanation: For example, consider a single voltage supply +15v. During positive half cycle the output
will be +5v and -10v during negative half cycle.

Therefore, the maximum peak to peak output swing, -5v (-10v) = -15v (Asymmetrical swing).

So, to get symmetrical swing both positive and negative supply voltage with bias point fixed suitably is
required.

4. What is the purpose of differential amplifier stage in internal circuit of Op-amp?

a) Low gain to differential mode signal

b) Cancel difference mode signal

c) Low gain to common mode signal

d) Cancel common mode signal

View Answer

Answer: d

Explanation: Any undesired noise, common to both of the input terminal is suppressed by differential
amplifier.

5. Which of the following is not preferred for input stage of Op-amp?

a) Dual Input Balanced Output

b) Differential Input Single ended Output

c) Cascaded DC amplifier

d) Single Input Differential Output

View Answer

Answer: c

Explanation: Cascaded DC amplifier suffers from major problem of drift of the operating point, due to
temperature dependency of the transistor.

6. What will be the emitter current in a differential amplifier, where both the transistor are biased and
matched? (Assume current to be IQ)

a) IE = IQ/2

b) IE = IQ

c) IE = (IQ)2/2

d) IE = (IQ)2

View Answer

Answer: a

Explanation: Due to symmetry of differential amplifier circuit, current IQ divides equally through both
transistors.

7. From the circuit, determine the output voltage (Assume αF=1)

linear-integrated-circuit-mcqs-operational-amplifier-internal-circuit-1-q7

a) VO1=3.9v , VO2=12v

b) VO1=12v , VO2=3.9v

c) VO1=12v , VO2=0v

d) VO1=3.9v , VO2=-3.9v

View Answer

Answer: b

Explanation: The voltage at the common emitter ‘E’ will be -0.7v, which make Q1 off and the entire
current will flow through Q2.
⇒ VO1 = VCC VO2= VCC-αF×IQ×RC,

⇒ VO1 = 12v , VO2=12v-1×3mA×2.7k = 3.9v.

8. At what condition differential amplifier function as a switch

a) 4VT < Vd < -4VT

b) -2VT ≤ Vd ≤ 2VT

c) 0 ≤ Vd < -4VT

d) 0 ≤ Vd ≤ 2VT

View Answer

Answer: a

Explanation: For Vd > 4VT, the output voltage are VO1 = VCC, VO2= VCC-αF IQRC. Therefore, a transistor
Q1 will be ON and Q2 will be OFF. Similarly for Vd> -4VT, both transistors Q2 & Q1 will be ON.

9. For Vd > ±4VT, the function of differential amplifier will be

a) Switch

b) Limiter

c) Automatic gain control

d) Linear Amplifier

View Answer

Answer: b

Explanation: At this condition, input voltage of the amplifier is greater than ±100mv and thus acts as a
limiter.

10. Change in value of common mode input signal in differential pair amplifier make

a) Change in voltage across collector

b) Slight change in collector voltage

c) Collector voltage decreases to zero

d) None of the mentioned

View Answer
Answer: a

Explanation: In differential amplifier due to symmetry, both transistors are biased and matched.
Therefore, Voltage at each collector will be same.

11. Find collector current IC2, given input voltages are V1=2.078v & V2=2.06v and total current
IQ=2.4mA. (Assume α=1)

linear-integrated-circuit-mcqs-operational-amplifier-internal-circuit-1-q11

a) 0.8mA

b) 1.6mA

c) 0.08mA

d) 0.16mA

View Answer

Answer: a

Explanation: Collector current, IC2=αF×IQ/(1+eVd⁄VT),

VT = Volts equivalent of temperature = 25mv,

⇒ Vd = V1-V2 =2.078v-2.06v=0.018v (equ1)

Substituting equation 1,

⇒ Vd/VT = 0.018v/25mv = 0.72v (equ2)

Substituting equation 2,

⇒ IC2= 1×2.4mA/(1+e0.72) = 2.4mA/(1+2.05) = 0.8mA.

12. A differential amplifier has a transistor with β0= 100, is biased at ICQ = 0.48mA. Determine the value
of CMRR and ACM, if RE =7.89kΩ and RC = 5kΩ.

a) 49.54 db

b) 49.65 d

c) 49.77 db

d) 49.60 db

View Answer

Answer: b

Explanation: Differential mode gain, ADM= -gmRC and Common mode gain,
⇒ ACM= -(gmRC)/(1+2gmRE)

(for β0≫1).

Substituting the values,

⇒ gm= ICQ/VT = 0.48mA/25mv=19.2×10-3Ω-1

⇒ ADM= -gm×RC= -19.2×10-3Ω-1×5kΩ= -96

⇒ ACM= -(gmRC)/(1+2gmRE)= -(19.2×10-3Ω-1×5kΩ) /(1+2×-⇒ 19.2×10-3Ω-1×7.89kΩ) = -0.3158

CMRR = -96/-0.3158= 303.976

=20log⁡303.976

=49.65db

SANFOUNDRY OP-AMP 2:

1. How are the arbitrary signal represented, that are applied to the input of transistor? (Assume
common mode signal and differential mode signal to be VCM & VDM respectively).

a) Sum of VCM & VDM

b) Difference of VCM & VDM

c) Sum and Difference of VCM & VDM

d) None of the mentioned

View Answer

Answer: c

Explanation: In practical situation, arbitrary signal are signal are represented as Sum and Difference of
common mode signal and differential mode signal.

2. How the differential mode gain is expressed using ‘h’ parameter for a single ended output?

a) – hfeRC/hie

b) 1/2×(hfeRC)/hie

c) – 1/2×hfeRC

d) None of the mentioned

View Answer
Answer: b

Explanation: Formula for differential mode gain using ‘h’ parameter model for a single ended output.

3. Find Common Mode Rejection Ration, given gm =16MΩ-1, RE=25kΩ

a) 58 db

b) 40 db

c) 63 db

d) 89 db

View Answer

Answer: a

Explanation: Formula for Common Mode Rejection Ration, CMRR= 1+2gmRE,

⇒ CMRR = 1+(2×16MΩ-1×25kΩ)

= 801 = 20log⁡801 = 58.07 db.

4. In differential amplifier the input are given as V1=30sin⁡Π(50t)+10sin⁡Π(25t) , V2=30sin⁡Π(50t)-10

sin⁡Π(25t), β0 =200,RE =1kΩ and RC = 15kΩ. Find the output voltages V01, V02 & gm=4MΩ-1

a) V01=-60[10 sin⁡Π(25t) ]-6.637[30sin⁡Π(50t) ], V02=60[10 sin⁡Π(25t) ]-6.637[30sin⁡Π(50t) ].

b) V01=-6.637[10 sin⁡Π(25t) ]-60[30sin⁡Π(50t) ], V02=6.637[10 sin⁡Π(25t) ]-60[30sin⁡Π(50t) ].

c) V01=-60[30 sin⁡Π(50t) ]-6.637[10sin⁡Π(25t) ], V02=60[30 sin⁡Π(50t) ]-6.637[10sin⁡Π(25t) ].

d) V01=-6.637[30 sin⁡Π(50t) ]-60[10sin⁡Π(25t) ], V02=6.637[30 sin⁡Π(50t) ]-60[10sin⁡Π(25t) ].

View Answer

Answer: a

Explanation: Differential mode gain, ADM = -gm RC,

⇒ ADM = -4MΩ-1×15kΩ = 60

⇒ rΠ=β0/gm =200/4MΩ-1 =50kΩ

Common mode gain, ACM=-βo×RC/rΠ+(βO+1)×RE

⇒ ACM =-200×15kΩ/50kΩ+2(1+200)×1kΩ=-6.637

Common mode signal, VCM=(V1+V2)/2= 30sin⁡Π(50t)

Differential mode signal, VDM=(V1-V2)/2= 10 sin⁡Π(25t)

Output voltages are given as

⇒ V01=ADM)× VDM)+ ACM× VCM

= -60[10 sin⁡Π(25t)]-6.637[30sin⁡Π(50t)],

⇒ V02=-ADM× VDM+ ACM× VCM

= 60[10 sin⁡Π(25t)]-6.637[30sin⁡Π(50t)].

5. If the value of Common Mode Rejection Ratio and Common Mode Gain are 40db and -0.12
respectively, then determine the value of differential mode gain

a) 0.036

b) -1.2

c) 4.8

d) 12

View Answer

Answer: d

Explanation: Common mode rejection ratio, CMRR =log-1×(40/20) = 100

⇒ CMRR =(∣ADM∣/ ∣ACM∣)

⇒ ∣ADM∣ =100×0.12 = 12.

6. To increase the value of CMRR, which circuit is used to replace the emitter resistance Re in differential
amplifier?

a) Constant current bias

b) Resistor in parallel with Re

c) Resistor in series with Re

d) Diode in parallel with Re

View Answer

Answer: a

Explanation: Constant current bias offers extremely large resistor under AC condition and thus provide
high CMRR value.

7. What is the purpose of diode in differential amplifier with constant current circuit?

a) Total current independent on temperature

b) Diode is dependent of temperature

c) Transistor is depend on temperature

d) None of the mentioned

View Answer

Answer: a

Explanation: The base emitter voltage of transistor (VBE) in constant current circuit by 2.5mv/oc, thus
diode also has same temperature. Hence two variations cancel each other and total current IQ become
in depend of temperature.

8. How to improve CMRR value

a) Increase common mode gain

b) Decrease common mode gain

c) Increase Differential mode gain

d) Decrease differential mode gain

View Answer

Answer: b

Explanation: For a large CMRR value, ACM should be small as possible.

9. Define total current (IQ) equation in differential amplifier with constant current bias current

a) IQ=1/R3×(VEE/R1+R2)

b) IQ =(VEE×R2)/(R1+R2)

c) IQ=1/R3×(VEE×R2/R1+R2)

d) IQ)=R3×(VEE/R1+R2)

View Answer

Answer: c

Explanation: The equation for total current is obtained by applying Kirchhoff’s Voltage Law to constant
current circuit in differential amplifier.

10. Constant current source in differential amplifier is also called as

a) Current Mirror
b) Current Source

c) Current Repeaters

d) All of the mentioned

View Answer

Answer: a

Explanation: The output current is reflection or mirror of the reference input current. Therefore, the
constant current source circuit referred as Current Mirror.

11. When will be the mirror effect valid

a) β≫1

b) β=1

c) β<1

d) β≠1

View Answer

Answer: a

Explanation: If value of β is used in the equation, IC=β/(β+2)×Iref. It almost become unity and the output
current become equal to reference current.

12. Calculate the value of reference current and input resistor for current mirror with IC=1.2μA &
VCC=12v. Assume β=50.

a) 1.248mA, 9kΩ

b) 1.248mA, 9.6kΩ

c) 1.248mA, 9.2kΩ

d) 1.2mA, 9.6kΩ

View Answer

Answer: a

Explanation: We know that collector current, IC=β/(β+2)×Iref,

⇒ Iref=(β+2)/β×IC= (50+2)/50× 1.2μA = 1.248mA

⇒ Iref=(VCC-VBE)/R1
⇒ R1=(12v-07v)/1.248mA = 9.05kΩ.

SANFOUNDRY OP AMP – 3

1. Determine the early voltage, if the output resistance is 2.5×2kΩ and input current is 2mA

a) 9.8v

b) 5.6v

c) 7.8v

d) 10v

View Answer

Answer: d

Explanation: Output resistance, Ro=VA/Iref

⇒ VA = Ro×Iref =2.5×2kΩ×2mA =10v.

2. In practical application of current mirror, early voltage is assumed to be

a) Infinite

b) Zero

c) Unity

d) None of the mentioned

View Answer

Answer: a

Explanation: Early voltage is assumed to be infinity, so that output resistance tend to infinity and the
output current is constant.

3. A widlar current source is used

a) to get low value of current

b) to get high value of CMRR

c) to get low voltage of gain

d) to get high value of Output

View Answer
Answer: a

Explanation: In the widlar current source Re is added to emitter lead of transistor, which consequently
results in smaller output current value.

4. What will be the value of emitter resistance in widlar current source for output current 10mA, having
Iref=2.7A

a) 67/(1+1/β)Ω

b) 13/(1+1/β)Ω

c) 14/(1+1/β)Ω

d) 1.36/(1+1/β)Ω

View Answer

Answer: c

Explanation: Emitter resistor, RE=VT/(1+1/β) Iref×ln(Io/Iref)

⇒ RE= 0.025/(1+1/β)10mA × ln(12.7A/10mA) = 14/(1+1/β)Ω.

5. A current repeater having identical transistor has collector current, IC1 =0.39mA. Find IC2,IC4& IC6

a) 0.39mA, 0.39mA, 0.78mA

b) 0.78mA, 0.39mA, 0.39mA

c) 0.39mA, 0.78mA, 0.39mA

d) None of the mentioned

View Answer

Answer: d

Explanation: In current repeater, the current IC = IC1 =IC2 =⋯= IC N≅ Iref . Where, N – Number of
transistors used in current repeater circuit.

6. If the reference and collector current are 0.539mA and 0.49mA respectively, how many transistors are
used in current repeater circuit? (Assume β =150)

a) 11

b) 14

c) 10
d) 8

View Answer

Answer: b

Explanation: The current equation is given as IC= Iref×β/(β+1+N)

⇒ 0.49mA= 0.539mA×150/(150+1+N)

⇒ N=14.

7. For the current repeater shown in the circuit, determine IC4 value, Where β = 75.

linear-integrated-circuits-questions-answers-freshers-q7

a) 0.035mA

b) 0.028mA

c) 0.04mA

d) 0.052mA

View Answer

Answer: a

Explanation: The reference current, Iref = VCC-VBE/R1 =(15v-0.7v)/39kΩ = 0.366mA.

⇒ Iref=IC+4×IB

=IC(1+1/β)

∴ IC= Iref×(1+1/β)

=Iref×(1+1/β) = 0.366mA×(1+1/75) =0.347mA

⇒ IC1=IC2=IC3=0.347mA

To determine IC4,

RE=VT/(1+1/β)×IC4×ln(C3/IC4)

⇒ 1.62kΩ = 25mv/(1+1/75)×IC4×ln(0.347mA/IC4)

⇒ IC4=0.035mA (find using trial and error method).

8. The requirements for a good current source is the one in which, (Take Output current – IO and Output
resistance – rO )

a) IO independent upon current gain and should be low

b) rO should be very high

c) IO in the circuit should be low

d) IO independent upon current gain and rO should be very high

View Answer

Answer: d

Explanation: The need for high output resistance current source can be seen because the common mode
gain of the differential amplifier can only be reduced by using high resistance current sources.

9. Which current source exhibits a very high output resistance?

a) Simple current mirror

b) Wilson current mirror

c) Widlar current mirror

d) All of the mentioned

View Answer

Answer: b

Explanation: The output resistance of Wilson current mirror is substantially greater than ≅(β× Output
resistance)/2 than Simple or Widlar current source.

10. What will be the overall gain in Darlington circuit, if the individual transistor gain is 200?

a) 10000

b) 40000

c) 8000

d) 1000

View Answer

Answer: b

Explanation: Overall current gain, β= β1×β2 (Multiplication of current gain of individual transistor)

⇒ β=200×200=40000

11. To increase the input resistance in differential amplifier, replace the transistor by
a) Current mirror

b) Current repeater

c) Darlington pair

d) All of the mentioned

View Answer

Answer: c

Explanation: Higher value of input resistance can be obtained by using Darlington pair in place of
transistor.

12. What is the drawback in using Darlington pair in differential amplifier?

a) Large current gain

b) Output current in milli ampere

c) Gain is proportional to load resistor

d) High offset voltage

View Answer

Answer: d

Explanation: Due to cascaded stage, Darlington differential amplifier offers higher offset voltage which is
two times larger than ordinary two transistor used in differential amplifier.

13. Determine the amount of shift happens in level shifter?

a) Vcc + 0.7v

b) Vcc – 0.7v

c) -0.7v

d) +0.7v

View Answer

Answer: c

Explanation: Level shifter is basically a simple type emitter follower. Hence, level shifter also act as a
buffer to isolate high gain stages from the output stage. Therefore, the amount of shift obtained is

VO – Vi = -VBE = -0.7v
SANFOUNDRY OP-AMP 3:

1. To increase the input resistance, the differential amplifier replaces transistor by

a) Current mirror

b) Current repeater

c) Darlington pair

d) All of the mentioned

View Answer

Answer: c

Explanation: Higher value of input resistance can be obtained by using Darlington pair in place of
transistor.

2. In Darlington pair differential amplifier the current gain is given as 100. Where IB1=5µA and
IC1=0.35mA. Determine IC2

a) 0.5mA

b) 1.5mA

c) 2mA

d) 0.15mA

View Answer

Answer: d

Explanation: The current gain in Darlington pair differential amplifier is given as β=( IC1+IC2)/IB1.

Substituting the values in the equation, we get

IC2=(β×IB1)-IC1 =(100×5µA)-0.35mA =0.15mA.

3. In the circuit shown, find the overall current gain?

linear-integrated-circuits-interview-questions-answers-freshers-q3

a) 456218
b) 444878

c) 444210

d) 455734

View Answer

Answer: b

Explanation: From the circuit given, IB= IB1 = 5.6µA.

IE1= IB1+ IC1 = 1.43mA + 5.6µA = 1.435mA.

IE1= IB2 = 1.435mA.

The individual current gain values,

β1=IC1/ IB1

=> β1 = 1.43mA/5.6µA= 255.36.

Similarly,β2=IC2/ IB2

=> β2 = 2.5A / 1.435mA =1742.16

Therefore, the overall current gain, β = β1 × β2 = 255.36 × 1742.16 = 444878.

4. Introducing FET differential amplifier pair at the input stage of differential amplifier produces

a) High output resistance

b) High input resistance

c) Low input impedance

d) All of the mentioned

View Answer

Answer: b

Explanation: Input resistance of the order 1012 Ω is possible with JFET at the input stage of differential
amplifier.

5. Why active load is used in amplifier to obtain large gain in intermediate stage of amplifier?

a) To obtain a very large voltage gain

b) To get High input resistance

c) To reduce the noises

d) To increase current gain

View Answer

Answer: a

Explanation: To increase gain usually large collector resistance value as gain is proportional to load
resistor. However, due to limitation of maximum value load resistor, active loads are used in amplifier to
obtain large gain in intermediate stages of amplifier.

6. Which circuit is used as active load for an amplifier

a) Wildar Current source

b) Darlington pair

c) Current Mirror

d) All of the mentioned

View Answer

Answer: c

Explanation: Current mirror has DC resistance (order of few kΩ), as quiescent voltage across it is a
fraction of supply voltage and current in milliampere.

7. What is the equation of load current for a differential amplifier with an active load?

a) IL = gm×vd

b) IL = Iq /2

c) IL = β×Iq×( Vin1 – Vin2)

d) IL = 2×gm/( Vin1 – Vin2)

View Answer

Answer: a

Explanation: The load current is given as product of difference between input & output voltage and
transconductance. Therefore, the equation of load current is ,

IL = gm×vd.

8. The input voltage of a difference amplifier are 2.5v and 4.9v. If the transconductance is 0.065Ω-1,
determine the load current entering the next stage
a) 0.156A

b) 1.56A

c) 0.156mA

d) 15.6µA

View Answer

Answer: a

Explanation: Load current entering the next stages of amplifier is the sum of individual load current,
which is given by IL = IL1+ IL2 (Since only two input voltages are given).

IL = gm×Vin1 + gm×Vin2

= gm×( Vin1 – Vin2) = 0.065 Ω-1×(4.9v-2.5v) = 0.156A.

9. Calculate the VI – VO for the level shifter shown in the figure (Assume identical silicon transistor and
very large value of β). Transistor QA and QB form current mirror.

linear-integrated-circuits-interview-questions-answers-freshers-q9

a) 5.56V

b) 6.00v

c) 7.98v

d) 6.65v

View Answer

Answer: d

Explanation: Since the transistor QA and QB form current mirror, ICA= ICB = I.

=> I = (VCC – VBE) / R0 = (15v-0.7)/12k Ω (for β>>1, output current =input current)

=> I= 1.19mA.

The shift in level is given as VI – VO = VBE + I×R1 =0.07v+1.19mA×5kΩ =6.65v.

10. Load resistors (Re) is neglected for maximizing the voltage gain in amplifier because,

a) Requires large chip are

b) Requires large power supply

c) Quiescent drop across Re increases

d) All of the mentioned

View Answer

Answer: d

Explanation: As gain is proportional to load resistor, large resistance value is required. Due to limitation
mentioned, it is neglected.

11. What is the need for level shifter in operational amplifier?

a) Level the quiescent voltage

b) Remove distortion at output

c) Limits the output voltage

d) Increase the quiescent voltage

View Answer

Answer: c

Explanation: Because of direct couple, Dc level rises stages to stage and tends to shift operating point.
This limits output swing (Voltage).

12. Limitation of an output stage amplifier, if it emitter follower with complementary transistor

a) Cross-over distortion

b) Low impedance output

c) Shift in level

d) Active load current

View Answer

Answer: a

Explanation:The limitation in the amplifier is that , the output voltage remains zero until the input
voltage exceeds cut in voltage VBE= 0.5v, which is known as cross-over distortion.

13. An output stage amplifier can produce output signal, when the input signal is

a) 0.48v

b) 0.9v

c) 1.2v
d) 0.5v

View Answer

Answer: c

Explanation: In an Output stage amplifier, due to cross-over distortion output voltage produces input
voltage is greater than two times of cut-in voltage which is equal to 1v.

Since, VBE= 0.5v

=> 2×VBE= 1v.

14. Find the disadvantage in the following circuit diagram:

linear-integrated-circuits-interview-questions-answers-freshers-q14

a) Voltage get attenuated by R1

b) Voltage get attenuated by R2

c) Voltage get attenuated by R1 and R2

d) Voltage shift get increased by the drop across R1 and R2

View Answer

Answer: b

Explanation: The output taken at the junction of R1 and R2 increases the voltage shift. However, the
disadvantage is that, the signal voltage gets attenuated by R2.

=> R2/(R1 + R2).

SANFOUNDRY – ALU DATAPATH

1. The ‘heart’ of the processor which performs many different operations _____________

a) Arithmetic and logic unit

b) Motherboard

c) Control Unit

d) Memory

View Answer
Answer: a

Explanation: The Arithmetic and logic unit performs all the basic operations of the computer system. It
performs all the arithmetic(+,-,*,/,etc) as well as the logical operations( AND, OR, NOT, etc.).

2. ALU is the place where the actual executions of instructions take place during the processing
operation.

a) True

b) False

View Answer

Answer: a

Explanation: ALU is a combinational electronic circuit which basically performs all the logical or the
bitwise operations and the arithmetic operations. Therefore, it is the place where the actual executions
of instructions take place.

3. Which of the following is not a bitwise operator?

a) |

b) ^

c) .

d) <<

View Answer

Answer: c

Explanation: All except the dot(.) operator are bitwise operators.

| : Bitwise OR

^ : Bitwise XOR

<< : Shift Left

4. The sign magnitude representation of -1 is __________

a) 0001

b) 1110

c) 1000

d) 1001
View Answer

Answer: d

Explanation: The first leftmost bit i.e. the most significant bit in the sign magnitude represents if the
number is positive or negative. If the MSB is 1, the number is negative else if it is 0, the number is
positive. Here, +1=0001 and for -1=1001.

5. IEEE stands for ___________

a) Instantaneous Electrical Engineering

b) Institute of Emerging Electrical Engineers

c) Institute of Emerging Electronic Engineers

d) Institute of Electrical and electronics engineers

View Answer

Answer: d

Explanation: The IEEE is an organization of professionals in the field of electronics and electrical
engineering. IEEE has given certain standards of its own which are followed in the field of computer
science and electrical engineering.

6. The ALU gives the output of the operations and the output is stored in the ________

a) Memory Devices

b) Registers

c) Flags

d) Output Unit

View Answer

Answer: b

Explanation: Any output generated by the ALU gets stored in the registers. The registers are the
temporary memory locations within the processor that are connected by signal paths to the CPU.

7. The process of division on memory spaces is called ______________

a) Paging

b) Segmentation
c) Bifurcation

d) Dynamic Division

View Answer

Answer: b

Explanation: The memory space is divided into segments of dynamic size. The programmer is aware of
the segmentation and can reallocate the segments accordingly.

8. Number of bits in ALU is _________

a) 4

b) 8

c) 16

d) 2

View Answer

Answer: c

Explanation: Arithmetic and Logic Unit consists of 16bits. They perform certain Arithmetic and bitwise
operations (add, subtract, AND, OR, XOR, Increment, decrement, shift).

9. Which flag indicates the number of 1 bit that results from an operation?

a) Zero

b) Parity

c) Auxiliary

d) Carry

View Answer

Answer: b

Explanation: The parity flag indicates the number of 1 bit in any operation. The resultant bit is called the
parity bit. The main aim of the parity bit is to check for errors.

10. The bitwise complement of 0 is ___________

a) 00000001

b) 10000000
c) 11111111

d) 11111110

View Answer

Answer: c

Explanation: Bitwise complement is basically used to convert all the 0 digits to 1 and the 1s to 0s.

So, for 0 = 00000000(in 8-bits) ::: 11111111(1s complement). The bitwise complement is often referred
to as the 1s complement.