Technical Article

A Unified LTspice AC
Model for Current-Mode
DC-to-DC Converters
Wei Gu, Applications Director

Introduction Current-Mode Control Modeling: A Very

When a power supply designer wants to gain a general understanding of a power Brief Overview
supply’s feedback loop, they turn to Bode plots of loop gain and phase. Knowing Here, we’ll revisit some of the highlights of current-mode control modeling. For a
the loop response can be predictive, helping to narrow the field of feedback loop more complete understanding of current-mode modeling, turn to the publica-
compensation components. The most accurate way to produce the gain and phase tions noted in the References section at the end of this article.
plots is to put the supply on the bench and use a network analyzer, but in the early
stages of design, most designers prefer turning to a computer simulation, which The purpose of the current loop is to make the inductor current follow the control
can help them quickly settle on a rough range of components—and help build an signal. In the current loop, averaged inductor-current information is fed back
intuitive understanding of the loop response to parametric changes. to a modulator with sensing gain. Modulator gain Fm is derived by geometrical
calculations, assuming a constant inductor current ramp and an external ramp.
This article focuses on a feedback control model for current-mode control power To model the effect of the variation of the inductor current ramp, two additional
supplies. Current-mode control is popular in switch-mode DC-to-DC converters gains are added to the model: feed forward gain (kf) and feedback gain (kr), as
and regulators because it has a number of advantages over voltage-mode con- shown in Figure 1.
trol: better line noise rejection, automatic overcurrent protection, easy parallel
operation, and improved dynamic response. Vo (s)
Vg (s)
Power Stage
Designers already have access to a significant number of current-mode power Model iL (s)

supply average models. Some are accurate to half the switching frequency—
d (s)
matching the increasing bandwidth of converters—but only for limited topologies,
such as buck, boost, and buck-boost (not 4-switch buck-boost). Unfortunately, kf
Fm Ri kr
3-terminal or 4-terminal average models for use with topologies such as SEPIC and
Ćuk are not accurate up to half the switching frequency.
In this article, we present an LTspice® simulation model that is accurate up
to half the frequency (even relatively high frequency), for a wide range of
Vc (s)
topologies, including:
Figure 1. Average model for current-mode control by R. D. Middlebrook.
X Buck
In order to extend the validity of the average model as shown in Figure 1 into the
X Boost
high frequency range, several modified average models are proposed based on
X Buck-boost the results of discrete-time analysis and sample-data analysis. In R. B. Ridley’s
X SEPIC model (see Figure 2), sample-and-hold effects are equivalently represented by
X Ćuk the He(s) function, which is inserted into the feedback path of the inductor cur-
rent in the continuous average model. Due to its origination from the discrete-
X Forward
time model, this model can accurately predict subharmonic oscillations.
X Flyback

Simulation for piecewise linear system (SIMPLIS) results are presented to

confirm the validity of the new model, and specific applications of the model
are shown in examples. For some examples, bench results are used to validate
the model.

VISIT ANALOG.COM
 Vo (s) Based on this equation and the canonical switch model, current-mode converter
Vg (s)
Power Stage
Model iL (s)
models can be obtained.

d (s) A New Modified Average Model

Ri
R. W. Erickson’s model gives power supply designers excellent physical insight,
kf
Fm kr but it is not accurate up to half the switching frequency. In order to extend the
He (s)
validation of the model to the high frequency range, a modified average model
(see Figure 5) is proposed based on the results of discrete-time analysis and
sample-data analysis.

Vc (s)
Vo (s)
Vg (s)
Figure 2. Modified average model for current-mode control by R. B. Ridley. Power Stage
Model iL (s)

Another modified average model is proposed by F. D. Tan and R. D. Middlebrook.

d (s)
In order to consider the sampling effects in the current loop, one additional pole
must be added to a current-loop gain derived from the low frequency model, as Fg
Fm Ti Fv
shown in Figure 3.

Vo (s)
Vg (s)
Power Stage
Model iL (s)
Gic (s)
d (s)
ic (s)
Fm
kf Figure 5. Proposed modified average model for current-mode control.
Ri kr
1/(s/ωp+1)
Sampled-data modeling of inductor dynamics establishes:
^
iL (s) 1 – α 1 – e –sT
= (3)
i^ (s) 1 – αe
–sT sT
C
Vc (s)
where T is the switch period and
Figure 3. Modified average model for current-mode control by F. D. Tan.

In addition to R. B. Ridley’s model, the current programmed controller model ma

1–
m2
introduced by R. W. Erickson is also very popular. The inductor current waveform α =– (4)
1 – D + ma
is illustrated in Figure 4. D m2

Gic(s) of the model shown in Figure 5 can be derived:

(ic − ia (t))
s 1 – α 1 – e –sT
Gic (s) = (1+ ) (5)
ic ωc 1 – αe –sT sT
−ma
iL (t)

m1
where ωc is the crossover frequency of the inner current loop Ti as shown in
−m2
ILO Figure 5, with the values ωc of various topologies derived and shown in Table 1.

Table 1. Inner Current Loop Crossover Frequency (ωc)

by Topology

0 dT T t Topologies Current Loop (ωc)

Figure 4. Steady-state inductor current waveform with an external ramp. Buck VIN/L/Ma/T

The average inductor current is expressed as: Boost VO/L/Ma/T

d2T (1 – d)2T Buck-boost, Ćuk* (VIN – VO)/L/Ma/T

<iL (t)>T = < ic (t) >T – Ma dT –
2 m 1 (t) –
2 m2 (t) (1)
SEPIC* (VIN + VO)/L/Ma/T

where iL is the sensed current, ic is the current command from the error ampli- Flyback** (VIN + VO /NSP)/L/Ma/T
fier, Ma is the artificial ramp slope, and m1 and m2 are the upward and downward
Forward** VIN × NSP2 /L/Ma/T
slopes of output inductor current. Perturbation and linearization results in:

*For two separated inductors, L=L1×L2/(L1+L2)

1 ^ D2T ^ (1 – D)2T ^
d^ (t) = i (t) – ^iL (t) – – (2)
MaT c 2 m1 (t) 2 m2 (t)
**NSP is the turns ratio of secondary to primary

2 A Unified LTspice AC Model for Current-Mode DC-to-DC Converters

A Buck Converter Example 20

In Figure 5, we treat the Fv feedback loop and iL feedback loops in parallel. We

could also draw the Fv feedback loop as internal to the iL feedback loop. A com- 0
plete buck converter model with the added Gic(s) stage is shown in Figure 6.

–20
Vo (s)

Gain
Zo (s)

–40
Vg (s) V D iL (s)
D2 Zi (s)

d (s) –60
Ri LTspice Simulation
Fm Gain-SIMPLIS
Fg Tv –80
Fv 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Ti Frequency

Gic (s)

Vc (s)

Figure 6. Block diagram of the modified average model for a buck converter. –100

The control-to-output transfer function Gvc (s) is

Phase
Ti (s)
Gvc (s) = Zo (s) G (s) (6) –200
1 + Ti (s) ic

The current loop gain Ti (s) and voltage loop gain Tv (s) are calculated by: LTspice Simulation
Phase-SIMPLIS
–300
Ri Tv (s) 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Ti (s) = (7)
Zo (s)Fv 1 + Tv (s) Frequency

and Figure 7. MathCAD results vs. SIMPLIS results (fSW = 500 kHz).

Tv (s) = Fm
V Zo (s)
F (8) A 4-Terminal Model with LTspice
D Zi (s) v
A 4-terminal model is built based on the modified average model shown in
where, Figure 5. This 4-terminal model can be used to analyze any PWM topology for
DC and small-signal characteristics using a standard electronic circuit analysis
(1–2D)T
Fv = , program, such as the free LTspice, in closed-loop operation.
2L
1 Figure 8 shows LTspice simulation schematics for various topologies using the
Fm = ,
MaT same model for each. The feedback resistor divider, error amplifier, and compensa-
(9)
Ro tion components are not drawn here. To use the model with a real DC-to-DC con-
Zo (s) =
1 + sCoutRo and verter model, the output of the error amplifier should be connected to the VC pin.
Ro
Zi (s) = + sL
1 + sCoutRo
In Figure 7, calculated loop gain based on the new current-mode model agrees
well with SIMPLIS results. In this example, VIN = 12 V, VOUT = 6 V, IOUT = 3 A, L = 10 µH,
COUT = 100 µF, and fSW = 500 kHz.

VISIT ANALOG.COM 3
 L L OUT
IN OUT IN

VIN VIN
Cout Cout
Ro
Ro

Drain Cathode Drain Cathode

Source Anode Source Anode
Vc Vc
VC Von VC Von
E1 E1
Current Voff Current Voff
D Vslope D Vslope
LTAVG E2 LTAVG E2
V3 V3

Ei Ei

(a) Buck (b) Boost

L1 SW C1 L1 SW C1 L2
IN SWB OUT IN SWB OUT

VIN Cout VIN Cout

L2 Ro Ro

Drain Cathode Drain Cathode

Source Anode Source Anode
Vc Vc
VC Von VC Von
E1 E1
Current Voff Current Voff
D Vslope D Vslope
LTAVG E2 LTAVG E2
V3 V3
Ei Ei

(c) SEPIC (d) Ćuk

IN OUT

VIN P-dot S-dot Cout

L Ro
P S
Transformer

Drain Cathode
Source Anode
Vc
VC Von
E1
Current Voff
D Vslope
LTAVG E2
V3
Ei

(e) Flyback

Figure 8. Using the LTspice model for various topologies: (a) buck, (b) boost, (c) SEPIC, (d) Ćuk, and (e) flyback.

4 A Unified LTspice AC Model for Current-Mode DC-to-DC Converters

The various LTspice behavioral voltage source directives in Figure 8 are shown 50
in Table 2. E1 is the voltage across the inductor when the switch is on, E2 is the
40
voltage when the switch is off, V3 is the slope compensation amplitude, and Ei is
the inductor current. 30

20
Table 2. LTspice Behavioral Voltage Source Directives
for the Circuits in Figure 8 10

Gain
0
Topology E1 E2 V3 Ei
–10
Buck V(IN) – V(OUT) V(OUT) Ma/fsw i(L)
–20
Boost V(IN) V(OUT) – V(IN) Ma/fsw i(L)
LTspice Simulation
–30
Gain-SIMPLIS
V(SW) – V(SWB) + V(OUT) + V(SW) – V(SWB)
SEPIC Ma/fsw i(L1) + i(L2) –40
V(IN) – V(IN) 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Frequency
V(SW) – V(SWB) + V(OUT) + V(SW) – V(SWB)
Ćuk Ma/fsw i(L1) + i(L2) 120
V(OUT) + V(IN) – V(IN)
100
Flyback V(IN) V(OUT)/Nsp Ma/fsw i(L)
80

60
The simulation results for a SEPIC converter with two separated inductors are
40
shown in Figure 9, which match the SIMPLIS results up to half the switching
20
frequency. In this example: VIN = 20 V, VOUT = 12 V, IOUT = 3 A, L = 4.7 µH, COUT = 120 µF,

Phase
C1 = 10 µF, and fSW = 300 kHz. 0

–20

–40

–60
LTspice Simulation
–80
Phase-SIMPLIS
–100
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Frequency
Figure 9. LTspice results vs. SIMPLIS results for a SEPIC converter (fSW = 300 kHz).

L1 DCR1 C1 DCR2 L2 OUT

{L} 0.1 Ω 2.2 μF 0.1 Ω {L}

VIN Cout
RL
12 V 6 μF 20 Ω
AC 1

VAC

SW Cathode RTOP
VIN Anode 60.4 kΩ
VOUT
Boost_op
Sepic_op FB
Cuk_op VC
.Param fsw = 2000 kHz LT3580 Cc2 Rc1 Cc1
.Param L = 4.7 μH 10 kΩ
47 pF 4.7 nF

Figure 10. LT3580 LTspice model.

VISIT ANALOG.COM 5
 60 Bench Verification of the New Models
LTspice Simulation
Bench Test Results
The new LTspice models in Figure 11 were bench verified for topologies previ-
40 ously unsupported by traditional models, including Ćuk, and 4-quadrant and
4-switch buck-boost.
20
Verifying the Ćuk Regulator Model on the Bench
The LT3580 is a PWM DC-to-DC converter containing an internal 2 A, 42 V switch.
Gain

The LT3580 can be configured as either a boost, SEPIC, or Ćuk converter, and its AC
–20 model can be used for all of these topologies. Figure 10 shows a Ćuk converter
with fSW = 2 MHz and VOUT = –5 V. Figure 11 compares the LTspice simulation Bode
–40 plots with bench results—they match well up to half the switching frequency.

–60 Verifying a 4-Quadrant Regulator Model on the Bench

100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Frequency The LT8714 is a synchronous PWM DC-to-DC controller designed for a 4-quadrant
output converter. The output voltage cleanly transitions through zero volts
180
LTspice Simulation
with sourcing and sinking output current capability. The LT8714 is ideal for
Bench Test Results regulating to positive, negative, or zero-volt outputs when configured for the
120
novel 4-quadrant topology. Applications include 4-quadrant power supplies, high
60
power bidirectional current sources, active loads, and high power, low frequency
signal amplification.
Phase

0 Based on the CONTROL pin voltage, the output can be positive or negative. In
the example shown in Figure 12, when the pin voltage is 0.1 V, the output is –5 V,
–60 and when the pin voltage is 1 V, the output is 5 V, VIN is 12 V, and the switching
frequency is 200 kHz.
–120
Figure 13 compares the LTspice simulation Bode plots with those produced on
–180
the benchtop—they match well up to half the switching frequency. The control
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz voltage (CONTROL) is 1 V, which sets VOUT (OUT) to 5 V.
Frequency

Figure 11. Bode plot (fSW = 2 MHz).

IN L1 R1 SW C1 SWB L2 R2 OUT
.Param fsw = 200 kHz
.Param L = 10 μH
{L} 0.02 Ω 20 μF {L} 0.02 Ω
.Param Rs = 0.0025
.Param RTOP = 73.2 kΩ VIN C2
R3
C3 R4
12 V 120 μF 1Ω AC 1
80 μF 1Ω VAC
R7
0.005 Ω

Drain Cathode RTOP

{RTOP}
V = v(SW) − v(SWB) + V(OUT) + V(IN) Source Anode
Von FB
E1 Control
Voff Control
E2 Vc
Current Vc
D Rc
E3 LT8714
6.98 kΩ
V = −v(OUT) + v(SW) − v(SWB) + v(IN) E4 Vctrl
Cc 0.1 V
V = i(L1) + i(L2)
10 nF

Figure 12. A 4-quadrant regulator LTspice model using the LT8714.

6 A Unified LTspice AC Model for Current-Mode DC-to-DC Converters

 80 80
LTspice Simulation
LTspice Simulation
Bench Test Results
60 60 Bench Test Results

40 40

20 20

Gain
Gain

0 0

–20 –20

–40 –40

–60 –60
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Frequency Frequency

200 200
LTspice Simulation LTspice Simulation
150 Bench Test Results 150 Bench Test Results

100 100

50 50

Phase
Phase

0 0

–50 –50

–100 –100

–150 –150

–200 –200
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Frequency Frequency
Figure 13. Bode plot (fSW = 200 kHz). Figure 14. Bode plot (fSW = 200 kHz).

L1 R2 OUT
IN
{L} 0.001 Ω
Cout Cout1
VIN
C1 660 μF 660 μF Rload
20 V 2.4 Ω
66 μF
Resr Resr1
SW1 SW2 0.006 Ω 0.006 Ω
VIN VOUT

Vc
VC FB AC 1
LT8390AC RTOP V1
Rc
Cc1 {RTOP}
15 kΩ .Param fsw = 150 kHz
.Param L = 3.3 μH RBOT
Cc 100 pF .Param Rs = 0.002
10 nF .Param RTOP = 549 kΩ {RBOT}
.Param RBOT = 49.9 kΩ

Figure 15. LT8390 LTspice model.

Figure 14 compares the LTspice simulation Bode plots with bench results— The LT8390 LTspice AC model monitors the input and output voltages and auto-
matching well up to half the switching frequency. The control voltage (CONTROL) is matically picks one of the four operation modes: buck, peak-buck, peak-boost,
0.1 V, which sets VOUT (OUT) to –5 V. and boost. An LT8390 example circuit is shown in Figure 15. The LTspice simula-
tion and bench results are shown in Figure 16 and Figure 17 for buck and boost
Verifying a 4-Switch Buck-Boost Model on the Bench
mode, respectively. The curves match well up to half the switching frequency.
The LT8390 is a synchronous 4-switch buck-boost DC-to-DC controller that can
regulate the output voltage (and input or output current) from an input voltage
above, below, or equal to the output voltage. The proprietary peak-buck/peak-
boost current-mode control scheme allows adjustable fixed frequency operation.

VISIT ANALOG.COM 7
 50 50
LTspice Simulation LTspice Simulation
40 40
Bench Test Results Bench Test Results
30 30

20 20

10 10

Gain
Gain

0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Frequency Frequency

120 100
LTspice Simulation LTspice Simulation
100 Bench Test Results 80 Bench Test Results

80 60

60 40

40 20

Phase
Phase

20 –20
0

0 –40

–20 –60

–40 –80

–60 –100
10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
Frequency Frequency

Figure 16. Bode plot (fSW = 150 kHz). VIN = 20 V, VOUT = 12 V, and IOUT = 5 A. Figure 17. Bode plot (fSW = 150 kHz). VIN = 8 V, VOUT = 12 V, and IOUT = 5 A.

Summary Li, Jian, and Lee, Fred C. “New Modeling Approach and Equivalent Circuit
Representation for Current-Mode Control,” IEEE Transactions on Power Electronics,
A current-mode control model is established to provide both the accuracy of the
Vol. 25, No. 5, May 2010.
sample-data model and the simplicity and versatility of a 4-terminal switch model.
A unified LTspice model—accurate up to half the switching frequency—for buck, Maksimović, Dragan. “Current Programmed Control,” ECEN 5807, University of
boost, buck-boost, SEPIC, Ćuk, flyback, and forward topologies is presented. The Colorado, 2009.
LTspice results are validated by bench data. The model is intended for loop analysis
Middlebrook, R. D. “Modeling Current-Programmed Buck and Boost Regulators,”
in design of current-mode converters in continuous conduction mode.
IEEE Transactions on Power Electronics, Vol. 4, No. 1, January 1989.
References Ridley, R. B. “A New, Continuous-Time Model for Current-Mode Control (Power
Basso, Christophe P. Switch-Mode Power Supply SPICE Cookbook, 1st edition, Converters),” IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991.
McGraw-Hill, 2001.
Tan, F. D., and Middlebrook, R. D. “A Unified Model for Current-Programmed
Erickson, Robert W., and Maksimovic, Dragan. Fundamentals of Power Electronics, Converters,” IEEE Transactions on Power Electronics, Vol. 10, No. 4, July 1995.
2nd edition, Chapter 11, Kluwer (Springer), 2001.

8 A Unified LTspice AC Model for Current-Mode DC-to-DC Converters

About the Author
Wei Gu is an applications director for power products. He has been with
Analog Devices (formerly Linear Technology) since 2006. He received
a B.S. in electrical engineering from Zhejiang University and a Ph.D. in
electrical engineering from the University of Central Florida. He can be
reached at [email protected].

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