ASIC Cell Delay Model Table Look-Up Method

 Three approaches for gate propagation delay

computation are based on: Cload (fF )
– Delay look-up tables
0 5 10 500 505 510
– K-factor approximation 50
– Effective capacitance
70
 Delay look-up table is currently in wide use especially 115pS
90
in the ASIC design flow T in (pS)
Effective capacitance promises to be more accurate
110


when the load is not purely capacitive

310
330

◼ What is the delay when Cload is 505f F and Tin is 90pS?

22 23

K-factor Approximation One Dimensional Table

-11
x 10 x 10
-11
11
tr (C1) = tr1
Size=69 Cout=23fF 11
Size=60 Tin=300pS
Size=48 Cout=15fF Size=81 Tin=350pS
10
Size=90 Cout=18fF 10 Size=45 Tin=200pS
Output Transition time (s)
Output Transition time (s)

9
tr (C2 ) = tr 2
8
9
Linear model
7
8
tr (C ) = a1C + a2
7
t − tr1
6

5
6 a1 = r 2
C2 − C1
1 1.4 1.8 2.2 2.6 3
2 2.4 2.8 3.2 3.6 4 -14
-10 x 10
10 -14
Input Transition Time (s) x 1010-10 CLoad (F)
t C − tr 2C1
a 2 = r1 2
We can fit the output transition time v.s. input C2 − C1
transition time and output load as a polynomial
function, e.g.
t − tr1 t C − tr 2C1
Toutput = k1 + k2Cload + Tin (k3 + k4Cload ) − k5Cload 2 tr (CL ) = r 2 CL + r1 2
C2 − C1 C2 − C1
A similar equation gives the gate delay

24 25

Two Dimensional Table Second-order RC- Model

◼ Using Taylor Expansion around s = 0

D1 D2
T in
R
D3 D4
T in Gate /Cell
Gate /Cell
C1 C2

Quadratic model

Yin (s) = A1s + A2s 2 + A3s3 + ..... Y in (s) = (C1 + C2 )s − R C22s 2 + R 2C23s3 + .....
D(C , tin ) = k1 + k2CL + k3tin + k4C Ltin

 k1  ( D4C1t1 − D3C2t1 − D2C1t2 + D1C2t2 ) / W 

k 2  ( D3t1 − D4t1 − D1t2 + D2t2 ) / W 
 k 3 =  ( D2C1 − D4C1 − D1C2 + D3C2 ) / W  A2 2 A32 A2 2
k 4  ( D1 − D2 − D3 + D4 ) / W  C1 = A1 − R = − C2 =
    A3 A2 3 A3

W = (C1 − C2 )(t1 − t2 )
26 27
 Second-order RC- Model (Cont’d)
Effective Capacitance Approach
T in
R
T in
Gate /Cell R
C1 C2 Gate /Cell
C1 C2

Gate Delay = f (Tin , C1, R , C2 )

T in

This equation requires creation of a four-

Gate /Cell
◼
dimensional table to achieve high accuracy
C eff

The “Effective Capacitance” approach attempts to

◼ This is however costly in terms of memory find a single capacitance value that can be replaced
space and computational requirements instead of the RC- load such that both circuits
behave similarly during transition

28 29

Effective Capacitance (Cont’d)

Output Response for Effective Capacitance

30 31

Effective Capacitance (Cont’d) Effective Capacitance for Different

Resistive Shielding

T in T in
R
Gate /Cell Gate /Cell
C1 C2 C eff

Ceff = C1 + kC2 0<k<1

◼ Because of the shielding effect of the interconnect resistance ,

the driver will only “see” a portion of the far-end capacitance C2

R  k=1
R ∞ k=0
32 33
 Macy’s Iterative Solution
Macy’s Approach
Tin1
1. Compute  from C1 and C2 GATE 1
R

Tin1
R
Tin2
R 2. Choose an initial value for C1 C2

GATE 1 GATE 2 Ceff

C1 C2 C1 C2
3. Compute Tout for the given =
C1
=
Tout
Ceff and Tin C1 + C2 R C2
4. Compute 
5. Compute  from  and 
Assumption: If two circuits have the same loads and
output transition times, then their effective 6. Find new Ceff
capacitances are the same 7. Go to step 3 until Ceff
=> the effective capacitance is only a function of the converges =
Ceff
output transition time and the load C1 + C2

34 35

Summary References
 Delay model ⚫ R. Macys and S. McCormick, “A New Algorithm for Computing
– Elmore delay the “Effective Capacitance” in Deep Sub-micron Circuits”,
– Gate delay: look-up table, k-factor Custom Integrated Circuits Conference 1998, pp. 313-316
approximation, effective capacitance ⚫ J. Cong, Z. Pan and P. V. Srinivas, "Improved Crosstalk
Modeling for Noise Constrained Interconnect Optimization",
Asia and South Pacific Design Automation Conference 2001,
pp. 373-378
⚫ L. H. Chen, M. M.-Sadowska, “Aggressor Alignment for
Worst-case Coupling Noise”, International Symposium on
Physical Design 2000, pp. 48-54

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Homework Homework
[1] Given the circuit as shown below and a unit step voltage [2] Give the circuit as shown below and a unit step voltage
source at the input node s, use SPICE to simulate the circuit source at node s, can we still use the “shared-path” formula to
and obtain the accurate 50% delay at node n. Also analytically calculate the Elmore delay? Explain why or why not. Use DC
calculate the delay using Elmore method and S2P method. How analysis method via MATLAB or SPICE to get the 0th -3rd
do they compare with the result obtained by SPICE? moments of C3 and C5.

R1 = 1mΩ
R1 = 1mΩ R1 R2 = 2mΩ
R1 R2 = 2mΩ s R3 = 2mΩ
s R3 = 2mΩ R3 R4 = 1mΩ
1v R3 R4 = 1mΩ 1v
C1
C1 R5 = 4mΩ n C1 = 1nF
n C6 C2 = 1nF
R5 C1 = 1nF C3 = 4nF
C2 = 1nF C3
C4 = 4nF
C3
C3 = 4nF C5 = 2nF
C4 = 4nF C6 = 1nF
C5 = 2nF C5
C5

38 39