Assignment 5 – Sanskar Sengar 1

Lab Assignment 5
Sanskar Sengar
E23CSEU0667

Question 1 What are Combinational and Sequential circuits?

Discuss in brief with appropriate block
diagram and examples.
Answer 1.1
Combinational Circuits: Combinational circuits are characterized by their outputs,
which depend only on the current inputs at any given time. They do not have memory
or a feedback loop, meaning the output is a pure function of the present input values.
Combinational circuits implement logical functions such as AND, OR, NOT, XOR, etc.,
and can be more complex functions like adders, multiplexers, and comparators.

Example: Adders (perform addition), Encoders (convert information from one format
or code to another), Multiplexers (select one out of several input signals).

Sequential Circuits: Sequential circuits, unlike combinational circuits, have memory.

Their output depends not only on the current inputs but also on the history of inputs.
This is because sequential circuits incorporate storage elements, like flip-flops or
latches, which can store bits of information. Sequential circuits are characterized by
the presence of feedback loops, allowing the circuit to maintain a state or memory of
past inputs. They can be further divided into synchronous (clock-driven) and
asynchronous (event-driven) circuits.

1.1
Assignment 5 – Sanskar Sengar 2

Example : Flip-Flops (basic memory element storing one bit of information), Counters
(increment or decrement in response to input pulses), Registers (store multiple bits
of data)

Question 2 Draw and explain 4-bit Controlled Inverter/

Buffer using Ex-OR gates.
Answer 2.1

2.1
Assignment 5 – Sanskar Sengar 3

When control is low, word passes through unchanged: Y = A

Ex: Let control = 0, A = In0, In1, In2, In3 then Y(Output of XOR gate) = In0, In1, In2,
In3

When control is high, word passes through inverted: Y = (not A)

Let control = 1, A = In0, In1, In2, In3 then Y(Output of XOR gate) = (In0, In1,

In2, In3) i.e Complement of input.

Control Input (In0) Output (Out0)

0 1 1
0 0 0
1 0 1
1 1 0
Question 3 Write truth table and Verilog code to implement
Half Adder using basic gates.
Answer 3.1
Design File:
module main ( input
a , input b,
output sum,
output carry
);

assign sum = aˆb; assign

carry = a && b; endmodule
//main

Testbench File: module

main tb ;

reg A,B; wire S,C; main q1 (. a(A) , .b(B) , .sum(S) , . carry

(C));

3.1
Assignment Assignment 5 – Sanskar Sengar 4

initial begin
$display(”A B SUM CARRY” );
$display(” ” );
end

initial begin
$monitor(”%d %d %d %d” ,A,B,S,C);
A = 0; B = 0; #10;
A = 1; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 1; #10;

$finish ; end

endmodule

Truth Table:

Table 1: Truth Table for a Half Adder

A B SUM CARRY
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1
Output:

3.1
Question 4 Write truth table and Verilog code to im-
Assignment 5 – Sanskar Sengar 5

plement Full Adder using Ex-OR and AND gates

Answer 4.1
Design File:
module full adder (
input a , input b,
input Cin , output
Sum, output Cout
);

wire A xor B ; wire

A and B ; wire B
and Cin ; wire A
and Cin ;

assign A xor B = a ˆ b; assign Sum = A

xor B ˆ Cin ;

assign A and B = a & b; assign B

and Cin = b & Cin ; assign A and Cin
= a & Cin ;

assign Cout = A and B | B and Cin | A and Cin ;

endmodule

Testbench File: module

main tb ;

reg A,B,C; wire sum, carry ; full adder q4 (. a(A) , .b(B) , . Cin(C) , .Sum(sum) , .
Cout( carry ) );

4.1
$display(”A B Cin SUM CARRY” ); end
initial begin
$monitor(”%d %d %d %d %d” , A,B,C,sum, carry
A = 0; B = 0; C = 0; #10;
Assignment Assignment 5 – Sanskar Sengar 6

initial begin
A = 0; B = 0; C = 1; #10;
A = 0; B = 1; C = 0; #10;
A = 0; B = 1; C = 1; #10;
A = 1; B = 0; C = 0; #10;
A = 1; B = 0; C = 1; #10;
A = 1; B = 1; C = 0; #10;
A = 1; B = 1; C = 1; #10; end
endmodule

Truth Table:

Table 2: Truth Table for a Full Adder

A B Cin SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Output:

4.1
Question 5 Write truth table and Verilog code to im-
plement Half Subtractor using only NAND gates.
Answer 5.1
Design File:
Assignment 5 – Sanskar Sengar 7

module half subtractor nand (

input a , input b, output d,
output Borrow
);

wire nand1 , nand2 , nand3 , nand4 , nand5 , nand6 , nand7 ;

assign nand1 = ˜(a & b ); assign nand2

= ˜(a & nand1 ); assign nand3 = ˜(b &
nand1 ); assign d = ˜(nand2 & nand3 );

assign nand4 = ˜(a & a ); assign nand5 =

˜(nand4 & b ); assign nand6 = ˜(nand4 &
nand4 ); assign nand7 = ˜(nand6 &
nand5 ); assign Borrow = nand7 ;
endmodule

Testbench File:
module main nand tb ; reg A,B; wire D, Borrow ; half subtractor nand q5 (. a(A) , .b(B) ,
.d(D) , . Borrow(Borrow ));

initial begin
$display(”A B DIFF CARRY” );
$display(” ” );
end

5.1
$monitor(”%d %d %d %d” ,A,B,D, Borrow );
A = 0; B = 0; #10;
A = 1; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 1; #10;

$finish ;
end endmodule

Truth Table:
Assignment Assignment 5 – Sanskar Sengar 8

initial begin
Table 3: Truth Table for Binary Subtraction
A B DIFF CARRY
0 0 0 1
1 0 1 0
0 1 1 1
1 1 0 0
Output:

5.1