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A1 - 16010322019 - 2 - HDL - Mux Using Structural Modelling

The document describes an experiment on implementing a 4:1 multiplexer using structural modeling in VHDL. It includes the aim, outcomes, VHDL code, circuit diagram, RTL schematic, simulation results, and post-lab questions for designing a 4:1 demultiplexer.

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divay.galani
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17 views

A1 - 16010322019 - 2 - HDL - Mux Using Structural Modelling

The document describes an experiment on implementing a 4:1 multiplexer using structural modeling in VHDL. It includes the aim, outcomes, VHDL code, circuit diagram, RTL schematic, simulation results, and post-lab questions for designing a 4:1 demultiplexer.

Uploaded by

divay.galani
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Somaiya Vidyavihar University

K. J. Somaiya College of Engineering, Mumbai -77


(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics and Telecommunication Engineering

Batch: A1 Roll No.: 16010322019


Experiment No. 02
DIVAY HEMENDRA GALANI Grade: AA / AB / BB / BC / CC / CD /DD

Signature of the faculty In-charge with date

Experiment No: 2
TITLE: Implementation of Multiplexer using Structural Modeling
AIM: i. Design 4:1 mux using with select.
ii. Write VHDL code for 4:1 mux using Structural modeling (2:1 mux
as acomponent).
iii. Verification of code using simulation.
iv. Verification of hardware results using CPLD/FPGA.CPLD/FPGA.
OUTCOME: Student will be able to
CO1: Describe combinational logic circuit using HDL
CO3: Simulate HDL code
CO4: Implement and verify of designed code on CPLD/FPGA

 VHDL Code:

1. VHDL Code for 4:1 mux using with select.

HDL/ Sem IV/ Jan- May 24


Somaiya Vidyavihar University
K. J. Somaiya College of Engineering, Mumbai -77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics and Telecommunication Engineering

 Circuit/Block Diagram:

 RTL Schematic:

 Simulation results:

2. VHDL Code for 4:1 mux using structural modeling.

 Circuit/Block Diagram:

 RTL Schematic:

 Simulation results:

HDL/ Sem IV/ Jan- May 24


Somaiya Vidyavihar University
K. J. Somaiya College of Engineering, Mumbai -77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics and Telecommunication Engineering

Post lab Questions

Design a 4:1 De-mux.

HDL/ Sem IV/ Jan- May 24


Somaiya Vidyavihar University
K. J. Somaiya College of Engineering, Mumbai -77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics and Telecommunication Engineering

CONCLUSION:

Signature of faculty in-charge

HDL/ Sem IV/ Jan- May 24

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