Volume III, Issue XI, November 2014 IJLTEMAS ISSN 2278 - 2540

A High Speed and Low Power Flip-Flop Design

Using Topologically Compressed Technique
R.Mohan1, K.Nanthakumar2
1
ASP/ECE, 2M.E VLSI Design
M.P.Nachimuthu M.Jaganathan Engineering College, Erode, Tamil Nadu.

Abstract—An extremely low-power flip-flop (FF) named Finally, in Section VII, we show the way to apply the
topologically-compressed flip-flop (TCFF) is proposed. As proposed FF effectively to various systems in view of
compared with conventional FFs, the FF reduces power power and performance.
dissipation by 75%. This power reduction ratio is the highest
among FFs that have been reported so far. The reduction is
achieved by applying topological compression method,
merger of logically equivalent transistors to an
unconventional latch structure. The very small number of
transistors connected to clock signal reduces the power
drastically, and the smaller transistor count assures the
reduces cell area as conventional FFs. Inaddition, fully
static full swing operation makes the cell tolerant of supply
voltage and input slew variation. An experimental chip
design with 25nm CMOS technology shows that almost all Fig.1.Conventional transmission-gate flip-flop(TGFF).
conventional FFs are replaceable with proposed FF while
preserving increasing system performance and reduces the
layout area.

Index Terms— Flip-flops, Tranmission gate, low-power,

CMOS, VLSI.

I. INTRODUCTION

T he mobile market keeps on expanding. In addition to

the conventional mobile phone, digital camera, and
tablet PC, development of various kinds of wearable
Fig.2.Differentialsense-amplifier flip-flop (DiffFF).

information equipment or healthcare associated equipment II. BACKGROUND

has newly
prospered in recent years. In those kinds of battery- In this section, we analyze problems on previously
working equipment, reduction of power is a very reporte-d typical low power FFs with comparison to a
important issue, and demand for power reduction in LSI is conventional FF shown in Fig. 1.
increasing. Based on such background, various kinds of
circuit technique have already been proposed. In LSI, Fig. 2 shows a typical circuit of differential sense
generally more than half of the power is dissipated in amplifier type FF (DiffFF) [1]–[3]. This type of circuit is
random logic, of which half of the power is dissipated by very effective to amplify small swing signals, so is
flip-flops (FFs). During the past dozen years, several low- generally used in output of memory circuits. In this FF,
power FFs have been rushed into development. However, however, the effect of power reduction goes down in the
in actual chip design, the conventional FF is still used condition of lower data activity, because these kinds of
most often as a preferred FF because of its well-balanced circuits have precharge operation in every clock low state.
power, performance and cell area. The purpose of this Moreover, if we use reduced clock swing, a customized
paper is to present a solution to achieve all of the goals: clock generator and an extra bias circuit are necessary.
power reduction without any degradation of timing
performance and cell area. Fig. 3 shows a circuit of conditional clocking type FF
(CCFF) [4]–[6]. This circuit is achieved from a functional
In Section II, we review existing low-power FFs. In point of view. The circuit monitors input data change in
Section III, we show our design approach. In Section IV, every clock cycle and disables the operation of internal
we propose FF realization with a new methodology. In clock if input data are not changed. By this operation,
Section V, the detailed power and performance power is reduced when input data are not changed. But
characteristics are shown compared to other FFs. In unfortunately, its cell area becomes almost double that of
Section VI, we show the effect of the proposed FF in the conventional circuit shown in Fig. 1
actual chip design by experimental layout. .

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Volume III, Issue XI, November 2014 IJLTEMAS ISSN 2278 - 2540
variation. Thus, their optimization is relatively difficult,
and performance degradation across various process
corners is a concern.
Let us summarize the analysis on previously reported low
power FFs. For DiffFF [1] and XCFF [7], pre-charge
operation is a concern especially in lower data activity. As
regards CCFF [4], its cell area becomes a bottleneck to
use. And for ACFF

Fig.3.Conditional-clocking flip-flop(CCFF).

Fig.6.Example of combinational type FF.

[9], tolerance for input clock slew variation becomes
subject to resolve.

III. DESIGN APPROACH

Fig.4.Cross-charge control flip-flop(XCFF). In order to reduce the power of the FF while keeping
competitive performance and similar cell area, we tried to
reduce the transistor count, especially those operating with
clock signals, without introducing any dynamic or pre-
charge circuit. The power of the FF is mostly dissipated in
the operation of clock-related transistors, and reduction of
transistor count is effective to avoid cell area increase and
to reduce load capacitance in internal nodes. In the
conventional FF shown in Fig. 1, there are 12 clock-related
transistors. To reduce clock-related transistor counts
directly from this circuit is quite difficult. One reason is
because transmission-gates need a 2-phase clock signal,
Fig.5.Adaptive-coupling flip-flop(ACFF).
thus the clock driver cannot be eliminated. Another reason
And mainly due to this size issue, it becomes hard to use is that transmission-gates should be constructed by both
if the logic area is relatively large in the chip. PMOS and NMOS to avoid degradation of data transfer
Fig. 4 shows the circuit of cross-charge control FF characteristics caused by single-channel MOS usage.
(XCFF) [7]. The feature of this circuit is to drive output Therefore, instead of transmission-gate type circuit, we start
transistors separately in order to reduce charged and with a combinational type circuit as shown in Fig. 6. To
discharged gate capacitance. However, in actual reduce the transistor-count based on logical equivalence,
operation, some of the internal nodes are pre-set with we consider a method consisting of the following two steps.
clock signal in the case of data is high, and this operation As the first step, we plan to have a circuit with two or more
dissipates extra power to charge and discharge internal logically equivalent AND or OR logic parts which have the
nodes. As a result, the effect of power reduction will same input signal combination, especially including clock
decrease. Circuits including pre-set operation have the signal as the input signals. Then, merge those parts in
same problem [8]. transistor level as the second step.
The adaptive-coupling type FF (ACFF) [9], shown in Fig.
5, is based on a 6-transistor memory cell. In this circuit, IV. PROPOSED TOPOLOGICALLY-COMPRESSED
instead of the commonly used double-channel FLIP-FLOP
transmission-gate, a single channel transmission-gate with
additional dynamic circuit has been used for the data line A. Proposed FF and Transistor Level Compression After
in order to reduce clock-related transistor count. However, investigating many kinds of latch circuits, we have set up
in this circuit, delay is easily affected by input clock slew an unconventionally structured FF, shown in Fig. 7. This
variation because different types of single channel FF consists of different types of latches in the master and
transmission-gates are used in the same data line and the slave parts. The slave-latch is a well-known Reset-Set
connected to the same clock signal. Moreover, (RS) type, but the master-latch is an asymmetrical single
characteristics of single channel transmission-gate circuits data-input type. The feature of this circuit is that it operates
and dynamic circuits are strongly affected by process in single phase clock, and it has two sets of logically

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equivalent input AND logic, X1 and Y1, and X2 and Y2.
Fig. 8 shows the transistor-level schematic of Fig. 7. Based
on this schematic, logically equivalent transistors are
merged as follows. For the PMOS side, two transistor pairs
in M1 and S1 blocks in Fig. 8 can be shared as shown in
Fig. 9. When either N3 or CP is Low, the shared common
node becomes VDD voltage level, and N2 and N5 nodes
are controlled by PMOS transistors gated N1 and N4
individually. When both N3 and CP are High, both N2 and
N5 nodes are pulled down to VSS by NMOS transistors
gated N3 and CP. As well as M1 and S1 blocks, two PMOS
transistor pairs in M2

Fig.10.Transistor merging in NMOS side.

and S2 blocks are shared. For the NMOS side, transistors of

logically equivalent operation can be shared as well. Two
transistors in M1 and M2 blocks in Fig. 10 can be shared.
Transistors in S1 and S2 are shared as well.

Fig.7.Schematic diagram of proposed FF.

Fig.11.Further transistor merging in PMOS side.

Fig.8.Transistor level schematic of Fig.7.

Fig.12.The state of internal nodes.

Fig.9.Transistor merging in PMOS side.
Further in the PMOS side, CP-input transistors in S1 and
S2, shown in Fig. 11, can be merged, because N2 and N3
are logically inverted to each other. When CP is Low,

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both nodes are in VDD voltage level, and either N2 or N3
is ON. When CP is High, each node is in independent
voltage level as shown in Fig. 12. In consideration of this
behavior, the CP-input transistors are shared and
connected as shown in Fig. 11. The CP-input transistor is
working as a switch to connect S1 and S2.
This process leads to the circuit shown in Fig. 13. This
circuit consists of seven fewer transistors than the original
circuit shown in Fig. 8. The number of clock-related Fig. 16. TCFF with reset type.
transistors is only three. Note that there is no dynamic off, the NMOS transistor connected to CP turns on, and
circuit or pre-charge circuit, thus, no extra power the slave latch becomes the data output mode. In this
dissipation emerges. We call this reduction method condition, the data in the master latch is transferred to the
Topological Compression (TC) method. The FF, TC- slave latch, and then outputted to Q. In this operation, all
Method applied, is called Topologically-Compressed Flip- nodes are fully static and
Flop (TCFF). full-swing. The current from the power supply does not
flow into the master and the slave latch simultaneously
B. Cell Operation because the master latch and the slave latch become active
alternately. Therefore, timing degradation is small on cell
Fig. 14 shows simulation waveforms of the circuit shown
performance even though many transistors are shared with
in Fig. 13. In Fig. 13, when CP is low, the PMOS
no increase in transistor size.
transistor connected to CP turns on and the master latch
becomes the data input mode. Both VD1 and VD2 are
C. Cell Variation
pulled up to power-supply level, and the input data from
D is stored in the master latch. When CP is high, the LSI designs require FFs having additional functions like
PMOS transistor connected to CP turn scan, reset, and set. The performance and cell area for
these cells are also important. TCFF easily realizes these
cells with less transistor-count than conventional FFs. The
circuit diagrams of TCFF with scan, reset, and set are
shown in Figs. 15–17. Each circuit can be designed with
similar structure, and these FFs also have three transistors
connected to CP so the power dissipation is nearly the
same as that of TCFF. Detailed characteristics are shown
in Section V.

Fig. 13. Transistor level schematic of topologically-

compressed flip-flop (TCFF).

Fig. 17. TCFF with set type.

Fig. 14. Waveform on SPICE simulation.

Fig. 15. TCFF with scan type. Fig. 18. Power simulation results of TCFF and other FFs

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V. PERFORMANCE SIMULATION

The performance of TCFF is demonstrated by SPICE

simulation with 40 nm CMOS technology. For
comparison with other FFs, the same transistor size is
applied for every transistor in each FF including TCFF in
order to simulate the same conditions. Some standard
values are assumed for transistor sizes for the purpose of
comparison; 0.24 𝜇m for width and 0.04𝜇m for length in
PMOS, and 0.12 𝜇m for width and 0.04 𝜇m for length in
NMOS. Fig. 19. Supply voltage dependency

Fig. 18 shows the normalized power dissipation versus

data activity compared to other FFs. TCFF consumes the
least power among them in almost all ranges of data
activity. Average data activity of FFs in an LSI is
typically between 5% and 15%. The power dissipation of
TCFF is 66% lower than that of TGFF at 10% data
activity. In the same way at 0% data activity, it is 75%
lower. Table I summarizes the transistor-count, the CP-Q
delay, the setup/hold time, and the power ratio of each FF.
Fig. 20. Input slew dependency.
As for delay, TCFF is almost the same as the conventional
FF, and better than other FFs. Setup time is the only has more clock-input-slew dependence compared to other
inferior parameter to the conventional FF, and about 70 ps FFs, thus it becomes difficult to use in large input
larger than the value of the conventional one. For hold transition time.The characteristics of TCFF are stable and
time, TCFF is better than the conventional FF. In the second best following TGFF.
summary, only setup time is large, but TCFF keeps Fig. 21 shows the normalized power versus the data
competitive performance to the conventional and other activityfor six varieties of TCFF including the basic type,
FFs. and Table II shows performances of various TCFFs in the
Fig. 19 shows the supply-voltage dependence of the CP-Q same conditions as Table I. Every cell inherits the strength
delay. TCFF is possible to operate down to 0.6 V supply of the original TCFF cell structure. No difference is
voltage due to essentially fully-static function. Though observed among cell variations.
TCFF operates with single phase clock signal, a clock Fig. 22 shows the layout of TGFF and TCFF with scan.
buffer is not necessary. The circuit is directly driven from Because TCFF needs more wiring resources for master
a clock pin. Fig. 20 shows the clock-input-slew and slave latch in the layout, it uses metal3 as compared
dependence of the CP-Q delay. ACFF to TGFF using up to metal2. But because the number of
transistors in TCFF is fewer than the TGFFs, TCFF can be
TABLE I realized in slightly smaller cell area than the conventional
PERFORMANCE COMPARISON OF TCFF AND OTHER FFS one. In this layout, the area is adjusted to grid base design,
resulting in the same area as the conventional one. Thus, it
is easy to replace the conventional FF with TCFF if the
cell replacement process is executed after pre-layout and
timing analysis. In this section, TCFF’s lowest power
dissipation, competitive performance,

Fig. 21. Power simulation results of various TCFFs.

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TABLE II and cell area are explained. In the next section, how
PERFORMANCE COMPARISONS OF VARIOUS effectively TCFF is applied to actual chip design is shown
TCFFS by placement and routing experiment.

VI. EXPERIMENTAL CHIP LAYOUT

In order to estimate the effect when applying to a chip

design, an experimental netlist is implemented in a 2 mm
square chip by utilizing commercial logic synthesis and
P&R tool. Fig. 23 shows the layout and outline of the
experimental chip. It consists of random logic, SRAM,
analog, and I/O. The random logic consists of FFs, clock
drivers, and other logic. In order to verify how TCFF is
effectively applied to chip design, two types of front-end
cell libraries are prepared. One is a conventional set with
TGFF, and the other is a set including TCFF in addition to
TGFF. Using these two libraries, logic synthesis and P&R
are

Fig. 22. The cell layout with scan.

TABLE III
EXPERIMENTAL CHIP LAYOUT DESIGN SUMMARY

Fig. 23. The experimental chip layout.

Fig. 24. Transistor count of random logic area with and without TCFF.

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executed independently and those results are compared. In various systems especially to a higher speed case in terms
logic synthesis, the power-reduction option is highly of power and performance. Fig. 26 shows the result about
applied. replacement rate of TGFF to TCFF in various clock
Fig. 24 and Table III show the logic synthesis and P&R frequencies. The same front-end cell libraries and netlists as
results at 250 MHz clock frequency. After applying the Section VI are used, and only clock cycle condition is set
library including TCFF, 98% of TGFFs which occupy up from 200 MHz to 333
44% of the random logic are replaced by TCFFs. Almost
all TCFFs meet the timingconstraints despite TCFF
having larger setup time of 105 ps instead of 38 ps of
TGFF as shown in Table I. As regards area size, only
1.3% increased with the TCFF-included library even
though TCFF uses one more metal layer than TGFF in
cell layout. This shows TCFF has no disadvantage in P&R
process.

Fig. 26. Frequency dependence of replacement from TGFF to TCFF

Fig. 27. Power dissipation for TCFF and the resized TCFF.

Fig. 25. Power reduction estimation in a chip

From these results, it is shown that the TCFF can easily

replace TGFF while keeping timing performance and
almost the same area size.
As regards total chip-level power reduction rate, it
strongly depends on the application. In general, the Fig. 28. Frequency dependence of replacement from TGFF to TCFF and
the resized TCFF
power-reduction effect by introducing TCFF is estimated
by the following formula (see Fig. 25): TABLE IV
PERFORMANCE OF TGFF, TCFF AND RESIZED TCFF.
= * *
where ∆𝑃 is chip power reduction ratio, 𝑃𝑂 is FF
occupation ratio, 𝑅𝑃 is replacement rate, and 𝑃(𝛼) is
power reduction ratio of FF with data activity ( 𝛼). In the
experimental chip layout, FF occupation ratio in random
logic is 44%, RP is 98%, and P( 𝛼 = 10%) is 66%.
Therefore, assuming the ratio of random logic power to the
whole chip is 60%, 17% chip power reduction ratio (∆𝑃 ) is as a parameter. In the condition from 200 MHz to 300
expected. MHz, more than 98% of TGFF are replaced to TCFF.
However, in case of 333 MHz condition, replacement rate
VII. COUNTERMEASURE TO VARIOUS SPEED goes down to 88%, probably because of setup timing issue.
SYSTEMS Finally, at 360 MHz the timing constraint is not satisfied
even if TGFFs are fully used.
In Section VI, we investigated the effect when applying In order to use TCFF around the critical condition,
to a 250 MHz system design in 40 nm CMOS technology. adjustment of transistor size is considered. In TCFF, since
In this section, we show how effectively TCFF is applied to data-input or data-output operation is controlled by three

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ACKNOWLEDGMENT
R.Mohan completed his M.E
Applied Electronics in Karunya
we would like to thank Mr.K.G.Parthiban, ASP Institute of Technology,
&HoD/ECE for the support. Completed B.E Electrical and
Electronics Engineering in
Government College of
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