DM74ALS125 Quad 3-STATE Buffer

November 1989
Revised February 2000

DM74ALS125
Quad 3-STATE Buffer
General Description Features
This device contains four independent gates each of which ■ Advanced low power oxide-isolated ion-implanted
performs a non-inverting buffer function. The outputs have Schottky TTL process
the 3-STATE feature. The 3-STATE circuitry contains a fea- ■ Functional and pin compatible with the 74LS counterpart
ture that maintains the buffer outputs in 3-STATE (high
■ Switching response specified into 500Ω and 50 pF load
impedance state) during power supply ramp-up or ramp-
down. This eliminates bus glitching problems that arise ■ Switching response specifications guaranteed over full
during power-up and power-down. To minimize the possi- temperature and VCC supply range
bility that two outputs will attempt to take a common bus to ■ PNP input design reduces input loading
opposite logic levels, the disable time is shorter than the ■ Low level drive current: 74ALS = 24 mA
enable time of the outputs.

Ordering Code:
Order Number Package Number Package Description
DM74ALS125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Logic Diagram

Functional Table
Y=A
Input Output
A C Y
L L L
H L H
X H Hi-Z
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
Hi-Z = 3-STATE (Outputs are disabled)

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DM74ALS125
Absolute Maximum Ratings(Note 1)
Supply Voltage, VCC 7V
Input Voltage 7V
Voltage Applied to Disabled Output 5.5V
Note 1: The Absolute Maximum Ratings are those values beyond which
Operating Free Air Temperature Range 0 to +70°C the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Storage Temperature Range −65°C to +150°C Characteristics tables are not guaranteed at the absolute maximum ratings.
Typical θJA The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
N Package 78.0°C/W
M Package 111.0°C/W

Recommended Operating Conditions

Symbol Parameter Min Typ Max Units
VCC Supply Voltage 4.5 5 5.5 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −15 mA
IOL LOW Level Output Current 24 mA
TA Operating Free-Air Temperature 0 70 °C

Electrical Characteristics
over recommended operating free air temperature (unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units

VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.5 V

VOH HIGH Level VCC = 4.5V to 5.5V IOH = −0.4 mA VCC − 2 V
Output Voltage VCC = 4.5V IOH = −3 mA 2.4 V
IOH = Max 2 V
VOL LOW Level VCC = 4.5V IOL = 12 mA 0.25 0.4 V
Output Voltage IOL = 24 mA 0.35 0.5 V
II Input Current at Max
VCC = 5.5V, VI = 7V 0.1 mA
Input Voltage
IIH HIGH Level
VCC = 5.5V, VI = 2.7V 20 µA
Input Current
IIL LOW Level
VCC = 5.5V, VIL = 0.4V −0.1 mA
Input Current
IO Output Drive
VCC = 5.5V, VO = 2.25V −30 −112 mA
Current
IOZH HIGH Level 3-STATE
VCC = 5.5V, VO = 2.7V 20 µA
Output Current
IOZL LOW Level 3-STATE
VCC = 5.5V, VO = 0.4V −20 µA
Output Current
ICC Supply Current VCC = 5.5V Outputs HIGH 7 10 mA
Outputs LOW 10 14 mA
3-STATE 13.5 18 mA

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 DM74ALS125
Switching Characteristics
From To
Symbol Parameter Conditions Min Units
(Input) (Output) Max
tPLH Propagation Delay Time VCC = 4.5V to 5.5V,
A Y 3 10 ns
LOW-to-HIGH Level Output CL = 50 pF,
tPHL Propagation Delay Time R1 = 500Ω,
A Y 2 10 ns
HIGH-to-LOW Level Output R2 = 500Ω,
tPZH Output Enable Time TA = Min to Max
C Y 2 13 ns
to HIGH Level Output
tPZL Output Enable Time
C Y 2 12 ns
to LOW Level Output
tPHZ Output Disable Time
C Y 1 8 ns
from HIGH Level Output
tPLZ Output Disable Time
C Y 2 13 ns
from LOW Level Output

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DM74ALS125
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M14A

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 DM74ALS125 Quad 3-STATE Buffer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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