IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO.

1, FEBRUARY 2008 361

An All-Digital Fast-Locking Programmable

DLL-Based Clock Generator
Chuan-Kang Liang, Student Member, IEEE, Rong-Jyi Yang, Member, IEEE, and Shen-Iuan Liu, Senior Member, IEEE

Abstract—An all-digital fast-locking programmable DLL-based

clock generator is presented. By resetting the output clock every
two input clock periods, the initial minimal delay constraint in the
conventional architecture is eliminated. Compared with the pre-
vious work, the short locking time is also achieved. The proposed
circuit has been fabricated in 0.35- m CMOS process and occu-
pies the active area of 0.216 mm2 . The clock multiplication ratio is
programmed from 2 to 15. The frequency ranges of the input and
output clocks are 4 200 MHz and 60 450 MHz, respectively.
It dissipates less than 17 mW at all operating frequencies from a
3.3-V supply.
Index Terms—All-digital delay-locked loop (DLL), clock gener-
ator, clock multiplier, fast-locking, frequency synthesizer.

I. INTRODUCTION Fig. 1. Proposed all-digital clock generator.

M ANY ON-CHIP clock generators in high-performance

systems utilize phase-locked loops (PLLs) to achieve
high frequencies and programmable clock multiplications. inaccuracy. However, there are some problems in an MDLL.
However, a PLL is a higher order system and it may have stable First, an MDLL has a locking initial constraint that it has to
problems. Process, voltage, and temperature (PVT) variations operate from the shortest delay line. Environmental variations
may influence the loop characteristics and hence increase the resulting in a longer delay line may make an MDLL reset to
design difficulties. In addition, the voltage-controlled oscilla- prevent the locking failure. If the variation disappears quickly,
tors (VCOs) in the PLLs will accumulate the jitter. resetting the system to lock wastes time. If the variation is peri-
On the contrary, the jitter is corrected when a clean refer- odic, the system would reset again and again and lose the ability
ence arrives at the delay-locked loops (DLLs). Also, a DLL to lock. Second, unlike a PLL-based clock generator, an MDLL
is a first-order system without stability considerations. There- cannot switch the clock frequency from low to high. Third, the
fore, the DLL-based clock generator is attractive in noisy envi- approach takes a long time to lock since it is an analog feedback
ronments. Two kinds of DLL-based clock generators have been system.
presented by using the multiphase clock mixing [1]–[3] and the In this paper, an all-digital fast-locking programmable DLL-
cyclic wave generations [4]–[8]. Although the former [1]–[3] based clock generator is presented. To resolve the initial delay
combines the multiphase clocks in the delay lines to achieve the constraint in the conventional MDLL, a new locking method is
frequency multipliers, the multiplication ratio is usually corre- adopted, and the digital phase-frequency detector is proposed.
lated with the number of delay cells in the delay lines, and it is Moreover, the modified successive approximation register-con-
difficult to program. Moreover, it suffers from duty cycle error trolled (MSAR) circuit is used to achieve a short locking time
caused by the delay cell mismatch. It also needs to avoid the and tracks the environmental variations. In addition, this all-dig-
false lock or harmonic lock to obtain the multiphase clocks uni- ital clock generator releases the effects of PVT variations and
formly distributed with one period. The latter [4]–[8], called a prevails in scaling down technology.
multiplying delay-locked loop (MDLL), uses the cyclic wave This paper is organized as follows. Section II shows the
to multiply the clock. The delay elements form a ring oscillator system architecture and Section III is the circuit description.
and transform into a delay line every reference cycle. Hence, Section IV gives the performance analysis of the proposed cir-
the MDLL behaves like a DLL and has the capability to mul- cuit. Section V shows the experimental results, and Section VI
tiply the clock frequency like a PLL [4]. Since the output clock gives the conclusions.
is generated through the same delay line, it avoids duty cycle
II. SYSTEM ARCHITECTURE
Manuscript received October 3, 2006; revised March 3, 2007. This paper was
recommended by Associate Editor P. Heydari. Fig. 1 shows the proposed DLL-based clock generator. It is
The authors are with Graduate Institute of Electronics Engineering and the mainly composed of the MSAR circuit, a timing control cir-
Department of Electrical Engineering, National Taiwan University, Taipei,
Taiwan 10617, R.O.C. (e-mail: [email protected]). cuit, a digital phase-frequency detector (PFD), and a digital-
Digital Object Identifier 10.1109/TCSI.2007.913612 controlled delay line. According to the different operations in
1549-8328/$25.00 © 2008 IEEE
362 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 1, FEBRUARY 2008

Fig. 2. Timing diagram of the clock generator with the multiplication ratio of 4.

the MSAR circuit, this clock generator is divided into two oper- increase the output frequency and vice versa. When the next
ating modes. One is the binary-search mode and the other is the “Select” rises, the clock generator enters the refresh cycle again.
sequential-search mode. Each mode has two execution cycles in The ring oscillator is disconnected and the process is repeated
turn, i.e., the refresh cycle and the compare cycle. Differing from until the binary-search mode finishes. Because “Compare” is
the conventional MDLL, refreshed every reference cycle, using generated every two reference cycles, this 8-b MSAR circuit
two execution cycles to refresh the output clock could eliminate takes 16 cycles to lock.
the initial constraint since the detection time and refresh time When the binary-search mode is complete, “Stop” goes high
are separated. Therefore, the longer delay line could be detected and then it causes the signal “En_Counter” to rise. The fre-
without violating the refresh time. The timing diagram is shown quency acquisition is finished, and the clock generator enters
in Fig. 2 with the external divisor of 4. The binary-search algo- the sequential-search mode. The MSAR circuit is converted into
rithm cannot be applied to the conventional MDLL, since the a counter. It allows this clock generator to operate in a closed
initial minimum delay constraint exits. The proposed two-cycle loop to track the PVT variations and compensate for the undealt
refreshing technique can solve the initial delay constraint and phase error in the binary-search mode. Once the clock generator
achieve the fast-locking time by using the MSAR circuit. How- enters the sequential-search mode, it will not go back to the bi-
ever, the disadvantages of the proposed MDLL exist. The dou- nary-search mode unless the system is reset.
bled accumulated jitter and a half-loop bandwidth are achieved, Fig. 3 shows the timing diagram in the sequential-search
compared with the conventional architecture having the same mode. Since the proposed MDLL is a digital system, the
loop parameters. digital-controlled code of the MSAR circuit in a closed loop
When the signal “Start” is enabled, the MSAR circuit per- may jump back and forth due to the finite quantization error
forms the binary search. This clock generator is in the binary- even in the locked situation. In order to avoid this problem, a
search mode. In the refresh cycle, the signal “Select” goes high, detection window is used. If the last desired output clock rises
and the rising edge of the internal clock (In_Clk) passes through within the detection window, “En_Counter” is low and the
the multiplexer and the digital-controlled delay line to correct code in the MSAR circuit sustains; otherwise, “En_Counter” is
the jitter accumulation in the output clock (Out_Clk). After the high and the code in the MSAR circuit is adjusted according
internal clock goes high, “Select” goes down immediately, and to “Compare.” Consequently, the clock generator could track
hence the multiplexer converters the delay line into a ring os- the environment variations and the phase error is corrected by
cillator. The counter counts how many output clocks have been sequentially increasing or decreasing the codes in the MSAR
generated in the refresh cycle. The internal clock is divided by circuit.
two to generate the signal “Reset_Counter.” At the beginning The detection window size directly influences the output
of the compare cycle, the falling edge of “Reset_Counter” stops clock jitter and the steady-state phase error. The small detection
the counter to assure that only the output clocks in the refresh window may cause the loop behavior to vary by the jitter and
cycle are counted. The counted number stored in the counter is the large one will result in a steady-state phase error. In this
compared with the external divisor by the PFD. study, the detection window size is determined by the
In the compare cycle, the MSAR circuit adjusts the dig- delay time between the reference clock (Ref_Clk) and the
ital-controlled delay line according to the signal, “SAR_Clk” postponed clock (Post_Clk). The detection window size is
and “Compare” by using the binary search method. If the chosen as a 1-LSB delay of the digital-controlled delay line
counted number is smaller than the desired one, “Compare” and is shown in Fig. 4. If Out_Clk leads In_Clk by more than
is low, and the digital-controlled delay line is shortened to , the controlled code for the digital-controlled delay line
LIANG et al.: ALL-DIGITAL FAST-LOCKING PROGRAMMABLE DLL-BASED CLOCK GENERATOR 363

Fig. 3. Timing diagram of the proposed clock generator in the sequential-search mode.

Fig. 4. Detection window. (a)

increases by one. If Out_Clk lags In_Clk by more than ,

the controlled code decreases by one. Once the phase error
between In_Clk and Out_Clk is within , i.e., Out_Clk
is within the detection window, the controlled code is held. The
detailed circuits are discussed in the next section.

III. CIRCUIT DESCRIPTION (b)

A. MSAR Circuit Fig. 5. (a) One-bit MSAR circuit. (b) Eight-bit MSAR circuit.
The conventional SAR circuit stops the operation after the last
bit is decided. So, the clock generator operates in an open loop
and fails to track the PVT variations. The proposed MSAR cir- binary-search circuit [10], it is important to choose the proper
cuit resolves this problem without an extra counter. The MSAR clock, SAR_Clk, for the MSAR circuit. To guarantee that all sig-
circuit performs the conventional binary search. Once the binary nals in the MSAR circuit work properly, “SAR_Clk” should be
search is completed, the additional logics will enable the func- sufficiently long, e.g., at least two input clocks. Fortunately, this
tion of the counter to execute the closed loop tracking. two-cycle refreshing technique provides the clock SAR_Clk by
Fig. 5(a) shows a one-bit cell for the MSAR circuit. In dividing Ref_Clk by two with additional D-flip-flops to adjust
the dashed-line area of Fig. 5(a), two Exclusive-OR gates, an its duty cycle as shown in Fig. 2. The SAR_Clk has the suffi-
inverter, and a NOR gate are added to allow the sequential cient time to allow the MSAR circuit to complete its operation.
search. The remaining logic gates perform the binary search To correct the jitter accumulations in the digital-controlled
as in [9]. Fig. 5(b) shows the 8-b MSAR circuit. Since the delay line, the signal “Select” is needed. In this study, “Select”
carry-in signal “C_in” comes from the lower bit cell as shown is generated by the reference clock divided by 2 and the internal
in Fig. 5(b), “En_Counter” decides whether the sequential clock as shown in Fig. 6. Since the reference clock leads the
search is executed or not. When “En_Counter” is high, the internal clock, “Select” can always catch the rising edge of the
carry-out signal “C_out” and the least significant bit (LSB), internal clock correctly. However, in [4], “Select” is generated
B7, propagate to the next stage and hence a counter is formed. by the output clock and the delay time in a delay line affects
When “En_Counter” is low, the carry-in signals in other cells the operation. Once the delay time is sufficiently long, “Select”
keep low and the code of MSAR also holds. in [4] disappears and the system does not sustain the locking
process.
B. Timing Control Circuit The limitation of the new selection method is that the signal
In the timing control circuit, two important controlling signals “Select” is no longer the appropriate window for the internal and
are generated: “Select” and “SAR_Clk.” Since the sufficient op- the multiplied output clocks to compare. Hence, a new PFD is
eration time is needed to compare and adjust the delay line in a required to deal with the problem.
364 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 1, FEBRUARY 2008

Fig. 6. Circuit to generate the signal “Select.”

(a)

(a)

(b)
(b)
Fig. 8. (a) Signal flow for the PFD in the binary-search mode. (b) Signal flow
Fig. 7. (a) Proposed digital PFD. (b) detailed circuits of the SAR comparator for the PFD in the sequential-search mode.
and counter comparator.

After the frequency acquisition is complete, this clock gener-

C. Digital PFD
ator enters the sequential-search mode. The output signal of the
This digital PFD consists of a SAR comparator, a counter counter comparator (Counter_Comp) is generated according
comparator, and a multiplexer. Fig. 7(a) shows its sketch to the phase relations among the last desired output clock
diagram and Fig. 7(b) is the detailed circuits of the two com- (Out_Clk), the reference clock (Ref_Clk), and the postponed
parators. The SAR comparator is used in the binary-search clock (Post_Clk). The two clocks realize the detection window
mode when “En_Counter” is low. The counter comparator is by the DFFs, D and G, as shown in Fig. 7(b). The external
adopted in the sequential-search mode when “En_Counter” is divisor subtracts one to compare with the counted number in
high. Fig. 8(a) and (b) shows the signal flow graphs for the pro- the counter. This produces the signal “Enable” to allow the
posed digital PFD in the binary-search and sequential-search DFFs, D and G, to detect the position of the last desired output
modes, respectively. clock. If the last desired output clock rises after this detection
In the binary-search mode, the frequency acquisition is real- window, “Counter_Comp” is low and vice versa. This signal
ized by comparing the counted number in the counter and the “Enable” is reset after the last desired output clock rises by the
external divisor. If the counted number is less than the external DFFs, B and C.
divisor, the output signal (SAR_Comp) of the SAR comparator In the sequential-search mode, the phase acquisition is
is low or else it is high. achieved by detecting whether the last desired output clock
LIANG et al.: ALL-DIGITAL FAST-LOCKING PROGRAMMABLE DLL-BASED CLOCK GENERATOR 365

(a)

Fig. 9. Digital-controlled delay cell.

Fig. 10. Linear Z -domain model for the proposed DLL-based clock generator. (b)

rises within the detection window or not. The frequency ac-

quisition is achieved by comparing the counted number in the
counter with the external divisor. It realizes the digital phase-
frequency detection.

D. Digital-Controlled Delay Line

The digital-controlled delay line is composed of three
inverter-type delay cells with an 8-b controlled code. The
digital-controlled delay cell is shown in Fig. 9 with a binary-
weighted switched-capacitor array. The capacitive loads are
(c)
increased when the code in the MSAR circuit becomes larger
and vice versa. In Fig. 9, two kinds of connections are adopted Fig. 11. (a) Simulated delay time of the digital-controlled delay line under the
for the switched capacitors. To prevent too large parasitic input jitters with peak-to-peak amplitudes of 30 and 60 ps and frequencies of 2
and 20 MHz. The period of the input clock is 20 ns. (b) Simulated delay time
capacitances to limit the system speed, larger capacitances are of the digital-controlled delay line under the input jitter with the peak-to-peak
connected to the output through switches to reduce parasitic amplitude of 60 ps and the frequency of 20 MHz. (c) Simulated delay time of
capacitance. Smaller capacitances are connected to the output the digital-controlled delay line with the detection window method under the
input jitters with peak-to-peak amplitudes of 30 and 60 ps and frequencies of 2
directly and the switches are connected to ground. Although and 20 MHz.
this method may result in linear and monotonic problems, it is
overcome by the careful design and layout.
the total delay would be amplified by a factor of . Although
IV. PERFORMANCE ANALYSIS this PFD works every two input cycles, the output of the PFD is
The linear model of the proposed all-digital DLL-based clock still based on the comparison between the present input phase
generator is shown in Fig. 10, where is the output phase, and the previous output phase as in [6].
is the input phase, and D is the delay time of the digital- Although the result is calculated every two input cycles, it does
controlled delay line. The delay time in the digital-controlled not violate how the input jitters affect the delay line variations
delay line is given as and the long-term average phase error. The relation between
the input and output phases can be expressed as

(1) (2)

where is the external divisor and represents the adjusted Assume and this clock gen-
delay step once the digital-controlled delay line is updated. When erator is locked. The polarity of may be negative or pos-
the clock generator is locked, is the minimum adjusted delay itive alternatively due to the quantization errors. This situation
step . Since this delay line is connected as a ring oscillator, occurs only when the input phase deviation ,
366 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 1, FEBRUARY 2008

(a)
Fig. 12. Die photograph.

(b)
Fig. 13. Measured transient response at 360 MHz.

caused by the input jitters, is small and the quantization errors

of the delay line and satisfy the
following inequality:

(3)

where is the period of the input clock. Then, the following

equation can be obtained:

(4) (c)

Fig. 14. (a) Input frequency is 30 MHz, and the external divisor is 2. (b) Input
According to (1) and (4), the delay time in the digital-controlled frequency is 30 MHz, and the external divisor is 15. (c) Input frequency is
delay line is 4 MHz, and the external divisor is 14.

(5)
phase error are. Fig. 11(a)-(c) gives the simulated delay time
Using (2) and (5), the input and output phases can be expressed of the digital-controlled delay line under the input jitters with
as peak-to-peak amplitudes of 30 and 60 ps and frequencies of 2
and 20 MHz. The input clock is 50 MHz ns ; the
(6) minimum adjusted delay step is 30 ps and is 2.
If the peak-to-peak amplitude of the input jitter is larger than
Equation (6) implies that the input jitter and the quantization the quantization errors, or , two
error will directly contribute to the output jitter. The smaller different cases may occur. When the jitter’s frequency is slow,
the external divisor and the higher the resolution of the digital- the input phase deviation is small enough
controlled delay line are, the smaller the output jitter and the not to exceed the quantization errors. The condition of (3) is
LIANG et al.: ALL-DIGITAL FAST-LOCKING PROGRAMMABLE DLL-BASED CLOCK GENERATOR 367

(a)

Fig. 16. Measured jitters at different output frequencies.

Hence, if the quantization error is small, even slight input jit-

ters can cause multiple controlled code transitions, and therefore
the jitters of the output clock become large. If the quantization
error is large, the large static phase error would result in a large
frequency offset of the output. The proposed detection window
method allows small quantization error and prevents the mul-
tiple controlled code transitions from the small quantization er-
rors. By using the detection window method, Fig. 11(c) gives the
(b)
simulated delay time of the digital-controlled delay line with the
same input conditions of Fig. 11(a) and (b).

V. EXPERIMENTAL RESULTS
The proposed DLL-based clock generator has been fabricated
in a 0.35- m CMOS process. Its die photograph is shown in
Fig. 12 and the active area is 540 m 400 m. The clock
multiplication ratio is from 2 to 15. The frequency ranges of the
input and output clocks are 4 200 MHz and 60 450 MHz,
respectively. Fig. 13 shows the measured transient response at
360 MHz. As “Start” goes high, the most significant bit B0 is set
to one and others are set to zero. In the binary-search mode, the
8-b MSAR circuit takes 16 input clocks to lock. In the sequen-
(c) tial-search mode, the MSAR circuit will track the environmental
Fig. 15. (a) Measured open-loop peak-peak jitter at 450 MHz. (b) Measured
variations in a closed loop.
closed-loop peak-peak jitter at 450 MHz. (c) Measured jitter at 450 MHz when Fig. 14(a) and (b) show the measured output clocks for the
the detection window is disabled. multiplication ratios of 2 and 15, respectively, at an input fre-
quency of 30 MHz. Fig. 14(c) shows the measured output clock
for the multiplication ratio of 14 at an input frequency of 4 MHz.
still held. Two controlled codes change alternatively as shown in A 4-b counter is used, and therefore the system can multiply the
Fig. 11(a). The simulated quantization errors are 40 and 80 ps. input clock from 2 to 15, which can be extended easily. Fig. 15
This means that this clock generator can track the low-frequency shows the measured peak-to-peak jitter of the output clock at
input jitters. 450 MHz. In Fig. 15(a), the peak-to-peak jitter is 33.3 ps when
However, when the jitter’s frequency is fast enough to violate the MSAR circuit operates as a conventional SAR circuit. In
(3), the multiple controlled codes may change instead of two Fig. 15(b), the peak-to-peak jitter is 37.8 ps when the MSAR cir-
codes. Fig. 11(b) gives the simulated delay time of the digital- cuit tracks the environmental variations in a closed loop. If the
controlled delay line under the input jitter with a peak-to-peak detection window is disabled, the measured peak-to-peak jitter
amplitude of 60 ps and frequency of 20 MHz. The quantization in the closed loop increases to 127.8 ps, as shown in Fig. 15(c).
errors are 160, 40, and 80 ps, respectively. This means that Fig. 16 summarizes the measured jitters at different frequen-
the output clock cannot track the input clock immediately and cies. The performance comparisons with the previous works are
its output jitter becomes large. listed in Table I.
368 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 1, FEBRUARY 2008

TABLE I
PERFORMANCE COMPARISONS

VI. CONCLUSION [6] M.-J. E. Lee, W. Dally, T. Greer, H. T. Ng, R. Farjad-Rad, J. Poulton,
and R. Senthinathan, “Jitter transfer characteristics of delay-locked
An all-digital DLL-based clock generator is presented in loops—Theories and design techniques,” IEEE J. Solid-State Circuits,
this paper. First, it succeeds the advantage of the conventional vol. 38, no. 4, pp. 614–621, Apr. 2003.
MDLL, the low jitter performance, but eliminates its initial [7] G. Y. Wei, J. T. Stonick, D. Weinlader, J. Sonntag, and S. Searles, “A
500 MHz MP/DLL clock generator for a 5 Gb/s backplane transceiver
minimal delay constraint and achieves better stability after in 0.25 um CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.
being locked. Second, it could switch the clock frequency Papers, Feb. 2003, pp. 464–465.
from low to high and program the multiplication ratios by the [8] M. Combes, K. Dioury, and A. Greiner, “A portable clock multiplier
generator using digital CMOS standard cells,” IEEE J. Solid-State Cir-
external divisor as can a PLL-based clock generator. Third, cuits, vol. 31, no. 7, pp. 958–965, Jul. 1996.
the modified SAR circuit not only achieves fast-locking, but [9] A. Rossi and G. Fucilli, “Nonredundant successive approximation
also sustains the closed-loop characteristics to track the PVT register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp.
variations. 1055–1057, Jun. 1996.
[10] G.-K. Dehng, J.-W. Lin, and S.-I. Liu, “A fast-lock mixed-mode DLL
using a 2-b SAR algorithm,” IEEE J. Solid-State Circuits, vol. 36, no.
ACKNOWLEDGMENT 10, pp. 1464–1471, Oct. 2001.
[11] J. Lin et al., “A PVT-tolerant 0.18 MHz to 600 MHz self-calibrated
The authors would like to thank National Chip Implementa- digital PLL in 90 nm CMOS process,” in IEEE Int. Solid-State Circuits
tion Center (CIC), Taiwan, R.O.C., for fabricating this chip. Conf. Dig. Tech. Papers, Feb. 2004, pp. 488–541.
[12] T. D. Chiueh, J. B. Yang, and J. S. Wu, “Design and implementation
of a low-voltage fast-switching mixed-signal-controlled frequency syn-
REFERENCES thesizer,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,
vol. 48, no. 10, pp. 961–971, Oct. 2001.
[1] G. Chien and P. R. Gray, “A 900-MHz local oscillator using a DLL- [13] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara,
based frequency multiplier technique for PCS applications,” IEEE J. “Digitally controlled oscillator (DCO)-based architecture for RF
Solid-State Circuits, vol. 35, no. 12, pp. 1996–1999, Dec. 2000. frequency synthesis in a deep-submicrometer CMOS process,” IEEE
[2] C. Kim, I. C. Hwang, and S. M. Kang, “Low-power small-area Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11,
6 7.28-ps-jitter 1-GHz DLL-based clock generator,” in IEEE Int. pp. 815–828, Nov. 2003.
Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 142–453.
[3] C. C. Wang, Y. L. Tseng, H. C. She, and R. Hu, “A 1.2 GHz pro-
grammable DLL-based frequency multiplier for wireless applications,”
IEEE Trans. Very Large-Scale Integr. (VLSI) Syst., vol. 12, no. 12, pp. Chuan-Kang Liang (S’06) received the B.S. and
1404–1408, Dec. 2004. M.S. degrees from the Department of Electrical
[4] R. Farjad-Rad, W. Dally, H. T. Ng, R. Senthinathan, M.-J. E. Lee, R. Engineering and Graduate Institute of Electronics
Rathi, and J. Poulton, “A low-power multiplying DLL for low-jitter Engineering, National Taiwan University (NTU),
multigigahertz clock generation in highly integrated digital chips,” Taipei, Taiwan, R.O.C., in 2004 and 2006, respec-
IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804–1812, Dec. tively. She is currently working toward the Ph.D.
2002. degree at the University of California, Los Angeles.
[5] C. S. Hwang, P. Chen, and H. W. Tsao, “A wide-range and fast-locking Her research interests include the architecture and
clock synthesizer IP based on delay-locked loop,” in Proc. Int. Symp. system design of high-speed transceivers and RFICs
Circuits Syst., May 2004, vol. I, pp. 785–788. for wireless communications.
LIANG et al.: ALL-DIGITAL FAST-LOCKING PROGRAMMABLE DLL-BASED CLOCK GENERATOR 369

Rong-Jyi Yang (S’03–M’06) was born in Taipei, Shen-Iuan Liu (S’88–M’93–SM’03) was born in
Taiwan, R.O.C., in 1973. He received the B.S. de- Keelung, Taiwan, R.O.C., in 1965. He received the
gree in electrical engineering from National Central B.S. and Ph.D. degrees in electrical engineering
University, Jhongli, Taiwan, R.O.C., in 1998, and the from National Taiwan University (NTU), Taipei,
M.S./Ph.D. degree from National Taiwan University, Taiwan, R.O.C., in 1987 and 1991, respectively.
Taipei, Taiwan, R.O.C., in 2006. From 1991 to 1993, he served as a second lieu-
Since August 2006, he has been an Assistant Pro- tenant in the Chinese Air Force. From 1991 to 1994,
fessor with the Department of Electrical Engineering, he was an Associate Professor with the Department
Chung Gung University, Tao-Yuan, Taiwan, R.O.C. of Electronic Engineering, National Taiwan Institute
His research interests include both analog and dig- of Technology. He joined in the Department of Elec-
ital approaches of phase-locked loops, delay-locked trical Engineering, NTU, in 1994, and he has been a
loops, and high-speed CMOS data-communication circuits for multiple gigabit Professor since 1998. His research interests are in analog and digital integrated
applications. circuits and systems.
Dr. Liu is a member of the Institute of Electrical, Information and Commu-
nication Engineers. He has served as a Chair for the IEEE Solid-State Circuits
Society Taipei Chapter from 2004. He has served as a General Chair for the
15th VLSI Design/CAD symposium, Taiwan, 2004 and a Program Co-chair
on the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated
Circuits, Japan, 2004. He was the recipient of the Engineering Paper Award
from the Chinese Institute of Engineers in 2003, the Young Professor Teaching
Award from MXIC Inc., the Research Achievement Award from NTU, and
the Outstanding Research Award from National Science Council in 2004. He
has served as a Technical Program Committee member for A-SSCC since
2005 and ISSCC since 2006, respectively. He was an Associate Editor of
the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS
in 2006–2007. Since 2006, he has been the Associate Editor of the IEEE
JOURNAL OF SOLID-STATE CIRCUITS and since 2008, an Associate Editor of
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. He is
a member of IEICE.